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1 /*
2 * QEMU sPAPR PCI host originated from Uninorth PCI host
3 *
4 * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation.
5 * Copyright (C) 2011 David Gibson, IBM Corporation.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
26 #include "qemu/osdep.h"
27 #include "qapi/error.h"
28 #include "hw/core/irq.h"
29 #include "hw/core/sysbus.h"
30 #include "migration/vmstate.h"
31 #include "hw/pci/pci.h"
32 #include "hw/pci/msi.h"
33 #include "hw/pci/msix.h"
34 #include "hw/pci/pci_host.h"
35 #include "hw/ppc/spapr.h"
36 #include "hw/pci-host/spapr.h"
37 #include <libfdt.h>
38 #include "trace.h"
39 #include "qemu/error-report.h"
40 #include "qemu/module.h"
41 #include "hw/ppc/fdt.h"
42 #include "hw/pci/pci_bridge.h"
43 #include "hw/pci/pci_bus.h"
44 #include "hw/pci/pci_ids.h"
45 #include "hw/ppc/spapr_drc.h"
46 #include "hw/core/qdev-properties.h"
47 #include "system/device_tree.h"
48 #include "system/kvm.h"
49 #include "system/hostmem.h"
50 #include "system/numa.h"
51 #include "hw/ppc/spapr_numa.h"
52 #include "qemu/log.h"
53
54 /* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */
55 #define RTAS_QUERY_FN 0
56 #define RTAS_CHANGE_FN 1
57 #define RTAS_RESET_FN 2
58 #define RTAS_CHANGE_MSI_FN 3
59 #define RTAS_CHANGE_MSIX_FN 4
60
61 /* Interrupt types to return on RTAS_CHANGE_* */
62 #define RTAS_TYPE_MSI 1
63 #define RTAS_TYPE_MSIX 2
64
65 SpaprPhbState *spapr_pci_find_phb(SpaprMachineState *spapr, uint64_t buid)
66 {
67 SpaprPhbState *sphb;
68
69 QLIST_FOREACH(sphb, &spapr->phbs, list) {
70 if (sphb->buid != buid) {
71 continue;
72 }
73 return sphb;
74 }
75
76 return NULL;
77 }
78
79 PCIDevice *spapr_pci_find_dev(SpaprMachineState *spapr, uint64_t buid,
80 uint32_t config_addr)
81 {
82 SpaprPhbState *sphb = spapr_pci_find_phb(spapr, buid);
83 PCIHostState *phb = PCI_HOST_BRIDGE(sphb);
84 int bus_num = (config_addr >> 16) & 0xFF;
85 int devfn = (config_addr >> 8) & 0xFF;
86
87 if (!phb) {
88 return NULL;
89 }
90
91 return pci_find_device(phb->bus, bus_num, devfn);
92 }
93
94 static uint32_t rtas_pci_cfgaddr(uint32_t arg)
95 {
96 /* This handles the encoding of extended config space addresses */
97 return ((arg >> 20) & 0xf00) | (arg & 0xff);
98 }
99
100 static void finish_read_pci_config(SpaprMachineState *spapr, uint64_t buid,
101 uint32_t addr, uint32_t size,
102 target_ulong rets)
103 {
104 PCIDevice *pci_dev;
105 uint32_t val;
106
107 if ((size != 1) && (size != 2) && (size != 4)) {
108 /* access must be 1, 2 or 4 bytes */
109 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
110 return;
111 }
112
113 pci_dev = spapr_pci_find_dev(spapr, buid, addr);
114 addr = rtas_pci_cfgaddr(addr);
115
116 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) {
117 /* Access must be to a valid device, within bounds and
118 * naturally aligned */
119 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
120 return;
121 }
122
123 val = pci_host_config_read_common(pci_dev, addr,
124 pci_config_size(pci_dev), size);
125
126 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
127 rtas_st(rets, 1, val);
128 }
129
130 static void rtas_ibm_read_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr,
131 uint32_t token, uint32_t nargs,
132 target_ulong args,
133 uint32_t nret, target_ulong rets)
134 {
135 uint64_t buid;
136 uint32_t size, addr;
137
138 if ((nargs != 4) || (nret != 2)) {
139 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
140 return;
141 }
142
143 buid = rtas_ldq(args, 1);
144 size = rtas_ld(args, 3);
145 addr = rtas_ld(args, 0);
146
147 finish_read_pci_config(spapr, buid, addr, size, rets);
148 }
149
150 static void rtas_read_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr,
151 uint32_t token, uint32_t nargs,
152 target_ulong args,
153 uint32_t nret, target_ulong rets)
154 {
155 uint32_t size, addr;
156
157 if ((nargs != 2) || (nret != 2)) {
158 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
159 return;
160 }
161
162 size = rtas_ld(args, 1);
163 addr = rtas_ld(args, 0);
164
165 finish_read_pci_config(spapr, 0, addr, size, rets);
166 }
167
168 static void finish_write_pci_config(SpaprMachineState *spapr, uint64_t buid,
169 uint32_t addr, uint32_t size,
170 uint32_t val, target_ulong rets)
171 {
172 PCIDevice *pci_dev;
173
174 if ((size != 1) && (size != 2) && (size != 4)) {
175 /* access must be 1, 2 or 4 bytes */
176 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
177 return;
178 }
179
180 pci_dev = spapr_pci_find_dev(spapr, buid, addr);
181 addr = rtas_pci_cfgaddr(addr);
182
183 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) {
184 /* Access must be to a valid device, within bounds and
185 * naturally aligned */
186 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
187 return;
188 }
189
190 pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev),
191 val, size);
192
193 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
194 }
195
196 static void rtas_ibm_write_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr,
197 uint32_t token, uint32_t nargs,
198 target_ulong args,
199 uint32_t nret, target_ulong rets)
200 {
201 uint64_t buid;
202 uint32_t val, size, addr;
203
204 if ((nargs != 5) || (nret != 1)) {
205 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
206 return;
207 }
208
209 buid = rtas_ldq(args, 1);
210 val = rtas_ld(args, 4);
211 size = rtas_ld(args, 3);
212 addr = rtas_ld(args, 0);
213
214 finish_write_pci_config(spapr, buid, addr, size, val, rets);
215 }
216
217 static void rtas_write_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr,
218 uint32_t token, uint32_t nargs,
219 target_ulong args,
220 uint32_t nret, target_ulong rets)
221 {
222 uint32_t val, size, addr;
223
224 if ((nargs != 3) || (nret != 1)) {
225 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
226 return;
227 }
228
229
230 val = rtas_ld(args, 2);
231 size = rtas_ld(args, 1);
232 addr = rtas_ld(args, 0);
233
234 finish_write_pci_config(spapr, 0, addr, size, val, rets);
235 }
236
237 /*
238 * Set MSI/MSIX message data.
239 * This is required for msi_notify()/msix_notify() which
240 * will write at the addresses via spapr_msi_write().
241 *
242 * If hwaddr == 0, all entries will have .data == first_irq i.e.
243 * table will be reset.
244 */
245 static void spapr_msi_setmsg(PCIDevice *pdev, hwaddr addr, bool msix,
246 unsigned first_irq, unsigned req_num)
247 {
248 unsigned i;
249 MSIMessage msg = { .address = addr, .data = first_irq };
250
251 if (!msix) {
252 msi_set_message(pdev, msg);
253 trace_spapr_pci_msi_setup(pdev->name, 0, msg.address);
254 return;
255 }
256
257 for (i = 0; i < req_num; ++i) {
258 msix_set_message(pdev, i, msg);
259 trace_spapr_pci_msi_setup(pdev->name, i, msg.address);
260 if (addr) {
261 ++msg.data;
262 }
263 }
264 }
265
266 static void rtas_ibm_change_msi(PowerPCCPU *cpu, SpaprMachineState *spapr,
267 uint32_t token, uint32_t nargs,
268 target_ulong args, uint32_t nret,
269 target_ulong rets)
270 {
271 uint32_t config_addr = rtas_ld(args, 0);
272 uint64_t buid = rtas_ldq(args, 1);
273 unsigned int func = rtas_ld(args, 3);
274 unsigned int req_num = rtas_ld(args, 4); /* 0 == remove all */
275 unsigned int seq_num = rtas_ld(args, 5);
276 unsigned int ret_intr_type;
277 unsigned int irq, max_irqs = 0;
278 SpaprPhbState *phb = NULL;
279 PCIDevice *pdev = NULL;
280 SpaprPciMsi *msi;
281 int *config_addr_key;
282 Error *err = NULL;
283 int i;
284
285 /* Fins SpaprPhbState */
286 phb = spapr_pci_find_phb(spapr, buid);
287 if (phb) {
288 pdev = spapr_pci_find_dev(spapr, buid, config_addr);
289 }
290 if (!phb || !pdev) {
291 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
292 return;
293 }
294
295 switch (func) {
296 case RTAS_CHANGE_FN:
297 if (msi_present(pdev)) {
298 ret_intr_type = RTAS_TYPE_MSI;
299 } else if (msix_present(pdev)) {
300 ret_intr_type = RTAS_TYPE_MSIX;
301 } else {
302 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
303 return;
304 }
305 break;
306 case RTAS_CHANGE_MSI_FN:
307 if (msi_present(pdev)) {
308 ret_intr_type = RTAS_TYPE_MSI;
309 } else {
310 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
311 return;
312 }
313 break;
314 case RTAS_CHANGE_MSIX_FN:
315 if (msix_present(pdev)) {
316 ret_intr_type = RTAS_TYPE_MSIX;
317 } else {
318 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
319 return;
320 }
321 break;
322 default:
323 error_report("rtas_ibm_change_msi(%u) is not implemented", func);
324 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
325 return;
326 }
327
328 msi = (SpaprPciMsi *) g_hash_table_lookup(phb->msi, &config_addr);
329
330 /* Releasing MSIs */
331 if (!req_num) {
332 if (!msi) {
333 trace_spapr_pci_msi("Releasing wrong config", config_addr);
334 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
335 return;
336 }
337
338 if (msi_present(pdev)) {
339 spapr_msi_setmsg(pdev, 0, false, 0, 0);
340 }
341 if (msix_present(pdev)) {
342 spapr_msi_setmsg(pdev, 0, true, 0, 0);
343 }
344 g_hash_table_remove(phb->msi, &config_addr);
345
346 trace_spapr_pci_msi("Released MSIs", config_addr);
347 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
348 rtas_st(rets, 1, 0);
349 return;
350 }
351
352 /* Enabling MSI */
353
354 /* Check if the device supports as many IRQs as requested */
355 if (ret_intr_type == RTAS_TYPE_MSI) {
356 max_irqs = msi_nr_vectors_allocated(pdev);
357 } else if (ret_intr_type == RTAS_TYPE_MSIX) {
358 max_irqs = pdev->msix_entries_nr;
359 }
360 if (!max_irqs) {
361 error_report("Requested interrupt type %d is not enabled for device %x",
362 ret_intr_type, config_addr);
363 rtas_st(rets, 0, -1); /* Hardware error */
364 return;
365 }
366 /* Correct the number if the guest asked for too many */
367 if (req_num > max_irqs) {
368 trace_spapr_pci_msi_retry(config_addr, req_num, max_irqs);
369 req_num = max_irqs;
370 irq = 0; /* to avoid misleading trace */
371 goto out;
372 }
373
374 /* Allocate MSIs */
375 irq = spapr_irq_msi_alloc(spapr, req_num,
376 ret_intr_type == RTAS_TYPE_MSI, &err);
377 if (err) {
378 error_reportf_err(err, "Can't allocate MSIs for device %x: ",
379 config_addr);
380 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
381 return;
382 }
383
384 for (i = 0; i < req_num; i++) {
385 spapr_irq_claim(spapr, irq + i, false, &err);
386 if (err) {
387 if (i) {
388 spapr_irq_free(spapr, irq, i);
389 }
390 spapr_irq_msi_free(spapr, irq, req_num);
391 error_reportf_err(err, "Can't allocate MSIs for device %x: ",
392 config_addr);
393 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
394 return;
395 }
396 }
397
398 /* Release previous MSIs */
399 if (msi) {
400 g_hash_table_remove(phb->msi, &config_addr);
401 }
402
403 /* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */
404 spapr_msi_setmsg(pdev, SPAPR_PCI_MSI_WINDOW, ret_intr_type == RTAS_TYPE_MSIX,
405 irq, req_num);
406
407 /* Add MSI device to cache */
408 msi = g_new(SpaprPciMsi, 1);
409 msi->first_irq = irq;
410 msi->num = req_num;
411 config_addr_key = g_new(int, 1);
412 *config_addr_key = config_addr;
413 g_hash_table_insert(phb->msi, config_addr_key, msi);
414
415 out:
416 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
417 rtas_st(rets, 1, req_num);
418 rtas_st(rets, 2, ++seq_num);
419 if (nret > 3) {
420 rtas_st(rets, 3, ret_intr_type);
421 }
422
423 trace_spapr_pci_rtas_ibm_change_msi(config_addr, func, req_num, irq);
424 }
425
426 static void rtas_ibm_query_interrupt_source_number(PowerPCCPU *cpu,
427 SpaprMachineState *spapr,
428 uint32_t token,
429 uint32_t nargs,
430 target_ulong args,
431 uint32_t nret,
432 target_ulong rets)
433 {
434 uint32_t config_addr = rtas_ld(args, 0);
435 uint64_t buid = rtas_ldq(args, 1);
436 unsigned int intr_src_num = -1, ioa_intr_num = rtas_ld(args, 3);
437 SpaprPhbState *phb = NULL;
438 PCIDevice *pdev = NULL;
439 SpaprPciMsi *msi;
440
441 /* Find SpaprPhbState */
442 phb = spapr_pci_find_phb(spapr, buid);
443 if (phb) {
444 pdev = spapr_pci_find_dev(spapr, buid, config_addr);
445 }
446 if (!phb || !pdev) {
447 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
448 return;
449 }
450
451 /* Find device descriptor and start IRQ */
452 msi = (SpaprPciMsi *) g_hash_table_lookup(phb->msi, &config_addr);
453 if (!msi || !msi->first_irq || !msi->num || (ioa_intr_num >= msi->num)) {
454 trace_spapr_pci_msi("Failed to return vector", config_addr);
455 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
456 return;
457 }
458 intr_src_num = msi->first_irq + ioa_intr_num;
459 trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num,
460 intr_src_num);
461
462 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
463 rtas_st(rets, 1, intr_src_num);
464 rtas_st(rets, 2, 1);/* 0 == level; 1 == edge */
465 }
466
467 static void rtas_ibm_set_eeh_option(PowerPCCPU *cpu,
468 SpaprMachineState *spapr,
469 uint32_t token, uint32_t nargs,
470 target_ulong args, uint32_t nret,
471 target_ulong rets)
472 {
473 SpaprPhbState *sphb;
474 uint32_t addr, option;
475 uint64_t buid;
476 int ret;
477
478 if ((nargs != 4) || (nret != 1)) {
479 goto param_error_exit;
480 }
481
482 buid = rtas_ldq(args, 1);
483 addr = rtas_ld(args, 0);
484 option = rtas_ld(args, 3);
485
486 sphb = spapr_pci_find_phb(spapr, buid);
487 if (!sphb) {
488 goto param_error_exit;
489 }
490
491 if (!spapr_phb_eeh_available(sphb)) {
492 goto param_error_exit;
493 }
494
495 ret = spapr_phb_vfio_eeh_set_option(sphb, addr, option);
496 rtas_st(rets, 0, ret);
497 return;
498
499 param_error_exit:
500 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
501 }
502
503 static void rtas_ibm_get_config_addr_info2(PowerPCCPU *cpu,
504 SpaprMachineState *spapr,
505 uint32_t token, uint32_t nargs,
506 target_ulong args, uint32_t nret,
507 target_ulong rets)
508 {
509 SpaprPhbState *sphb;
510 PCIDevice *pdev;
511 uint32_t addr, option;
512 uint64_t buid;
513
514 if ((nargs != 4) || (nret != 2)) {
515 goto param_error_exit;
516 }
517
518 buid = rtas_ldq(args, 1);
519 sphb = spapr_pci_find_phb(spapr, buid);
520 if (!sphb) {
521 goto param_error_exit;
522 }
523
524 if (!spapr_phb_eeh_available(sphb)) {
525 goto param_error_exit;
526 }
527
528 /*
529 * We always have PE address of form "00BB0001". "BB"
530 * represents the bus number of PE's primary bus.
531 */
532 option = rtas_ld(args, 3);
533 switch (option) {
534 case RTAS_GET_PE_ADDR:
535 addr = rtas_ld(args, 0);
536 pdev = spapr_pci_find_dev(spapr, buid, addr);
537 if (!pdev) {
538 goto param_error_exit;
539 }
540
541 rtas_st(rets, 1, (pci_bus_num(pci_get_bus(pdev)) << 16) + 1);
542 break;
543 case RTAS_GET_PE_MODE:
544 rtas_st(rets, 1, RTAS_PE_MODE_SHARED);
545 break;
546 default:
547 goto param_error_exit;
548 }
549
550 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
551 return;
552
553 param_error_exit:
554 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
555 }
556
557 static void rtas_ibm_read_slot_reset_state2(PowerPCCPU *cpu,
558 SpaprMachineState *spapr,
559 uint32_t token, uint32_t nargs,
560 target_ulong args, uint32_t nret,
561 target_ulong rets)
562 {
563 SpaprPhbState *sphb;
564 uint64_t buid;
565 int state, ret;
566
567 if ((nargs != 3) || (nret != 4 && nret != 5)) {
568 goto param_error_exit;
569 }
570
571 buid = rtas_ldq(args, 1);
572 sphb = spapr_pci_find_phb(spapr, buid);
573 if (!sphb) {
574 goto param_error_exit;
575 }
576
577 if (!spapr_phb_eeh_available(sphb)) {
578 goto param_error_exit;
579 }
580
581 ret = spapr_phb_vfio_eeh_get_state(sphb, &state);
582 rtas_st(rets, 0, ret);
583 if (ret != RTAS_OUT_SUCCESS) {
584 return;
585 }
586
587 rtas_st(rets, 1, state);
588 rtas_st(rets, 2, RTAS_EEH_SUPPORT);
589 rtas_st(rets, 3, RTAS_EEH_PE_UNAVAIL_INFO);
590 if (nret >= 5) {
591 rtas_st(rets, 4, RTAS_EEH_PE_RECOVER_INFO);
592 }
593 return;
594
595 param_error_exit:
596 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
597 }
598
599 static void rtas_ibm_set_slot_reset(PowerPCCPU *cpu,
600 SpaprMachineState *spapr,
601 uint32_t token, uint32_t nargs,
602 target_ulong args, uint32_t nret,
603 target_ulong rets)
604 {
605 SpaprPhbState *sphb;
606 uint32_t option;
607 uint64_t buid;
608 int ret;
609
610 if ((nargs != 4) || (nret != 1)) {
611 goto param_error_exit;
612 }
613
614 buid = rtas_ldq(args, 1);
615 option = rtas_ld(args, 3);
616 sphb = spapr_pci_find_phb(spapr, buid);
617 if (!sphb) {
618 goto param_error_exit;
619 }
620
621 if (!spapr_phb_eeh_available(sphb)) {
622 goto param_error_exit;
623 }
624
625 ret = spapr_phb_vfio_eeh_reset(sphb, option);
626 rtas_st(rets, 0, ret);
627 return;
628
629 param_error_exit:
630 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
631 }
632
633 static void rtas_ibm_configure_pe(PowerPCCPU *cpu,
634 SpaprMachineState *spapr,
635 uint32_t token, uint32_t nargs,
636 target_ulong args, uint32_t nret,
637 target_ulong rets)
638 {
639 SpaprPhbState *sphb;
640 uint64_t buid;
641 int ret;
642
643 if ((nargs != 3) || (nret != 1)) {
644 goto param_error_exit;
645 }
646
647 buid = rtas_ldq(args, 1);
648 sphb = spapr_pci_find_phb(spapr, buid);
649 if (!sphb) {
650 goto param_error_exit;
651 }
652
653 if (!spapr_phb_eeh_available(sphb)) {
654 goto param_error_exit;
655 }
656
657 ret = spapr_phb_vfio_eeh_configure(sphb);
658 rtas_st(rets, 0, ret);
659 return;
660
661 param_error_exit:
662 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
663 }
664
665 /* To support it later */
666 static void rtas_ibm_slot_error_detail(PowerPCCPU *cpu,
667 SpaprMachineState *spapr,
668 uint32_t token, uint32_t nargs,
669 target_ulong args, uint32_t nret,
670 target_ulong rets)
671 {
672 SpaprPhbState *sphb;
673 int option;
674 uint64_t buid;
675
676 if ((nargs != 8) || (nret != 1)) {
677 goto param_error_exit;
678 }
679
680 buid = rtas_ldq(args, 1);
681 sphb = spapr_pci_find_phb(spapr, buid);
682 if (!sphb) {
683 goto param_error_exit;
684 }
685
686 if (!spapr_phb_eeh_available(sphb)) {
687 goto param_error_exit;
688 }
689
690 option = rtas_ld(args, 7);
691 switch (option) {
692 case RTAS_SLOT_TEMP_ERR_LOG:
693 case RTAS_SLOT_PERM_ERR_LOG:
694 break;
695 default:
696 goto param_error_exit;
697 }
698
699 /* We don't have error log yet */
700 rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND);
701 return;
702
703 param_error_exit:
704 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
705 }
706
707 static void pci_spapr_set_irq(void *opaque, int irq_num, int level)
708 {
709 /*
710 * Here we use the number returned by pci_swizzle_map_irq_fn to find a
711 * corresponding qemu_irq.
712 */
713 SpaprPhbState *phb = opaque;
714 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
715
716 trace_spapr_pci_lsi_set(phb->dtbusname, irq_num, phb->lsi_table[irq_num].irq);
717 qemu_set_irq(spapr_qirq(spapr, phb->lsi_table[irq_num].irq), level);
718 }
719
720 static PCIINTxRoute spapr_route_intx_pin_to_irq(void *opaque, int pin)
721 {
722 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(opaque);
723 PCIINTxRoute route;
724
725 route.mode = PCI_INTX_ENABLED;
726 route.irq = sphb->lsi_table[pin].irq;
727
728 return route;
729 }
730
731 static uint64_t spapr_msi_read(void *opaque, hwaddr addr, unsigned size)
732 {
733 qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid access\n", __func__);
734 return 0;
735 }
736
737 /*
738 * MSI/MSIX memory region implementation.
739 * The handler handles both MSI and MSIX.
740 * The vector number is encoded in least bits in data.
741 */
742 static void spapr_msi_write(void *opaque, hwaddr addr,
743 uint64_t data, unsigned size)
744 {
745 SpaprMachineState *spapr = opaque;
746 uint32_t irq = data;
747
748 trace_spapr_pci_msi_write(addr, data, irq);
749
750 qemu_irq_pulse(spapr_qirq(spapr, irq));
751 }
752
753 static const MemoryRegionOps spapr_msi_ops = {
754 /*
755 * .read result is undefined by PCI spec.
756 * define .read method to avoid assert failure in memory_region_init_io
757 */
758 .read = spapr_msi_read,
759 .write = spapr_msi_write,
760 .endianness = DEVICE_LITTLE_ENDIAN
761 };
762
763 /*
764 * PHB PCI device
765 */
766 static AddressSpace *spapr_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
767 {
768 SpaprPhbState *phb = opaque;
769
770 return &phb->iommu_as;
771 }
772
773 static const PCIIOMMUOps spapr_iommu_ops = {
774 .get_address_space = spapr_pci_dma_iommu,
775 };
776
777 static char *spapr_phb_vfio_get_loc_code(SpaprPhbState *sphb, PCIDevice *pdev)
778 {
779 g_autofree char *path = NULL;
780 g_autofree char *host = NULL;
781 g_autofree char *devspec = NULL;
782 char *buf = NULL;
783
784 /* Get the PCI VFIO host id */
785 host = object_property_get_str(OBJECT(pdev), "host", NULL);
786 if (!host) {
787 return NULL;
788 }
789
790 /* Construct the path of the file that will give us the DT location */
791 path = g_strdup_printf("/sys/bus/pci/devices/%s/devspec", host);
792 if (!g_file_get_contents(path, &devspec, NULL, NULL)) {
793 return NULL;
794 }
795
796 /* Construct and read from host device tree the loc-code */
797 g_free(path);
798 path = g_strdup_printf("/proc/device-tree%s/ibm,loc-code", devspec);
799 if (!g_file_get_contents(path, &buf, NULL, NULL)) {
800 return NULL;
801 }
802 return buf;
803 }
804
805 static char *spapr_phb_get_loc_code(SpaprPhbState *sphb, PCIDevice *pdev)
806 {
807 char *buf;
808 const char *devtype = "qemu";
809 uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev))));
810
811 if (object_dynamic_cast(OBJECT(pdev), "vfio-pci")) {
812 buf = spapr_phb_vfio_get_loc_code(sphb, pdev);
813 if (buf) {
814 return buf;
815 }
816 devtype = "vfio";
817 }
818 /*
819 * For emulated devices and VFIO-failure case, make up
820 * the loc-code.
821 */
822 buf = g_strdup_printf("%s_%s:%04x:%02x:%02x.%x",
823 devtype, pdev->name, sphb->index, busnr,
824 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
825 return buf;
826 }
827
828 /* Macros to operate with address in OF binding to PCI */
829 #define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p))
830 #define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */
831 #define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */
832 #define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */
833 #define b_ss(x) b_x((x), 24, 2) /* the space code */
834 #define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */
835 #define b_ddddd(x) b_x((x), 11, 5) /* device number */
836 #define b_fff(x) b_x((x), 8, 3) /* function number */
837 #define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */
838
839 /* for 'reg' OF properties */
840 #define RESOURCE_CELLS_SIZE 2
841 #define RESOURCE_CELLS_ADDRESS 3
842
843 typedef struct ResourceFields {
844 uint32_t phys_hi;
845 uint32_t phys_mid;
846 uint32_t phys_lo;
847 uint32_t size_hi;
848 uint32_t size_lo;
849 } QEMU_PACKED ResourceFields;
850
851 typedef struct ResourceProps {
852 ResourceFields reg[8];
853 uint32_t reg_len;
854 } ResourceProps;
855
856 /* fill in the 'reg' OF properties for
857 * a PCI device. 'reg' describes resource requirements for a
858 * device's IO/MEM regions.
859 *
860 * the property is an array of ('phys-addr', 'size') pairs describing
861 * the addressable regions of the PCI device, where 'phys-addr' is a
862 * RESOURCE_CELLS_ADDRESS-tuple of 32-bit integers corresponding to
863 * (phys.hi, phys.mid, phys.lo), and 'size' is a
864 * RESOURCE_CELLS_SIZE-tuple corresponding to (size.hi, size.lo).
865 *
866 * phys.hi = 0xYYXXXXZZ, where:
867 * 0xYY = npt000ss
868 * ||| |
869 * ||| +-- space code
870 * ||| |
871 * ||| + 00 if configuration space
872 * ||| + 01 if IO region,
873 * ||| + 10 if 32-bit MEM region
874 * ||| + 11 if 64-bit MEM region
875 * |||
876 * ||+------ for non-relocatable IO: 1 if aliased
877 * || for relocatable IO: 1 if below 64KB
878 * || for MEM: 1 if below 1MB
879 * |+------- 1 if region is prefetchable
880 * +-------- 1 if region is non-relocatable
881 * 0xXXXX = bbbbbbbb dddddfff, encoding bus, slot, and function
882 * bits respectively
883 * 0xZZ = rrrrrrrr, the register number of the BAR corresponding
884 * to the region
885 *
886 * phys.mid and phys.lo correspond respectively to the hi/lo portions
887 * of the actual address of the region.
888 *
889 * note also that addresses defined in this property are, at least
890 * for PAPR guests, relative to the PHBs IO/MEM windows, and
891 * correspond directly to the addresses in the BARs.
892 *
893 * in accordance with PCI Bus Binding to Open Firmware,
894 * IEEE Std 1275-1994, section 4.1.1, as implemented by PAPR+ v2.7,
895 * Appendix C.
896 */
897 static void populate_resource_props(PCIDevice *d, ResourceProps *rp)
898 {
899 int bus_num = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(d))));
900 uint32_t dev_id = (b_bbbbbbbb(bus_num) |
901 b_ddddd(PCI_SLOT(d->devfn)) |
902 b_fff(PCI_FUNC(d->devfn)));
903 ResourceFields *reg;
904 int i, reg_idx = 0;
905
906 /* config space region */
907 reg = &rp->reg[reg_idx++];
908 reg->phys_hi = cpu_to_be32(dev_id);
909 reg->phys_mid = 0;
910 reg->phys_lo = 0;
911 reg->size_hi = 0;
912 reg->size_lo = 0;
913
914 for (i = 0; i < PCI_NUM_REGIONS; i++) {
915 if (!d->io_regions[i].size) {
916 continue;
917 }
918
919 reg = &rp->reg[reg_idx++];
920
921 reg->phys_hi = cpu_to_be32(dev_id | b_rrrrrrrr(pci_bar(d, i)));
922 if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) {
923 reg->phys_hi |= cpu_to_be32(b_ss(1));
924 } else if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
925 reg->phys_hi |= cpu_to_be32(b_ss(3));
926 } else {
927 reg->phys_hi |= cpu_to_be32(b_ss(2));
928 }
929 reg->phys_mid = 0;
930 reg->phys_lo = 0;
931 reg->size_hi = cpu_to_be32(d->io_regions[i].size >> 32);
932 reg->size_lo = cpu_to_be32(d->io_regions[i].size);
933 }
934
935 rp->reg_len = reg_idx * sizeof(ResourceFields);
936 }
937
938 typedef struct PCIClass PCIClass;
939 typedef struct PCISubClass PCISubClass;
940 typedef struct PCIIFace PCIIFace;
941
942 struct PCIIFace {
943 int iface;
944 const char *name;
945 };
946
947 struct PCISubClass {
948 int subclass;
949 const char *name;
950 const PCIIFace *iface;
951 };
952
953 struct PCIClass {
954 const char *name;
955 const PCISubClass *subc;
956 };
957
958 static const PCISubClass undef_subclass[] = {
959 { PCI_CLASS_NOT_DEFINED_VGA, "display", NULL },
960 { 0xFF, NULL, NULL },
961 };
962
963 static const PCISubClass mass_subclass[] = {
964 { PCI_CLASS_STORAGE_SCSI, "scsi", NULL },
965 { PCI_CLASS_STORAGE_IDE, "ide", NULL },
966 { PCI_CLASS_STORAGE_FLOPPY, "fdc", NULL },
967 { PCI_CLASS_STORAGE_IPI, "ipi", NULL },
968 { PCI_CLASS_STORAGE_RAID, "raid", NULL },
969 { PCI_CLASS_STORAGE_ATA, "ata", NULL },
970 { PCI_CLASS_STORAGE_SATA, "sata", NULL },
971 { PCI_CLASS_STORAGE_SAS, "sas", NULL },
972 { 0xFF, NULL, NULL },
973 };
974
975 static const PCISubClass net_subclass[] = {
976 { PCI_CLASS_NETWORK_ETHERNET, "ethernet", NULL },
977 { PCI_CLASS_NETWORK_TOKEN_RING, "token-ring", NULL },
978 { PCI_CLASS_NETWORK_FDDI, "fddi", NULL },
979 { PCI_CLASS_NETWORK_ATM, "atm", NULL },
980 { PCI_CLASS_NETWORK_ISDN, "isdn", NULL },
981 { PCI_CLASS_NETWORK_WORLDFIP, "worldfip", NULL },
982 { PCI_CLASS_NETWORK_PICMG214, "picmg", NULL },
983 { 0xFF, NULL, NULL },
984 };
985
986 static const PCISubClass displ_subclass[] = {
987 { PCI_CLASS_DISPLAY_VGA, "vga", NULL },
988 { PCI_CLASS_DISPLAY_XGA, "xga", NULL },
989 { PCI_CLASS_DISPLAY_3D, "3d-controller", NULL },
990 { 0xFF, NULL, NULL },
991 };
992
993 static const PCISubClass media_subclass[] = {
994 { PCI_CLASS_MULTIMEDIA_VIDEO, "video", NULL },
995 { PCI_CLASS_MULTIMEDIA_AUDIO, "sound", NULL },
996 { PCI_CLASS_MULTIMEDIA_PHONE, "telephony", NULL },
997 { 0xFF, NULL, NULL },
998 };
999
1000 static const PCISubClass mem_subclass[] = {
1001 { PCI_CLASS_MEMORY_RAM, "memory", NULL },
1002 { PCI_CLASS_MEMORY_FLASH, "flash", NULL },
1003 { 0xFF, NULL, NULL },
1004 };
1005
1006 static const PCISubClass bridg_subclass[] = {
1007 { PCI_CLASS_BRIDGE_HOST, "host", NULL },
1008 { PCI_CLASS_BRIDGE_ISA, "isa", NULL },
1009 { PCI_CLASS_BRIDGE_EISA, "eisa", NULL },
1010 { PCI_CLASS_BRIDGE_MC, "mca", NULL },
1011 { PCI_CLASS_BRIDGE_PCI, "pci", NULL },
1012 { PCI_CLASS_BRIDGE_PCMCIA, "pcmcia", NULL },
1013 { PCI_CLASS_BRIDGE_NUBUS, "nubus", NULL },
1014 { PCI_CLASS_BRIDGE_CARDBUS, "cardbus", NULL },
1015 { PCI_CLASS_BRIDGE_RACEWAY, "raceway", NULL },
1016 { PCI_CLASS_BRIDGE_PCI_SEMITP, "semi-transparent-pci", NULL },
1017 { PCI_CLASS_BRIDGE_IB_PCI, "infiniband", NULL },
1018 { 0xFF, NULL, NULL },
1019 };
1020
1021 static const PCISubClass comm_subclass[] = {
1022 { PCI_CLASS_COMMUNICATION_SERIAL, "serial", NULL },
1023 { PCI_CLASS_COMMUNICATION_PARALLEL, "parallel", NULL },
1024 { PCI_CLASS_COMMUNICATION_MULTISERIAL, "multiport-serial", NULL },
1025 { PCI_CLASS_COMMUNICATION_MODEM, "modem", NULL },
1026 { PCI_CLASS_COMMUNICATION_GPIB, "gpib", NULL },
1027 { PCI_CLASS_COMMUNICATION_SC, "smart-card", NULL },
1028 { 0xFF, NULL, NULL, },
1029 };
1030
1031 static const PCIIFace pic_iface[] = {
1032 { PCI_CLASS_SYSTEM_PIC_IOAPIC, "io-apic" },
1033 { PCI_CLASS_SYSTEM_PIC_IOXAPIC, "io-xapic" },
1034 { 0xFF, NULL },
1035 };
1036
1037 static const PCISubClass sys_subclass[] = {
1038 { PCI_CLASS_SYSTEM_PIC, "interrupt-controller", pic_iface },
1039 { PCI_CLASS_SYSTEM_DMA, "dma-controller", NULL },
1040 { PCI_CLASS_SYSTEM_TIMER, "timer", NULL },
1041 { PCI_CLASS_SYSTEM_RTC, "rtc", NULL },
1042 { PCI_CLASS_SYSTEM_PCI_HOTPLUG, "hot-plug-controller", NULL },
1043 { PCI_CLASS_SYSTEM_SDHCI, "sd-host-controller", NULL },
1044 { 0xFF, NULL, NULL },
1045 };
1046
1047 static const PCISubClass inp_subclass[] = {
1048 { PCI_CLASS_INPUT_KEYBOARD, "keyboard", NULL },
1049 { PCI_CLASS_INPUT_PEN, "pen", NULL },
1050 { PCI_CLASS_INPUT_MOUSE, "mouse", NULL },
1051 { PCI_CLASS_INPUT_SCANNER, "scanner", NULL },
1052 { PCI_CLASS_INPUT_GAMEPORT, "gameport", NULL },
1053 { 0xFF, NULL, NULL },
1054 };
1055
1056 static const PCISubClass dock_subclass[] = {
1057 { PCI_CLASS_DOCKING_GENERIC, "dock", NULL },
1058 { 0xFF, NULL, NULL },
1059 };
1060
1061 static const PCISubClass cpu_subclass[] = {
1062 { PCI_CLASS_PROCESSOR_PENTIUM, "pentium", NULL },
1063 { PCI_CLASS_PROCESSOR_POWERPC, "powerpc", NULL },
1064 { PCI_CLASS_PROCESSOR_MIPS, "mips", NULL },
1065 { PCI_CLASS_PROCESSOR_CO, "co-processor", NULL },
1066 { 0xFF, NULL, NULL },
1067 };
1068
1069 static const PCIIFace usb_iface[] = {
1070 { PCI_CLASS_SERIAL_USB_UHCI, "usb-uhci" },
1071 { PCI_CLASS_SERIAL_USB_OHCI, "usb-ohci", },
1072 { PCI_CLASS_SERIAL_USB_EHCI, "usb-ehci" },
1073 { PCI_CLASS_SERIAL_USB_XHCI, "usb-xhci" },
1074 { PCI_CLASS_SERIAL_USB_UNKNOWN, "usb-unknown" },
1075 { PCI_CLASS_SERIAL_USB_DEVICE, "usb-device" },
1076 { 0xFF, NULL },
1077 };
1078
1079 static const PCISubClass ser_subclass[] = {
1080 { PCI_CLASS_SERIAL_FIREWIRE, "firewire", NULL },
1081 { PCI_CLASS_SERIAL_ACCESS, "access-bus", NULL },
1082 { PCI_CLASS_SERIAL_SSA, "ssa", NULL },
1083 { PCI_CLASS_SERIAL_USB, "usb", usb_iface },
1084 { PCI_CLASS_SERIAL_FIBER, "fibre-channel", NULL },
1085 { PCI_CLASS_SERIAL_SMBUS, "smb", NULL },
1086 { PCI_CLASS_SERIAL_IB, "infiniband", NULL },
1087 { PCI_CLASS_SERIAL_IPMI, "ipmi", NULL },
1088 { PCI_CLASS_SERIAL_SERCOS, "sercos", NULL },
1089 { PCI_CLASS_SERIAL_CANBUS, "canbus", NULL },
1090 { 0xFF, NULL, NULL },
1091 };
1092
1093 static const PCISubClass wrl_subclass[] = {
1094 { PCI_CLASS_WIRELESS_IRDA, "irda", NULL },
1095 { PCI_CLASS_WIRELESS_CIR, "consumer-ir", NULL },
1096 { PCI_CLASS_WIRELESS_RF_CONTROLLER, "rf-controller", NULL },
1097 { PCI_CLASS_WIRELESS_BLUETOOTH, "bluetooth", NULL },
1098 { PCI_CLASS_WIRELESS_BROADBAND, "broadband", NULL },
1099 { 0xFF, NULL, NULL },
1100 };
1101
1102 static const PCISubClass sat_subclass[] = {
1103 { PCI_CLASS_SATELLITE_TV, "satellite-tv", NULL },
1104 { PCI_CLASS_SATELLITE_AUDIO, "satellite-audio", NULL },
1105 { PCI_CLASS_SATELLITE_VOICE, "satellite-voice", NULL },
1106 { PCI_CLASS_SATELLITE_DATA, "satellite-data", NULL },
1107 { 0xFF, NULL, NULL },
1108 };
1109
1110 static const PCISubClass crypt_subclass[] = {
1111 { PCI_CLASS_CRYPT_NETWORK, "network-encryption", NULL },
1112 { PCI_CLASS_CRYPT_ENTERTAINMENT,
1113 "entertainment-encryption", NULL },
1114 { 0xFF, NULL, NULL },
1115 };
1116
1117 static const PCISubClass spc_subclass[] = {
1118 { PCI_CLASS_SP_DPIO, "dpio", NULL },
1119 { PCI_CLASS_SP_PERF, "counter", NULL },
1120 { PCI_CLASS_SP_SYNCH, "measurement", NULL },
1121 { PCI_CLASS_SP_MANAGEMENT, "management-card", NULL },
1122 { 0xFF, NULL, NULL },
1123 };
1124
1125 static const PCIClass pci_classes[] = {
1126 { "legacy-device", undef_subclass },
1127 { "mass-storage", mass_subclass },
1128 { "network", net_subclass },
1129 { "display", displ_subclass, },
1130 { "multimedia-device", media_subclass },
1131 { "memory-controller", mem_subclass },
1132 { "unknown-bridge", bridg_subclass },
1133 { "communication-controller", comm_subclass},
1134 { "system-peripheral", sys_subclass },
1135 { "input-controller", inp_subclass },
1136 { "docking-station", dock_subclass },
1137 { "cpu", cpu_subclass },
1138 { "serial-bus", ser_subclass },
1139 { "wireless-controller", wrl_subclass },
1140 { "intelligent-io", NULL },
1141 { "satellite-device", sat_subclass },
1142 { "encryption", crypt_subclass },
1143 { "data-processing-controller", spc_subclass },
1144 };
1145
1146 static const char *dt_name_from_class(uint8_t class, uint8_t subclass,
1147 uint8_t iface)
1148 {
1149 const PCIClass *pclass;
1150 const PCISubClass *psubclass;
1151 const PCIIFace *piface;
1152 const char *name;
1153
1154 if (class >= ARRAY_SIZE(pci_classes)) {
1155 return "pci";
1156 }
1157
1158 pclass = pci_classes + class;
1159 name = pclass->name;
1160
1161 if (pclass->subc == NULL) {
1162 return name;
1163 }
1164
1165 psubclass = pclass->subc;
1166 while ((psubclass->subclass & 0xff) != 0xff) {
1167 if ((psubclass->subclass & 0xff) == subclass) {
1168 name = psubclass->name;
1169 break;
1170 }
1171 psubclass++;
1172 }
1173
1174 piface = psubclass->iface;
1175 if (piface == NULL) {
1176 return name;
1177 }
1178 while ((piface->iface & 0xff) != 0xff) {
1179 if ((piface->iface & 0xff) == iface) {
1180 name = piface->name;
1181 break;
1182 }
1183 piface++;
1184 }
1185
1186 return name;
1187 }
1188
1189 /*
1190 * DRC helper functions
1191 */
1192
1193 static uint32_t drc_id_from_devfn(SpaprPhbState *phb,
1194 uint8_t chassis, int32_t devfn)
1195 {
1196 return (phb->index << 16) | (chassis << 8) | devfn;
1197 }
1198
1199 static SpaprDrc *drc_from_devfn(SpaprPhbState *phb,
1200 uint8_t chassis, int32_t devfn)
1201 {
1202 return spapr_drc_by_id(TYPE_SPAPR_DRC_PCI,
1203 drc_id_from_devfn(phb, chassis, devfn));
1204 }
1205
1206 static uint8_t chassis_from_bus(PCIBus *bus)
1207 {
1208 if (pci_bus_is_root(bus)) {
1209 return 0;
1210 } else {
1211 PCIDevice *bridge = pci_bridge_get_device(bus);
1212
1213 return object_property_get_uint(OBJECT(bridge), "chassis_nr",
1214 &error_abort);
1215 }
1216 }
1217
1218 static SpaprDrc *drc_from_dev(SpaprPhbState *phb, PCIDevice *dev)
1219 {
1220 uint8_t chassis = chassis_from_bus(pci_get_bus(dev));
1221
1222 return drc_from_devfn(phb, chassis, dev->devfn);
1223 }
1224
1225 static void add_drcs(SpaprPhbState *phb, PCIBus *bus)
1226 {
1227 Object *owner;
1228 int i;
1229 uint8_t chassis;
1230
1231 chassis = chassis_from_bus(bus);
1232
1233 if (pci_bus_is_root(bus)) {
1234 owner = OBJECT(phb);
1235 } else {
1236 owner = OBJECT(pci_bridge_get_device(bus));
1237 }
1238
1239 for (i = 0; i < PCI_SLOT_MAX * PCI_FUNC_MAX; i++) {
1240 spapr_dr_connector_new(owner, TYPE_SPAPR_DRC_PCI,
1241 drc_id_from_devfn(phb, chassis, i));
1242 }
1243 }
1244
1245 static void remove_drcs(SpaprPhbState *phb, PCIBus *bus)
1246 {
1247 int i;
1248 uint8_t chassis;
1249
1250 chassis = chassis_from_bus(bus);
1251
1252 for (i = PCI_SLOT_MAX * PCI_FUNC_MAX - 1; i >= 0; i--) {
1253 SpaprDrc *drc = drc_from_devfn(phb, chassis, i);
1254
1255 if (drc) {
1256 object_unparent(OBJECT(drc));
1257 }
1258 }
1259 }
1260
1261 typedef struct PciWalkFdt {
1262 void *fdt;
1263 int offset;
1264 SpaprPhbState *sphb;
1265 int err;
1266 } PciWalkFdt;
1267
1268 static int spapr_dt_pci_device(SpaprPhbState *sphb, PCIDevice *dev,
1269 void *fdt, int parent_offset);
1270
1271 static void spapr_dt_pci_device_cb(PCIBus *bus, PCIDevice *pdev,
1272 void *opaque)
1273 {
1274 PciWalkFdt *p = opaque;
1275 int err;
1276
1277 if (p->err || !pdev->enabled) {
1278 return;
1279 }
1280
1281 err = spapr_dt_pci_device(p->sphb, pdev, p->fdt, p->offset);
1282 if (err < 0) {
1283 p->err = err;
1284 }
1285 }
1286
1287 /* Augment PCI device node with bridge specific information */
1288 static int spapr_dt_pci_bus(SpaprPhbState *sphb, PCIBus *bus,
1289 void *fdt, int offset)
1290 {
1291 Object *owner;
1292 PciWalkFdt cbinfo = {
1293 .fdt = fdt,
1294 .offset = offset,
1295 .sphb = sphb,
1296 .err = 0,
1297 };
1298 int ret;
1299
1300 _FDT(fdt_setprop_cell(fdt, offset, "#address-cells",
1301 RESOURCE_CELLS_ADDRESS));
1302 _FDT(fdt_setprop_cell(fdt, offset, "#size-cells",
1303 RESOURCE_CELLS_SIZE));
1304
1305 assert(bus);
1306 pci_for_each_device_under_bus_reverse(bus, spapr_dt_pci_device_cb, &cbinfo);
1307 if (cbinfo.err) {
1308 return cbinfo.err;
1309 }
1310
1311 if (pci_bus_is_root(bus)) {
1312 owner = OBJECT(sphb);
1313 } else {
1314 owner = OBJECT(pci_bridge_get_device(bus));
1315 }
1316
1317 ret = spapr_dt_drc(fdt, offset, owner,
1318 SPAPR_DR_CONNECTOR_TYPE_PCI);
1319 if (ret) {
1320 return ret;
1321 }
1322
1323 return offset;
1324 }
1325
1326 char *spapr_pci_fw_dev_name(PCIDevice *dev)
1327 {
1328 const gchar *basename;
1329 int slot = PCI_SLOT(dev->devfn);
1330 int func = PCI_FUNC(dev->devfn);
1331 uint32_t ccode = pci_default_read_config(dev, PCI_CLASS_PROG, 3);
1332
1333 basename = dt_name_from_class((ccode >> 16) & 0xff, (ccode >> 8) & 0xff,
1334 ccode & 0xff);
1335
1336 if (func != 0) {
1337 return g_strdup_printf("%s@%x,%x", basename, slot, func);
1338 } else {
1339 return g_strdup_printf("%s@%x", basename, slot);
1340 }
1341 }
1342
1343 /* create OF node for pci device and required OF DT properties */
1344 static int spapr_dt_pci_device(SpaprPhbState *sphb, PCIDevice *dev,
1345 void *fdt, int parent_offset)
1346 {
1347 int offset;
1348 g_autofree gchar *nodename = spapr_pci_fw_dev_name(dev);
1349 ResourceProps rp;
1350 SpaprDrc *drc = drc_from_dev(sphb, dev);
1351 uint32_t vendor_id = pci_default_read_config(dev, PCI_VENDOR_ID, 2);
1352 uint32_t device_id = pci_default_read_config(dev, PCI_DEVICE_ID, 2);
1353 uint32_t revision_id = pci_default_read_config(dev, PCI_REVISION_ID, 1);
1354 uint32_t ccode = pci_default_read_config(dev, PCI_CLASS_PROG, 3);
1355 uint32_t irq_pin = pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1);
1356 uint32_t subsystem_id = pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2);
1357 uint32_t subsystem_vendor_id =
1358 pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2);
1359 uint32_t cache_line_size =
1360 pci_default_read_config(dev, PCI_CACHE_LINE_SIZE, 1);
1361 uint32_t pci_status = pci_default_read_config(dev, PCI_STATUS, 2);
1362 gchar *loc_code;
1363
1364 _FDT(offset = fdt_add_subnode(fdt, parent_offset, nodename));
1365
1366 /* in accordance with PAPR+ v2.7 13.6.3, Table 181 */
1367 _FDT(fdt_setprop_cell(fdt, offset, "vendor-id", vendor_id));
1368 _FDT(fdt_setprop_cell(fdt, offset, "device-id", device_id));
1369 _FDT(fdt_setprop_cell(fdt, offset, "revision-id", revision_id));
1370
1371 _FDT(fdt_setprop_cell(fdt, offset, "class-code", ccode));
1372 if (irq_pin) {
1373 _FDT(fdt_setprop_cell(fdt, offset, "interrupts", irq_pin));
1374 }
1375
1376 if (subsystem_id) {
1377 _FDT(fdt_setprop_cell(fdt, offset, "subsystem-id", subsystem_id));
1378 }
1379
1380 if (subsystem_vendor_id) {
1381 _FDT(fdt_setprop_cell(fdt, offset, "subsystem-vendor-id",
1382 subsystem_vendor_id));
1383 }
1384
1385 _FDT(fdt_setprop_cell(fdt, offset, "cache-line-size", cache_line_size));
1386
1387
1388 /* the following fdt cells are masked off the pci status register */
1389 _FDT(fdt_setprop_cell(fdt, offset, "devsel-speed",
1390 PCI_STATUS_DEVSEL_MASK & pci_status));
1391
1392 if (pci_status & PCI_STATUS_FAST_BACK) {
1393 _FDT(fdt_setprop(fdt, offset, "fast-back-to-back", NULL, 0));
1394 }
1395 if (pci_status & PCI_STATUS_66MHZ) {
1396 _FDT(fdt_setprop(fdt, offset, "66mhz-capable", NULL, 0));
1397 }
1398 if (pci_status & PCI_STATUS_UDF) {
1399 _FDT(fdt_setprop(fdt, offset, "udf-supported", NULL, 0));
1400 }
1401
1402 loc_code = spapr_phb_get_loc_code(sphb, dev);
1403 _FDT(fdt_setprop_string(fdt, offset, "ibm,loc-code", loc_code));
1404 g_free(loc_code);
1405
1406 if (drc) {
1407 _FDT(fdt_setprop_cell(fdt, offset, "ibm,my-drc-index",
1408 spapr_drc_index(drc)));
1409 }
1410
1411 if (msi_present(dev)) {
1412 uint32_t max_msi = msi_nr_vectors_allocated(dev);
1413 if (max_msi) {
1414 _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi", max_msi));
1415 }
1416 }
1417 if (msix_present(dev)) {
1418 uint32_t max_msix = dev->msix_entries_nr;
1419 if (max_msix) {
1420 _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi-x", max_msix));
1421 }
1422 }
1423
1424 populate_resource_props(dev, &rp);
1425 _FDT(fdt_setprop(fdt, offset, "reg", (uint8_t *)rp.reg, rp.reg_len));
1426
1427 if (sphb->pcie_ecs && pci_is_express(dev)) {
1428 _FDT(fdt_setprop_cell(fdt, offset, "ibm,pci-config-space-type", 0x1));
1429 }
1430
1431 if (!IS_PCI_BRIDGE(dev)) {
1432 /* Properties only for non-bridges */
1433 uint32_t min_grant = pci_default_read_config(dev, PCI_MIN_GNT, 1);
1434 uint32_t max_latency = pci_default_read_config(dev, PCI_MAX_LAT, 1);
1435 _FDT(fdt_setprop_cell(fdt, offset, "min-grant", min_grant));
1436 _FDT(fdt_setprop_cell(fdt, offset, "max-latency", max_latency));
1437 return offset;
1438 } else {
1439 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev));
1440
1441 return spapr_dt_pci_bus(sphb, sec_bus, fdt, offset);
1442 }
1443 }
1444
1445 /* Callback to be called during DRC release. */
1446 void spapr_phb_remove_pci_device_cb(DeviceState *dev)
1447 {
1448 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev);
1449
1450 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
1451 object_unparent(OBJECT(dev));
1452 }
1453
1454 int spapr_pci_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
1455 void *fdt, int *fdt_start_offset, Error **errp)
1456 {
1457 HotplugHandler *plug_handler = qdev_get_hotplug_handler(drc->dev);
1458 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(plug_handler);
1459 PCIDevice *pdev = PCI_DEVICE(drc->dev);
1460
1461 *fdt_start_offset = spapr_dt_pci_device(sphb, pdev, fdt, 0);
1462 return 0;
1463 }
1464
1465 static void spapr_pci_bridge_plug(SpaprPhbState *phb,
1466 PCIBridge *bridge)
1467 {
1468 PCIBus *bus = pci_bridge_get_sec_bus(bridge);
1469
1470 add_drcs(phb, bus);
1471 }
1472
1473 /* Returns non-zero if the value of "chassis_nr" is already in use */
1474 static int check_chassis_nr(Object *obj, void *opaque)
1475 {
1476 int new_chassis_nr =
1477 object_property_get_uint(opaque, "chassis_nr", &error_abort);
1478 int chassis_nr =
1479 object_property_get_uint(obj, "chassis_nr", NULL);
1480
1481 if (!object_dynamic_cast(obj, TYPE_PCI_BRIDGE)) {
1482 return 0;
1483 }
1484
1485 /* Skip unsupported bridge types */
1486 if (!chassis_nr) {
1487 return 0;
1488 }
1489
1490 /* Skip self */
1491 if (obj == opaque) {
1492 return 0;
1493 }
1494
1495 return chassis_nr == new_chassis_nr;
1496 }
1497
1498 static bool bridge_has_valid_chassis_nr(Object *bridge, Error **errp)
1499 {
1500 int chassis_nr =
1501 object_property_get_uint(bridge, "chassis_nr", NULL);
1502
1503 /*
1504 * slotid_cap_init() already ensures that "chassis_nr" isn't null for
1505 * standard PCI bridges, so this really tells if "chassis_nr" is present
1506 * or not.
1507 */
1508 if (!chassis_nr) {
1509 error_setg(errp, "PCI Bridge lacks a \"chassis_nr\" property");
1510 error_append_hint(errp, "Try -device pci-bridge instead.\n");
1511 return false;
1512 }
1513
1514 /* We want unique values for "chassis_nr" */
1515 if (object_child_foreach_recursive(object_get_root(), check_chassis_nr,
1516 bridge)) {
1517 error_setg(errp, "Bridge chassis %d already in use", chassis_nr);
1518 return false;
1519 }
1520
1521 return true;
1522 }
1523
1524 static void spapr_pci_pre_plug(HotplugHandler *plug_handler,
1525 DeviceState *plugged_dev, Error **errp)
1526 {
1527 SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler));
1528 PCIDevice *pdev = PCI_DEVICE(plugged_dev);
1529 SpaprDrc *drc = drc_from_dev(phb, pdev);
1530 PCIBus *bus = PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)));
1531 uint32_t slotnr = PCI_SLOT(pdev->devfn);
1532
1533 if (IS_PCI_BRIDGE(plugged_dev)) {
1534 if (!bridge_has_valid_chassis_nr(OBJECT(plugged_dev), errp)) {
1535 return;
1536 }
1537 }
1538
1539 /* Following the QEMU convention used for PCIe multifunction
1540 * hotplug, we do not allow functions to be hotplugged to a
1541 * slot that already has function 0 present
1542 */
1543 if (plugged_dev->hotplugged &&
1544 !pci_is_vf(pdev) &&
1545 bus->devices[PCI_DEVFN(slotnr, 0)] &&
1546 PCI_FUNC(pdev->devfn) != 0) {
1547 error_setg(errp, "PCI: slot %d function 0 already occupied by %s,"
1548 " additional functions can no longer be exposed to guest.",
1549 slotnr, bus->devices[PCI_DEVFN(slotnr, 0)]->name);
1550 }
1551
1552 if (drc && drc->dev) {
1553 error_setg(errp, "PCI: slot %d already occupied by %s", slotnr,
1554 pci_get_function_0(PCI_DEVICE(drc->dev))->name);
1555 return;
1556 }
1557 }
1558
1559 static void spapr_pci_plug(HotplugHandler *plug_handler,
1560 DeviceState *plugged_dev, Error **errp)
1561 {
1562 SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler));
1563 PCIDevice *pdev = PCI_DEVICE(plugged_dev);
1564 SpaprDrc *drc = drc_from_dev(phb, pdev);
1565 uint32_t slotnr = PCI_SLOT(pdev->devfn);
1566
1567 /*
1568 * If DR or the PCI device is disabled we don't need to do anything
1569 * in the case of hotplug or coldplug callbacks.
1570 */
1571 if (!pdev->enabled) {
1572 return;
1573 }
1574
1575 g_assert(drc);
1576
1577 if (IS_PCI_BRIDGE(plugged_dev)) {
1578 spapr_pci_bridge_plug(phb, PCI_BRIDGE(plugged_dev));
1579 }
1580
1581 /* spapr_pci_pre_plug() already checked the DRC is attachable */
1582 spapr_drc_attach(drc, DEVICE(pdev));
1583
1584 /* If this is function 0, signal hotplug for all the device functions.
1585 * Otherwise defer sending the hotplug event.
1586 */
1587 if (!spapr_drc_hotplugged(plugged_dev)) {
1588 spapr_drc_reset(drc);
1589 } else if (PCI_FUNC(pdev->devfn) == 0) {
1590 int i;
1591 uint8_t chassis = chassis_from_bus(pci_get_bus(pdev));
1592
1593 for (i = 0; i < 8; i++) {
1594 SpaprDrc *func_drc;
1595 SpaprDrcClass *func_drck;
1596 SpaprDREntitySense state;
1597
1598 func_drc = drc_from_devfn(phb, chassis, PCI_DEVFN(slotnr, i));
1599 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc);
1600 state = func_drck->dr_entity_sense(func_drc);
1601
1602 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) {
1603 spapr_hotplug_req_add_by_index(func_drc);
1604 }
1605 }
1606 }
1607 }
1608
1609 static void spapr_pci_bridge_unplug(SpaprPhbState *phb,
1610 PCIBridge *bridge)
1611 {
1612 PCIBus *bus = pci_bridge_get_sec_bus(bridge);
1613
1614 remove_drcs(phb, bus);
1615 }
1616
1617 static void spapr_pci_unplug(HotplugHandler *plug_handler,
1618 DeviceState *plugged_dev, Error **errp)
1619 {
1620 SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler));
1621
1622 /* some version guests do not wait for completion of a device
1623 * cleanup (generally done asynchronously by the kernel) before
1624 * signaling to QEMU that the device is safe, but instead sleep
1625 * for some 'safe' period of time. unfortunately on a busy host
1626 * this sleep isn't guaranteed to be long enough, resulting in
1627 * bad things like IRQ lines being left asserted during final
1628 * device removal. to deal with this we call reset just prior
1629 * to finalizing the device, which will put the device back into
1630 * an 'idle' state, as the device cleanup code expects.
1631 */
1632 pci_device_reset(PCI_DEVICE(plugged_dev));
1633
1634 if (IS_PCI_BRIDGE(plugged_dev)) {
1635 spapr_pci_bridge_unplug(phb, PCI_BRIDGE(plugged_dev));
1636 return;
1637 }
1638
1639 qdev_unrealize(plugged_dev);
1640 }
1641
1642 static void spapr_pci_unplug_request(HotplugHandler *plug_handler,
1643 DeviceState *plugged_dev, Error **errp)
1644 {
1645 SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler));
1646 PCIDevice *pdev = PCI_DEVICE(plugged_dev);
1647 SpaprDrc *drc = drc_from_dev(phb, pdev);
1648
1649 g_assert(drc);
1650
1651 if (!drc->dev) {
1652 return;
1653 }
1654
1655 g_assert(drc->dev == plugged_dev);
1656
1657 if (!spapr_drc_unplug_requested(drc)) {
1658 uint32_t slotnr = PCI_SLOT(pdev->devfn);
1659 SpaprDrc *func_drc;
1660 SpaprDrcClass *func_drck;
1661 SpaprDREntitySense state;
1662 int i;
1663 uint8_t chassis = chassis_from_bus(pci_get_bus(pdev));
1664
1665 if (IS_PCI_BRIDGE(plugged_dev)) {
1666 error_setg(errp, "PCI: Hot unplug of PCI bridges not supported");
1667 return;
1668 }
1669 if (object_property_get_uint(OBJECT(pdev), "nvlink2-tgt", NULL)) {
1670 error_setg(errp, "PCI: Cannot unplug NVLink2 devices");
1671 return;
1672 }
1673
1674 /* ensure any other present functions are pending unplug */
1675 if (PCI_FUNC(pdev->devfn) == 0) {
1676 for (i = 1; i < 8; i++) {
1677 func_drc = drc_from_devfn(phb, chassis, PCI_DEVFN(slotnr, i));
1678 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc);
1679 state = func_drck->dr_entity_sense(func_drc);
1680 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT
1681 && !spapr_drc_unplug_requested(func_drc)) {
1682 /*
1683 * Attempting to remove function 0 of a multifunction
1684 * device will will cascade into removing all child
1685 * functions, even if their unplug weren't requested
1686 * beforehand.
1687 */
1688 spapr_drc_unplug_request(func_drc);
1689 }
1690 }
1691 }
1692
1693 spapr_drc_unplug_request(drc);
1694
1695 /* if this isn't func 0, defer unplug event. otherwise signal removal
1696 * for all present functions
1697 */
1698 if (PCI_FUNC(pdev->devfn) == 0) {
1699 for (i = 7; i >= 0; i--) {
1700 func_drc = drc_from_devfn(phb, chassis, PCI_DEVFN(slotnr, i));
1701 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc);
1702 state = func_drck->dr_entity_sense(func_drc);
1703 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) {
1704 spapr_hotplug_req_remove_by_index(func_drc);
1705 }
1706 }
1707 }
1708 } else {
1709 error_setg(errp,
1710 "PCI device unplug already in progress for device %s",
1711 drc->dev->id);
1712 }
1713 }
1714
1715 static void spapr_phb_finalizefn(Object *obj)
1716 {
1717 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(obj);
1718
1719 g_free(sphb->dtbusname);
1720 sphb->dtbusname = NULL;
1721 }
1722
1723 static void spapr_phb_unrealize(DeviceState *dev)
1724 {
1725 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
1726 SysBusDevice *s = SYS_BUS_DEVICE(dev);
1727 PCIHostState *phb = PCI_HOST_BRIDGE(s);
1728 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(phb);
1729 SpaprTceTable *tcet;
1730 int i;
1731 const unsigned windows_supported = spapr_phb_windows_supported(sphb);
1732
1733 if (sphb->msi) {
1734 g_hash_table_unref(sphb->msi);
1735 sphb->msi = NULL;
1736 }
1737
1738 /*
1739 * Remove IO/MMIO subregions and aliases, rest should get cleaned
1740 * via PHB's unrealize->object_finalize
1741 */
1742 for (i = windows_supported - 1; i >= 0; i--) {
1743 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[i]);
1744 if (tcet) {
1745 memory_region_del_subregion(&sphb->iommu_root,
1746 spapr_tce_get_iommu(tcet));
1747 }
1748 }
1749
1750 remove_drcs(sphb, phb->bus);
1751
1752 for (i = PCI_NUM_PINS - 1; i >= 0; i--) {
1753 if (sphb->lsi_table[i].irq) {
1754 spapr_irq_free(spapr, sphb->lsi_table[i].irq, 1);
1755 sphb->lsi_table[i].irq = 0;
1756 }
1757 }
1758
1759 QLIST_REMOVE(sphb, list);
1760
1761 memory_region_del_subregion(&sphb->iommu_root, &sphb->msiwindow);
1762
1763 /*
1764 * An attached PCI device may have memory listeners, eg. VFIO PCI. We have
1765 * unmapped all sections. Remove the listeners now, before destroying the
1766 * address space.
1767 */
1768 address_space_remove_listeners(&sphb->iommu_as);
1769 address_space_destroy(&sphb->iommu_as);
1770
1771 qbus_set_hotplug_handler(BUS(phb->bus), NULL);
1772 pci_unregister_root_bus(phb->bus);
1773
1774 memory_region_del_subregion(get_system_memory(), &sphb->iowindow);
1775 if (sphb->mem64_win_pciaddr != (hwaddr)-1) {
1776 memory_region_del_subregion(get_system_memory(), &sphb->mem64window);
1777 }
1778 memory_region_del_subregion(get_system_memory(), &sphb->mem32window);
1779 }
1780
1781 static void spapr_phb_destroy_msi(gpointer opaque)
1782 {
1783 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
1784 SpaprPciMsi *msi = opaque;
1785
1786 spapr_irq_msi_free(spapr, msi->first_irq, msi->num);
1787 spapr_irq_free(spapr, msi->first_irq, msi->num);
1788 g_free(msi);
1789 }
1790
1791 static void spapr_phb_realize(DeviceState *dev, Error **errp)
1792 {
1793 ERRP_GUARD();
1794 /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user
1795 * tries to add a sPAPR PHB to a non-pseries machine.
1796 */
1797 SpaprMachineState *spapr =
1798 (SpaprMachineState *) object_dynamic_cast(qdev_get_machine(),
1799 TYPE_SPAPR_MACHINE);
1800 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1801 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(sbd);
1802 PCIHostState *phb = PCI_HOST_BRIDGE(sbd);
1803 MachineState *ms = MACHINE(spapr);
1804 char *namebuf;
1805 int i;
1806 PCIBus *bus;
1807 uint64_t msi_window_size = 4096;
1808 SpaprTceTable *tcet;
1809 const unsigned windows_supported = spapr_phb_windows_supported(sphb);
1810
1811 if (!spapr) {
1812 error_setg(errp, TYPE_SPAPR_PCI_HOST_BRIDGE " needs a pseries machine");
1813 return;
1814 }
1815
1816 assert(sphb->index != (uint32_t)-1); /* checked in spapr_phb_pre_plug() */
1817
1818 if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) {
1819 error_setg(errp, "32-bit memory window of size 0x%"HWADDR_PRIx
1820 " (max 2 GiB)", sphb->mem_win_size);
1821 return;
1822 }
1823
1824 /* 64-bit window defaults to identity mapping */
1825 sphb->mem64_win_pciaddr = sphb->mem64_win_addr;
1826
1827 if (spapr_pci_find_phb(spapr, sphb->buid)) {
1828 SpaprPhbState *s;
1829
1830 error_setg(errp, "PCI host bridges must have unique indexes");
1831 error_append_hint(errp, "The following indexes are already in use:");
1832 QLIST_FOREACH(s, &spapr->phbs, list) {
1833 error_append_hint(errp, " %d", s->index);
1834 }
1835 error_append_hint(errp, "\nTry another value for the index property\n");
1836 return;
1837 }
1838
1839 if (sphb->numa_node != -1 &&
1840 (sphb->numa_node >= MAX_NODES ||
1841 !ms->numa_state->nodes[sphb->numa_node].present)) {
1842 error_setg(errp, "Invalid NUMA node ID for PCI host bridge");
1843 return;
1844 }
1845
1846 sphb->dtbusname = g_strdup_printf("pci@%" PRIx64, sphb->buid);
1847
1848 /* Initialize memory regions */
1849 namebuf = g_strdup_printf("%s.mmio", sphb->dtbusname);
1850 memory_region_init(&sphb->memspace, OBJECT(sphb), namebuf, UINT64_MAX);
1851 g_free(namebuf);
1852
1853 namebuf = g_strdup_printf("%s.mmio32-alias", sphb->dtbusname);
1854 memory_region_init_alias(&sphb->mem32window, OBJECT(sphb),
1855 namebuf, &sphb->memspace,
1856 SPAPR_PCI_MEM_WIN_BUS_OFFSET, sphb->mem_win_size);
1857 g_free(namebuf);
1858 memory_region_add_subregion(get_system_memory(), sphb->mem_win_addr,
1859 &sphb->mem32window);
1860
1861 if (sphb->mem64_win_size != 0) {
1862 namebuf = g_strdup_printf("%s.mmio64-alias", sphb->dtbusname);
1863 memory_region_init_alias(&sphb->mem64window, OBJECT(sphb),
1864 namebuf, &sphb->memspace,
1865 sphb->mem64_win_pciaddr, sphb->mem64_win_size);
1866 g_free(namebuf);
1867
1868 memory_region_add_subregion(get_system_memory(),
1869 sphb->mem64_win_addr,
1870 &sphb->mem64window);
1871 }
1872
1873 /* Initialize IO regions */
1874 namebuf = g_strdup_printf("%s.io", sphb->dtbusname);
1875 memory_region_init(&sphb->iospace, OBJECT(sphb),
1876 namebuf, SPAPR_PCI_IO_WIN_SIZE);
1877 g_free(namebuf);
1878
1879 namebuf = g_strdup_printf("%s.io-alias", sphb->dtbusname);
1880 memory_region_init_alias(&sphb->iowindow, OBJECT(sphb), namebuf,
1881 &sphb->iospace, 0, SPAPR_PCI_IO_WIN_SIZE);
1882 g_free(namebuf);
1883 memory_region_add_subregion(get_system_memory(), sphb->io_win_addr,
1884 &sphb->iowindow);
1885
1886 bus = pci_register_root_bus(dev, NULL,
1887 pci_spapr_set_irq, pci_swizzle_map_irq_fn, sphb,
1888 &sphb->memspace, &sphb->iospace,
1889 PCI_DEVFN(0, 0), PCI_NUM_PINS,
1890 TYPE_PCI_BUS);
1891
1892 /*
1893 * Despite resembling a vanilla PCI bus in most ways, the PAPR
1894 * para-virtualized PCI bus *does* permit PCI-E extended config
1895 * space access
1896 */
1897 if (sphb->pcie_ecs) {
1898 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE;
1899 }
1900 phb->bus = bus;
1901 qbus_set_hotplug_handler(BUS(phb->bus), OBJECT(sphb));
1902
1903 /*
1904 * Initialize PHB address space.
1905 * By default there will be at least one subregion for default
1906 * 32bit DMA window.
1907 * Later the guest might want to create another DMA window
1908 * which will become another memory subregion.
1909 */
1910 namebuf = g_strdup_printf("%s.iommu-root", sphb->dtbusname);
1911 memory_region_init(&sphb->iommu_root, OBJECT(sphb),
1912 namebuf, UINT64_MAX);
1913 g_free(namebuf);
1914 address_space_init(&sphb->iommu_as, &sphb->iommu_root,
1915 sphb->dtbusname);
1916
1917 /*
1918 * As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors,
1919 * we need to allocate some memory to catch those writes coming
1920 * from msi_notify()/msix_notify().
1921 * As MSIMessage:addr is going to be the same and MSIMessage:data
1922 * is going to be a VIRQ number, 4 bytes of the MSI MR will only
1923 * be used.
1924 *
1925 * For KVM we want to ensure that this memory is a full page so that
1926 * our memory slot is of page size granularity.
1927 */
1928 if (kvm_enabled()) {
1929 msi_window_size = qemu_real_host_page_size();
1930 }
1931
1932 memory_region_init_io(&sphb->msiwindow, OBJECT(sphb), &spapr_msi_ops, spapr,
1933 "msi", msi_window_size);
1934 memory_region_add_subregion(&sphb->iommu_root, SPAPR_PCI_MSI_WINDOW,
1935 &sphb->msiwindow);
1936
1937 pci_setup_iommu(bus, &spapr_iommu_ops, sphb);
1938
1939 pci_bus_set_route_irq_fn(bus, spapr_route_intx_pin_to_irq);
1940
1941 QLIST_INSERT_HEAD(&spapr->phbs, sphb, list);
1942
1943 /* Initialize the LSI table */
1944 for (i = 0; i < PCI_NUM_PINS; i++) {
1945 int irq = SPAPR_IRQ_PCI_LSI + sphb->index * PCI_NUM_PINS + i;
1946
1947 if (spapr_irq_claim(spapr, irq, true, errp) < 0) {
1948 error_prepend(errp, "can't allocate LSIs: ");
1949 goto unrealize;
1950 }
1951
1952 sphb->lsi_table[i].irq = irq;
1953 }
1954
1955 /* allocate connectors for child PCI devices */
1956 add_drcs(sphb, phb->bus);
1957
1958 /* DMA setup */
1959 for (i = 0; i < windows_supported; ++i) {
1960 tcet = spapr_tce_new_table(DEVICE(sphb), sphb->dma_liobn[i]);
1961 if (!tcet) {
1962 error_setg(errp, "Creating window#%d failed for %s",
1963 i, sphb->dtbusname);
1964 goto unrealize;
1965 }
1966 memory_region_add_subregion(&sphb->iommu_root, 0,
1967 spapr_tce_get_iommu(tcet));
1968 }
1969
1970 sphb->msi = g_hash_table_new_full(g_int_hash, g_int_equal, g_free,
1971 spapr_phb_destroy_msi);
1972 return;
1973
1974 unrealize:
1975 spapr_phb_unrealize(dev);
1976 }
1977
1978 static int spapr_phb_children_reset(Object *child, void *opaque)
1979 {
1980 DeviceState *dev = (DeviceState *) object_dynamic_cast(child, TYPE_DEVICE);
1981
1982 if (dev) {
1983 device_cold_reset(dev);
1984 }
1985
1986 return 0;
1987 }
1988
1989 void spapr_phb_dma_reset(SpaprPhbState *sphb)
1990 {
1991 int i;
1992 SpaprTceTable *tcet;
1993
1994 for (i = 0; i < SPAPR_PCI_DMA_MAX_WINDOWS; ++i) {
1995 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[i]);
1996
1997 if (tcet && tcet->nb_table) {
1998 spapr_tce_table_disable(tcet);
1999 }
2000 }
2001
2002 /* Register default 32bit DMA window */
2003 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[0]);
2004 spapr_tce_table_enable(tcet, SPAPR_TCE_PAGE_SHIFT, sphb->dma_win_addr,
2005 sphb->dma_win_size >> SPAPR_TCE_PAGE_SHIFT);
2006 tcet->def_win = true;
2007 }
2008
2009 static void spapr_phb_reset(DeviceState *qdev)
2010 {
2011 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(qdev);
2012
2013 spapr_phb_dma_reset(sphb);
2014
2015 /* Reset the IOMMU state */
2016 object_child_foreach(OBJECT(qdev), spapr_phb_children_reset, NULL);
2017
2018 if (spapr_phb_eeh_available(SPAPR_PCI_HOST_BRIDGE(qdev))) {
2019 spapr_phb_vfio_reset(qdev);
2020 }
2021
2022 g_hash_table_remove_all(sphb->msi);
2023 }
2024
2025 static const Property spapr_phb_properties[] = {
2026 DEFINE_PROP_UINT32("index", SpaprPhbState, index, -1),
2027 DEFINE_PROP_UINT64("mem_win_size", SpaprPhbState, mem_win_size,
2028 SPAPR_PCI_MEM32_WIN_SIZE),
2029 DEFINE_PROP_UINT64("mem64_win_size", SpaprPhbState, mem64_win_size,
2030 SPAPR_PCI_MEM64_WIN_SIZE),
2031 DEFINE_PROP_UINT64("io_win_size", SpaprPhbState, io_win_size,
2032 SPAPR_PCI_IO_WIN_SIZE),
2033 /* Default DMA window is 0..1GB */
2034 DEFINE_PROP_UINT64("dma_win_addr", SpaprPhbState, dma_win_addr, 0),
2035 DEFINE_PROP_UINT64("dma_win_size", SpaprPhbState, dma_win_size, 0x40000000),
2036 DEFINE_PROP_UINT64("dma64_win_addr", SpaprPhbState, dma64_win_addr,
2037 0x800000000000000ULL),
2038 DEFINE_PROP_BOOL("ddw", SpaprPhbState, ddw_enabled, true),
2039 DEFINE_PROP_UINT64("pgsz", SpaprPhbState, page_size_mask,
2040 (1ULL << 12) | (1ULL << 16)
2041 | (1ULL << 21) | (1ULL << 24)),
2042 DEFINE_PROP_UINT32("numa_node", SpaprPhbState, numa_node, -1),
2043 DEFINE_PROP_BOOL("pcie-extended-configuration-space", SpaprPhbState,
2044 pcie_ecs, true),
2045 DEFINE_PROP_BOOL("pre-5.1-associativity", SpaprPhbState,
2046 pre_5_1_assoc, false),
2047 };
2048
2049 static const VMStateDescription vmstate_spapr_pci_lsi = {
2050 .name = "spapr_pci/lsi",
2051 .version_id = 1,
2052 .minimum_version_id = 1,
2053 .fields = (const VMStateField[]) {
2054 VMSTATE_UINT32_EQUAL(irq, SpaprPciLsi),
2055
2056 VMSTATE_END_OF_LIST()
2057 },
2058 };
2059
2060 static const VMStateDescription vmstate_spapr_pci_msi = {
2061 .name = "spapr_pci/msi",
2062 .version_id = 1,
2063 .minimum_version_id = 1,
2064 .fields = (const VMStateField []) {
2065 VMSTATE_UINT32(key, SpaprPciMsiMig),
2066 VMSTATE_UINT32(value.first_irq, SpaprPciMsiMig),
2067 VMSTATE_UINT32(value.num, SpaprPciMsiMig),
2068 VMSTATE_END_OF_LIST()
2069 },
2070 };
2071
2072 static int spapr_pci_pre_save(void *opaque)
2073 {
2074 SpaprPhbState *sphb = opaque;
2075 GHashTableIter iter;
2076 gpointer key, value;
2077 int i;
2078
2079 g_free(sphb->msi_devs);
2080 sphb->msi_devs = NULL;
2081 sphb->msi_devs_num = g_hash_table_size(sphb->msi);
2082 if (!sphb->msi_devs_num) {
2083 return 0;
2084 }
2085 sphb->msi_devs = g_new(SpaprPciMsiMig, sphb->msi_devs_num);
2086
2087 g_hash_table_iter_init(&iter, sphb->msi);
2088 for (i = 0; g_hash_table_iter_next(&iter, &key, &value); ++i) {
2089 sphb->msi_devs[i].key = *(uint32_t *) key;
2090 sphb->msi_devs[i].value = *(SpaprPciMsi *) value;
2091 }
2092
2093 return 0;
2094 }
2095
2096 static void spapr_pci_post_save(void *opaque)
2097 {
2098 SpaprPhbState *sphb = opaque;
2099
2100 g_free(sphb->msi_devs);
2101 sphb->msi_devs = NULL;
2102 sphb->msi_devs_num = 0;
2103 }
2104
2105 static int spapr_pci_post_load(void *opaque, int version_id)
2106 {
2107 SpaprPhbState *sphb = opaque;
2108 gpointer key, value;
2109 int i;
2110
2111 for (i = 0; i < sphb->msi_devs_num; ++i) {
2112 key = g_memdup2(&sphb->msi_devs[i].key, sizeof(sphb->msi_devs[i].key));
2113 value = g_memdup2(&sphb->msi_devs[i].value,
2114 sizeof(sphb->msi_devs[i].value));
2115 g_hash_table_insert(sphb->msi, key, value);
2116 }
2117 g_free(sphb->msi_devs);
2118 sphb->msi_devs = NULL;
2119 sphb->msi_devs_num = 0;
2120
2121 return 0;
2122 }
2123
2124 static const VMStateDescription vmstate_spapr_pci = {
2125 .name = "spapr_pci",
2126 .version_id = 2,
2127 .minimum_version_id = 2,
2128 .pre_save = spapr_pci_pre_save,
2129 .post_save = spapr_pci_post_save,
2130 .post_load = spapr_pci_post_load,
2131 .fields = (const VMStateField[]) {
2132 VMSTATE_UINT64_EQUAL(buid, SpaprPhbState),
2133 VMSTATE_STRUCT_ARRAY(lsi_table, SpaprPhbState, PCI_NUM_PINS, 0,
2134 vmstate_spapr_pci_lsi, SpaprPciLsi),
2135 VMSTATE_INT32(msi_devs_num, SpaprPhbState),
2136 VMSTATE_STRUCT_VARRAY_ALLOC(msi_devs, SpaprPhbState, msi_devs_num, 0,
2137 vmstate_spapr_pci_msi, SpaprPciMsiMig),
2138 VMSTATE_END_OF_LIST()
2139 },
2140 };
2141
2142 static const char *spapr_phb_root_bus_path(PCIHostState *host_bridge,
2143 PCIBus *rootbus)
2144 {
2145 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(host_bridge);
2146
2147 return sphb->dtbusname;
2148 }
2149
2150 static void spapr_phb_class_init(ObjectClass *klass, const void *data)
2151 {
2152 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
2153 DeviceClass *dc = DEVICE_CLASS(klass);
2154 HotplugHandlerClass *hp = HOTPLUG_HANDLER_CLASS(klass);
2155
2156 hc->root_bus_path = spapr_phb_root_bus_path;
2157 dc->realize = spapr_phb_realize;
2158 dc->unrealize = spapr_phb_unrealize;
2159 device_class_set_props(dc, spapr_phb_properties);
2160 device_class_set_legacy_reset(dc, spapr_phb_reset);
2161 dc->vmsd = &vmstate_spapr_pci;
2162 /* Supported by TYPE_SPAPR_MACHINE */
2163 dc->user_creatable = true;
2164 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
2165 hp->pre_plug = spapr_pci_pre_plug;
2166 hp->plug = spapr_pci_plug;
2167 hp->unplug = spapr_pci_unplug;
2168 hp->unplug_request = spapr_pci_unplug_request;
2169 }
2170
2171 static const TypeInfo spapr_phb_info = {
2172 .name = TYPE_SPAPR_PCI_HOST_BRIDGE,
2173 .parent = TYPE_PCI_HOST_BRIDGE,
2174 .instance_size = sizeof(SpaprPhbState),
2175 .instance_finalize = spapr_phb_finalizefn,
2176 .class_init = spapr_phb_class_init,
2177 .interfaces = (const InterfaceInfo[]) {
2178 { TYPE_HOTPLUG_HANDLER },
2179 { }
2180 }
2181 };
2182
2183 static void spapr_phb_pci_enumerate_bridge(PCIBus *bus, PCIDevice *pdev,
2184 void *opaque)
2185 {
2186 unsigned int *bus_no = opaque;
2187 PCIBus *sec_bus = NULL;
2188
2189 if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) !=
2190 PCI_HEADER_TYPE_BRIDGE)) {
2191 return;
2192 }
2193
2194 (*bus_no)++;
2195 pci_default_write_config(pdev, PCI_PRIMARY_BUS, pci_dev_bus_num(pdev), 1);
2196 pci_default_write_config(pdev, PCI_SECONDARY_BUS, *bus_no, 1);
2197 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1);
2198
2199 sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
2200 if (!sec_bus) {
2201 return;
2202 }
2203
2204 pci_for_each_device_under_bus(sec_bus, spapr_phb_pci_enumerate_bridge,
2205 bus_no);
2206 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1);
2207 }
2208
2209 static void spapr_phb_pci_enumerate(SpaprPhbState *phb)
2210 {
2211 PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus;
2212 unsigned int bus_no = 0;
2213
2214 pci_for_each_device_under_bus(bus, spapr_phb_pci_enumerate_bridge,
2215 &bus_no);
2216
2217 }
2218
2219 int spapr_dt_phb(SpaprMachineState *spapr, SpaprPhbState *phb,
2220 uint32_t intc_phandle, void *fdt, int *node_offset)
2221 {
2222 int bus_off, i, j, ret;
2223 uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) };
2224 struct {
2225 uint32_t hi;
2226 uint64_t child;
2227 uint64_t parent;
2228 uint64_t size;
2229 } QEMU_PACKED ranges[] = {
2230 {
2231 cpu_to_be32(b_ss(1)), cpu_to_be64(0),
2232 cpu_to_be64(phb->io_win_addr),
2233 cpu_to_be64(memory_region_size(&phb->iospace)),
2234 },
2235 {
2236 cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET),
2237 cpu_to_be64(phb->mem_win_addr),
2238 cpu_to_be64(phb->mem_win_size),
2239 },
2240 {
2241 cpu_to_be32(b_ss(3)), cpu_to_be64(phb->mem64_win_pciaddr),
2242 cpu_to_be64(phb->mem64_win_addr),
2243 cpu_to_be64(phb->mem64_win_size),
2244 },
2245 };
2246 const unsigned sizeof_ranges =
2247 (phb->mem64_win_size ? 3 : 2) * sizeof(ranges[0]);
2248 uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 };
2249 uint32_t interrupt_map_mask[] = {
2250 cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)};
2251 uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7];
2252 uint32_t ddw_applicable[] = {
2253 cpu_to_be32(RTAS_IBM_QUERY_PE_DMA_WINDOW),
2254 cpu_to_be32(RTAS_IBM_CREATE_PE_DMA_WINDOW),
2255 cpu_to_be32(RTAS_IBM_REMOVE_PE_DMA_WINDOW)
2256 };
2257 uint32_t ddw_extensions[] = {
2258 cpu_to_be32(2),
2259 cpu_to_be32(RTAS_IBM_RESET_PE_DMA_WINDOW),
2260 cpu_to_be32(1), /* 1: ibm,query-pe-dma-window 6 outputs, PAPR 2.8 */
2261 };
2262 SpaprTceTable *tcet;
2263 SpaprDrc *drc;
2264
2265 /* Start populating the FDT */
2266 _FDT(bus_off = fdt_add_subnode(fdt, 0, phb->dtbusname));
2267 if (node_offset) {
2268 *node_offset = bus_off;
2269 }
2270
2271 /* Write PHB properties */
2272 _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci"));
2273 _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB"));
2274 _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1));
2275 _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0));
2276 _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range)));
2277 _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof_ranges));
2278 _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg)));
2279 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1));
2280 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi",
2281 SPAPR_IRQ_NR_MSIS));
2282
2283 /* Dynamic DMA window */
2284 if (phb->ddw_enabled) {
2285 _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-applicable", &ddw_applicable,
2286 sizeof(ddw_applicable)));
2287 _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-extensions",
2288 &ddw_extensions, sizeof(ddw_extensions)));
2289 }
2290
2291 /* Advertise NUMA via ibm,associativity */
2292 if (phb->numa_node != -1) {
2293 spapr_numa_write_associativity_dt(spapr, fdt, bus_off, phb->numa_node);
2294 }
2295
2296 /* Build the interrupt-map, this must matches what is done
2297 * in pci_swizzle_map_irq_fn
2298 */
2299 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask",
2300 &interrupt_map_mask, sizeof(interrupt_map_mask)));
2301 for (i = 0; i < PCI_SLOT_MAX; i++) {
2302 for (j = 0; j < PCI_NUM_PINS; j++) {
2303 uint32_t *irqmap = interrupt_map[i*PCI_NUM_PINS + j];
2304 int lsi_num = pci_swizzle(i, j);
2305
2306 irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0));
2307 irqmap[1] = 0;
2308 irqmap[2] = 0;
2309 irqmap[3] = cpu_to_be32(j+1);
2310 irqmap[4] = cpu_to_be32(intc_phandle);
2311 spapr_dt_irq(&irqmap[5], phb->lsi_table[lsi_num].irq, true);
2312 }
2313 }
2314 /* Write interrupt map */
2315 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map,
2316 sizeof(interrupt_map)));
2317
2318 tcet = spapr_tce_find_by_liobn(phb->dma_liobn[0]);
2319 if (!tcet) {
2320 return -1;
2321 }
2322 spapr_dma_dt(fdt, bus_off, "ibm,dma-window",
2323 tcet->liobn, tcet->bus_offset,
2324 tcet->nb_table << tcet->page_shift);
2325
2326 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, phb->index);
2327 if (drc) {
2328 uint32_t drc_index = cpu_to_be32(spapr_drc_index(drc));
2329
2330 _FDT(fdt_setprop(fdt, bus_off, "ibm,my-drc-index", &drc_index,
2331 sizeof(drc_index)));
2332 }
2333
2334 /* Walk the bridges and program the bus numbers*/
2335 spapr_phb_pci_enumerate(phb);
2336 _FDT(fdt_setprop_cell(fdt, bus_off, "qemu,phb-enumerated", 0x1));
2337
2338 /* Walk the bridge and subordinate buses */
2339 ret = spapr_dt_pci_bus(phb, PCI_HOST_BRIDGE(phb)->bus, fdt, bus_off);
2340 if (ret < 0) {
2341 return ret;
2342 }
2343
2344 return 0;
2345 }
2346
2347 void spapr_pci_rtas_init(void)
2348 {
2349 spapr_rtas_register(RTAS_READ_PCI_CONFIG, "read-pci-config",
2350 rtas_read_pci_config);
2351 spapr_rtas_register(RTAS_WRITE_PCI_CONFIG, "write-pci-config",
2352 rtas_write_pci_config);
2353 spapr_rtas_register(RTAS_IBM_READ_PCI_CONFIG, "ibm,read-pci-config",
2354 rtas_ibm_read_pci_config);
2355 spapr_rtas_register(RTAS_IBM_WRITE_PCI_CONFIG, "ibm,write-pci-config",
2356 rtas_ibm_write_pci_config);
2357 if (msi_nonbroken) {
2358 spapr_rtas_register(RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER,
2359 "ibm,query-interrupt-source-number",
2360 rtas_ibm_query_interrupt_source_number);
2361 spapr_rtas_register(RTAS_IBM_CHANGE_MSI, "ibm,change-msi",
2362 rtas_ibm_change_msi);
2363 }
2364
2365 spapr_rtas_register(RTAS_IBM_SET_EEH_OPTION,
2366 "ibm,set-eeh-option",
2367 rtas_ibm_set_eeh_option);
2368 spapr_rtas_register(RTAS_IBM_GET_CONFIG_ADDR_INFO2,
2369 "ibm,get-config-addr-info2",
2370 rtas_ibm_get_config_addr_info2);
2371 spapr_rtas_register(RTAS_IBM_READ_SLOT_RESET_STATE2,
2372 "ibm,read-slot-reset-state2",
2373 rtas_ibm_read_slot_reset_state2);
2374 spapr_rtas_register(RTAS_IBM_SET_SLOT_RESET,
2375 "ibm,set-slot-reset",
2376 rtas_ibm_set_slot_reset);
2377 spapr_rtas_register(RTAS_IBM_CONFIGURE_PE,
2378 "ibm,configure-pe",
2379 rtas_ibm_configure_pe);
2380 spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL,
2381 "ibm,slot-error-detail",
2382 rtas_ibm_slot_error_detail);
2383 }
2384
2385 static void spapr_pci_register_types(void)
2386 {
2387 type_register_static(&spapr_phb_info);
2388 }
2389
2390 type_init(spapr_pci_register_types)
2391
2392 static int spapr_switch_one_vga(DeviceState *dev, void *opaque)
2393 {
2394 bool be = *(bool *)opaque;
2395
2396 if (object_dynamic_cast(OBJECT(dev), "VGA")
2397 || object_dynamic_cast(OBJECT(dev), "secondary-vga")
2398 || object_dynamic_cast(OBJECT(dev), "bochs-display")
2399 || object_dynamic_cast(OBJECT(dev), "virtio-vga")) {
2400 object_property_set_bool(OBJECT(dev), "big-endian-framebuffer", be,
2401 &error_abort);
2402 }
2403 return 0;
2404 }
2405
2406 void spapr_pci_switch_vga(SpaprMachineState *spapr, bool big_endian)
2407 {
2408 SpaprPhbState *sphb;
2409
2410 /*
2411 * For backward compatibility with existing guests, we switch
2412 * the endianness of the VGA controller when changing the guest
2413 * interrupt mode
2414 */
2415 QLIST_FOREACH(sphb, &spapr->phbs, list) {
2416 BusState *bus = &PCI_HOST_BRIDGE(sphb)->bus->qbus;
2417 qbus_walk_children(bus, spapr_switch_one_vga, NULL, NULL, NULL,
2418 &big_endian);
2419 }
2420 }