| 1 | /* |
| 2 | * Copyright © 2018, 2021 Oracle and/or its affiliates. |
| 3 | * |
| 4 | * This work is licensed under the terms of the GNU GPL, version 2 or later. |
| 5 | * See the COPYING file in the top-level directory. |
| 6 | * |
| 7 | */ |
| 8 | |
| 9 | #include "qemu/osdep.h" |
| 10 | |
| 11 | #include "hw/remote/proxy.h" |
| 12 | #include "hw/pci/pci.h" |
| 13 | #include "qapi/error.h" |
| 14 | #include "io/channel-util.h" |
| 15 | #include "hw/core/qdev-properties.h" |
| 16 | #include "monitor/monitor.h" |
| 17 | #include "migration/blocker.h" |
| 18 | #include "qemu/sockets.h" |
| 19 | #include "hw/remote/mpqemu-link.h" |
| 20 | #include "qemu/error-report.h" |
| 21 | #include "hw/remote/proxy-memory-listener.h" |
| 22 | #include "qom/object.h" |
| 23 | #include "qemu/event_notifier.h" |
| 24 | #include "system/kvm.h" |
| 25 | |
| 26 | static void probe_pci_info(PCIDevice *dev, Error **errp); |
| 27 | static void proxy_device_reset(DeviceState *dev); |
| 28 | |
| 29 | static void proxy_intx_update(PCIDevice *pci_dev) |
| 30 | { |
| 31 | PCIProxyDev *dev = PCI_PROXY_DEV(pci_dev); |
| 32 | PCIINTxRoute route; |
| 33 | int pin = pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1; |
| 34 | |
| 35 | if (dev->virq != -1) { |
| 36 | kvm_irqchip_remove_irqfd_notifier_gsi(kvm_state, &dev->intr, dev->virq); |
| 37 | dev->virq = -1; |
| 38 | } |
| 39 | |
| 40 | route = pci_device_route_intx_to_irq(pci_dev, pin); |
| 41 | |
| 42 | dev->virq = route.irq; |
| 43 | |
| 44 | if (dev->virq != -1) { |
| 45 | kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, &dev->intr, |
| 46 | &dev->resample, dev->virq); |
| 47 | } |
| 48 | } |
| 49 | |
| 50 | static void setup_irqfd(PCIProxyDev *dev) |
| 51 | { |
| 52 | PCIDevice *pci_dev = PCI_DEVICE(dev); |
| 53 | MPQemuMsg msg; |
| 54 | Error *local_err = NULL; |
| 55 | int ret = 0; |
| 56 | |
| 57 | ret = event_notifier_init(&dev->intr, 0); |
| 58 | if (ret < 0) { |
| 59 | error_report("Failed to init intr notifier: %s", strerror(-ret)); |
| 60 | return; |
| 61 | } |
| 62 | |
| 63 | ret = event_notifier_init(&dev->resample, 0); |
| 64 | if (ret < 0) { |
| 65 | error_report("Failed to init resample notifier: %s", strerror(-ret)); |
| 66 | event_notifier_cleanup(&dev->intr); |
| 67 | return; |
| 68 | } |
| 69 | |
| 70 | memset(&msg, 0, sizeof(MPQemuMsg)); |
| 71 | msg.cmd = MPQEMU_CMD_SET_IRQFD; |
| 72 | msg.num_fds = 2; |
| 73 | msg.fds[0] = event_notifier_get_fd(&dev->intr); |
| 74 | msg.fds[1] = event_notifier_get_fd(&dev->resample); |
| 75 | msg.size = 0; |
| 76 | |
| 77 | if (!mpqemu_msg_send(&msg, dev->ioc, &local_err)) { |
| 78 | error_report_err(local_err); |
| 79 | } |
| 80 | |
| 81 | dev->virq = -1; |
| 82 | |
| 83 | proxy_intx_update(pci_dev); |
| 84 | |
| 85 | pci_device_set_intx_routing_notifier(pci_dev, proxy_intx_update); |
| 86 | } |
| 87 | |
| 88 | static void pci_proxy_dev_realize(PCIDevice *device, Error **errp) |
| 89 | { |
| 90 | ERRP_GUARD(); |
| 91 | PCIProxyDev *dev = PCI_PROXY_DEV(device); |
| 92 | uint8_t *pci_conf = device->config; |
| 93 | int fd; |
| 94 | |
| 95 | if (!dev->fd) { |
| 96 | error_setg(errp, "fd parameter not specified for %s", |
| 97 | DEVICE(device)->id); |
| 98 | return; |
| 99 | } |
| 100 | |
| 101 | fd = monitor_fd_param(monitor_cur(), dev->fd, errp); |
| 102 | if (fd == -1) { |
| 103 | error_prepend(errp, "proxy: unable to parse fd %s: ", dev->fd); |
| 104 | return; |
| 105 | } |
| 106 | |
| 107 | if (!fd_is_socket(fd)) { |
| 108 | error_setg(errp, "proxy: fd %d is not a socket", fd); |
| 109 | close(fd); |
| 110 | return; |
| 111 | } |
| 112 | |
| 113 | dev->ioc = qio_channel_new_fd(fd, errp); |
| 114 | if (!dev->ioc) { |
| 115 | close(fd); |
| 116 | return; |
| 117 | } |
| 118 | |
| 119 | error_setg(&dev->migration_blocker, "%s does not support migration", |
| 120 | TYPE_PCI_PROXY_DEV); |
| 121 | if (migrate_add_blocker(&dev->migration_blocker, errp) < 0) { |
| 122 | object_unref(dev->ioc); |
| 123 | return; |
| 124 | } |
| 125 | |
| 126 | if (!qio_channel_set_blocking(dev->ioc, true, errp)) { |
| 127 | object_unref(dev->ioc); |
| 128 | return; |
| 129 | } |
| 130 | |
| 131 | qemu_mutex_init(&dev->io_mutex); |
| 132 | |
| 133 | pci_conf[PCI_LATENCY_TIMER] = 0xff; |
| 134 | pci_conf[PCI_INTERRUPT_PIN] = 0x01; |
| 135 | |
| 136 | proxy_memory_listener_configure(&dev->proxy_listener, dev->ioc); |
| 137 | |
| 138 | setup_irqfd(dev); |
| 139 | |
| 140 | probe_pci_info(PCI_DEVICE(dev), errp); |
| 141 | } |
| 142 | |
| 143 | static void pci_proxy_dev_exit(PCIDevice *pdev) |
| 144 | { |
| 145 | PCIProxyDev *dev = PCI_PROXY_DEV(pdev); |
| 146 | |
| 147 | if (dev->ioc) { |
| 148 | qio_channel_close(dev->ioc, NULL); |
| 149 | } |
| 150 | |
| 151 | migrate_del_blocker(&dev->migration_blocker); |
| 152 | |
| 153 | proxy_memory_listener_deconfigure(&dev->proxy_listener); |
| 154 | |
| 155 | event_notifier_cleanup(&dev->intr); |
| 156 | event_notifier_cleanup(&dev->resample); |
| 157 | } |
| 158 | |
| 159 | static void config_op_send(PCIProxyDev *pdev, uint32_t addr, uint32_t *val, |
| 160 | int len, unsigned int op) |
| 161 | { |
| 162 | MPQemuMsg msg = { 0 }; |
| 163 | uint64_t ret = -EINVAL; |
| 164 | Error *local_err = NULL; |
| 165 | |
| 166 | msg.cmd = op; |
| 167 | msg.data.pci_conf_data.addr = addr; |
| 168 | msg.data.pci_conf_data.val = (op == MPQEMU_CMD_PCI_CFGWRITE) ? *val : 0; |
| 169 | msg.data.pci_conf_data.len = len; |
| 170 | msg.size = sizeof(PciConfDataMsg); |
| 171 | |
| 172 | ret = mpqemu_msg_send_and_await_reply(&msg, pdev, &local_err); |
| 173 | if (local_err) { |
| 174 | error_report_err(local_err); |
| 175 | } |
| 176 | |
| 177 | if (ret == UINT64_MAX) { |
| 178 | error_report("Failed to perform PCI config %s operation", |
| 179 | (op == MPQEMU_CMD_PCI_CFGREAD) ? "READ" : "WRITE"); |
| 180 | } |
| 181 | |
| 182 | if (op == MPQEMU_CMD_PCI_CFGREAD) { |
| 183 | *val = (uint32_t)ret; |
| 184 | } |
| 185 | } |
| 186 | |
| 187 | static uint32_t pci_proxy_read_config(PCIDevice *d, uint32_t addr, int len) |
| 188 | { |
| 189 | uint32_t val; |
| 190 | |
| 191 | config_op_send(PCI_PROXY_DEV(d), addr, &val, len, MPQEMU_CMD_PCI_CFGREAD); |
| 192 | |
| 193 | return val; |
| 194 | } |
| 195 | |
| 196 | static void pci_proxy_write_config(PCIDevice *d, uint32_t addr, uint32_t val, |
| 197 | int len) |
| 198 | { |
| 199 | /* |
| 200 | * Some of the functions access the copy of remote device's PCI config |
| 201 | * space which is cached in the proxy device. Therefore, maintain |
| 202 | * it updated. |
| 203 | */ |
| 204 | pci_default_write_config(d, addr, val, len); |
| 205 | |
| 206 | config_op_send(PCI_PROXY_DEV(d), addr, &val, len, MPQEMU_CMD_PCI_CFGWRITE); |
| 207 | } |
| 208 | |
| 209 | static const Property proxy_properties[] = { |
| 210 | DEFINE_PROP_STRING("fd", PCIProxyDev, fd), |
| 211 | }; |
| 212 | |
| 213 | static void pci_proxy_dev_class_init(ObjectClass *klass, const void *data) |
| 214 | { |
| 215 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 216 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
| 217 | |
| 218 | k->realize = pci_proxy_dev_realize; |
| 219 | k->exit = pci_proxy_dev_exit; |
| 220 | k->config_read = pci_proxy_read_config; |
| 221 | k->config_write = pci_proxy_write_config; |
| 222 | |
| 223 | device_class_set_legacy_reset(dc, proxy_device_reset); |
| 224 | |
| 225 | device_class_set_props(dc, proxy_properties); |
| 226 | } |
| 227 | |
| 228 | static const TypeInfo pci_proxy_dev_type_info = { |
| 229 | .name = TYPE_PCI_PROXY_DEV, |
| 230 | .parent = TYPE_PCI_DEVICE, |
| 231 | .instance_size = sizeof(PCIProxyDev), |
| 232 | .class_init = pci_proxy_dev_class_init, |
| 233 | .interfaces = (const InterfaceInfo[]) { |
| 234 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, |
| 235 | { }, |
| 236 | }, |
| 237 | }; |
| 238 | |
| 239 | static void pci_proxy_dev_register_types(void) |
| 240 | { |
| 241 | type_register_static(&pci_proxy_dev_type_info); |
| 242 | } |
| 243 | |
| 244 | type_init(pci_proxy_dev_register_types) |
| 245 | |
| 246 | static void send_bar_access_msg(PCIProxyDev *pdev, MemoryRegion *mr, |
| 247 | bool write, hwaddr addr, uint64_t *val, |
| 248 | unsigned size, bool memory) |
| 249 | { |
| 250 | MPQemuMsg msg = { 0 }; |
| 251 | long ret = -EINVAL; |
| 252 | Error *local_err = NULL; |
| 253 | |
| 254 | msg.size = sizeof(BarAccessMsg); |
| 255 | msg.data.bar_access.addr = mr->addr + addr; |
| 256 | msg.data.bar_access.size = size; |
| 257 | msg.data.bar_access.memory = memory; |
| 258 | |
| 259 | if (write) { |
| 260 | msg.cmd = MPQEMU_CMD_BAR_WRITE; |
| 261 | msg.data.bar_access.val = *val; |
| 262 | } else { |
| 263 | msg.cmd = MPQEMU_CMD_BAR_READ; |
| 264 | } |
| 265 | |
| 266 | ret = mpqemu_msg_send_and_await_reply(&msg, pdev, &local_err); |
| 267 | if (local_err) { |
| 268 | error_report_err(local_err); |
| 269 | } |
| 270 | |
| 271 | if (!write) { |
| 272 | *val = ret; |
| 273 | } |
| 274 | } |
| 275 | |
| 276 | static void proxy_bar_write(void *opaque, hwaddr addr, uint64_t val, |
| 277 | unsigned size) |
| 278 | { |
| 279 | ProxyMemoryRegion *pmr = opaque; |
| 280 | |
| 281 | send_bar_access_msg(pmr->dev, &pmr->mr, true, addr, &val, size, |
| 282 | pmr->memory); |
| 283 | } |
| 284 | |
| 285 | static uint64_t proxy_bar_read(void *opaque, hwaddr addr, unsigned size) |
| 286 | { |
| 287 | ProxyMemoryRegion *pmr = opaque; |
| 288 | uint64_t val; |
| 289 | |
| 290 | send_bar_access_msg(pmr->dev, &pmr->mr, false, addr, &val, size, |
| 291 | pmr->memory); |
| 292 | |
| 293 | return val; |
| 294 | } |
| 295 | |
| 296 | const MemoryRegionOps proxy_mr_ops = { |
| 297 | .read = proxy_bar_read, |
| 298 | .write = proxy_bar_write, |
| 299 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 300 | .impl = { |
| 301 | .min_access_size = 1, |
| 302 | .max_access_size = 8, |
| 303 | }, |
| 304 | }; |
| 305 | |
| 306 | static void probe_pci_info(PCIDevice *dev, Error **errp) |
| 307 | { |
| 308 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); |
| 309 | uint32_t orig_val, new_val, base_class, val; |
| 310 | PCIProxyDev *pdev = PCI_PROXY_DEV(dev); |
| 311 | DeviceClass *dc = DEVICE_CLASS(pc); |
| 312 | uint8_t type; |
| 313 | int i, size; |
| 314 | |
| 315 | config_op_send(pdev, PCI_VENDOR_ID, &val, 2, MPQEMU_CMD_PCI_CFGREAD); |
| 316 | pc->vendor_id = (uint16_t)val; |
| 317 | |
| 318 | config_op_send(pdev, PCI_DEVICE_ID, &val, 2, MPQEMU_CMD_PCI_CFGREAD); |
| 319 | pc->device_id = (uint16_t)val; |
| 320 | |
| 321 | config_op_send(pdev, PCI_CLASS_DEVICE, &val, 2, MPQEMU_CMD_PCI_CFGREAD); |
| 322 | pc->class_id = (uint16_t)val; |
| 323 | |
| 324 | config_op_send(pdev, PCI_SUBSYSTEM_ID, &val, 2, MPQEMU_CMD_PCI_CFGREAD); |
| 325 | pc->subsystem_id = (uint16_t)val; |
| 326 | |
| 327 | base_class = pc->class_id >> 4; |
| 328 | switch (base_class) { |
| 329 | case PCI_BASE_CLASS_BRIDGE: |
| 330 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
| 331 | break; |
| 332 | case PCI_BASE_CLASS_STORAGE: |
| 333 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); |
| 334 | break; |
| 335 | case PCI_BASE_CLASS_NETWORK: |
| 336 | case PCI_BASE_CLASS_WIRELESS: |
| 337 | set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); |
| 338 | break; |
| 339 | case PCI_BASE_CLASS_INPUT: |
| 340 | set_bit(DEVICE_CATEGORY_INPUT, dc->categories); |
| 341 | break; |
| 342 | case PCI_BASE_CLASS_DISPLAY: |
| 343 | set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); |
| 344 | break; |
| 345 | case PCI_BASE_CLASS_PROCESSOR: |
| 346 | set_bit(DEVICE_CATEGORY_CPU, dc->categories); |
| 347 | break; |
| 348 | default: |
| 349 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); |
| 350 | break; |
| 351 | } |
| 352 | |
| 353 | for (i = 0; i < PCI_NUM_REGIONS; i++) { |
| 354 | config_op_send(pdev, PCI_BASE_ADDRESS_0 + (4 * i), &orig_val, 4, |
| 355 | MPQEMU_CMD_PCI_CFGREAD); |
| 356 | new_val = 0xffffffff; |
| 357 | config_op_send(pdev, PCI_BASE_ADDRESS_0 + (4 * i), &new_val, 4, |
| 358 | MPQEMU_CMD_PCI_CFGWRITE); |
| 359 | config_op_send(pdev, PCI_BASE_ADDRESS_0 + (4 * i), &new_val, 4, |
| 360 | MPQEMU_CMD_PCI_CFGREAD); |
| 361 | size = (~(new_val & 0xFFFFFFF0)) + 1; |
| 362 | config_op_send(pdev, PCI_BASE_ADDRESS_0 + (4 * i), &orig_val, 4, |
| 363 | MPQEMU_CMD_PCI_CFGWRITE); |
| 364 | type = (new_val & 0x1) ? |
| 365 | PCI_BASE_ADDRESS_SPACE_IO : PCI_BASE_ADDRESS_SPACE_MEMORY; |
| 366 | |
| 367 | if (size) { |
| 368 | g_autofree char *name = g_strdup_printf("bar-region-%d", i); |
| 369 | pdev->region[i].dev = pdev; |
| 370 | pdev->region[i].present = true; |
| 371 | if (type == PCI_BASE_ADDRESS_SPACE_MEMORY) { |
| 372 | pdev->region[i].memory = true; |
| 373 | } |
| 374 | memory_region_init_io(&pdev->region[i].mr, OBJECT(pdev), |
| 375 | &proxy_mr_ops, &pdev->region[i], |
| 376 | name, size); |
| 377 | pci_register_bar(dev, i, type, &pdev->region[i].mr); |
| 378 | } |
| 379 | } |
| 380 | } |
| 381 | |
| 382 | static void proxy_device_reset(DeviceState *dev) |
| 383 | { |
| 384 | PCIProxyDev *pdev = PCI_PROXY_DEV(dev); |
| 385 | MPQemuMsg msg = { 0 }; |
| 386 | Error *local_err = NULL; |
| 387 | |
| 388 | msg.cmd = MPQEMU_CMD_DEVICE_RESET; |
| 389 | msg.size = 0; |
| 390 | |
| 391 | mpqemu_msg_send_and_await_reply(&msg, pdev, &local_err); |
| 392 | if (local_err) { |
| 393 | error_report_err(local_err); |
| 394 | } |
| 395 | |
| 396 | } |