| 1 | /* |
| 2 | * QEMU RISC-V Boot Helper |
| 3 | * |
| 4 | * Copyright (c) 2017 SiFive, Inc. |
| 5 | * Copyright (c) 2019 Alistair Francis <alistair.francis@wdc.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it |
| 8 | * under the terms and conditions of the GNU General Public License, |
| 9 | * version 2 or later, as published by the Free Software Foundation. |
| 10 | * |
| 11 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 14 | * more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License along with |
| 17 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #include "qemu/osdep.h" |
| 21 | #include "qemu/bswap.h" |
| 22 | #include "qemu/datadir.h" |
| 23 | #include "qemu/units.h" |
| 24 | #include "qemu/error-report.h" |
| 25 | #include "exec/cpu-defs.h" |
| 26 | #include "hw/core/boards.h" |
| 27 | #include "hw/core/loader.h" |
| 28 | #include "hw/riscv/boot.h" |
| 29 | #include "hw/riscv/boot_opensbi.h" |
| 30 | #include "elf.h" |
| 31 | #include "system/device_tree.h" |
| 32 | #include "system/qtest.h" |
| 33 | #include "system/kvm.h" |
| 34 | #include "system/reset.h" |
| 35 | |
| 36 | #include <libfdt.h> |
| 37 | |
| 38 | bool riscv_is_32bit(RISCVHartArrayState *harts) |
| 39 | { |
| 40 | RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(&harts->harts[0]); |
| 41 | return mcc->def->misa_mxl_max == MXL_RV32; |
| 42 | } |
| 43 | |
| 44 | /* |
| 45 | * Return the per-socket PLIC hart topology configuration string |
| 46 | * (caller must free with g_free()) |
| 47 | */ |
| 48 | char *riscv_plic_hart_config_string(int hart_count) |
| 49 | { |
| 50 | g_autofree const char **vals = g_new(const char *, hart_count + 1); |
| 51 | int i; |
| 52 | |
| 53 | for (i = 0; i < hart_count; i++) { |
| 54 | CPUState *cs = qemu_get_cpu(i); |
| 55 | CPURISCVState *env = &RISCV_CPU(cs)->env; |
| 56 | |
| 57 | if (kvm_enabled()) { |
| 58 | vals[i] = "S"; |
| 59 | } else if (riscv_has_ext(env, RVS)) { |
| 60 | vals[i] = "MS"; |
| 61 | } else { |
| 62 | vals[i] = "M"; |
| 63 | } |
| 64 | } |
| 65 | vals[i] = NULL; |
| 66 | |
| 67 | /* g_strjoinv() obliges us to cast away const here */ |
| 68 | return g_strjoinv(",", (char **)vals); |
| 69 | } |
| 70 | |
| 71 | void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts) |
| 72 | { |
| 73 | info->ram_low_start = 0; |
| 74 | info->ram_low_size = 0; |
| 75 | info->kernel_size = 0; |
| 76 | info->initrd_size = 0; |
| 77 | info->is_32bit = riscv_is_32bit(harts); |
| 78 | } |
| 79 | |
| 80 | /* |
| 81 | * This can be used instead of riscv_boot_info_init() if the machine has |
| 82 | * discontiguous physical memory. The low memory range specified will be |
| 83 | * used to place firmware images. |
| 84 | */ |
| 85 | void riscv_boot_info_init_discontig_mem(RISCVBootInfo *info, |
| 86 | RISCVHartArrayState *harts, |
| 87 | hwaddr low_start, hwaddr low_size) |
| 88 | { |
| 89 | riscv_boot_info_init(info, harts); |
| 90 | info->ram_low_start = low_start; |
| 91 | info->ram_low_size = low_size; |
| 92 | } |
| 93 | |
| 94 | vaddr riscv_calc_kernel_start_addr(RISCVBootInfo *info, |
| 95 | hwaddr firmware_end_addr) { |
| 96 | if (info->is_32bit) { |
| 97 | return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB); |
| 98 | } else { |
| 99 | return QEMU_ALIGN_UP(firmware_end_addr, 2 * MiB); |
| 100 | } |
| 101 | } |
| 102 | |
| 103 | const char *riscv_default_firmware_name(RISCVHartArrayState *harts) |
| 104 | { |
| 105 | if (riscv_is_32bit(harts)) { |
| 106 | return RISCV32_BIOS_BIN; |
| 107 | } |
| 108 | |
| 109 | return RISCV64_BIOS_BIN; |
| 110 | } |
| 111 | |
| 112 | static char *riscv_find_bios(const char *bios_filename) |
| 113 | { |
| 114 | char *filename; |
| 115 | |
| 116 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_filename); |
| 117 | if (filename == NULL) { |
| 118 | if (!qtest_enabled()) { |
| 119 | /* |
| 120 | * We only ship OpenSBI binary bios images in the QEMU source. |
| 121 | * For machines that use images other than the default bios, |
| 122 | * running QEMU test will complain hence let's suppress the error |
| 123 | * report for QEMU testing. |
| 124 | */ |
| 125 | error_report("Unable to find the RISC-V BIOS \"%s\"", |
| 126 | bios_filename); |
| 127 | exit(1); |
| 128 | } |
| 129 | } |
| 130 | |
| 131 | return filename; |
| 132 | } |
| 133 | |
| 134 | char *riscv_find_firmware(const char *firmware_filename, |
| 135 | const char *default_machine_firmware) |
| 136 | { |
| 137 | char *filename = NULL; |
| 138 | |
| 139 | if ((!firmware_filename) || (!strcmp(firmware_filename, "default"))) { |
| 140 | /* |
| 141 | * The user didn't specify -bios, or has specified "-bios default". |
| 142 | * That means we are going to load the OpenSBI binary included in |
| 143 | * the QEMU source. |
| 144 | */ |
| 145 | filename = riscv_find_bios(default_machine_firmware); |
| 146 | } else if (strcmp(firmware_filename, "none")) { |
| 147 | filename = riscv_find_bios(firmware_filename); |
| 148 | } |
| 149 | |
| 150 | return filename; |
| 151 | } |
| 152 | |
| 153 | hwaddr riscv_find_and_load_firmware(MachineState *machine, |
| 154 | RISCVBootInfo *info, |
| 155 | const char *default_machine_firmware, |
| 156 | hwaddr *firmware_load_addr, |
| 157 | symbol_fn_t sym_cb) |
| 158 | { |
| 159 | char *firmware_filename; |
| 160 | hwaddr firmware_end_addr = *firmware_load_addr; |
| 161 | |
| 162 | firmware_filename = riscv_find_firmware(machine->firmware, |
| 163 | default_machine_firmware); |
| 164 | |
| 165 | if (firmware_filename) { |
| 166 | /* If not "none" load the firmware */ |
| 167 | firmware_end_addr = riscv_load_firmware(machine, info, |
| 168 | firmware_filename, |
| 169 | firmware_load_addr, sym_cb); |
| 170 | g_free(firmware_filename); |
| 171 | } |
| 172 | |
| 173 | return firmware_end_addr; |
| 174 | } |
| 175 | |
| 176 | hwaddr riscv_load_firmware(MachineState *machine, |
| 177 | const RISCVBootInfo *info, |
| 178 | const char *firmware_filename, |
| 179 | hwaddr *firmware_load_addr, |
| 180 | symbol_fn_t sym_cb) |
| 181 | { |
| 182 | uint64_t mem_size = info->ram_low_size ?: machine->ram_size; |
| 183 | uint64_t firmware_entry, firmware_end; |
| 184 | ssize_t firmware_size; |
| 185 | |
| 186 | g_assert(firmware_filename != NULL); |
| 187 | |
| 188 | firmware_size = load_elf_ram_sym(firmware_filename, NULL, NULL, NULL, |
| 189 | &firmware_entry, NULL, &firmware_end, |
| 190 | NULL, 0, EM_RISCV, 1, 0, NULL, false, |
| 191 | sym_cb); |
| 192 | if (firmware_size > 0) { |
| 193 | *firmware_load_addr = firmware_entry; |
| 194 | return firmware_end; |
| 195 | } |
| 196 | |
| 197 | if (firmware_size != ELF_LOAD_NOT_ELF) { |
| 198 | /* |
| 199 | * If the user specified an ELF format firmware that could not be |
| 200 | * loaded as an ELF, it's possible that loading it as a binary is |
| 201 | * not what was intended. |
| 202 | */ |
| 203 | warn_report("could not load ELF format firmware '%s' (%s). " |
| 204 | "Attempting to load as binary.", |
| 205 | firmware_filename, |
| 206 | load_elf_strerror(firmware_size)); |
| 207 | } |
| 208 | |
| 209 | firmware_size = load_image_targphys_as(firmware_filename, |
| 210 | *firmware_load_addr, |
| 211 | mem_size, NULL, |
| 212 | NULL); |
| 213 | |
| 214 | if (firmware_size > 0) { |
| 215 | return *firmware_load_addr + firmware_size; |
| 216 | } |
| 217 | |
| 218 | error_report("could not load firmware '%s': %s", firmware_filename, |
| 219 | load_elf_strerror(firmware_size)); |
| 220 | exit(1); |
| 221 | } |
| 222 | |
| 223 | static void riscv_load_initrd(MachineState *machine, RISCVBootInfo *info) |
| 224 | { |
| 225 | const char *filename = machine->initrd_filename; |
| 226 | uint64_t mem_size = info->ram_low_size ?: machine->ram_size; |
| 227 | void *fdt = machine->fdt; |
| 228 | hwaddr start, end; |
| 229 | ssize_t size; |
| 230 | |
| 231 | g_assert(filename != NULL); |
| 232 | |
| 233 | /* |
| 234 | * We want to put the initrd far enough into RAM that when the |
| 235 | * kernel is uncompressed it will not clobber the initrd. However |
| 236 | * on boards without much RAM we must ensure that we still leave |
| 237 | * enough room for a decent sized initrd, and on boards with large |
| 238 | * amounts of RAM, we put the initrd at 512MB to allow large kernels |
| 239 | * to boot. |
| 240 | * So for boards with less than 1GB of RAM we put the initrd |
| 241 | * halfway into RAM, and for boards with 1GB of RAM or more we put |
| 242 | * the initrd at 512MB. |
| 243 | */ |
| 244 | start = info->image_low_addr + MIN(mem_size / 2, 512 * MiB); |
| 245 | |
| 246 | size = load_ramdisk(filename, start, mem_size - start); |
| 247 | if (size == -1) { |
| 248 | size = load_image_targphys(filename, start, mem_size - start, NULL); |
| 249 | if (size == -1) { |
| 250 | error_report("could not load ramdisk '%s'", filename); |
| 251 | exit(1); |
| 252 | } |
| 253 | } |
| 254 | |
| 255 | info->initrd_start = start; |
| 256 | info->initrd_size = size; |
| 257 | |
| 258 | /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ |
| 259 | if (fdt) { |
| 260 | end = start + size; |
| 261 | qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-start", start); |
| 262 | qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-end", end); |
| 263 | } |
| 264 | } |
| 265 | |
| 266 | void riscv_load_kernel(MachineState *machine, |
| 267 | RISCVBootInfo *info, |
| 268 | vaddr kernel_start_addr, |
| 269 | bool load_initrd, |
| 270 | symbol_fn_t sym_cb) |
| 271 | { |
| 272 | uint64_t mem_size = info->ram_low_size ?: machine->ram_size; |
| 273 | const char *kernel_filename = machine->kernel_filename; |
| 274 | ssize_t kernel_size; |
| 275 | void *fdt = machine->fdt; |
| 276 | |
| 277 | g_assert(kernel_filename != NULL); |
| 278 | |
| 279 | /* |
| 280 | * NB: Use low address not ELF entry point to ensure that the fw_dynamic |
| 281 | * behaviour when loading an ELF matches the fw_payload, fw_jump and BBL |
| 282 | * behaviour, as well as fw_dynamic with a raw binary, all of which jump to |
| 283 | * the (expected) load address load address. This allows kernels to have |
| 284 | * separate SBI and ELF entry points (used by FreeBSD, for example). |
| 285 | */ |
| 286 | kernel_size = load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, NULL, |
| 287 | &info->image_low_addr, &info->image_high_addr, |
| 288 | NULL, ELFDATA2LSB, EM_RISCV, |
| 289 | 1, 0, NULL, true, sym_cb); |
| 290 | if (kernel_size > 0) { |
| 291 | info->kernel_size = kernel_size; |
| 292 | goto out; |
| 293 | } |
| 294 | |
| 295 | kernel_size = load_uimage_as(kernel_filename, &info->image_low_addr, |
| 296 | NULL, NULL, NULL, NULL, NULL); |
| 297 | if (kernel_size > 0) { |
| 298 | info->kernel_size = kernel_size; |
| 299 | info->image_high_addr = info->image_low_addr + kernel_size; |
| 300 | goto out; |
| 301 | } |
| 302 | |
| 303 | kernel_size = load_image_targphys_as(kernel_filename, kernel_start_addr, |
| 304 | mem_size, NULL, NULL); |
| 305 | if (kernel_size > 0) { |
| 306 | info->kernel_size = kernel_size; |
| 307 | info->image_low_addr = kernel_start_addr; |
| 308 | info->image_high_addr = info->image_low_addr + kernel_size; |
| 309 | goto out; |
| 310 | } |
| 311 | |
| 312 | error_report("could not load kernel '%s'", kernel_filename); |
| 313 | exit(1); |
| 314 | |
| 315 | out: |
| 316 | /* |
| 317 | * For 32 bit CPUs 'image_low_addr' can be sign-extended by |
| 318 | * load_elf_ram_sym(). |
| 319 | */ |
| 320 | if (info->is_32bit) { |
| 321 | info->image_low_addr = extract64(info->image_low_addr, 0, 32); |
| 322 | } |
| 323 | |
| 324 | if (load_initrd && machine->initrd_filename) { |
| 325 | riscv_load_initrd(machine, info); |
| 326 | } |
| 327 | |
| 328 | if (fdt && machine->kernel_cmdline && *machine->kernel_cmdline) { |
| 329 | qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", |
| 330 | machine->kernel_cmdline); |
| 331 | } |
| 332 | } |
| 333 | |
| 334 | /* |
| 335 | * This function makes an assumption that the DRAM interval |
| 336 | * 'dram_base' + 'dram_size' is contiguous. |
| 337 | * |
| 338 | * Considering that 'dram_end' is the lowest value between |
| 339 | * the end of the DRAM block and MachineState->ram_size, the |
| 340 | * FDT location will vary according to 'dram_base': |
| 341 | * |
| 342 | * - if 'dram_base' is less that 3072 MiB, the FDT will be |
| 343 | * put at the lowest value between 3072 MiB and 'dram_end'; |
| 344 | * |
| 345 | * - if 'dram_base' is higher than 3072 MiB, the FDT will be |
| 346 | * put at 'dram_end'. |
| 347 | * |
| 348 | * The FDT is fdt_packed() during the calculation. |
| 349 | */ |
| 350 | uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size, |
| 351 | MachineState *ms, RISCVBootInfo *info) |
| 352 | { |
| 353 | int ret = fdt_pack(ms->fdt); |
| 354 | hwaddr dram_end, temp; |
| 355 | int fdtsize; |
| 356 | uint64_t dtb_start, dtb_start_limit; |
| 357 | |
| 358 | /* Should only fail if we've built a corrupted tree */ |
| 359 | g_assert(ret == 0); |
| 360 | |
| 361 | fdtsize = fdt_totalsize(ms->fdt); |
| 362 | if (fdtsize <= 0) { |
| 363 | error_report("invalid device-tree"); |
| 364 | exit(1); |
| 365 | } |
| 366 | |
| 367 | if (info->initrd_size) { |
| 368 | /* If initrd is successfully loaded, place DTB after it. */ |
| 369 | dtb_start_limit = info->initrd_start + info->initrd_size; |
| 370 | } else if (info->kernel_size) { |
| 371 | /* If only kernel is successfully loaded, place DTB after it. */ |
| 372 | dtb_start_limit = info->image_high_addr; |
| 373 | } else { |
| 374 | /* Otherwise, do not check DTB overlapping */ |
| 375 | dtb_start_limit = 0; |
| 376 | } |
| 377 | |
| 378 | /* |
| 379 | * A dram_size == 0, usually from a MemMapEntry[].size element, |
| 380 | * means that the DRAM block goes all the way to ms->ram_size. |
| 381 | */ |
| 382 | dram_end = dram_base; |
| 383 | dram_end += dram_size ? MIN(ms->ram_size, dram_size) : ms->ram_size; |
| 384 | |
| 385 | /* |
| 386 | * We should put fdt as far as possible to avoid kernel/initrd overwriting |
| 387 | * its content. But it should be addressable by 32 bit system as well in RV32. |
| 388 | * Thus, put it near to the end of dram in RV64, and put it near to the end |
| 389 | * of dram or 3GB whichever is lesser in RV32. |
| 390 | */ |
| 391 | if (!info->is_32bit) { |
| 392 | temp = dram_end; |
| 393 | } else { |
| 394 | temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end; |
| 395 | } |
| 396 | |
| 397 | dtb_start = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); |
| 398 | |
| 399 | if (dtb_start_limit && (dtb_start < dtb_start_limit)) { |
| 400 | error_report("Not enough memory to place DTB after kernel/initrd"); |
| 401 | exit(1); |
| 402 | } |
| 403 | |
| 404 | return dtb_start; |
| 405 | } |
| 406 | |
| 407 | /* |
| 408 | * 'fdt_addr' is received as hwaddr because boards might put |
| 409 | * the FDT beyond 32-bit addressing boundary. |
| 410 | */ |
| 411 | void riscv_load_fdt(hwaddr fdt_addr, void *fdt) |
| 412 | { |
| 413 | uint32_t fdtsize = fdt_totalsize(fdt); |
| 414 | |
| 415 | /* copy in the device tree */ |
| 416 | rom_add_blob_fixed_as("fdt", fdt, fdtsize, fdt_addr, |
| 417 | &address_space_memory); |
| 418 | qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds, |
| 419 | rom_ptr_for_as(&address_space_memory, fdt_addr, fdtsize)); |
| 420 | } |
| 421 | |
| 422 | void riscv_rom_copy_firmware_info(MachineState *machine, |
| 423 | RISCVHartArrayState *harts, |
| 424 | hwaddr rom_base, hwaddr rom_size, |
| 425 | uint32_t reset_vec_size, |
| 426 | uint64_t kernel_entry) |
| 427 | { |
| 428 | struct fw_dynamic_info32 dinfo32; |
| 429 | struct fw_dynamic_info64 dinfo64; |
| 430 | void *dinfo_ptr = NULL; |
| 431 | size_t dinfo_len; |
| 432 | const bool rv32 = riscv_is_32bit(harts); |
| 433 | const bool be = harts->harts[0].cfg.big_endian; |
| 434 | |
| 435 | if (rv32) { |
| 436 | dinfo32.magic = be ? cpu_to_be32(FW_DYNAMIC_INFO_MAGIC_VALUE) |
| 437 | : cpu_to_le32(FW_DYNAMIC_INFO_MAGIC_VALUE); |
| 438 | dinfo32.version = be ? cpu_to_be32(FW_DYNAMIC_INFO_VERSION) |
| 439 | : cpu_to_le32(FW_DYNAMIC_INFO_VERSION); |
| 440 | dinfo32.next_mode = be ? cpu_to_be32(FW_DYNAMIC_INFO_NEXT_MODE_S) |
| 441 | : cpu_to_le32(FW_DYNAMIC_INFO_NEXT_MODE_S); |
| 442 | dinfo32.next_addr = be ? cpu_to_be32(kernel_entry) |
| 443 | : cpu_to_le32(kernel_entry); |
| 444 | dinfo32.options = 0; |
| 445 | dinfo32.boot_hart = 0; |
| 446 | dinfo_ptr = &dinfo32; |
| 447 | dinfo_len = sizeof(dinfo32); |
| 448 | } else { |
| 449 | dinfo64.magic = be ? cpu_to_be64(FW_DYNAMIC_INFO_MAGIC_VALUE) |
| 450 | : cpu_to_le64(FW_DYNAMIC_INFO_MAGIC_VALUE); |
| 451 | dinfo64.version = be ? cpu_to_be64(FW_DYNAMIC_INFO_VERSION) |
| 452 | : cpu_to_le64(FW_DYNAMIC_INFO_VERSION); |
| 453 | dinfo64.next_mode = be ? cpu_to_be64(FW_DYNAMIC_INFO_NEXT_MODE_S) |
| 454 | : cpu_to_le64(FW_DYNAMIC_INFO_NEXT_MODE_S); |
| 455 | dinfo64.next_addr = be ? cpu_to_be64(kernel_entry) |
| 456 | : cpu_to_le64(kernel_entry); |
| 457 | dinfo64.options = 0; |
| 458 | dinfo64.boot_hart = 0; |
| 459 | dinfo_ptr = &dinfo64; |
| 460 | dinfo_len = sizeof(dinfo64); |
| 461 | } |
| 462 | |
| 463 | /** |
| 464 | * copy the dynamic firmware info. This information is specific to |
| 465 | * OpenSBI but doesn't break any other firmware as long as they don't |
| 466 | * expect any certain value in "a2" register. |
| 467 | */ |
| 468 | if (dinfo_len > (rom_size - reset_vec_size)) { |
| 469 | error_report("not enough space to store dynamic firmware info"); |
| 470 | exit(1); |
| 471 | } |
| 472 | |
| 473 | rom_add_blob_fixed_as("mrom.finfo", |
| 474 | dinfo_ptr, |
| 475 | dinfo_len, |
| 476 | rom_base + reset_vec_size, |
| 477 | &address_space_memory); |
| 478 | } |
| 479 | |
| 480 | #define CODE_WORDS 6 |
| 481 | #define DATA_WORDS 4 |
| 482 | |
| 483 | void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, |
| 484 | hwaddr start_addr, |
| 485 | hwaddr rom_base, hwaddr rom_size, |
| 486 | uint64_t kernel_entry, |
| 487 | uint64_t fdt_load_addr) |
| 488 | { |
| 489 | const bool rv32 = riscv_is_32bit(harts); |
| 490 | const bool big_endian = harts->harts[0].cfg.big_endian; |
| 491 | uint32_t reset_vec[CODE_WORDS + DATA_WORDS]; |
| 492 | |
| 493 | /* .text (RISC-V instructions are always little-endian) */ |
| 494 | reset_vec[0] = const_le32(0x00000297); /* 1: auipc t0, %pcrel_hi(fw_dyn) */ |
| 495 | reset_vec[1] = const_le32(0x02828613); /* addi a2, t0, %pcrel_lo(1b) */ |
| 496 | reset_vec[2] = const_le32(0xf1402573); /* csrr a0, mhartid */ |
| 497 | if (harts->harts[0].cfg.ext_zicsr) { |
| 498 | reset_vec[2] = const_le32(0xf1402573); /* csrr a0, mhartid */ |
| 499 | } else { |
| 500 | /* |
| 501 | * The Zicsr extension has been disabled, so let's ensure we don't |
| 502 | * run the CSR instruction. Let's fill the address with a non |
| 503 | * compressed nop. |
| 504 | */ |
| 505 | reset_vec[2] = const_le32(0x00000013); /* addi x0, x0, 0 */ |
| 506 | } |
| 507 | if (rv32) { |
| 508 | reset_vec[3] = const_le32(0x0202a583); /* lw a1, 32(t0) */ |
| 509 | reset_vec[4] = const_le32(0x0182a283); /* lw t0, 24(t0) */ |
| 510 | } else { |
| 511 | reset_vec[3] = const_le32(0x0202b583); /* ld a1, 32(t0) */ |
| 512 | reset_vec[4] = const_le32(0x0182b283); /* ld t0, 24(t0) */ |
| 513 | } |
| 514 | reset_vec[5] = const_le32(0x00028067); /* jr t0 */ |
| 515 | |
| 516 | /* .data (must match the firmware's data endianness) */ |
| 517 | if (big_endian) { |
| 518 | stq_be_p(&reset_vec[6], start_addr); /* start: .dword */ |
| 519 | stq_be_p(&reset_vec[8], fdt_load_addr); /* fdt_laddr: .dword */ |
| 520 | } else { |
| 521 | stq_le_p(&reset_vec[6], start_addr); |
| 522 | stq_le_p(&reset_vec[8], fdt_load_addr); |
| 523 | } |
| 524 | |
| 525 | rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), |
| 526 | rom_base, &address_space_memory); |
| 527 | riscv_rom_copy_firmware_info(machine, harts, |
| 528 | rom_base, rom_size, |
| 529 | sizeof(reset_vec), |
| 530 | kernel_entry); |
| 531 | } |
| 532 | |
| 533 | void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr) |
| 534 | { |
| 535 | CPUState *cs; |
| 536 | |
| 537 | CPU_FOREACH(cs) { |
| 538 | CPURISCVState *env = cpu_env(cs); |
| 539 | |
| 540 | env->kernel_addr = kernel_addr; |
| 541 | env->fdt_addr = fdt_addr; |
| 542 | } |
| 543 | } |
| 544 | |
| 545 | void riscv_setup_firmware_boot(MachineState *machine) |
| 546 | { |
| 547 | if (machine->kernel_filename) { |
| 548 | FWCfgState *fw_cfg; |
| 549 | fw_cfg = fw_cfg_find(); |
| 550 | |
| 551 | assert(fw_cfg); |
| 552 | /* |
| 553 | * Expose the kernel, the command line, and the initrd in fw_cfg. |
| 554 | * We don't process them here at all, it's all left to the |
| 555 | * firmware. |
| 556 | */ |
| 557 | load_image_to_fw_cfg(fw_cfg, |
| 558 | FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, |
| 559 | machine->kernel_filename, |
| 560 | true); |
| 561 | load_image_to_fw_cfg(fw_cfg, |
| 562 | FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, |
| 563 | machine->initrd_filename, false); |
| 564 | |
| 565 | if (machine->kernel_cmdline) { |
| 566 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, |
| 567 | strlen(machine->kernel_cmdline) + 1); |
| 568 | fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, |
| 569 | machine->kernel_cmdline); |
| 570 | } |
| 571 | } |
| 572 | } |