| 1 | riscv_ss = ss.source_set() |
| 2 | riscv_ss.add(files('aia.c')) |
| 3 | riscv_ss.add(files('boot.c')) |
| 4 | riscv_ss.add(files('fdt-common.c')) |
| 5 | riscv_ss.add(when: 'CONFIG_RISCV_NUMA', if_true: files('numa.c')) |
| 6 | riscv_ss.add(files('riscv_hart.c')) |
| 7 | riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c')) |
| 8 | riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c')) |
| 9 | riscv_ss.add(when: 'CONFIG_SHAKTI_C', if_true: files('shakti_c.c')) |
| 10 | riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c')) |
| 11 | riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) |
| 12 | riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c')) |
| 13 | riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c')) |
| 14 | riscv_ss.add(when: 'CONFIG_TENSTORRENT', if_true: files('tt_atlantis.c')) |
| 15 | riscv_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c')) |
| 16 | riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files( |
| 17 | 'riscv-iommu.c', 'riscv-iommu-pci.c', 'riscv-iommu-sys.c', 'riscv-iommu-hpm.c')) |
| 18 | riscv_ss.add(when: 'CONFIG_MICROBLAZE_V', if_true: files('microblaze-v-generic.c')) |
| 19 | riscv_ss.add(when: 'CONFIG_XIANGSHAN_KUNMINGHU', if_true: files('xiangshan_kmh.c')) |
| 20 | riscv_ss.add(when: 'CONFIG_RISCV_MIPS_CPS', if_true: files('cps.c')) |
| 21 | riscv_ss.add(when: 'CONFIG_MIPS_BOSTON_AIA', if_true: files('boston-aia.c')) |
| 22 | riscv_ss.add(when: 'CONFIG_K230', if_true: files('k230.c')) |
| 23 | |
| 24 | hw_arch += {'riscv': riscv_ss} |