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1 /*
2 * QEMU model of Microblaze V generic board.
3 *
4 * based on hw/microblaze/petalogix_ml605_mmu.c
5 *
6 * Copyright (c) 2011 Michal Simek <monstr@monstr.eu>
7 * Copyright (c) 2011 PetaLogix
8 * Copyright (c) 2009 Edgar E. Iglesias.
9 * Copyright (C) 2024, Advanced Micro Devices, Inc.
10 * SPDX-License-Identifier: GPL-2.0-or-later
11 *
12 * Written by Sai Pavan Boddu <sai.pavan.boddu@amd.com
13 * and by Michal Simek <michal.simek@amd.com>.
14 */
15
16 #include "qemu/osdep.h"
17 #include "qemu/units.h"
18 #include "qapi/error.h"
19 #include "target/riscv/cpu.h"
20 #include "hw/core/sysbus.h"
21 #include "system/system.h"
22 #include "net/net.h"
23 #include "hw/core/boards.h"
24 #include "hw/char/serial-mm.h"
25 #include "system/address-spaces.h"
26 #include "hw/char/xilinx_uartlite.h"
27 #include "hw/misc/unimp.h"
28 #include "hw/riscv/machines-qom.h"
29
30 #define LMB_BRAM_SIZE (128 * KiB)
31 #define MEMORY_BASEADDR 0x80000000
32 #define INTC_BASEADDR 0x41200000
33 #define TIMER_BASEADDR 0x41c00000
34 #define TIMER_BASEADDR2 0x41c10000
35 #define UARTLITE_BASEADDR 0x40600000
36 #define ETHLITE_BASEADDR 0x40e00000
37 #define UART16550_BASEADDR 0x44a10000
38 #define AXIENET_BASEADDR 0x40c00000
39 #define AXIDMA_BASEADDR 0x41e00000
40 #define GPIO_BASEADDR 0x40000000
41 #define GPIO_BASEADDR2 0x40010000
42 #define GPIO_BASEADDR3 0x40020000
43 #define I2C_BASEADDR 0x40800000
44 #define QSPI_BASEADDR 0x44a00000
45
46 #define TIMER_IRQ 0
47 #define UARTLITE_IRQ 1
48 #define UART16550_IRQ 4
49 #define ETHLITE_IRQ 5
50 #define TIMER_IRQ2 6
51 #define AXIENET_IRQ 7
52 #define AXIDMA_IRQ1 8
53 #define AXIDMA_IRQ0 9
54
55 static void mb_v_generic_init(MachineState *machine)
56 {
57 ram_addr_t ram_size = machine->ram_size;
58 DeviceState *dev, *dma, *eth0;
59 Object *ds, *cs;
60 int i;
61 RISCVCPU *cpu;
62 hwaddr ddr_base = MEMORY_BASEADDR;
63 MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1);
64 MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
65 qemu_irq irq[32];
66 MemoryRegion *sysmem = get_system_memory();
67
68 cpu = RISCV_CPU(object_new(machine->cpu_type));
69 object_property_set_bool(OBJECT(cpu), "h", false, NULL);
70 object_property_set_bool(OBJECT(cpu), "d", false, NULL);
71 qdev_realize(DEVICE(cpu), NULL, &error_abort);
72 /* Attach emulated BRAM through the LMB. */
73 memory_region_init_ram(phys_lmb_bram, NULL,
74 "mb_v.lmb_bram", LMB_BRAM_SIZE,
75 &error_fatal);
76 memory_region_add_subregion(sysmem, 0x00000000, phys_lmb_bram);
77
78 memory_region_init_ram(phys_ram, NULL, "mb_v.ram",
79 ram_size, &error_fatal);
80 memory_region_add_subregion(sysmem, ddr_base, phys_ram);
81
82 dev = qdev_new("xlnx.xps-intc");
83 qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_LITTLE);
84 qdev_prop_set_uint32(dev, "kind-of-intr",
85 1 << UARTLITE_IRQ);
86 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
87 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
88 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
89 qdev_get_gpio_in(DEVICE(cpu), 11));
90 for (i = 0; i < 32; i++) {
91 irq[i] = qdev_get_gpio_in(dev, i);
92 }
93
94 /* Uartlite */
95 dev = qdev_new(TYPE_XILINX_UARTLITE);
96 qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_LITTLE);
97 qdev_prop_set_chr(dev, "chardev", serial_hd(0));
98 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
99 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, UARTLITE_BASEADDR);
100 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[UARTLITE_IRQ]);
101
102 /* Full uart */
103 serial_mm_init(sysmem, UART16550_BASEADDR + 0x1000, 2,
104 irq[UART16550_IRQ], 115200, serial_hd(1),
105 DEVICE_LITTLE_ENDIAN);
106
107 /* 2 timers at irq 0 @ 100 Mhz. */
108 dev = qdev_new("xlnx.xps-timer");
109 qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_LITTLE);
110 qdev_prop_set_uint32(dev, "one-timer-only", 0);
111 qdev_prop_set_uint32(dev, "clock-frequency", 100000000);
112 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
113 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR);
114 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);
115
116 /* 2 timers at irq 3 @ 100 Mhz. */
117 dev = qdev_new("xlnx.xps-timer");
118 qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_LITTLE);
119 qdev_prop_set_uint32(dev, "one-timer-only", 0);
120 qdev_prop_set_uint32(dev, "clock-frequency", 100000000);
121 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
122 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR2);
123 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ2]);
124
125 /* Emaclite */
126 dev = qdev_new("xlnx.xps-ethernetlite");
127 qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_LITTLE);
128 qemu_configure_nic_device(dev, true, NULL);
129 qdev_prop_set_uint32(dev, "tx-ping-pong", 0);
130 qdev_prop_set_uint32(dev, "rx-ping-pong", 0);
131 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
132 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ETHLITE_BASEADDR);
133 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[ETHLITE_IRQ]);
134
135 /* axi ethernet and dma initialization. */
136 eth0 = qdev_new("xlnx.axi-ethernet");
137 dma = qdev_new("xlnx.axi-dma");
138
139 /* FIXME: attach to the sysbus instead */
140 object_property_add_child(qdev_get_machine(), "xilinx-eth", OBJECT(eth0));
141 object_property_add_child(qdev_get_machine(), "xilinx-dma", OBJECT(dma));
142
143 ds = object_property_get_link(OBJECT(dma),
144 "axistream-connected-target", NULL);
145 cs = object_property_get_link(OBJECT(dma),
146 "axistream-control-connected-target", NULL);
147 qemu_configure_nic_device(eth0, true, NULL);
148 qdev_prop_set_uint32(eth0, "rxmem", 0x1000);
149 qdev_prop_set_uint32(eth0, "txmem", 0x1000);
150 object_property_set_link(OBJECT(eth0), "axistream-connected", ds,
151 &error_abort);
152 object_property_set_link(OBJECT(eth0), "axistream-control-connected", cs,
153 &error_abort);
154 sysbus_realize_and_unref(SYS_BUS_DEVICE(eth0), &error_fatal);
155 sysbus_mmio_map(SYS_BUS_DEVICE(eth0), 0, AXIENET_BASEADDR);
156 sysbus_connect_irq(SYS_BUS_DEVICE(eth0), 0, irq[AXIENET_IRQ]);
157
158 ds = object_property_get_link(OBJECT(eth0),
159 "axistream-connected-target", NULL);
160 cs = object_property_get_link(OBJECT(eth0),
161 "axistream-control-connected-target", NULL);
162 qdev_prop_set_uint32(dma, "freqhz", 100000000);
163 object_property_set_link(OBJECT(dma), "axistream-connected", ds,
164 &error_abort);
165 object_property_set_link(OBJECT(dma), "axistream-control-connected", cs,
166 &error_abort);
167 sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal);
168 sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, AXIDMA_BASEADDR);
169 sysbus_connect_irq(SYS_BUS_DEVICE(dma), 0, irq[AXIDMA_IRQ0]);
170 sysbus_connect_irq(SYS_BUS_DEVICE(dma), 1, irq[AXIDMA_IRQ1]);
171
172 /* unimplemented devices */
173 create_unimplemented_device("gpio", GPIO_BASEADDR, 0x10000);
174 create_unimplemented_device("gpio2", GPIO_BASEADDR2, 0x10000);
175 create_unimplemented_device("gpio3", GPIO_BASEADDR3, 0x10000);
176 create_unimplemented_device("i2c", I2C_BASEADDR, 0x10000);
177 create_unimplemented_device("qspi", QSPI_BASEADDR, 0x10000);
178 }
179
180 static void mb_v_generic_machine_init(MachineClass *mc)
181 {
182 mc->desc = "AMD Microblaze-V generic platform";
183 mc->init = mb_v_generic_init;
184 mc->min_cpus = 1;
185 mc->max_cpus = 1;
186 mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
187 mc->default_cpus = 1;
188 }
189
190 DEFINE_MACHINE_RISCV32_64("amd-microblaze-v-generic", mb_v_generic_machine_init)