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1 /*
2 * QEMU RISC-V Board Compatible with OpenTitan FPGA platform
3 *
4 * Copyright (c) 2020 Western Digital
5 *
6 * Provides a board compatible with the OpenTitan FPGA platform:
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "qemu/cutils.h"
23 #include "hw/riscv/opentitan.h"
24 #include "qapi/error.h"
25 #include "qemu/error-report.h"
26 #include "hw/core/boards.h"
27 #include "hw/misc/unimp.h"
28 #include "hw/riscv/boot.h"
29 #include "hw/riscv/machines-qom.h"
30 #include "qemu/units.h"
31 #include "system/system.h"
32 #include "system/address-spaces.h"
33
34 /*
35 * This version of the OpenTitan machine currently supports
36 * OpenTitan RTL version:
37 * <lowRISC/opentitan@565e4af39760a123c59a184aa2f5812a961fde47>
38 *
39 * MMIO mapping as per (specified commit):
40 * lowRISC/opentitan: hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h
41 */
42 static const MemMapEntry ibex_memmap[] = {
43 [IBEX_DEV_ROM] = { 0x00008000, 0x8000 },
44 [IBEX_DEV_RAM] = { 0x10000000, 0x20000 },
45 [IBEX_DEV_FLASH] = { 0x20000000, 0x100000 },
46 [IBEX_DEV_UART] = { 0x40000000, 0x40 },
47 [IBEX_DEV_GPIO] = { 0x40040000, 0x40 },
48 [IBEX_DEV_SPI_DEVICE] = { 0x40050000, 0x2000 },
49 [IBEX_DEV_I2C] = { 0x40080000, 0x80 },
50 [IBEX_DEV_PATTGEN] = { 0x400e0000, 0x40 },
51 [IBEX_DEV_TIMER] = { 0x40100000, 0x200 },
52 [IBEX_DEV_OTP_CTRL] = { 0x40130000, 0x2000 },
53 [IBEX_DEV_LC_CTRL] = { 0x40140000, 0x100 },
54 [IBEX_DEV_ALERT_HANDLER] = { 0x40150000, 0x800 },
55 [IBEX_DEV_SPI_HOST0] = { 0x40300000, 0x40 },
56 [IBEX_DEV_SPI_HOST1] = { 0x40310000, 0x40 },
57 [IBEX_DEV_USBDEV] = { 0x40320000, 0x1000 },
58 [IBEX_DEV_PWRMGR] = { 0x40400000, 0x80 },
59 [IBEX_DEV_RSTMGR] = { 0x40410000, 0x80 },
60 [IBEX_DEV_CLKMGR] = { 0x40420000, 0x80 },
61 [IBEX_DEV_PINMUX] = { 0x40460000, 0x1000 },
62 [IBEX_DEV_AON_TIMER] = { 0x40470000, 0x40 },
63 [IBEX_DEV_SENSOR_CTRL] = { 0x40490000, 0x40 },
64 [IBEX_DEV_FLASH_CTRL] = { 0x41000000, 0x200 },
65 [IBEX_DEV_AES] = { 0x41100000, 0x100 },
66 [IBEX_DEV_HMAC] = { 0x41110000, 0x1000 },
67 [IBEX_DEV_KMAC] = { 0x41120000, 0x1000 },
68 [IBEX_DEV_OTBN] = { 0x41130000, 0x10000 },
69 [IBEX_DEV_KEYMGR] = { 0x41140000, 0x100 },
70 [IBEX_DEV_CSRNG] = { 0x41150000, 0x80 },
71 [IBEX_DEV_ENTROPY] = { 0x41160000, 0x100 },
72 [IBEX_DEV_EDNO] = { 0x41170000, 0x80 },
73 [IBEX_DEV_EDN1] = { 0x41180000, 0x80 },
74 [IBEX_DEV_SRAM_CTRL] = { 0x411c0000, 0x20 },
75 [IBEX_DEV_IBEX_CFG] = { 0x411f0000, 0x100 },
76 [IBEX_DEV_PLIC] = { 0x48000000, 0x8000000 },
77 [IBEX_DEV_FLASH_VIRTUAL] = { 0x80000000, 0x80000 },
78 };
79
80 static void opentitan_machine_init(MachineState *machine)
81 {
82 MachineClass *mc = MACHINE_GET_CLASS(machine);
83 OpenTitanState *s = OPENTITAN_MACHINE(machine);
84 const MemMapEntry *memmap = ibex_memmap;
85 MemoryRegion *sys_mem = get_system_memory();
86 RISCVBootInfo boot_info;
87
88 if (machine->ram_size != mc->default_ram_size) {
89 char *sz = size_to_str(mc->default_ram_size);
90 error_report("Invalid RAM size, should be %s", sz);
91 g_free(sz);
92 exit(EXIT_FAILURE);
93 }
94
95 /* Initialize SoC */
96 object_initialize_child(OBJECT(machine), "soc", &s->soc,
97 TYPE_RISCV_IBEX_SOC);
98 qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
99
100 memory_region_add_subregion(sys_mem,
101 memmap[IBEX_DEV_RAM].base, machine->ram);
102
103 riscv_boot_info_init(&boot_info, &s->soc.cpus);
104
105 if (machine->firmware) {
106 hwaddr firmware_load_addr = memmap[IBEX_DEV_RAM].base;
107 riscv_load_firmware(machine, &boot_info, machine->firmware,
108 &firmware_load_addr, NULL);
109 }
110
111 if (machine->kernel_filename) {
112 riscv_load_kernel(machine, &boot_info,
113 memmap[IBEX_DEV_RAM].base,
114 false, NULL);
115 }
116 }
117
118 static void opentitan_machine_class_init(ObjectClass *oc, const void *data)
119 {
120 MachineClass *mc = MACHINE_CLASS(oc);
121
122 mc->desc = "RISC-V Board compatible with OpenTitan";
123 mc->init = opentitan_machine_init;
124 mc->max_cpus = 1;
125 mc->default_cpu_type = TYPE_RISCV_CPU_IBEX;
126 mc->default_ram_id = "riscv.lowrisc.ibex.ram";
127 mc->default_ram_size = ibex_memmap[IBEX_DEV_RAM].size;
128 }
129
130 static void lowrisc_ibex_soc_init(Object *obj)
131 {
132 LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj);
133
134 object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
135
136 object_initialize_child(obj, "plic", &s->plic, TYPE_SIFIVE_PLIC);
137
138 object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART);
139
140 object_initialize_child(obj, "timer", &s->timer, TYPE_IBEX_TIMER);
141
142 for (int i = 0; i < OPENTITAN_NUM_SPI_HOSTS; i++) {
143 object_initialize_child(obj, "spi_host[*]", &s->spi_host[i],
144 TYPE_IBEX_SPI_HOST);
145 }
146 }
147
148 static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
149 {
150 const MemMapEntry *memmap = ibex_memmap;
151 DeviceState *dev;
152 SysBusDevice *busdev;
153 MachineState *ms = MACHINE(qdev_get_machine());
154 LowRISCIbexSoCState *s = RISCV_IBEX_SOC(dev_soc);
155 MemoryRegion *sys_mem = get_system_memory();
156 int i;
157
158 object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
159 &error_abort);
160 object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
161 &error_abort);
162 object_property_set_int(OBJECT(&s->cpus), "resetvec", s->resetvec,
163 &error_abort);
164 sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);
165
166 /* Boot ROM */
167 memory_region_init_rom(&s->rom, OBJECT(dev_soc), "riscv.lowrisc.ibex.rom",
168 memmap[IBEX_DEV_ROM].size, &error_fatal);
169 memory_region_add_subregion(sys_mem,
170 memmap[IBEX_DEV_ROM].base, &s->rom);
171
172 /* Flash memory */
173 memory_region_init_rom(&s->flash_mem, OBJECT(dev_soc), "riscv.lowrisc.ibex.flash",
174 memmap[IBEX_DEV_FLASH].size, &error_fatal);
175 memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc),
176 "riscv.lowrisc.ibex.flash_virtual", &s->flash_mem, 0,
177 memmap[IBEX_DEV_FLASH_VIRTUAL].size);
178 memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH].base,
179 &s->flash_mem);
180 memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH_VIRTUAL].base,
181 &s->flash_alias);
182
183 /* PLIC */
184 qdev_prop_set_string(DEVICE(&s->plic), "hart-config", "M");
185 qdev_prop_set_uint32(DEVICE(&s->plic), "num-sources", 180);
186 qdev_prop_set_uint32(DEVICE(&s->plic), "num-priorities", 3);
187 qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000);
188 qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000);
189 qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 32);
190 qdev_prop_set_uint32(DEVICE(&s->plic), "context-base", 0x200000);
191 qdev_prop_set_uint32(DEVICE(&s->plic), "context-stride", 8);
192 qdev_prop_set_uint32(DEVICE(&s->plic), "aperture-size", memmap[IBEX_DEV_PLIC].size);
193
194 if (!sysbus_realize(SYS_BUS_DEVICE(&s->plic), errp)) {
195 return;
196 }
197 sysbus_mmio_map(SYS_BUS_DEVICE(&s->plic), 0, memmap[IBEX_DEV_PLIC].base);
198
199 for (i = 0; i < ms->smp.cpus; i++) {
200 CPUState *cpu = qemu_get_cpu(i);
201
202 qdev_connect_gpio_out(DEVICE(&s->plic), ms->smp.cpus + i,
203 qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
204 }
205
206 /* UART */
207 qdev_prop_set_chr(DEVICE(&(s->uart)), "chardev", serial_hd(0));
208 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) {
209 return;
210 }
211 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, memmap[IBEX_DEV_UART].base);
212 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
213 0, qdev_get_gpio_in(DEVICE(&s->plic),
214 IBEX_UART0_TX_WATERMARK_IRQ));
215 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
216 1, qdev_get_gpio_in(DEVICE(&s->plic),
217 IBEX_UART0_RX_WATERMARK_IRQ));
218 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
219 2, qdev_get_gpio_in(DEVICE(&s->plic),
220 IBEX_UART0_TX_EMPTY_IRQ));
221 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
222 3, qdev_get_gpio_in(DEVICE(&s->plic),
223 IBEX_UART0_RX_OVERFLOW_IRQ));
224
225 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer), errp)) {
226 return;
227 }
228 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, memmap[IBEX_DEV_TIMER].base);
229 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer),
230 0, qdev_get_gpio_in(DEVICE(&s->plic),
231 IBEX_TIMER_TIMEREXPIRED0_0));
232 qdev_connect_gpio_out(DEVICE(&s->timer), 0,
233 qdev_get_gpio_in(DEVICE(qemu_get_cpu(0)),
234 IRQ_M_TIMER));
235
236 /* SPI-Hosts */
237 for (i = 0; i < OPENTITAN_NUM_SPI_HOSTS; ++i) {
238 dev = DEVICE(&(s->spi_host[i]));
239 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi_host[i]), errp)) {
240 return;
241 }
242 busdev = SYS_BUS_DEVICE(dev);
243 sysbus_mmio_map(busdev, 0, memmap[IBEX_DEV_SPI_HOST0 + i].base);
244
245 switch (i) {
246 case OPENTITAN_SPI_HOST0:
247 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->plic),
248 IBEX_SPI_HOST0_ERR_IRQ));
249 sysbus_connect_irq(busdev, 1, qdev_get_gpio_in(DEVICE(&s->plic),
250 IBEX_SPI_HOST0_SPI_EVENT_IRQ));
251 break;
252 case OPENTITAN_SPI_HOST1:
253 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->plic),
254 IBEX_SPI_HOST1_ERR_IRQ));
255 sysbus_connect_irq(busdev, 1, qdev_get_gpio_in(DEVICE(&s->plic),
256 IBEX_SPI_HOST1_SPI_EVENT_IRQ));
257 break;
258 }
259 }
260
261 create_unimplemented_device("riscv.lowrisc.ibex.gpio",
262 memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);
263 create_unimplemented_device("riscv.lowrisc.ibex.spi_device",
264 memmap[IBEX_DEV_SPI_DEVICE].base, memmap[IBEX_DEV_SPI_DEVICE].size);
265 create_unimplemented_device("riscv.lowrisc.ibex.i2c",
266 memmap[IBEX_DEV_I2C].base, memmap[IBEX_DEV_I2C].size);
267 create_unimplemented_device("riscv.lowrisc.ibex.pattgen",
268 memmap[IBEX_DEV_PATTGEN].base, memmap[IBEX_DEV_PATTGEN].size);
269 create_unimplemented_device("riscv.lowrisc.ibex.sensor_ctrl",
270 memmap[IBEX_DEV_SENSOR_CTRL].base, memmap[IBEX_DEV_SENSOR_CTRL].size);
271 create_unimplemented_device("riscv.lowrisc.ibex.otp_ctrl",
272 memmap[IBEX_DEV_OTP_CTRL].base, memmap[IBEX_DEV_OTP_CTRL].size);
273 create_unimplemented_device("riscv.lowrisc.ibex.lc_ctrl",
274 memmap[IBEX_DEV_LC_CTRL].base, memmap[IBEX_DEV_LC_CTRL].size);
275 create_unimplemented_device("riscv.lowrisc.ibex.pwrmgr",
276 memmap[IBEX_DEV_PWRMGR].base, memmap[IBEX_DEV_PWRMGR].size);
277 create_unimplemented_device("riscv.lowrisc.ibex.rstmgr",
278 memmap[IBEX_DEV_RSTMGR].base, memmap[IBEX_DEV_RSTMGR].size);
279 create_unimplemented_device("riscv.lowrisc.ibex.clkmgr",
280 memmap[IBEX_DEV_CLKMGR].base, memmap[IBEX_DEV_CLKMGR].size);
281 create_unimplemented_device("riscv.lowrisc.ibex.pinmux",
282 memmap[IBEX_DEV_PINMUX].base, memmap[IBEX_DEV_PINMUX].size);
283 create_unimplemented_device("riscv.lowrisc.ibex.aon_timer",
284 memmap[IBEX_DEV_AON_TIMER].base, memmap[IBEX_DEV_AON_TIMER].size);
285 create_unimplemented_device("riscv.lowrisc.ibex.usbdev",
286 memmap[IBEX_DEV_USBDEV].base, memmap[IBEX_DEV_USBDEV].size);
287 create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl",
288 memmap[IBEX_DEV_FLASH_CTRL].base, memmap[IBEX_DEV_FLASH_CTRL].size);
289 create_unimplemented_device("riscv.lowrisc.ibex.aes",
290 memmap[IBEX_DEV_AES].base, memmap[IBEX_DEV_AES].size);
291 create_unimplemented_device("riscv.lowrisc.ibex.hmac",
292 memmap[IBEX_DEV_HMAC].base, memmap[IBEX_DEV_HMAC].size);
293 create_unimplemented_device("riscv.lowrisc.ibex.kmac",
294 memmap[IBEX_DEV_KMAC].base, memmap[IBEX_DEV_KMAC].size);
295 create_unimplemented_device("riscv.lowrisc.ibex.keymgr",
296 memmap[IBEX_DEV_KEYMGR].base, memmap[IBEX_DEV_KEYMGR].size);
297 create_unimplemented_device("riscv.lowrisc.ibex.csrng",
298 memmap[IBEX_DEV_CSRNG].base, memmap[IBEX_DEV_CSRNG].size);
299 create_unimplemented_device("riscv.lowrisc.ibex.entropy",
300 memmap[IBEX_DEV_ENTROPY].base, memmap[IBEX_DEV_ENTROPY].size);
301 create_unimplemented_device("riscv.lowrisc.ibex.edn0",
302 memmap[IBEX_DEV_EDNO].base, memmap[IBEX_DEV_EDNO].size);
303 create_unimplemented_device("riscv.lowrisc.ibex.edn1",
304 memmap[IBEX_DEV_EDN1].base, memmap[IBEX_DEV_EDN1].size);
305 create_unimplemented_device("riscv.lowrisc.ibex.alert_handler",
306 memmap[IBEX_DEV_ALERT_HANDLER].base, memmap[IBEX_DEV_ALERT_HANDLER].size);
307 create_unimplemented_device("riscv.lowrisc.ibex.sram_ctrl",
308 memmap[IBEX_DEV_SRAM_CTRL].base, memmap[IBEX_DEV_SRAM_CTRL].size);
309 create_unimplemented_device("riscv.lowrisc.ibex.otbn",
310 memmap[IBEX_DEV_OTBN].base, memmap[IBEX_DEV_OTBN].size);
311 create_unimplemented_device("riscv.lowrisc.ibex.ibex_cfg",
312 memmap[IBEX_DEV_IBEX_CFG].base, memmap[IBEX_DEV_IBEX_CFG].size);
313 }
314
315 static const Property lowrisc_ibex_soc_props[] = {
316 DEFINE_PROP_UINT32("resetvec", LowRISCIbexSoCState, resetvec, 0x20000400),
317 };
318
319 static void lowrisc_ibex_soc_class_init(ObjectClass *oc, const void *data)
320 {
321 DeviceClass *dc = DEVICE_CLASS(oc);
322
323 device_class_set_props(dc, lowrisc_ibex_soc_props);
324 dc->realize = lowrisc_ibex_soc_realize;
325 /* Reason: Uses serial_hds in realize function, thus can't be used twice */
326 dc->user_creatable = false;
327 }
328
329 static const TypeInfo open_titan_types[] = {
330 {
331 .name = TYPE_RISCV_IBEX_SOC,
332 .parent = TYPE_DEVICE,
333 .instance_size = sizeof(LowRISCIbexSoCState),
334 .instance_init = lowrisc_ibex_soc_init,
335 .class_init = lowrisc_ibex_soc_class_init,
336 }, {
337 .name = TYPE_OPENTITAN_MACHINE,
338 .parent = TYPE_MACHINE,
339 .instance_size = sizeof(OpenTitanState),
340 .class_init = opentitan_machine_class_init,
341 .interfaces = riscv32_machine_interfaces,
342 }
343 };
344
345 DEFINE_TYPES(open_titan_types)