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1 /*
2 * QEMU emulation of an RISC-V IOMMU
3 *
4 * Copyright (C) 2022-2023 Rivos Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 */
18
19 #include "qemu/osdep.h"
20 #include "exec/target_page.h"
21 #include "hw/pci/msi.h"
22 #include "hw/pci/msix.h"
23 #include "hw/pci/pci_bus.h"
24 #include "hw/core/qdev-properties.h"
25 #include "hw/riscv/riscv_hart.h"
26 #include "migration/vmstate.h"
27 #include "qapi/error.h"
28 #include "qemu/error-report.h"
29 #include "qemu/host-utils.h"
30 #include "qom/object.h"
31
32 #include "cpu_bits.h"
33 #include "riscv-iommu.h"
34 #include "riscv-iommu-bits.h"
35 #include "trace.h"
36
37 /* RISC-V IOMMU PCI Device Emulation */
38 #define RISCV_PCI_CLASS_SYSTEM_IOMMU 0x0806
39
40 /*
41 * 4 MSIx vectors for ICVEC, one for MRIF. The spec mentions in
42 * the "Placement and data flow" section that:
43 *
44 * "The interfaces related to recording an incoming MSI in a memory-resident
45 * interrupt file (MRIF) are implementation-specific. The partitioning of
46 * responsibility between the IOMMU and the IO bridge for recording the
47 * incoming MSI in an MRIF and generating the associated notice MSI are
48 * implementation-specific."
49 *
50 * We're making a design decision to create the MSIx for MRIF in the
51 * IOMMU MSIx emulation.
52 */
53 #define RISCV_IOMMU_PCI_MSIX_VECTORS 5
54
55 /*
56 * 4 vectors that can be used by civ, fiv, pmiv and piv. Number of
57 * vectors is represented by 2^N, where N = number of writable bits
58 * in each cause. For 4 vectors we'll write 0b11 (3) in each reg.
59 */
60 #define RISCV_IOMMU_PCI_ICVEC_VECTORS 0x3333
61
62 typedef struct RISCVIOMMUStatePci {
63 PCIDevice pci; /* Parent PCIe device state */
64 uint16_t vendor_id;
65 uint16_t device_id;
66 uint8_t revision;
67 MemoryRegion bar0; /* PCI BAR (including MSI-x config) */
68 RISCVIOMMUState iommu; /* common IOMMU state */
69 } RISCVIOMMUStatePci;
70
71 /* interrupt delivery callback */
72 static void riscv_iommu_pci_notify(RISCVIOMMUState *iommu, unsigned vector)
73 {
74 RISCVIOMMUStatePci *s = container_of(iommu, RISCVIOMMUStatePci, iommu);
75
76 if (msix_enabled(&(s->pci))) {
77 msix_notify(&(s->pci), vector);
78 }
79 }
80
81 static void riscv_iommu_pci_realize(PCIDevice *dev, Error **errp)
82 {
83 RISCVIOMMUStatePci *s = DO_UPCAST(RISCVIOMMUStatePci, pci, dev);
84 RISCVIOMMUState *iommu = &s->iommu;
85 uint8_t *pci_conf = dev->config;
86 Error *err = NULL;
87
88 pci_set_word(pci_conf + PCI_VENDOR_ID, s->vendor_id);
89 pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, s->vendor_id);
90 pci_set_word(pci_conf + PCI_DEVICE_ID, s->device_id);
91 pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, s->device_id);
92 pci_set_byte(pci_conf + PCI_REVISION_ID, s->revision);
93
94 /* Set device id for trace / debug */
95 DEVICE(iommu)->id = g_strdup_printf("%02x:%02x.%01x",
96 pci_dev_bus_num(dev), PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
97 qdev_realize(DEVICE(iommu), NULL, errp);
98
99 memory_region_init(&s->bar0, OBJECT(s), "riscv-iommu-bar0",
100 QEMU_ALIGN_UP(memory_region_size(&iommu->regs_mr), TARGET_PAGE_SIZE));
101 memory_region_add_subregion(&s->bar0, 0, &iommu->regs_mr);
102
103 pcie_endpoint_cap_init(dev, 0);
104
105 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY |
106 PCI_BASE_ADDRESS_MEM_TYPE_64, &s->bar0);
107
108 int ret = msix_init(dev, RISCV_IOMMU_PCI_MSIX_VECTORS,
109 &s->bar0, 0, RISCV_IOMMU_REG_MSI_CONFIG,
110 &s->bar0, 0, RISCV_IOMMU_REG_MSI_CONFIG + 256, 0, &err);
111
112 if (ret == -ENOTSUP) {
113 /*
114 * MSI-x is not supported by the platform.
115 * Driver should use timer/polling based notification handlers.
116 */
117 warn_report_err(err);
118 } else if (ret < 0) {
119 error_propagate(errp, err);
120 return;
121 } else {
122 /* Mark all ICVEC MSIx vectors as used */
123 for (int i = 0; i < RISCV_IOMMU_PCI_MSIX_VECTORS; i++) {
124 msix_vector_use(dev, i);
125 }
126
127 iommu->notify = riscv_iommu_pci_notify;
128 }
129
130 PCIBus *bus = pci_device_root_bus(dev);
131 if (!bus) {
132 error_setg(errp, "can't find PCIe root port for %02x:%02x.%x",
133 pci_bus_num(pci_get_bus(dev)), PCI_SLOT(dev->devfn),
134 PCI_FUNC(dev->devfn));
135 return;
136 }
137
138 riscv_iommu_pci_setup_iommu(iommu, bus, errp);
139 }
140
141 static void riscv_iommu_pci_exit(PCIDevice *pci_dev)
142 {
143 pci_setup_iommu(pci_device_root_bus(pci_dev), NULL, NULL);
144 }
145
146 static const VMStateDescription riscv_iommu_vmstate = {
147 .name = "riscv-iommu",
148 .unmigratable = 1
149 };
150
151 static void riscv_iommu_pci_init(Object *obj)
152 {
153 RISCVIOMMUStatePci *s = RISCV_IOMMU_PCI(obj);
154 RISCVIOMMUState *iommu = &s->iommu;
155
156 object_initialize_child(obj, "iommu", iommu, TYPE_RISCV_IOMMU);
157 qdev_alias_all_properties(DEVICE(iommu), obj);
158
159 iommu->icvec_avail_vectors = RISCV_IOMMU_PCI_ICVEC_VECTORS;
160 riscv_iommu_set_cap_igs(iommu, RISCV_IOMMU_CAP_IGS_MSI);
161
162 /* Report maximum physical address size of riscv64 */
163 iommu->pas_bits = 56;
164 }
165
166 static const Property riscv_iommu_pci_properties[] = {
167 DEFINE_PROP_UINT16("vendor-id", RISCVIOMMUStatePci, vendor_id,
168 PCI_VENDOR_ID_REDHAT),
169 DEFINE_PROP_UINT16("device-id", RISCVIOMMUStatePci, device_id,
170 PCI_DEVICE_ID_REDHAT_RISCV_IOMMU),
171 DEFINE_PROP_UINT8("revision", RISCVIOMMUStatePci, revision, 0x01),
172 };
173
174 static void riscv_iommu_pci_reset_hold(Object *obj, ResetType type)
175 {
176 RISCVIOMMUStatePci *pci = RISCV_IOMMU_PCI(obj);
177 RISCVIOMMUState *iommu = &pci->iommu;
178
179 riscv_iommu_reset(iommu);
180
181 trace_riscv_iommu_pci_reset_hold(type);
182 }
183
184 static void riscv_iommu_pci_class_init(ObjectClass *klass, const void *data)
185 {
186 DeviceClass *dc = DEVICE_CLASS(klass);
187 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
188 ResettableClass *rc = RESETTABLE_CLASS(klass);
189
190 rc->phases.hold = riscv_iommu_pci_reset_hold;
191
192 k->realize = riscv_iommu_pci_realize;
193 k->exit = riscv_iommu_pci_exit;
194 k->class_id = RISCV_PCI_CLASS_SYSTEM_IOMMU;
195 dc->desc = "RISCV-IOMMU DMA Remapping device";
196 dc->vmsd = &riscv_iommu_vmstate;
197 dc->hotpluggable = false;
198 dc->user_creatable = true;
199 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
200 device_class_set_props(dc, riscv_iommu_pci_properties);
201 }
202
203 static const TypeInfo riscv_iommu_pci = {
204 .name = TYPE_RISCV_IOMMU_PCI,
205 .parent = TYPE_PCI_DEVICE,
206 .class_init = riscv_iommu_pci_class_init,
207 .instance_init = riscv_iommu_pci_init,
208 .instance_size = sizeof(RISCVIOMMUStatePci),
209 .interfaces = (const InterfaceInfo[]) {
210 { INTERFACE_PCIE_DEVICE },
211 { },
212 },
213 };
214
215 static void riscv_iommu_register_pci_types(void)
216 {
217 type_register_static(&riscv_iommu_pci);
218 }
219
220 type_init(riscv_iommu_register_pci_types);