| 1 | /* |
| 2 | * QEMU RISCV Hart Array |
| 3 | * |
| 4 | * Copyright (c) 2017 SiFive, Inc. |
| 5 | * |
| 6 | * Holds the state of a homogeneous array of RISC-V harts |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify it |
| 9 | * under the terms and conditions of the GNU General Public License, |
| 10 | * version 2 or later, as published by the Free Software Foundation. |
| 11 | * |
| 12 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 15 | * more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License along with |
| 18 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 19 | */ |
| 20 | |
| 21 | #include "qemu/osdep.h" |
| 22 | #include "qapi/error.h" |
| 23 | #include "qemu/module.h" |
| 24 | #include "system/reset.h" |
| 25 | #include "system/qtest.h" |
| 26 | #include "qemu/cutils.h" |
| 27 | #include "hw/core/sysbus.h" |
| 28 | #include "target/riscv/cpu.h" |
| 29 | #include "hw/core/qdev-properties.h" |
| 30 | #include "hw/riscv/riscv_hart.h" |
| 31 | #include "qemu/error-report.h" |
| 32 | |
| 33 | static const Property riscv_harts_props[] = { |
| 34 | DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1), |
| 35 | DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0), |
| 36 | DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type), |
| 37 | DEFINE_PROP_UINT64("resetvec", RISCVHartArrayState, resetvec, |
| 38 | DEFAULT_RSTVEC), |
| 39 | |
| 40 | /* |
| 41 | * Smrnmi implementation-defined interrupt and exception trap handlers. |
| 42 | * |
| 43 | * When an RNMI interrupt is detected, the hart then enters M-mode and |
| 44 | * jumps to the address defined by "rnmi-interrupt-vector". |
| 45 | * |
| 46 | * When the hart encounters an exception while executing in M-mode with |
| 47 | * the mnstatus.NMIE bit clear, the hart then jumps to the address |
| 48 | * defined by "rnmi-exception-vector". |
| 49 | */ |
| 50 | DEFINE_PROP_ARRAY("rnmi-interrupt-vector", RISCVHartArrayState, |
| 51 | num_rnmi_irqvec, rnmi_irqvec, qdev_prop_uint64, |
| 52 | uint64_t), |
| 53 | DEFINE_PROP_ARRAY("rnmi-exception-vector", RISCVHartArrayState, |
| 54 | num_rnmi_excpvec, rnmi_excpvec, qdev_prop_uint64, |
| 55 | uint64_t), |
| 56 | }; |
| 57 | |
| 58 | static void riscv_harts_cpu_reset(void *opaque) |
| 59 | { |
| 60 | RISCVCPU *cpu = opaque; |
| 61 | cpu_reset(CPU(cpu)); |
| 62 | } |
| 63 | |
| 64 | #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) |
| 65 | static void csr_call(char *cmd, uint64_t cpu_num, int csrno, uint64_t *val) |
| 66 | { |
| 67 | RISCVCPU *cpu = RISCV_CPU(cpu_by_arch_id(cpu_num)); |
| 68 | CPURISCVState *env = &cpu->env; |
| 69 | |
| 70 | RISCVException ret = RISCV_EXCP_NONE; |
| 71 | if (strcmp(cmd, "get_csr") == 0) { |
| 72 | ret = riscv_csr_read_i64(env, csrno, val); |
| 73 | } else if (strcmp(cmd, "set_csr") == 0) { |
| 74 | ret = riscv_csr_write_i64(env, csrno, *val); |
| 75 | } |
| 76 | |
| 77 | g_assert(ret == RISCV_EXCP_NONE); |
| 78 | } |
| 79 | |
| 80 | static bool csr_qtest_callback(CharFrontend *chr, gchar **words) |
| 81 | { |
| 82 | if (strcmp(words[0], "csr") == 0) { |
| 83 | |
| 84 | uint64_t cpu; |
| 85 | uint64_t val; |
| 86 | int rc, csr; |
| 87 | |
| 88 | rc = qemu_strtou64(words[2], NULL, 0, &cpu); |
| 89 | g_assert(rc == 0); |
| 90 | rc = qemu_strtoi(words[3], NULL, 0, &csr); |
| 91 | g_assert(rc == 0); |
| 92 | rc = qemu_strtou64(words[4], NULL, 0, &val); |
| 93 | g_assert(rc == 0); |
| 94 | csr_call(words[1], cpu, csr, &val); |
| 95 | |
| 96 | qtest_sendf(chr, "OK 0 %"PRIx64"\n", val); |
| 97 | |
| 98 | return true; |
| 99 | } |
| 100 | |
| 101 | return false; |
| 102 | } |
| 103 | |
| 104 | static void riscv_cpu_register_csr_qtest_callback(void) |
| 105 | { |
| 106 | static bool first = true; |
| 107 | if (first) { |
| 108 | first = false; |
| 109 | qtest_set_command_cb(csr_qtest_callback); |
| 110 | } |
| 111 | } |
| 112 | #endif |
| 113 | |
| 114 | static bool riscv_hart_realize(RISCVHartArrayState *s, int idx, |
| 115 | char *cpu_type, Error **errp) |
| 116 | { |
| 117 | object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], cpu_type); |
| 118 | qdev_prop_set_uint64(DEVICE(&s->harts[idx]), "resetvec", s->resetvec); |
| 119 | |
| 120 | if (s->harts[idx].cfg.ext_smrnmi) { |
| 121 | if (idx < s->num_rnmi_irqvec) { |
| 122 | qdev_prop_set_uint64(DEVICE(&s->harts[idx]), |
| 123 | "rnmi-interrupt-vector", s->rnmi_irqvec[idx]); |
| 124 | } |
| 125 | |
| 126 | if (idx < s->num_rnmi_excpvec) { |
| 127 | qdev_prop_set_uint64(DEVICE(&s->harts[idx]), |
| 128 | "rnmi-exception-vector", s->rnmi_excpvec[idx]); |
| 129 | } |
| 130 | } else { |
| 131 | if (s->num_rnmi_irqvec > 0) { |
| 132 | warn_report_once("rnmi-interrupt-vector property is ignored " |
| 133 | "because Smrnmi extension is not enabled."); |
| 134 | } |
| 135 | |
| 136 | if (s->num_rnmi_excpvec > 0) { |
| 137 | warn_report_once("rnmi-exception-vector property is ignored " |
| 138 | "because Smrnmi extension is not enabled."); |
| 139 | } |
| 140 | } |
| 141 | |
| 142 | s->harts[idx].env.mhartid = s->hartid_base + idx; |
| 143 | qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]); |
| 144 | return qdev_realize(DEVICE(&s->harts[idx]), NULL, errp); |
| 145 | } |
| 146 | |
| 147 | static void riscv_harts_realize(DeviceState *dev, Error **errp) |
| 148 | { |
| 149 | RISCVHartArrayState *s = RISCV_HART_ARRAY(dev); |
| 150 | int n; |
| 151 | |
| 152 | s->harts = g_new0(RISCVCPU, s->num_harts); |
| 153 | |
| 154 | #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) |
| 155 | if (qtest_enabled()) { |
| 156 | riscv_cpu_register_csr_qtest_callback(); |
| 157 | } |
| 158 | #endif |
| 159 | |
| 160 | for (n = 0; n < s->num_harts; n++) { |
| 161 | if (!riscv_hart_realize(s, n, s->cpu_type, errp)) { |
| 162 | return; |
| 163 | } |
| 164 | } |
| 165 | } |
| 166 | |
| 167 | static void riscv_harts_class_init(ObjectClass *klass, const void *data) |
| 168 | { |
| 169 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 170 | |
| 171 | device_class_set_props(dc, riscv_harts_props); |
| 172 | dc->realize = riscv_harts_realize; |
| 173 | } |
| 174 | |
| 175 | static const TypeInfo riscv_harts_info = { |
| 176 | .name = TYPE_RISCV_HART_ARRAY, |
| 177 | .parent = TYPE_SYS_BUS_DEVICE, |
| 178 | .instance_size = sizeof(RISCVHartArrayState), |
| 179 | .class_init = riscv_harts_class_init, |
| 180 | }; |
| 181 | |
| 182 | static void riscv_harts_register_types(void) |
| 183 | { |
| 184 | type_register_static(&riscv_harts_info); |
| 185 | } |
| 186 | |
| 187 | type_init(riscv_harts_register_types) |