| 1 | /* |
| 2 | * Shakti C-class SoC emulation |
| 3 | * |
| 4 | * Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms and conditions of the GNU General Public License, |
| 8 | * version 2 or later, as published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | * more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License along with |
| 16 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 17 | */ |
| 18 | |
| 19 | #include "qemu/osdep.h" |
| 20 | #include "hw/core/boards.h" |
| 21 | #include "hw/riscv/shakti_c.h" |
| 22 | #include "hw/riscv/machines-qom.h" |
| 23 | #include "qapi/error.h" |
| 24 | #include "qemu/error-report.h" |
| 25 | #include "hw/intc/sifive_plic.h" |
| 26 | #include "hw/intc/riscv_aclint.h" |
| 27 | #include "system/system.h" |
| 28 | #include "hw/core/qdev-properties.h" |
| 29 | #include "system/address-spaces.h" |
| 30 | #include "hw/riscv/boot.h" |
| 31 | |
| 32 | static const struct MemmapEntry { |
| 33 | hwaddr base; |
| 34 | hwaddr size; |
| 35 | } shakti_c_memmap[] = { |
| 36 | [SHAKTI_C_ROM] = { 0x00001000, 0x2000 }, |
| 37 | [SHAKTI_C_RAM] = { 0x80000000, 0x0 }, |
| 38 | [SHAKTI_C_UART] = { 0x00011300, 0x00040 }, |
| 39 | [SHAKTI_C_GPIO] = { 0x020d0000, 0x00100 }, |
| 40 | [SHAKTI_C_PLIC] = { 0x0c000000, 0x20000 }, |
| 41 | [SHAKTI_C_CLINT] = { 0x02000000, 0xc0000 }, |
| 42 | [SHAKTI_C_I2C] = { 0x20c00000, 0x00100 }, |
| 43 | }; |
| 44 | |
| 45 | static void shakti_c_machine_state_init(MachineState *mstate) |
| 46 | { |
| 47 | ShaktiCMachineState *sms = RISCV_SHAKTI_MACHINE(mstate); |
| 48 | MemoryRegion *system_memory = get_system_memory(); |
| 49 | RISCVBootInfo boot_info; |
| 50 | hwaddr firmware_load_addr = shakti_c_memmap[SHAKTI_C_RAM].base; |
| 51 | |
| 52 | /* Initialize SoC */ |
| 53 | object_initialize_child(OBJECT(mstate), "soc", &sms->soc, |
| 54 | TYPE_RISCV_SHAKTI_SOC); |
| 55 | qdev_realize(DEVICE(&sms->soc), NULL, &error_abort); |
| 56 | |
| 57 | /* register RAM */ |
| 58 | memory_region_add_subregion(system_memory, |
| 59 | shakti_c_memmap[SHAKTI_C_RAM].base, |
| 60 | mstate->ram); |
| 61 | |
| 62 | riscv_boot_info_init(&boot_info, &sms->soc.cpus); |
| 63 | |
| 64 | if (mstate->firmware) { |
| 65 | riscv_load_firmware(mstate, &boot_info, mstate->firmware, |
| 66 | &firmware_load_addr, NULL); |
| 67 | } |
| 68 | |
| 69 | /* ROM reset vector */ |
| 70 | riscv_setup_rom_reset_vec(mstate, &sms->soc.cpus, firmware_load_addr, |
| 71 | shakti_c_memmap[SHAKTI_C_ROM].base, |
| 72 | shakti_c_memmap[SHAKTI_C_ROM].size, 0, 0); |
| 73 | } |
| 74 | |
| 75 | static void shakti_c_machine_instance_init(Object *obj) |
| 76 | { |
| 77 | } |
| 78 | |
| 79 | static void shakti_c_machine_class_init(ObjectClass *klass, const void *data) |
| 80 | { |
| 81 | MachineClass *mc = MACHINE_CLASS(klass); |
| 82 | static const char * const valid_cpu_types[] = { |
| 83 | RISCV_CPU_TYPE_NAME("shakti-c"), |
| 84 | NULL |
| 85 | }; |
| 86 | |
| 87 | mc->desc = "RISC-V Board compatible with Shakti SDK"; |
| 88 | mc->init = shakti_c_machine_state_init; |
| 89 | mc->default_cpu_type = TYPE_RISCV_CPU_SHAKTI_C; |
| 90 | mc->valid_cpu_types = valid_cpu_types; |
| 91 | mc->deprecation_reason = "Currently unmaintained with no known users"; |
| 92 | mc->default_ram_id = "riscv.shakti.c.ram"; |
| 93 | } |
| 94 | |
| 95 | static const TypeInfo shakti_c_machine_type_info = { |
| 96 | .name = TYPE_RISCV_SHAKTI_MACHINE, |
| 97 | .parent = TYPE_MACHINE, |
| 98 | .class_init = shakti_c_machine_class_init, |
| 99 | .instance_init = shakti_c_machine_instance_init, |
| 100 | .instance_size = sizeof(ShaktiCMachineState), |
| 101 | .interfaces = riscv64_machine_interfaces, |
| 102 | }; |
| 103 | |
| 104 | static void shakti_c_machine_type_info_register(void) |
| 105 | { |
| 106 | type_register_static(&shakti_c_machine_type_info); |
| 107 | } |
| 108 | type_init(shakti_c_machine_type_info_register) |
| 109 | |
| 110 | static void shakti_c_soc_state_realize(DeviceState *dev, Error **errp) |
| 111 | { |
| 112 | MachineState *ms = MACHINE(qdev_get_machine()); |
| 113 | ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(dev); |
| 114 | MemoryRegion *system_memory = get_system_memory(); |
| 115 | |
| 116 | sysbus_realize(SYS_BUS_DEVICE(&sss->cpus), &error_abort); |
| 117 | |
| 118 | sss->plic = sifive_plic_create(shakti_c_memmap[SHAKTI_C_PLIC].base, |
| 119 | (char *)SHAKTI_C_PLIC_HART_CONFIG, ms->smp.cpus, 0, |
| 120 | SHAKTI_C_PLIC_NUM_SOURCES, |
| 121 | SHAKTI_C_PLIC_NUM_PRIORITIES, |
| 122 | SHAKTI_C_PLIC_PRIORITY_BASE, |
| 123 | SHAKTI_C_PLIC_PENDING_BASE, |
| 124 | SHAKTI_C_PLIC_ENABLE_BASE, |
| 125 | SHAKTI_C_PLIC_ENABLE_STRIDE, |
| 126 | SHAKTI_C_PLIC_CONTEXT_BASE, |
| 127 | SHAKTI_C_PLIC_CONTEXT_STRIDE, |
| 128 | shakti_c_memmap[SHAKTI_C_PLIC].size); |
| 129 | |
| 130 | riscv_aclint_swi_create(shakti_c_memmap[SHAKTI_C_CLINT].base, |
| 131 | 0, 1, false); |
| 132 | riscv_aclint_mtimer_create(shakti_c_memmap[SHAKTI_C_CLINT].base + |
| 133 | RISCV_ACLINT_SWI_SIZE, |
| 134 | RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, 1, |
| 135 | RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, |
| 136 | RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, false); |
| 137 | |
| 138 | qdev_prop_set_chr(DEVICE(&(sss->uart)), "chardev", serial_hd(0)); |
| 139 | if (!sysbus_realize(SYS_BUS_DEVICE(&sss->uart), errp)) { |
| 140 | return; |
| 141 | } |
| 142 | sysbus_mmio_map(SYS_BUS_DEVICE(&sss->uart), 0, |
| 143 | shakti_c_memmap[SHAKTI_C_UART].base); |
| 144 | |
| 145 | /* ROM */ |
| 146 | memory_region_init_rom(&sss->rom, OBJECT(dev), "riscv.shakti.c.rom", |
| 147 | shakti_c_memmap[SHAKTI_C_ROM].size, &error_fatal); |
| 148 | memory_region_add_subregion(system_memory, |
| 149 | shakti_c_memmap[SHAKTI_C_ROM].base, &sss->rom); |
| 150 | } |
| 151 | |
| 152 | static void shakti_c_soc_class_init(ObjectClass *klass, const void *data) |
| 153 | { |
| 154 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 155 | dc->realize = shakti_c_soc_state_realize; |
| 156 | /* |
| 157 | * Reasons: |
| 158 | * - Creates CPUS in riscv_hart_realize(), and can create unintended |
| 159 | * CPUs |
| 160 | * - Uses serial_hds in realize function, thus can't be used twice |
| 161 | */ |
| 162 | dc->user_creatable = false; |
| 163 | } |
| 164 | |
| 165 | static void shakti_c_soc_instance_init(Object *obj) |
| 166 | { |
| 167 | ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(obj); |
| 168 | |
| 169 | object_initialize_child(obj, "cpus", &sss->cpus, TYPE_RISCV_HART_ARRAY); |
| 170 | object_initialize_child(obj, "uart", &sss->uart, TYPE_SHAKTI_UART); |
| 171 | |
| 172 | /* |
| 173 | * CPU type is fixed and we are not supporting passing from commandline yet. |
| 174 | * So let it be in instance_init. When supported should use ms->cpu_type |
| 175 | * instead of TYPE_RISCV_CPU_SHAKTI_C |
| 176 | */ |
| 177 | object_property_set_str(OBJECT(&sss->cpus), "cpu-type", |
| 178 | TYPE_RISCV_CPU_SHAKTI_C, &error_abort); |
| 179 | object_property_set_int(OBJECT(&sss->cpus), "num-harts", 1, |
| 180 | &error_abort); |
| 181 | } |
| 182 | |
| 183 | static const TypeInfo shakti_c_type_info = { |
| 184 | .name = TYPE_RISCV_SHAKTI_SOC, |
| 185 | .parent = TYPE_DEVICE, |
| 186 | .class_init = shakti_c_soc_class_init, |
| 187 | .instance_init = shakti_c_soc_instance_init, |
| 188 | .instance_size = sizeof(ShaktiCSoCState), |
| 189 | }; |
| 190 | |
| 191 | static void shakti_c_type_info_register(void) |
| 192 | { |
| 193 | type_register_static(&shakti_c_type_info); |
| 194 | } |
| 195 | type_init(shakti_c_type_info_register) |