@samitouri / QOSamiQemu
Code Commits Issues Pulls Sessions CI/CD
master
master
c 314 lines 11.3 KB
Raw
1 /*
2 * QEMU RISC-V Board Compatible with SiFive Freedom E SDK
3 *
4 * Copyright (c) 2017 SiFive, Inc.
5 *
6 * Provides a board compatible with the SiFive Freedom E SDK:
7 *
8 * 0) UART
9 * 1) CLINT (Core Level Interruptor)
10 * 2) PLIC (Platform Level Interrupt Controller)
11 * 3) PRCI (Power, Reset, Clock, Interrupt)
12 * 4) Registers emulated as RAM: AON, GPIO, QSPI, PWM
13 * 5) Flash memory emulated as RAM
14 *
15 * The Mask ROM reset vector jumps to the flash payload at 0x2040_0000.
16 * The OTP ROM and Flash boot code will be emulated in a future version.
17 *
18 * This program is free software; you can redistribute it and/or modify it
19 * under the terms and conditions of the GNU General Public License,
20 * version 2 or later, as published by the Free Software Foundation.
21 *
22 * This program is distributed in the hope it will be useful, but WITHOUT
23 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
24 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
25 * more details.
26 *
27 * You should have received a copy of the GNU General Public License along with
28 * this program. If not, see <http://www.gnu.org/licenses/>.
29 */
30
31 #include "qemu/osdep.h"
32 #include "qemu/cutils.h"
33 #include "qemu/error-report.h"
34 #include "qapi/error.h"
35 #include "hw/core/boards.h"
36 #include "hw/core/loader.h"
37 #include "hw/core/sysbus.h"
38 #include "hw/misc/unimp.h"
39 #include "target/riscv/cpu.h"
40 #include "hw/riscv/riscv_hart.h"
41 #include "hw/riscv/sifive_e.h"
42 #include "hw/riscv/boot.h"
43 #include "hw/riscv/machines-qom.h"
44 #include "hw/char/sifive_uart.h"
45 #include "hw/intc/riscv_aclint.h"
46 #include "hw/intc/sifive_plic.h"
47 #include "hw/misc/sifive_e_prci.h"
48 #include "hw/misc/sifive_e_aon.h"
49 #include "chardev/char.h"
50 #include "system/system.h"
51
52 static const MemMapEntry sifive_e_memmap[] = {
53 [SIFIVE_E_DEV_DEBUG] = { 0x0, 0x1000 },
54 [SIFIVE_E_DEV_MROM] = { 0x1000, 0x2000 },
55 [SIFIVE_E_DEV_OTP] = { 0x20000, 0x2000 },
56 [SIFIVE_E_DEV_CLINT] = { 0x2000000, 0x10000 },
57 [SIFIVE_E_DEV_PLIC] = { 0xc000000, 0x4000000 },
58 [SIFIVE_E_DEV_AON] = { 0x10000000, 0x8000 },
59 [SIFIVE_E_DEV_PRCI] = { 0x10008000, 0x8000 },
60 [SIFIVE_E_DEV_OTP_CTRL] = { 0x10010000, 0x1000 },
61 [SIFIVE_E_DEV_GPIO0] = { 0x10012000, 0x1000 },
62 [SIFIVE_E_DEV_UART0] = { 0x10013000, 0x1000 },
63 [SIFIVE_E_DEV_QSPI0] = { 0x10014000, 0x1000 },
64 [SIFIVE_E_DEV_PWM0] = { 0x10015000, 0x1000 },
65 [SIFIVE_E_DEV_UART1] = { 0x10023000, 0x1000 },
66 [SIFIVE_E_DEV_QSPI1] = { 0x10024000, 0x1000 },
67 [SIFIVE_E_DEV_PWM1] = { 0x10025000, 0x1000 },
68 [SIFIVE_E_DEV_QSPI2] = { 0x10034000, 0x1000 },
69 [SIFIVE_E_DEV_PWM2] = { 0x10035000, 0x1000 },
70 [SIFIVE_E_DEV_XIP] = { 0x20000000, 0x20000000 },
71 [SIFIVE_E_DEV_DTIM] = { 0x80000000, 0x4000 }
72 };
73
74 static void sifive_e_machine_init(MachineState *machine)
75 {
76 MachineClass *mc = MACHINE_GET_CLASS(machine);
77 const MemMapEntry *memmap = sifive_e_memmap;
78
79 SiFiveEState *s = RISCV_E_MACHINE(machine);
80 MemoryRegion *sys_mem = get_system_memory();
81 int i;
82 RISCVBootInfo boot_info;
83
84 if (machine->ram_size != mc->default_ram_size) {
85 char *sz = size_to_str(mc->default_ram_size);
86 error_report("Invalid RAM size, should be %s", sz);
87 g_free(sz);
88 exit(EXIT_FAILURE);
89 }
90
91 /* Initialize SoC */
92 object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_E_SOC);
93 qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
94
95 /* Data Tightly Integrated Memory */
96 memory_region_add_subregion(sys_mem,
97 memmap[SIFIVE_E_DEV_DTIM].base, machine->ram);
98
99 /* Mask ROM reset vector */
100 uint32_t reset_vec[4];
101
102 if (s->revb) {
103 reset_vec[1] = 0x200102b7; /* 0x1004: lui t0,0x20010 */
104 } else {
105 reset_vec[1] = 0x204002b7; /* 0x1004: lui t0,0x20400 */
106 }
107 reset_vec[2] = 0x00028067; /* 0x1008: jr t0 */
108
109 reset_vec[0] = reset_vec[3] = 0;
110
111 /* copy in the reset vector in little_endian byte order */
112 for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
113 reset_vec[i] = cpu_to_le32(reset_vec[i]);
114 }
115 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
116 memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory);
117
118 riscv_boot_info_init(&boot_info, &s->soc.cpus);
119 if (machine->kernel_filename) {
120 riscv_load_kernel(machine, &boot_info,
121 memmap[SIFIVE_E_DEV_DTIM].base,
122 false, NULL);
123 }
124 }
125
126 static bool sifive_e_machine_get_revb(Object *obj, Error **errp)
127 {
128 SiFiveEState *s = RISCV_E_MACHINE(obj);
129
130 return s->revb;
131 }
132
133 static void sifive_e_machine_set_revb(Object *obj, bool value, Error **errp)
134 {
135 SiFiveEState *s = RISCV_E_MACHINE(obj);
136
137 s->revb = value;
138 }
139
140 static void sifive_e_machine_instance_init(Object *obj)
141 {
142 SiFiveEState *s = RISCV_E_MACHINE(obj);
143
144 s->revb = false;
145 }
146
147 static void sifive_e_machine_class_init(ObjectClass *oc, const void *data)
148 {
149 MachineClass *mc = MACHINE_CLASS(oc);
150
151 mc->desc = "RISC-V Board compatible with SiFive E SDK";
152 mc->init = sifive_e_machine_init;
153 mc->max_cpus = 1;
154 mc->default_cpu_type = SIFIVE_E_CPU;
155 mc->default_ram_id = "riscv.sifive.e.ram";
156 mc->default_ram_size = sifive_e_memmap[SIFIVE_E_DEV_DTIM].size;
157
158 object_class_property_add_bool(oc, "revb", sifive_e_machine_get_revb,
159 sifive_e_machine_set_revb);
160 object_class_property_set_description(oc, "revb",
161 "Set on to tell QEMU that it should model "
162 "the revB HiFive1 board");
163 }
164
165 static const TypeInfo sifive_e_machine_typeinfo = {
166 .name = MACHINE_TYPE_NAME("sifive_e"),
167 .parent = TYPE_MACHINE,
168 .class_init = sifive_e_machine_class_init,
169 .instance_init = sifive_e_machine_instance_init,
170 .instance_size = sizeof(SiFiveEState),
171 .interfaces = riscv32_64_machine_interfaces,
172 };
173
174 static void sifive_e_machine_init_register_types(void)
175 {
176 type_register_static(&sifive_e_machine_typeinfo);
177 }
178
179 type_init(sifive_e_machine_init_register_types)
180
181 static void sifive_e_soc_init(Object *obj)
182 {
183 SiFiveESoCState *s = RISCV_E_SOC(obj);
184
185 object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
186 /*
187 * Set the `num-harts` property later as the machine is potentially not
188 * created yet.
189 */
190 object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x1004, &error_abort);
191 object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio,
192 TYPE_SIFIVE_GPIO);
193 object_initialize_child(obj, "riscv.sifive.e.aon", &s->aon,
194 TYPE_SIFIVE_E_AON);
195 }
196
197 static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
198 {
199 MachineState *ms = MACHINE(qdev_get_machine());
200 const MemMapEntry *memmap = sifive_e_memmap;
201 SiFiveESoCState *s = RISCV_E_SOC(dev);
202 MemoryRegion *sys_mem = get_system_memory();
203
204 object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
205 &error_abort);
206 object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
207 &error_abort);
208 sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);
209
210 /* Mask ROM */
211 memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom",
212 memmap[SIFIVE_E_DEV_MROM].size, &error_fatal);
213 memory_region_add_subregion(sys_mem,
214 memmap[SIFIVE_E_DEV_MROM].base, &s->mask_rom);
215
216 /* MMIO */
217 s->plic = sifive_plic_create(memmap[SIFIVE_E_DEV_PLIC].base,
218 (char *)SIFIVE_E_PLIC_HART_CONFIG, ms->smp.cpus, 0,
219 SIFIVE_E_PLIC_NUM_SOURCES,
220 SIFIVE_E_PLIC_NUM_PRIORITIES,
221 SIFIVE_E_PLIC_PRIORITY_BASE,
222 SIFIVE_E_PLIC_PENDING_BASE,
223 SIFIVE_E_PLIC_ENABLE_BASE,
224 SIFIVE_E_PLIC_ENABLE_STRIDE,
225 SIFIVE_E_PLIC_CONTEXT_BASE,
226 SIFIVE_E_PLIC_CONTEXT_STRIDE,
227 memmap[SIFIVE_E_DEV_PLIC].size);
228 riscv_aclint_swi_create(memmap[SIFIVE_E_DEV_CLINT].base,
229 0, ms->smp.cpus, false);
230 riscv_aclint_mtimer_create(memmap[SIFIVE_E_DEV_CLINT].base +
231 RISCV_ACLINT_SWI_SIZE,
232 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus,
233 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
234 SIFIVE_E_LFCLK_DEFAULT_FREQ, false);
235 sifive_e_prci_create(memmap[SIFIVE_E_DEV_PRCI].base);
236
237 /* AON */
238
239 if (!sysbus_realize(SYS_BUS_DEVICE(&s->aon), errp)) {
240 return;
241 }
242
243 /* Map AON registers */
244 sysbus_mmio_map(SYS_BUS_DEVICE(&s->aon), 0, memmap[SIFIVE_E_DEV_AON].base);
245
246 /* GPIO */
247
248 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
249 return;
250 }
251
252 /* Map GPIO registers */
253 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_E_DEV_GPIO0].base);
254
255 /* Pass all GPIOs to the SOC layer so they are available to the board */
256 qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);
257
258 /* Connect GPIO interrupts to the PLIC */
259 for (int i = 0; i < 32; i++) {
260 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i,
261 qdev_get_gpio_in(DEVICE(s->plic),
262 SIFIVE_E_GPIO0_IRQ0 + i));
263 }
264 sysbus_connect_irq(SYS_BUS_DEVICE(&s->aon), 0,
265 qdev_get_gpio_in(DEVICE(s->plic),
266 SIFIVE_E_AON_WDT_IRQ));
267
268 sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART0].base,
269 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ));
270 create_unimplemented_device("riscv.sifive.e.qspi0",
271 memmap[SIFIVE_E_DEV_QSPI0].base, memmap[SIFIVE_E_DEV_QSPI0].size);
272 create_unimplemented_device("riscv.sifive.e.pwm0",
273 memmap[SIFIVE_E_DEV_PWM0].base, memmap[SIFIVE_E_DEV_PWM0].size);
274 sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART1].base,
275 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART1_IRQ));
276 create_unimplemented_device("riscv.sifive.e.qspi1",
277 memmap[SIFIVE_E_DEV_QSPI1].base, memmap[SIFIVE_E_DEV_QSPI1].size);
278 create_unimplemented_device("riscv.sifive.e.pwm1",
279 memmap[SIFIVE_E_DEV_PWM1].base, memmap[SIFIVE_E_DEV_PWM1].size);
280 create_unimplemented_device("riscv.sifive.e.qspi2",
281 memmap[SIFIVE_E_DEV_QSPI2].base, memmap[SIFIVE_E_DEV_QSPI2].size);
282 create_unimplemented_device("riscv.sifive.e.pwm2",
283 memmap[SIFIVE_E_DEV_PWM2].base, memmap[SIFIVE_E_DEV_PWM2].size);
284
285 /* Flash memory */
286 memory_region_init_rom(&s->xip_mem, OBJECT(dev), "riscv.sifive.e.xip",
287 memmap[SIFIVE_E_DEV_XIP].size, &error_fatal);
288 memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_DEV_XIP].base,
289 &s->xip_mem);
290 }
291
292 static void sifive_e_soc_class_init(ObjectClass *oc, const void *data)
293 {
294 DeviceClass *dc = DEVICE_CLASS(oc);
295
296 dc->realize = sifive_e_soc_realize;
297 /* Reason: Uses serial_hds in realize function, thus can't be used twice */
298 dc->user_creatable = false;
299 }
300
301 static const TypeInfo sifive_e_soc_type_info = {
302 .name = TYPE_RISCV_E_SOC,
303 .parent = TYPE_DEVICE,
304 .instance_size = sizeof(SiFiveESoCState),
305 .instance_init = sifive_e_soc_init,
306 .class_init = sifive_e_soc_class_init,
307 };
308
309 static void sifive_e_soc_register_types(void)
310 {
311 type_register_static(&sifive_e_soc_type_info);
312 }
313
314 type_init(sifive_e_soc_register_types)