| 1 | /* |
| 2 | * QEMU RISC-V Board Compatible with SiFive Freedom U SDK |
| 3 | * |
| 4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu |
| 5 | * Copyright (c) 2017 SiFive, Inc. |
| 6 | * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> |
| 7 | * |
| 8 | * Provides a board compatible with the SiFive Freedom U SDK: |
| 9 | * |
| 10 | * 0) UART |
| 11 | * 1) CLINT (Core Level Interruptor) |
| 12 | * 2) PLIC (Platform Level Interrupt Controller) |
| 13 | * 3) PRCI (Power, Reset, Clock, Interrupt) |
| 14 | * 4) GPIO (General Purpose Input/Output Controller) |
| 15 | * 5) OTP (One-Time Programmable) memory with stored serial number |
| 16 | * 6) GEM (Gigabit Ethernet Controller) and management block |
| 17 | * 7) DMA (Direct Memory Access Controller) |
| 18 | * 8) SPI0 connected to an SPI flash |
| 19 | * 9) SPI2 connected to an SD card |
| 20 | * 10) PWM0 and PWM1 |
| 21 | * |
| 22 | * This board currently generates devicetree dynamically that indicates at least |
| 23 | * two harts and up to five harts. |
| 24 | * |
| 25 | * This program is free software; you can redistribute it and/or modify it |
| 26 | * under the terms and conditions of the GNU General Public License, |
| 27 | * version 2 or later, as published by the Free Software Foundation. |
| 28 | * |
| 29 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 30 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 31 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 32 | * more details. |
| 33 | * |
| 34 | * You should have received a copy of the GNU General Public License along with |
| 35 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 36 | */ |
| 37 | |
| 38 | #include "qemu/osdep.h" |
| 39 | #include "qemu/error-report.h" |
| 40 | #include "qapi/error.h" |
| 41 | #include "qapi/visitor.h" |
| 42 | #include "hw/core/boards.h" |
| 43 | #include "hw/core/irq.h" |
| 44 | #include "hw/core/loader.h" |
| 45 | #include "hw/core/sysbus.h" |
| 46 | #include "hw/cpu/cluster.h" |
| 47 | #include "hw/misc/unimp.h" |
| 48 | #include "hw/sd/sd.h" |
| 49 | #include "hw/ssi/ssi.h" |
| 50 | #include "target/riscv/cpu.h" |
| 51 | #include "hw/riscv/riscv_hart.h" |
| 52 | #include "hw/riscv/sifive_u.h" |
| 53 | #include "hw/riscv/boot.h" |
| 54 | #include "hw/riscv/machines-qom.h" |
| 55 | #include "hw/riscv/fdt-common.h" |
| 56 | #include "hw/char/sifive_uart.h" |
| 57 | #include "hw/intc/riscv_aclint.h" |
| 58 | #include "hw/intc/sifive_plic.h" |
| 59 | #include "chardev/char.h" |
| 60 | #include "net/eth.h" |
| 61 | #include "system/device_tree.h" |
| 62 | #include "system/runstate.h" |
| 63 | #include "system/system.h" |
| 64 | |
| 65 | #include <libfdt.h> |
| 66 | |
| 67 | /* CLINT timebase frequency */ |
| 68 | #define CLINT_TIMEBASE_FREQ 1000000 |
| 69 | |
| 70 | static const MemMapEntry sifive_u_memmap[] = { |
| 71 | [SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 }, |
| 72 | [SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 }, |
| 73 | [SIFIVE_U_DEV_CLINT] = { 0x2000000, 0x10000 }, |
| 74 | [SIFIVE_U_DEV_L2CC] = { 0x2010000, 0x1000 }, |
| 75 | [SIFIVE_U_DEV_PDMA] = { 0x3000000, 0x100000 }, |
| 76 | [SIFIVE_U_DEV_L2LIM] = { 0x8000000, 0x2000000 }, |
| 77 | [SIFIVE_U_DEV_PLIC] = { 0xc000000, 0x4000000 }, |
| 78 | [SIFIVE_U_DEV_PRCI] = { 0x10000000, 0x1000 }, |
| 79 | [SIFIVE_U_DEV_UART0] = { 0x10010000, 0x1000 }, |
| 80 | [SIFIVE_U_DEV_UART1] = { 0x10011000, 0x1000 }, |
| 81 | [SIFIVE_U_DEV_PWM0] = { 0x10020000, 0x1000 }, |
| 82 | [SIFIVE_U_DEV_PWM1] = { 0x10021000, 0x1000 }, |
| 83 | [SIFIVE_U_DEV_QSPI0] = { 0x10040000, 0x1000 }, |
| 84 | [SIFIVE_U_DEV_QSPI2] = { 0x10050000, 0x1000 }, |
| 85 | [SIFIVE_U_DEV_GPIO] = { 0x10060000, 0x1000 }, |
| 86 | [SIFIVE_U_DEV_OTP] = { 0x10070000, 0x1000 }, |
| 87 | [SIFIVE_U_DEV_GEM] = { 0x10090000, 0x2000 }, |
| 88 | [SIFIVE_U_DEV_GEM_MGMT] = { 0x100a0000, 0x1000 }, |
| 89 | [SIFIVE_U_DEV_DMC] = { 0x100b0000, 0x10000 }, |
| 90 | [SIFIVE_U_DEV_FLASH0] = { 0x20000000, 0x10000000 }, |
| 91 | [SIFIVE_U_DEV_DRAM] = { 0x80000000, 0x0 }, |
| 92 | }; |
| 93 | |
| 94 | #define OTP_SERIAL 1 |
| 95 | #define GEM_REVISION 0x10070109 |
| 96 | |
| 97 | static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, |
| 98 | bool is_32_bit) |
| 99 | { |
| 100 | MachineState *ms = MACHINE(s); |
| 101 | void *fdt; |
| 102 | int cpu; |
| 103 | uint32_t *cells, cells_length; |
| 104 | char *nodename; |
| 105 | uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1; |
| 106 | uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle; |
| 107 | static const char * const ethclk_names[2] = { "pclk", "hclk" }; |
| 108 | g_autofree uint32_t *intc_phandles = g_new0(uint32_t, ms->smp.cpus); |
| 109 | g_autofree char *clust_name = NULL; |
| 110 | |
| 111 | fdt = ms->fdt = create_board_device_tree("SiFive HiFive Unleashed A00", |
| 112 | "sifive,hifive-unleashed-a00", &s->fdt_size); |
| 113 | |
| 114 | hfclk_phandle = phandle++; |
| 115 | nodename = g_strdup_printf("/hfclk"); |
| 116 | qemu_fdt_add_subnode(fdt, nodename); |
| 117 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle); |
| 118 | qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk"); |
| 119 | qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", |
| 120 | SIFIVE_U_HFCLK_FREQ); |
| 121 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); |
| 122 | qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); |
| 123 | g_free(nodename); |
| 124 | |
| 125 | rtcclk_phandle = phandle++; |
| 126 | nodename = g_strdup_printf("/rtcclk"); |
| 127 | qemu_fdt_add_subnode(fdt, nodename); |
| 128 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle); |
| 129 | qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk"); |
| 130 | qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", |
| 131 | SIFIVE_U_RTCCLK_FREQ); |
| 132 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); |
| 133 | qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); |
| 134 | g_free(nodename); |
| 135 | |
| 136 | create_fdt_socket_memory(fdt, memmap[SIFIVE_U_DEV_DRAM].base, |
| 137 | ms->ram_size, 0, false); |
| 138 | |
| 139 | fdt_create_cpu_socket_subnode(fdt, CLINT_TIMEBASE_FREQ); |
| 140 | |
| 141 | clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", 0); |
| 142 | qemu_fdt_add_subnode(fdt, clust_name); |
| 143 | |
| 144 | for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) { |
| 145 | nodename = g_strdup_printf("/cpus/cpu@%d", cpu); |
| 146 | qemu_fdt_add_subnode(fdt, nodename); |
| 147 | |
| 148 | /* cpu 0 is the management hart that does not have mmu */ |
| 149 | if (cpu != 0) { |
| 150 | if (is_32_bit) { |
| 151 | qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32"); |
| 152 | } else { |
| 153 | qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv39"); |
| 154 | } |
| 155 | riscv_isa_write_fdt(&s->soc.u_cpus.harts[cpu - 1], fdt, nodename); |
| 156 | } else { |
| 157 | riscv_isa_write_fdt(&s->soc.e_cpus.harts[0], fdt, nodename); |
| 158 | } |
| 159 | |
| 160 | create_fdt_socket_cpu_sifive(fdt, clust_name, cpu, 0, 0, |
| 161 | &phandle, intc_phandles); |
| 162 | |
| 163 | g_free(nodename); |
| 164 | } |
| 165 | |
| 166 | create_fdt_socket_clint(fdt, memmap[SIFIVE_U_DEV_CLINT].base, |
| 167 | memmap[SIFIVE_U_DEV_CLINT].size, 0, |
| 168 | intc_phandles, ms->smp.cpus, false); |
| 169 | |
| 170 | nodename = g_strdup_printf("/soc/otp@%lx", |
| 171 | (long)memmap[SIFIVE_U_DEV_OTP].base); |
| 172 | qemu_fdt_add_subnode(fdt, nodename); |
| 173 | qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE); |
| 174 | qemu_fdt_setprop_cells(fdt, nodename, "reg", |
| 175 | 0x0, memmap[SIFIVE_U_DEV_OTP].base, |
| 176 | 0x0, memmap[SIFIVE_U_DEV_OTP].size); |
| 177 | qemu_fdt_setprop_string(fdt, nodename, "compatible", |
| 178 | "sifive,fu540-c000-otp"); |
| 179 | g_free(nodename); |
| 180 | |
| 181 | prci_phandle = phandle++; |
| 182 | nodename = g_strdup_printf("/soc/clock-controller@%lx", |
| 183 | (long)memmap[SIFIVE_U_DEV_PRCI].base); |
| 184 | qemu_fdt_add_subnode(fdt, nodename); |
| 185 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle); |
| 186 | qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1); |
| 187 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", |
| 188 | hfclk_phandle, rtcclk_phandle); |
| 189 | qemu_fdt_setprop_cells(fdt, nodename, "reg", |
| 190 | 0x0, memmap[SIFIVE_U_DEV_PRCI].base, |
| 191 | 0x0, memmap[SIFIVE_U_DEV_PRCI].size); |
| 192 | qemu_fdt_setprop_string(fdt, nodename, "compatible", |
| 193 | "sifive,fu540-c000-prci"); |
| 194 | g_free(nodename); |
| 195 | |
| 196 | plic_phandle = phandle++; |
| 197 | cells_length = ms->smp.cpus * 4 - 2; |
| 198 | cells = g_new0(uint32_t, cells_length); |
| 199 | for (cpu = 0; cpu < ms->smp.cpus; cpu++) { |
| 200 | /* cpu 0 is the management hart that does not have S-mode */ |
| 201 | if (cpu == 0) { |
| 202 | cells[0] = cpu_to_be32(intc_phandles[cpu]); |
| 203 | cells[1] = cpu_to_be32(IRQ_M_EXT); |
| 204 | } else { |
| 205 | cells[cpu * 4 - 2] = cpu_to_be32(intc_phandles[cpu]); |
| 206 | cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT); |
| 207 | cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); |
| 208 | cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT); |
| 209 | } |
| 210 | } |
| 211 | |
| 212 | create_fdt_plic(fdt, memmap[SIFIVE_U_DEV_PLIC].base, |
| 213 | memmap[SIFIVE_U_DEV_PLIC].size, |
| 214 | plic_phandle, SIFIVE_U_PLIC_INT_CELLS, |
| 215 | SIFIVE_U_PLIC_ADDR_CELLS, cells, |
| 216 | cells_length * sizeof(uint32_t), |
| 217 | SIFIVE_U_PLIC_NUM_SOURCES - 1, false, 0); |
| 218 | g_free(cells); |
| 219 | |
| 220 | gpio_phandle = phandle++; |
| 221 | nodename = g_strdup_printf("/soc/gpio@%lx", |
| 222 | (long)memmap[SIFIVE_U_DEV_GPIO].base); |
| 223 | qemu_fdt_add_subnode(fdt, nodename); |
| 224 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle); |
| 225 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", |
| 226 | prci_phandle, PRCI_CLK_TLCLK); |
| 227 | qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2); |
| 228 | qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); |
| 229 | qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2); |
| 230 | qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0); |
| 231 | qemu_fdt_setprop_cells(fdt, nodename, "reg", |
| 232 | 0x0, memmap[SIFIVE_U_DEV_GPIO].base, |
| 233 | 0x0, memmap[SIFIVE_U_DEV_GPIO].size); |
| 234 | qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0, |
| 235 | SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3, |
| 236 | SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6, |
| 237 | SIFIVE_U_GPIO_IRQ7, SIFIVE_U_GPIO_IRQ8, SIFIVE_U_GPIO_IRQ9, |
| 238 | SIFIVE_U_GPIO_IRQ10, SIFIVE_U_GPIO_IRQ11, SIFIVE_U_GPIO_IRQ12, |
| 239 | SIFIVE_U_GPIO_IRQ13, SIFIVE_U_GPIO_IRQ14, SIFIVE_U_GPIO_IRQ15); |
| 240 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); |
| 241 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,gpio0"); |
| 242 | g_free(nodename); |
| 243 | |
| 244 | nodename = g_strdup_printf("/gpio-restart"); |
| 245 | qemu_fdt_add_subnode(fdt, nodename); |
| 246 | qemu_fdt_setprop_cells(fdt, nodename, "gpios", gpio_phandle, 10, 1); |
| 247 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart"); |
| 248 | g_free(nodename); |
| 249 | |
| 250 | nodename = g_strdup_printf("/soc/dma@%lx", |
| 251 | (long)memmap[SIFIVE_U_DEV_PDMA].base); |
| 252 | qemu_fdt_add_subnode(fdt, nodename); |
| 253 | qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1); |
| 254 | qemu_fdt_setprop_cells(fdt, nodename, "interrupts", |
| 255 | SIFIVE_U_PDMA_IRQ0, SIFIVE_U_PDMA_IRQ1, SIFIVE_U_PDMA_IRQ2, |
| 256 | SIFIVE_U_PDMA_IRQ3, SIFIVE_U_PDMA_IRQ4, SIFIVE_U_PDMA_IRQ5, |
| 257 | SIFIVE_U_PDMA_IRQ6, SIFIVE_U_PDMA_IRQ7); |
| 258 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); |
| 259 | qemu_fdt_setprop_cells(fdt, nodename, "reg", |
| 260 | 0x0, memmap[SIFIVE_U_DEV_PDMA].base, |
| 261 | 0x0, memmap[SIFIVE_U_DEV_PDMA].size); |
| 262 | qemu_fdt_setprop_string(fdt, nodename, "compatible", |
| 263 | "sifive,fu540-c000-pdma"); |
| 264 | g_free(nodename); |
| 265 | |
| 266 | nodename = g_strdup_printf("/soc/cache-controller@%lx", |
| 267 | (long)memmap[SIFIVE_U_DEV_L2CC].base); |
| 268 | qemu_fdt_add_subnode(fdt, nodename); |
| 269 | qemu_fdt_setprop_cells(fdt, nodename, "reg", |
| 270 | 0x0, memmap[SIFIVE_U_DEV_L2CC].base, |
| 271 | 0x0, memmap[SIFIVE_U_DEV_L2CC].size); |
| 272 | qemu_fdt_setprop_cells(fdt, nodename, "interrupts", |
| 273 | SIFIVE_U_L2CC_IRQ0, SIFIVE_U_L2CC_IRQ1, SIFIVE_U_L2CC_IRQ2); |
| 274 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); |
| 275 | qemu_fdt_setprop(fdt, nodename, "cache-unified", NULL, 0); |
| 276 | qemu_fdt_setprop_cell(fdt, nodename, "cache-size", 2097152); |
| 277 | qemu_fdt_setprop_cell(fdt, nodename, "cache-sets", 1024); |
| 278 | qemu_fdt_setprop_cell(fdt, nodename, "cache-level", 2); |
| 279 | qemu_fdt_setprop_cell(fdt, nodename, "cache-block-size", 64); |
| 280 | qemu_fdt_setprop_string(fdt, nodename, "compatible", |
| 281 | "sifive,fu540-c000-ccache"); |
| 282 | g_free(nodename); |
| 283 | |
| 284 | nodename = g_strdup_printf("/soc/spi@%lx", |
| 285 | (long)memmap[SIFIVE_U_DEV_QSPI2].base); |
| 286 | qemu_fdt_add_subnode(fdt, nodename); |
| 287 | qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); |
| 288 | qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); |
| 289 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", |
| 290 | prci_phandle, PRCI_CLK_TLCLK); |
| 291 | qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI2_IRQ); |
| 292 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); |
| 293 | qemu_fdt_setprop_cells(fdt, nodename, "reg", |
| 294 | 0x0, memmap[SIFIVE_U_DEV_QSPI2].base, |
| 295 | 0x0, memmap[SIFIVE_U_DEV_QSPI2].size); |
| 296 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0"); |
| 297 | g_free(nodename); |
| 298 | |
| 299 | nodename = g_strdup_printf("/soc/spi@%lx/mmc@0", |
| 300 | (long)memmap[SIFIVE_U_DEV_QSPI2].base); |
| 301 | qemu_fdt_add_subnode(fdt, nodename); |
| 302 | qemu_fdt_setprop(fdt, nodename, "disable-wp", NULL, 0); |
| 303 | qemu_fdt_setprop_cells(fdt, nodename, "voltage-ranges", 3300, 3300); |
| 304 | qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 20000000); |
| 305 | qemu_fdt_setprop_cell(fdt, nodename, "reg", 0); |
| 306 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "mmc-spi-slot"); |
| 307 | g_free(nodename); |
| 308 | |
| 309 | nodename = g_strdup_printf("/soc/spi@%lx", |
| 310 | (long)memmap[SIFIVE_U_DEV_QSPI0].base); |
| 311 | qemu_fdt_add_subnode(fdt, nodename); |
| 312 | qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); |
| 313 | qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); |
| 314 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", |
| 315 | prci_phandle, PRCI_CLK_TLCLK); |
| 316 | qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI0_IRQ); |
| 317 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); |
| 318 | qemu_fdt_setprop_cells(fdt, nodename, "reg", |
| 319 | 0x0, memmap[SIFIVE_U_DEV_QSPI0].base, |
| 320 | 0x0, memmap[SIFIVE_U_DEV_QSPI0].size); |
| 321 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0"); |
| 322 | g_free(nodename); |
| 323 | |
| 324 | nodename = g_strdup_printf("/soc/spi@%lx/flash@0", |
| 325 | (long)memmap[SIFIVE_U_DEV_QSPI0].base); |
| 326 | qemu_fdt_add_subnode(fdt, nodename); |
| 327 | qemu_fdt_setprop_cell(fdt, nodename, "spi-rx-bus-width", 4); |
| 328 | qemu_fdt_setprop_cell(fdt, nodename, "spi-tx-bus-width", 4); |
| 329 | qemu_fdt_setprop(fdt, nodename, "m25p,fast-read", NULL, 0); |
| 330 | qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 50000000); |
| 331 | qemu_fdt_setprop_cell(fdt, nodename, "reg", 0); |
| 332 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "jedec,spi-nor"); |
| 333 | g_free(nodename); |
| 334 | |
| 335 | phy_phandle = phandle++; |
| 336 | nodename = g_strdup_printf("/soc/ethernet@%lx", |
| 337 | (long)memmap[SIFIVE_U_DEV_GEM].base); |
| 338 | qemu_fdt_add_subnode(fdt, nodename); |
| 339 | qemu_fdt_setprop_string(fdt, nodename, "compatible", |
| 340 | "sifive,fu540-c000-gem"); |
| 341 | qemu_fdt_setprop_cells(fdt, nodename, "reg", |
| 342 | 0x0, memmap[SIFIVE_U_DEV_GEM].base, |
| 343 | 0x0, memmap[SIFIVE_U_DEV_GEM].size, |
| 344 | 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].base, |
| 345 | 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].size); |
| 346 | qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); |
| 347 | qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii"); |
| 348 | qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle); |
| 349 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); |
| 350 | qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); |
| 351 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", |
| 352 | prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL); |
| 353 | qemu_fdt_setprop_string_array(fdt, nodename, "clock-names", |
| 354 | (char **)ðclk_names, ARRAY_SIZE(ethclk_names)); |
| 355 | qemu_fdt_setprop(fdt, nodename, "local-mac-address", |
| 356 | s->soc.gem.conf.macaddr.a, ETH_ALEN); |
| 357 | qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); |
| 358 | qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); |
| 359 | |
| 360 | qemu_fdt_add_subnode(fdt, "/aliases"); |
| 361 | qemu_fdt_setprop_string(fdt, "/aliases", "ethernet0", nodename); |
| 362 | |
| 363 | g_free(nodename); |
| 364 | |
| 365 | nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0", |
| 366 | (long)memmap[SIFIVE_U_DEV_GEM].base); |
| 367 | qemu_fdt_add_subnode(fdt, nodename); |
| 368 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle); |
| 369 | qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0); |
| 370 | g_free(nodename); |
| 371 | |
| 372 | nodename = g_strdup_printf("/soc/pwm@%lx", |
| 373 | (long)memmap[SIFIVE_U_DEV_PWM0].base); |
| 374 | qemu_fdt_add_subnode(fdt, nodename); |
| 375 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,pwm0"); |
| 376 | qemu_fdt_setprop_cells(fdt, nodename, "reg", |
| 377 | 0x0, memmap[SIFIVE_U_DEV_PWM0].base, |
| 378 | 0x0, memmap[SIFIVE_U_DEV_PWM0].size); |
| 379 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); |
| 380 | qemu_fdt_setprop_cells(fdt, nodename, "interrupts", |
| 381 | SIFIVE_U_PWM0_IRQ0, SIFIVE_U_PWM0_IRQ1, |
| 382 | SIFIVE_U_PWM0_IRQ2, SIFIVE_U_PWM0_IRQ3); |
| 383 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", |
| 384 | prci_phandle, PRCI_CLK_TLCLK); |
| 385 | qemu_fdt_setprop_cell(fdt, nodename, "#pwm-cells", 0); |
| 386 | g_free(nodename); |
| 387 | |
| 388 | nodename = g_strdup_printf("/soc/pwm@%lx", |
| 389 | (long)memmap[SIFIVE_U_DEV_PWM1].base); |
| 390 | qemu_fdt_add_subnode(fdt, nodename); |
| 391 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,pwm0"); |
| 392 | qemu_fdt_setprop_cells(fdt, nodename, "reg", |
| 393 | 0x0, memmap[SIFIVE_U_DEV_PWM1].base, |
| 394 | 0x0, memmap[SIFIVE_U_DEV_PWM1].size); |
| 395 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); |
| 396 | qemu_fdt_setprop_cells(fdt, nodename, "interrupts", |
| 397 | SIFIVE_U_PWM1_IRQ0, SIFIVE_U_PWM1_IRQ1, |
| 398 | SIFIVE_U_PWM1_IRQ2, SIFIVE_U_PWM1_IRQ3); |
| 399 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", |
| 400 | prci_phandle, PRCI_CLK_TLCLK); |
| 401 | qemu_fdt_setprop_cell(fdt, nodename, "#pwm-cells", 0); |
| 402 | g_free(nodename); |
| 403 | |
| 404 | nodename = g_strdup_printf("/soc/serial@%lx", |
| 405 | (long)memmap[SIFIVE_U_DEV_UART1].base); |
| 406 | qemu_fdt_add_subnode(fdt, nodename); |
| 407 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); |
| 408 | qemu_fdt_setprop_cells(fdt, nodename, "reg", |
| 409 | 0x0, memmap[SIFIVE_U_DEV_UART1].base, |
| 410 | 0x0, memmap[SIFIVE_U_DEV_UART1].size); |
| 411 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", |
| 412 | prci_phandle, PRCI_CLK_TLCLK); |
| 413 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); |
| 414 | qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART1_IRQ); |
| 415 | |
| 416 | qemu_fdt_setprop_string(fdt, "/aliases", "serial1", nodename); |
| 417 | g_free(nodename); |
| 418 | |
| 419 | nodename = g_strdup_printf("/soc/serial@%lx", |
| 420 | (long)memmap[SIFIVE_U_DEV_UART0].base); |
| 421 | qemu_fdt_add_subnode(fdt, nodename); |
| 422 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); |
| 423 | qemu_fdt_setprop_cells(fdt, nodename, "reg", |
| 424 | 0x0, memmap[SIFIVE_U_DEV_UART0].base, |
| 425 | 0x0, memmap[SIFIVE_U_DEV_UART0].size); |
| 426 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", |
| 427 | prci_phandle, PRCI_CLK_TLCLK); |
| 428 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); |
| 429 | qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ); |
| 430 | |
| 431 | qemu_fdt_add_subnode(fdt, "/chosen"); |
| 432 | qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); |
| 433 | qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename); |
| 434 | |
| 435 | g_free(nodename); |
| 436 | } |
| 437 | |
| 438 | static void sifive_u_machine_reset(void *opaque, int n, int level) |
| 439 | { |
| 440 | /* gpio pin active low triggers reset */ |
| 441 | if (!level) { |
| 442 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
| 443 | } |
| 444 | } |
| 445 | |
| 446 | static void sifive_u_machine_init(MachineState *machine) |
| 447 | { |
| 448 | const MemMapEntry *memmap = sifive_u_memmap; |
| 449 | SiFiveUState *s = RISCV_U_MACHINE(machine); |
| 450 | MemoryRegion *system_memory = get_system_memory(); |
| 451 | MemoryRegion *flash0 = g_new(MemoryRegion, 1); |
| 452 | hwaddr start_addr = memmap[SIFIVE_U_DEV_DRAM].base; |
| 453 | hwaddr firmware_end_addr; |
| 454 | vaddr kernel_start_addr; |
| 455 | const char *firmware_name; |
| 456 | uint32_t start_addr_hi32 = 0x00000000; |
| 457 | uint32_t fdt_load_addr_hi32 = 0x00000000; |
| 458 | int i; |
| 459 | uint64_t fdt_load_addr; |
| 460 | uint64_t kernel_entry; |
| 461 | DriveInfo *dinfo; |
| 462 | BlockBackend *blk; |
| 463 | DeviceState *flash_dev, *sd_dev, *card_dev; |
| 464 | qemu_irq flash_cs, sd_cs; |
| 465 | RISCVBootInfo boot_info; |
| 466 | |
| 467 | /* Initialize SoC */ |
| 468 | object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC); |
| 469 | object_property_set_uint(OBJECT(&s->soc), "serial", s->serial, |
| 470 | &error_abort); |
| 471 | object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type, |
| 472 | &error_abort); |
| 473 | qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); |
| 474 | |
| 475 | /* register RAM */ |
| 476 | memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].base, |
| 477 | machine->ram); |
| 478 | |
| 479 | /* register QSPI0 Flash */ |
| 480 | memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0", |
| 481 | memmap[SIFIVE_U_DEV_FLASH0].size, &error_fatal); |
| 482 | memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_FLASH0].base, |
| 483 | flash0); |
| 484 | |
| 485 | /* register gpio-restart */ |
| 486 | qdev_connect_gpio_out(DEVICE(&(s->soc.gpio)), 10, |
| 487 | qemu_allocate_irq(sifive_u_machine_reset, NULL, 0)); |
| 488 | |
| 489 | /* load/create device tree */ |
| 490 | if (machine->dtb) { |
| 491 | machine->fdt = load_device_tree(machine->dtb, &s->fdt_size); |
| 492 | if (!machine->fdt) { |
| 493 | error_report("load_device_tree() failed"); |
| 494 | exit(1); |
| 495 | } |
| 496 | } else { |
| 497 | create_fdt(s, memmap, riscv_is_32bit(&s->soc.u_cpus)); |
| 498 | } |
| 499 | |
| 500 | if (s->start_in_flash) { |
| 501 | /* |
| 502 | * If start_in_flash property is given, assign s->msel to a value |
| 503 | * that representing booting from QSPI0 memory-mapped flash. |
| 504 | * |
| 505 | * This also means that when both start_in_flash and msel properties |
| 506 | * are given, start_in_flash takes the precedence over msel. |
| 507 | * |
| 508 | * Note this is to keep backward compatibility not to break existing |
| 509 | * users that use start_in_flash property. |
| 510 | */ |
| 511 | s->msel = MSEL_MEMMAP_QSPI0_FLASH; |
| 512 | } |
| 513 | |
| 514 | switch (s->msel) { |
| 515 | case MSEL_MEMMAP_QSPI0_FLASH: |
| 516 | start_addr = memmap[SIFIVE_U_DEV_FLASH0].base; |
| 517 | break; |
| 518 | case MSEL_L2LIM_QSPI0_FLASH: |
| 519 | case MSEL_L2LIM_QSPI2_SD: |
| 520 | start_addr = memmap[SIFIVE_U_DEV_L2LIM].base; |
| 521 | break; |
| 522 | default: |
| 523 | start_addr = memmap[SIFIVE_U_DEV_DRAM].base; |
| 524 | break; |
| 525 | } |
| 526 | |
| 527 | riscv_boot_info_init(&boot_info, &s->soc.u_cpus); |
| 528 | |
| 529 | firmware_name = riscv_default_firmware_name(&s->soc.u_cpus); |
| 530 | firmware_end_addr = riscv_find_and_load_firmware(machine, &boot_info, |
| 531 | firmware_name, |
| 532 | &start_addr, NULL); |
| 533 | |
| 534 | if (machine->kernel_filename) { |
| 535 | kernel_start_addr = riscv_calc_kernel_start_addr(&boot_info, |
| 536 | firmware_end_addr); |
| 537 | riscv_load_kernel(machine, &boot_info, kernel_start_addr, |
| 538 | true, NULL); |
| 539 | kernel_entry = boot_info.image_low_addr; |
| 540 | } else { |
| 541 | /* |
| 542 | * If dynamic firmware is used, it doesn't know where is the next mode |
| 543 | * if kernel argument is not set. |
| 544 | */ |
| 545 | kernel_entry = 0; |
| 546 | } |
| 547 | |
| 548 | fdt_load_addr = riscv_compute_fdt_addr(memmap[SIFIVE_U_DEV_DRAM].base, |
| 549 | memmap[SIFIVE_U_DEV_DRAM].size, |
| 550 | machine, &boot_info); |
| 551 | riscv_load_fdt(fdt_load_addr, machine->fdt); |
| 552 | |
| 553 | if (!riscv_is_32bit(&s->soc.u_cpus)) { |
| 554 | start_addr_hi32 = (uint64_t)start_addr >> 32; |
| 555 | fdt_load_addr_hi32 = fdt_load_addr >> 32; |
| 556 | } |
| 557 | |
| 558 | /* reset vector */ |
| 559 | uint32_t reset_vec[12] = { |
| 560 | s->msel, /* MSEL pin state */ |
| 561 | 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */ |
| 562 | 0x02c28613, /* addi a2, t0, %pcrel_lo(1b) */ |
| 563 | 0xf1402573, /* csrr a0, mhartid */ |
| 564 | 0, |
| 565 | 0, |
| 566 | 0x00028067, /* jr t0 */ |
| 567 | 0x00000000, /* padding for alignment */ |
| 568 | start_addr, /* start: .dword */ |
| 569 | start_addr_hi32, |
| 570 | fdt_load_addr, /* fdt_laddr: .dword */ |
| 571 | fdt_load_addr_hi32, |
| 572 | /* fw_dyn: */ |
| 573 | }; |
| 574 | |
| 575 | if (riscv_is_32bit(&s->soc.u_cpus)) { |
| 576 | reset_vec[4] = 0x0242a583; /* lw a1, 36(t0) */ |
| 577 | reset_vec[5] = 0x01c2a283; /* lw t0, 28(t0) */ |
| 578 | } else { |
| 579 | reset_vec[4] = 0x0242b583; /* ld a1, 36(t0) */ |
| 580 | reset_vec[5] = 0x01c2b283; /* ld t0, 28(t0) */ |
| 581 | } |
| 582 | |
| 583 | |
| 584 | /* copy in the reset vector in little_endian byte order */ |
| 585 | for (i = 0; i < ARRAY_SIZE(reset_vec); i++) { |
| 586 | reset_vec[i] = cpu_to_le32(reset_vec[i]); |
| 587 | } |
| 588 | rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), |
| 589 | memmap[SIFIVE_U_DEV_MROM].base, &address_space_memory); |
| 590 | |
| 591 | riscv_rom_copy_firmware_info(machine, &s->soc.u_cpus, |
| 592 | memmap[SIFIVE_U_DEV_MROM].base, |
| 593 | memmap[SIFIVE_U_DEV_MROM].size, |
| 594 | sizeof(reset_vec), kernel_entry); |
| 595 | |
| 596 | /* Connect an SPI flash to SPI0 */ |
| 597 | flash_dev = qdev_new("is25wp256"); |
| 598 | dinfo = drive_get(IF_MTD, 0, 0); |
| 599 | if (dinfo) { |
| 600 | qdev_prop_set_drive_err(flash_dev, "drive", |
| 601 | blk_by_legacy_dinfo(dinfo), |
| 602 | &error_fatal); |
| 603 | } |
| 604 | qdev_realize_and_unref(flash_dev, BUS(s->soc.spi0.spi), &error_fatal); |
| 605 | |
| 606 | flash_cs = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); |
| 607 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi0), 1, flash_cs); |
| 608 | |
| 609 | /* Connect an SD card to SPI2 */ |
| 610 | sd_dev = ssi_create_peripheral(s->soc.spi2.spi, "ssi-sd"); |
| 611 | |
| 612 | sd_cs = qdev_get_gpio_in_named(sd_dev, SSI_GPIO_CS, 0); |
| 613 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi2), 1, sd_cs); |
| 614 | |
| 615 | dinfo = drive_get(IF_SD, 0, 0); |
| 616 | blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; |
| 617 | card_dev = qdev_new(TYPE_SD_CARD_SPI); |
| 618 | qdev_prop_set_drive_err(card_dev, "drive", blk, &error_fatal); |
| 619 | qdev_realize_and_unref(card_dev, |
| 620 | qdev_get_child_bus(sd_dev, "sd-bus"), |
| 621 | &error_fatal); |
| 622 | } |
| 623 | |
| 624 | static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp) |
| 625 | { |
| 626 | SiFiveUState *s = RISCV_U_MACHINE(obj); |
| 627 | |
| 628 | return s->start_in_flash; |
| 629 | } |
| 630 | |
| 631 | static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error **errp) |
| 632 | { |
| 633 | SiFiveUState *s = RISCV_U_MACHINE(obj); |
| 634 | |
| 635 | s->start_in_flash = value; |
| 636 | } |
| 637 | |
| 638 | static void sifive_u_machine_instance_init(Object *obj) |
| 639 | { |
| 640 | SiFiveUState *s = RISCV_U_MACHINE(obj); |
| 641 | |
| 642 | s->start_in_flash = false; |
| 643 | s->msel = 0; |
| 644 | object_property_add_uint32_ptr(obj, "msel", &s->msel, |
| 645 | OBJ_PROP_FLAG_READWRITE); |
| 646 | object_property_set_description(obj, "msel", |
| 647 | "Mode Select (MSEL[3:0]) pin state"); |
| 648 | |
| 649 | s->serial = OTP_SERIAL; |
| 650 | object_property_add_uint32_ptr(obj, "serial", &s->serial, |
| 651 | OBJ_PROP_FLAG_READWRITE); |
| 652 | object_property_set_description(obj, "serial", "Board serial number"); |
| 653 | } |
| 654 | |
| 655 | static void sifive_u_machine_class_init(ObjectClass *oc, const void *data) |
| 656 | { |
| 657 | MachineClass *mc = MACHINE_CLASS(oc); |
| 658 | |
| 659 | mc->desc = "RISC-V Board compatible with SiFive U SDK"; |
| 660 | mc->init = sifive_u_machine_init; |
| 661 | mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT; |
| 662 | mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; |
| 663 | mc->default_cpu_type = SIFIVE_U_CPU; |
| 664 | mc->default_cpus = mc->min_cpus; |
| 665 | mc->default_ram_id = "riscv.sifive.u.ram"; |
| 666 | mc->auto_create_sdcard = true; |
| 667 | |
| 668 | object_class_property_add_bool(oc, "start-in-flash", |
| 669 | sifive_u_machine_get_start_in_flash, |
| 670 | sifive_u_machine_set_start_in_flash); |
| 671 | object_class_property_set_description(oc, "start-in-flash", |
| 672 | "Set on to tell QEMU's ROM to jump to " |
| 673 | "flash. Otherwise QEMU will jump to DRAM " |
| 674 | "or L2LIM depending on the msel value"); |
| 675 | } |
| 676 | |
| 677 | static const TypeInfo sifive_u_machine_typeinfo = { |
| 678 | .name = MACHINE_TYPE_NAME("sifive_u"), |
| 679 | .parent = TYPE_MACHINE, |
| 680 | .class_init = sifive_u_machine_class_init, |
| 681 | .instance_init = sifive_u_machine_instance_init, |
| 682 | .instance_size = sizeof(SiFiveUState), |
| 683 | .interfaces = riscv32_64_machine_interfaces, |
| 684 | }; |
| 685 | |
| 686 | static void sifive_u_machine_init_register_types(void) |
| 687 | { |
| 688 | type_register_static(&sifive_u_machine_typeinfo); |
| 689 | } |
| 690 | |
| 691 | type_init(sifive_u_machine_init_register_types) |
| 692 | |
| 693 | static void sifive_u_soc_instance_init(Object *obj) |
| 694 | { |
| 695 | SiFiveUSoCState *s = RISCV_U_SOC(obj); |
| 696 | |
| 697 | object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER); |
| 698 | qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); |
| 699 | |
| 700 | object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus, |
| 701 | TYPE_RISCV_HART_ARRAY); |
| 702 | qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); |
| 703 | qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); |
| 704 | qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU); |
| 705 | qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004); |
| 706 | |
| 707 | object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER); |
| 708 | qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1); |
| 709 | |
| 710 | object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus, |
| 711 | TYPE_RISCV_HART_ARRAY); |
| 712 | |
| 713 | object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI); |
| 714 | object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP); |
| 715 | object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM); |
| 716 | object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO); |
| 717 | object_initialize_child(obj, "pdma", &s->dma, TYPE_SIFIVE_PDMA); |
| 718 | object_initialize_child(obj, "spi0", &s->spi0, TYPE_SIFIVE_SPI); |
| 719 | object_initialize_child(obj, "spi2", &s->spi2, TYPE_SIFIVE_SPI); |
| 720 | object_initialize_child(obj, "pwm0", &s->pwm[0], TYPE_SIFIVE_PWM); |
| 721 | object_initialize_child(obj, "pwm1", &s->pwm[1], TYPE_SIFIVE_PWM); |
| 722 | } |
| 723 | |
| 724 | static void sifive_u_soc_realize(DeviceState *dev, Error **errp) |
| 725 | { |
| 726 | MachineState *ms = MACHINE(qdev_get_machine()); |
| 727 | SiFiveUSoCState *s = RISCV_U_SOC(dev); |
| 728 | const MemMapEntry *memmap = sifive_u_memmap; |
| 729 | MemoryRegion *system_memory = get_system_memory(); |
| 730 | MemoryRegion *mask_rom = g_new(MemoryRegion, 1); |
| 731 | MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1); |
| 732 | char *plic_hart_config; |
| 733 | int i, j; |
| 734 | |
| 735 | qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); |
| 736 | qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); |
| 737 | qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", s->cpu_type); |
| 738 | qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004); |
| 739 | |
| 740 | sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_fatal); |
| 741 | sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_fatal); |
| 742 | /* |
| 743 | * The cluster must be realized after the RISC-V hart array container, |
| 744 | * as the container's CPU object is only created on realize, and the |
| 745 | * CPU must exist and have been parented into the cluster before the |
| 746 | * cluster is realized. |
| 747 | */ |
| 748 | qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort); |
| 749 | qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort); |
| 750 | |
| 751 | /* boot rom */ |
| 752 | memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom", |
| 753 | memmap[SIFIVE_U_DEV_MROM].size, &error_fatal); |
| 754 | memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_MROM].base, |
| 755 | mask_rom); |
| 756 | |
| 757 | /* |
| 758 | * Add L2-LIM at reset size. |
| 759 | * This should be reduced in size as the L2 Cache Controller WayEnable |
| 760 | * register is incremented. Unfortunately I don't see a nice (or any) way |
| 761 | * to handle reducing or blocking out the L2 LIM while still allowing it |
| 762 | * be re returned to all enabled after a reset. For the time being, just |
| 763 | * leave it enabled all the time. This won't break anything, but will be |
| 764 | * too generous to misbehaving guests. |
| 765 | */ |
| 766 | memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim", |
| 767 | memmap[SIFIVE_U_DEV_L2LIM].size, &error_fatal); |
| 768 | memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_L2LIM].base, |
| 769 | l2lim_mem); |
| 770 | |
| 771 | /* create PLIC hart topology configuration string */ |
| 772 | plic_hart_config = riscv_plic_hart_config_string(ms->smp.cpus); |
| 773 | |
| 774 | /* MMIO */ |
| 775 | s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base, |
| 776 | plic_hart_config, ms->smp.cpus, 0, |
| 777 | SIFIVE_U_PLIC_NUM_SOURCES, |
| 778 | SIFIVE_U_PLIC_NUM_PRIORITIES, |
| 779 | SIFIVE_U_PLIC_PRIORITY_BASE, |
| 780 | SIFIVE_U_PLIC_PENDING_BASE, |
| 781 | SIFIVE_U_PLIC_ENABLE_BASE, |
| 782 | SIFIVE_U_PLIC_ENABLE_STRIDE, |
| 783 | SIFIVE_U_PLIC_CONTEXT_BASE, |
| 784 | SIFIVE_U_PLIC_CONTEXT_STRIDE, |
| 785 | memmap[SIFIVE_U_DEV_PLIC].size); |
| 786 | g_free(plic_hart_config); |
| 787 | sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART0].base, |
| 788 | serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ)); |
| 789 | sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART1].base, |
| 790 | serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ)); |
| 791 | riscv_aclint_swi_create(memmap[SIFIVE_U_DEV_CLINT].base, 0, |
| 792 | ms->smp.cpus, false); |
| 793 | riscv_aclint_mtimer_create(memmap[SIFIVE_U_DEV_CLINT].base + |
| 794 | RISCV_ACLINT_SWI_SIZE, |
| 795 | RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus, |
| 796 | RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, |
| 797 | CLINT_TIMEBASE_FREQ, false); |
| 798 | |
| 799 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) { |
| 800 | return; |
| 801 | } |
| 802 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_DEV_PRCI].base); |
| 803 | |
| 804 | qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16); |
| 805 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { |
| 806 | return; |
| 807 | } |
| 808 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_DEV_GPIO].base); |
| 809 | |
| 810 | /* Pass all GPIOs to the SOC layer so they are available to the board */ |
| 811 | qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL); |
| 812 | |
| 813 | /* Connect GPIO interrupts to the PLIC */ |
| 814 | for (i = 0; i < 16; i++) { |
| 815 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i, |
| 816 | qdev_get_gpio_in(DEVICE(s->plic), |
| 817 | SIFIVE_U_GPIO_IRQ0 + i)); |
| 818 | } |
| 819 | |
| 820 | /* PDMA */ |
| 821 | sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp); |
| 822 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_DEV_PDMA].base); |
| 823 | |
| 824 | /* Connect PDMA interrupts to the PLIC */ |
| 825 | for (i = 0; i < SIFIVE_PDMA_IRQS; i++) { |
| 826 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i, |
| 827 | qdev_get_gpio_in(DEVICE(s->plic), |
| 828 | SIFIVE_U_PDMA_IRQ0 + i)); |
| 829 | } |
| 830 | |
| 831 | qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial); |
| 832 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) { |
| 833 | return; |
| 834 | } |
| 835 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_DEV_OTP].base); |
| 836 | |
| 837 | qemu_configure_nic_device(DEVICE(&s->gem), true, NULL); |
| 838 | object_property_set_int(OBJECT(&s->gem), "revision", GEM_REVISION, |
| 839 | &error_abort); |
| 840 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), errp)) { |
| 841 | return; |
| 842 | } |
| 843 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_DEV_GEM].base); |
| 844 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0, |
| 845 | qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ)); |
| 846 | |
| 847 | /* PWM */ |
| 848 | for (i = 0; i < 2; i++) { |
| 849 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->pwm[i]), errp)) { |
| 850 | return; |
| 851 | } |
| 852 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->pwm[i]), 0, |
| 853 | memmap[SIFIVE_U_DEV_PWM0].base + (0x1000 * i)); |
| 854 | |
| 855 | /* Connect PWM interrupts to the PLIC */ |
| 856 | for (j = 0; j < SIFIVE_PWM_IRQS; j++) { |
| 857 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->pwm[i]), j, |
| 858 | qdev_get_gpio_in(DEVICE(s->plic), |
| 859 | SIFIVE_U_PWM0_IRQ0 + (i * 4) + j)); |
| 860 | } |
| 861 | } |
| 862 | |
| 863 | create_unimplemented_device("riscv.sifive.u.gem-mgmt", |
| 864 | memmap[SIFIVE_U_DEV_GEM_MGMT].base, memmap[SIFIVE_U_DEV_GEM_MGMT].size); |
| 865 | |
| 866 | create_unimplemented_device("riscv.sifive.u.dmc", |
| 867 | memmap[SIFIVE_U_DEV_DMC].base, memmap[SIFIVE_U_DEV_DMC].size); |
| 868 | |
| 869 | create_unimplemented_device("riscv.sifive.u.l2cc", |
| 870 | memmap[SIFIVE_U_DEV_L2CC].base, memmap[SIFIVE_U_DEV_L2CC].size); |
| 871 | |
| 872 | sysbus_realize(SYS_BUS_DEVICE(&s->spi0), errp); |
| 873 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi0), 0, |
| 874 | memmap[SIFIVE_U_DEV_QSPI0].base); |
| 875 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi0), 0, |
| 876 | qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI0_IRQ)); |
| 877 | sysbus_realize(SYS_BUS_DEVICE(&s->spi2), errp); |
| 878 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi2), 0, |
| 879 | memmap[SIFIVE_U_DEV_QSPI2].base); |
| 880 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi2), 0, |
| 881 | qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI2_IRQ)); |
| 882 | } |
| 883 | |
| 884 | static const Property sifive_u_soc_props[] = { |
| 885 | DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL), |
| 886 | DEFINE_PROP_STRING("cpu-type", SiFiveUSoCState, cpu_type), |
| 887 | }; |
| 888 | |
| 889 | static void sifive_u_soc_class_init(ObjectClass *oc, const void *data) |
| 890 | { |
| 891 | DeviceClass *dc = DEVICE_CLASS(oc); |
| 892 | |
| 893 | device_class_set_props(dc, sifive_u_soc_props); |
| 894 | dc->realize = sifive_u_soc_realize; |
| 895 | /* Reason: Uses serial_hds in realize function, thus can't be used twice */ |
| 896 | dc->user_creatable = false; |
| 897 | } |
| 898 | |
| 899 | static const TypeInfo sifive_u_soc_type_info = { |
| 900 | .name = TYPE_RISCV_U_SOC, |
| 901 | .parent = TYPE_DEVICE, |
| 902 | .instance_size = sizeof(SiFiveUSoCState), |
| 903 | .instance_init = sifive_u_soc_instance_init, |
| 904 | .class_init = sifive_u_soc_class_init, |
| 905 | }; |
| 906 | |
| 907 | static void sifive_u_soc_register_types(void) |
| 908 | { |
| 909 | type_register_static(&sifive_u_soc_type_info); |
| 910 | } |
| 911 | |
| 912 | type_init(sifive_u_soc_register_types) |