| 1 | /* |
| 2 | * QEMU RISC-V VirtIO Board |
| 3 | * |
| 4 | * Copyright (c) 2017 SiFive, Inc. |
| 5 | * |
| 6 | * RISC-V machine with 16550a UART and VirtIO MMIO |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify it |
| 9 | * under the terms and conditions of the GNU General Public License, |
| 10 | * version 2 or later, as published by the Free Software Foundation. |
| 11 | * |
| 12 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 15 | * more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License along with |
| 18 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 19 | */ |
| 20 | |
| 21 | #include "qemu/osdep.h" |
| 22 | #include "qemu/units.h" |
| 23 | #include "qemu/error-report.h" |
| 24 | #include "qemu/guest-random.h" |
| 25 | #include "qapi/error.h" |
| 26 | #include "hw/core/boards.h" |
| 27 | #include "hw/core/loader.h" |
| 28 | #include "hw/core/sysbus.h" |
| 29 | #include "hw/core/qdev-properties.h" |
| 30 | #include "hw/char/serial-mm.h" |
| 31 | #include "target/riscv/cpu.h" |
| 32 | #include "hw/core/sysbus-fdt.h" |
| 33 | #include "hw/riscv/riscv_hart.h" |
| 34 | #include "hw/riscv/iommu.h" |
| 35 | #include "hw/riscv/riscv-iommu-bits.h" |
| 36 | #include "hw/riscv/virt.h" |
| 37 | #include "hw/riscv/boot.h" |
| 38 | #include "hw/riscv/fdt-common.h" |
| 39 | #include "hw/riscv/machines-qom.h" |
| 40 | #include "hw/riscv/numa.h" |
| 41 | #include "kvm/kvm_riscv.h" |
| 42 | #include "hw/firmware/smbios.h" |
| 43 | #include "hw/intc/riscv_aclint.h" |
| 44 | #include "hw/intc/riscv_aplic.h" |
| 45 | #include "hw/intc/sifive_plic.h" |
| 46 | #include "hw/misc/sifive_test.h" |
| 47 | #include "hw/core/platform-bus.h" |
| 48 | #include "chardev/char.h" |
| 49 | #include "system/device_tree.h" |
| 50 | #include "system/system.h" |
| 51 | #include "system/tcg.h" |
| 52 | #include "system/kvm.h" |
| 53 | #include "system/tpm.h" |
| 54 | #include "system/qtest.h" |
| 55 | #include "hw/pci/pci.h" |
| 56 | #include "hw/pci-host/gpex.h" |
| 57 | #include "hw/display/ramfb.h" |
| 58 | #include "hw/acpi/aml-build.h" |
| 59 | #include "qapi/qapi-visit-common.h" |
| 60 | #include "hw/virtio/virtio-iommu.h" |
| 61 | #include "hw/uefi/var-service-api.h" |
| 62 | |
| 63 | #include "aia.h" |
| 64 | |
| 65 | /* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU. */ |
| 66 | static bool virt_use_kvm_aia_aplic_imsic(RISCVVirtAIAType aia_type) |
| 67 | { |
| 68 | bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC; |
| 69 | |
| 70 | return riscv_is_kvm_aia_aplic_imsic(msimode); |
| 71 | } |
| 72 | |
| 73 | static bool virt_use_emulated_aplic(RISCVVirtAIAType aia_type) |
| 74 | { |
| 75 | bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC; |
| 76 | |
| 77 | return riscv_use_emulated_aplic(msimode); |
| 78 | } |
| 79 | |
| 80 | static bool virt_aclint_allowed(void) |
| 81 | { |
| 82 | return tcg_enabled() || qtest_enabled(); |
| 83 | } |
| 84 | |
| 85 | static const MemMapEntry virt_memmap[] = { |
| 86 | [VIRT_DEBUG] = { 0x0, 0x100 }, |
| 87 | [VIRT_MROM] = { 0x1000, 0xf000 }, |
| 88 | [VIRT_TEST] = { 0x100000, 0x1000 }, |
| 89 | [VIRT_RTC] = { 0x101000, 0x1000 }, |
| 90 | [VIRT_CLINT] = { 0x2000000, 0x10000 }, |
| 91 | [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 }, |
| 92 | [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 }, |
| 93 | [VIRT_IOMMU_SYS] = { 0x3010000, 0x1000 }, |
| 94 | [VIRT_PLATFORM_BUS] = { 0x4000000, 0x2000000 }, |
| 95 | [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, |
| 96 | [VIRT_APLIC_M] = { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) }, |
| 97 | [VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) }, |
| 98 | [VIRT_UART0] = { 0x10000000, 0x100 }, |
| 99 | [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, |
| 100 | /* UART1 supports page isolation from UART0 */ |
| 101 | [VIRT_UART1] = { 0x1000a000, 0x100 }, |
| 102 | [VIRT_FW_CFG] = { 0x10100000, 0x18 }, |
| 103 | [VIRT_FLASH] = { 0x20000000, 0x4000000 }, |
| 104 | [VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE }, |
| 105 | [VIRT_IMSIC_S] = { 0x28000000, VIRT_IMSIC_MAX_SIZE }, |
| 106 | [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, |
| 107 | [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, |
| 108 | [VIRT_DRAM] = { 0x80000000, 0x0 }, |
| 109 | }; |
| 110 | |
| 111 | /* PCIe high mmio is fixed for RV32 */ |
| 112 | #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL |
| 113 | #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB) |
| 114 | |
| 115 | /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */ |
| 116 | #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB) |
| 117 | |
| 118 | static MemMapEntry virt_high_pcie_memmap; |
| 119 | |
| 120 | #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) |
| 121 | |
| 122 | static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, |
| 123 | const char *name, |
| 124 | const char *alias_prop_name) |
| 125 | { |
| 126 | /* |
| 127 | * Create a single flash device. We use the same parameters as |
| 128 | * the flash devices on the ARM virt board. |
| 129 | */ |
| 130 | DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); |
| 131 | |
| 132 | qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); |
| 133 | qdev_prop_set_uint8(dev, "width", 4); |
| 134 | qdev_prop_set_uint8(dev, "device-width", 2); |
| 135 | qdev_prop_set_bit(dev, "big-endian", false); |
| 136 | qdev_prop_set_uint16(dev, "id0", 0x89); |
| 137 | qdev_prop_set_uint16(dev, "id1", 0x18); |
| 138 | qdev_prop_set_uint16(dev, "id2", 0x00); |
| 139 | qdev_prop_set_uint16(dev, "id3", 0x00); |
| 140 | qdev_prop_set_string(dev, "name", name); |
| 141 | |
| 142 | object_property_add_child(OBJECT(s), name, OBJECT(dev)); |
| 143 | object_property_add_alias(OBJECT(s), alias_prop_name, |
| 144 | OBJECT(dev), "drive"); |
| 145 | |
| 146 | return PFLASH_CFI01(dev); |
| 147 | } |
| 148 | |
| 149 | static void virt_flash_create(RISCVVirtState *s) |
| 150 | { |
| 151 | s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0"); |
| 152 | s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1"); |
| 153 | } |
| 154 | |
| 155 | static void virt_flash_map1(PFlashCFI01 *flash, |
| 156 | hwaddr base, hwaddr size, |
| 157 | MemoryRegion *sysmem) |
| 158 | { |
| 159 | DeviceState *dev = DEVICE(flash); |
| 160 | |
| 161 | assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); |
| 162 | assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); |
| 163 | qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); |
| 164 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
| 165 | |
| 166 | memory_region_add_subregion(sysmem, base, |
| 167 | sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), |
| 168 | 0)); |
| 169 | } |
| 170 | |
| 171 | static void virt_flash_map(RISCVVirtState *s, |
| 172 | MemoryRegion *sysmem) |
| 173 | { |
| 174 | hwaddr flashsize = s->memmap[VIRT_FLASH].size / 2; |
| 175 | hwaddr flashbase = s->memmap[VIRT_FLASH].base; |
| 176 | |
| 177 | virt_flash_map1(s->flash[0], flashbase, flashsize, |
| 178 | sysmem); |
| 179 | virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize, |
| 180 | sysmem); |
| 181 | } |
| 182 | |
| 183 | static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename, |
| 184 | uint32_t irqchip_phandle) |
| 185 | { |
| 186 | int pin, dev; |
| 187 | uint32_t irq_map_stride = 0; |
| 188 | uint32_t full_irq_map[PCI_NUM_PINS * PCI_NUM_PINS * |
| 189 | FDT_MAX_INT_MAP_WIDTH] = {}; |
| 190 | uint32_t *irq_map = full_irq_map; |
| 191 | |
| 192 | /* |
| 193 | * This code creates a standard swizzle of interrupts such that |
| 194 | * each device's first interrupt is based on it's PCI_SLOT number. |
| 195 | * (See pci_swizzle_map_irq_fn()) |
| 196 | * |
| 197 | * We only need one entry per interrupt in the table (not one per |
| 198 | * possible slot) seeing the interrupt-map-mask will allow the table |
| 199 | * to wrap to any number of devices. |
| 200 | */ |
| 201 | for (dev = 0; dev < PCI_NUM_PINS; dev++) { |
| 202 | int devfn = dev * 0x8; |
| 203 | |
| 204 | for (pin = 0; pin < PCI_NUM_PINS; pin++) { |
| 205 | int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS); |
| 206 | int i = 0; |
| 207 | |
| 208 | /* Fill PCI address cells */ |
| 209 | irq_map[i] = cpu_to_be32(devfn << 8); |
| 210 | i += FDT_PCI_ADDR_CELLS; |
| 211 | |
| 212 | /* Fill PCI Interrupt cells */ |
| 213 | irq_map[i] = cpu_to_be32(pin + 1); |
| 214 | i += FDT_PCI_INT_CELLS; |
| 215 | |
| 216 | /* Fill interrupt controller phandle and cells */ |
| 217 | irq_map[i++] = cpu_to_be32(irqchip_phandle); |
| 218 | irq_map[i++] = cpu_to_be32(irq_nr); |
| 219 | if (s->aia_type != VIRT_AIA_TYPE_NONE) { |
| 220 | irq_map[i++] = cpu_to_be32(0x4); |
| 221 | } |
| 222 | |
| 223 | if (!irq_map_stride) { |
| 224 | irq_map_stride = i; |
| 225 | } |
| 226 | irq_map += irq_map_stride; |
| 227 | } |
| 228 | } |
| 229 | |
| 230 | qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map, |
| 231 | PCI_NUM_PINS * PCI_NUM_PINS * |
| 232 | irq_map_stride * sizeof(uint32_t)); |
| 233 | |
| 234 | qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", |
| 235 | 0x1800, 0, 0, 0x7); |
| 236 | } |
| 237 | |
| 238 | static void create_fdt_socket_aclint(RISCVVirtState *s, |
| 239 | int socket, |
| 240 | uint32_t *intc_phandles) |
| 241 | { |
| 242 | int cpu; |
| 243 | char *name; |
| 244 | unsigned long addr, size; |
| 245 | uint32_t aclint_cells_size; |
| 246 | g_autofree uint32_t *aclint_mswi_cells = NULL; |
| 247 | g_autofree uint32_t *aclint_sswi_cells = NULL; |
| 248 | g_autofree uint32_t *aclint_mtimer_cells = NULL; |
| 249 | MachineState *ms = MACHINE(s); |
| 250 | |
| 251 | aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); |
| 252 | aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); |
| 253 | aclint_sswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); |
| 254 | |
| 255 | for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { |
| 256 | aclint_mswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); |
| 257 | aclint_mswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_SOFT); |
| 258 | aclint_mtimer_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); |
| 259 | aclint_mtimer_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_TIMER); |
| 260 | aclint_sswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); |
| 261 | aclint_sswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_SOFT); |
| 262 | } |
| 263 | aclint_cells_size = s->soc[socket].num_harts * sizeof(uint32_t) * 2; |
| 264 | |
| 265 | if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { |
| 266 | addr = s->memmap[VIRT_CLINT].base + |
| 267 | (s->memmap[VIRT_CLINT].size * socket); |
| 268 | name = g_strdup_printf("/soc/mswi@%lx", addr); |
| 269 | |
| 270 | qemu_fdt_add_subnode(ms->fdt, name); |
| 271 | qemu_fdt_setprop_string(ms->fdt, name, "compatible", |
| 272 | "riscv,aclint-mswi"); |
| 273 | qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", |
| 274 | 2, addr, 2, RISCV_ACLINT_SWI_SIZE); |
| 275 | qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", |
| 276 | aclint_mswi_cells, aclint_cells_size); |
| 277 | qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); |
| 278 | qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); |
| 279 | riscv_socket_fdt_write_id(ms, name, socket); |
| 280 | g_free(name); |
| 281 | } |
| 282 | |
| 283 | if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { |
| 284 | addr = s->memmap[VIRT_CLINT].base + |
| 285 | (RISCV_ACLINT_DEFAULT_MTIMER_SIZE * socket); |
| 286 | size = RISCV_ACLINT_DEFAULT_MTIMER_SIZE; |
| 287 | } else { |
| 288 | addr = s->memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE + |
| 289 | (s->memmap[VIRT_CLINT].size * socket); |
| 290 | size = s->memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE; |
| 291 | } |
| 292 | name = g_strdup_printf("/soc/mtimer@%lx", addr); |
| 293 | qemu_fdt_add_subnode(ms->fdt, name); |
| 294 | qemu_fdt_setprop_string(ms->fdt, name, "compatible", |
| 295 | "riscv,aclint-mtimer"); |
| 296 | qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", |
| 297 | 2, addr + RISCV_ACLINT_DEFAULT_MTIME, |
| 298 | 2, size - RISCV_ACLINT_DEFAULT_MTIME, |
| 299 | 2, addr + RISCV_ACLINT_DEFAULT_MTIMECMP, |
| 300 | 2, RISCV_ACLINT_DEFAULT_MTIME); |
| 301 | qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", |
| 302 | aclint_mtimer_cells, aclint_cells_size); |
| 303 | riscv_socket_fdt_write_id(ms, name, socket); |
| 304 | g_free(name); |
| 305 | |
| 306 | if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { |
| 307 | addr = s->memmap[VIRT_ACLINT_SSWI].base + |
| 308 | (s->memmap[VIRT_ACLINT_SSWI].size * socket); |
| 309 | |
| 310 | name = g_strdup_printf("/soc/sswi@%lx", addr); |
| 311 | qemu_fdt_add_subnode(ms->fdt, name); |
| 312 | qemu_fdt_setprop_string(ms->fdt, name, "compatible", |
| 313 | "riscv,aclint-sswi"); |
| 314 | qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", |
| 315 | 2, addr, 2, s->memmap[VIRT_ACLINT_SSWI].size); |
| 316 | qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", |
| 317 | aclint_sswi_cells, aclint_cells_size); |
| 318 | qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); |
| 319 | qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); |
| 320 | riscv_socket_fdt_write_id(ms, name, socket); |
| 321 | g_free(name); |
| 322 | } |
| 323 | } |
| 324 | |
| 325 | static void create_fdt_socket_plic(RISCVVirtState *s, |
| 326 | int socket, |
| 327 | uint32_t *phandle, uint32_t *intc_phandles, |
| 328 | uint32_t *plic_phandles) |
| 329 | { |
| 330 | int cpu; |
| 331 | g_autofree char *plic_name = NULL; |
| 332 | g_autofree uint32_t *plic_cells; |
| 333 | MachineState *ms = MACHINE(s); |
| 334 | unsigned long plic_addr = s->memmap[VIRT_PLIC].base + |
| 335 | (s->memmap[VIRT_PLIC].size * socket); |
| 336 | bool numa_enabled = riscv_numa_enabled(MACHINE(s)); |
| 337 | uint32_t cells_length; |
| 338 | |
| 339 | plic_name = g_strdup_printf("/soc/interrupt-controller@%lx", plic_addr); |
| 340 | |
| 341 | if (kvm_enabled()) { |
| 342 | cells_length = s->soc[socket].num_harts * 2; |
| 343 | plic_cells = g_new0(uint32_t, cells_length); |
| 344 | |
| 345 | for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { |
| 346 | plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); |
| 347 | plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); |
| 348 | } |
| 349 | } else { |
| 350 | cells_length = s->soc[socket].num_harts * 4; |
| 351 | plic_cells = g_new0(uint32_t, cells_length); |
| 352 | |
| 353 | for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { |
| 354 | plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); |
| 355 | plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); |
| 356 | plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); |
| 357 | plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); |
| 358 | } |
| 359 | } |
| 360 | |
| 361 | plic_phandles[socket] = (*phandle)++; |
| 362 | |
| 363 | create_fdt_plic(ms->fdt, plic_addr, s->memmap[VIRT_PLIC].size, |
| 364 | plic_phandles[socket], FDT_PLIC_INT_CELLS, |
| 365 | FDT_PLIC_ADDR_CELLS, plic_cells, |
| 366 | cells_length * sizeof(uint32_t), |
| 367 | VIRT_IRQCHIP_NUM_SOURCES - 1, |
| 368 | numa_enabled, socket); |
| 369 | |
| 370 | if (!socket) { |
| 371 | platform_bus_add_all_fdt_nodes(ms->fdt, plic_name, |
| 372 | s->memmap[VIRT_PLATFORM_BUS].base, |
| 373 | s->memmap[VIRT_PLATFORM_BUS].size, |
| 374 | VIRT_PLATFORM_BUS_IRQ); |
| 375 | } |
| 376 | } |
| 377 | |
| 378 | static void create_fdt_one_imsic(RISCVVirtState *s, hwaddr base_addr, |
| 379 | uint32_t *intc_phandles, uint32_t msi_phandle, |
| 380 | bool m_mode, uint32_t imsic_guest_bits) |
| 381 | { |
| 382 | int cpu, socket; |
| 383 | g_autofree char *imsic_name = NULL; |
| 384 | MachineState *ms = MACHINE(s); |
| 385 | int socket_count = riscv_socket_count(ms); |
| 386 | uint32_t imsic_max_hart_per_socket, imsic_addr, imsic_size; |
| 387 | g_autofree uint32_t *imsic_cells = NULL; |
| 388 | g_autofree uint32_t *imsic_regs = NULL; |
| 389 | static const char * const imsic_compat[2] = { |
| 390 | "qemu,imsics", "riscv,imsics" |
| 391 | }; |
| 392 | |
| 393 | imsic_cells = g_new0(uint32_t, ms->smp.cpus * 2); |
| 394 | imsic_regs = g_new0(uint32_t, socket_count * 4); |
| 395 | |
| 396 | for (cpu = 0; cpu < ms->smp.cpus; cpu++) { |
| 397 | imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); |
| 398 | imsic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT); |
| 399 | } |
| 400 | |
| 401 | imsic_max_hart_per_socket = 0; |
| 402 | for (socket = 0; socket < socket_count; socket++) { |
| 403 | imsic_addr = base_addr + socket * VIRT_IMSIC_GROUP_MAX_SIZE; |
| 404 | imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) * |
| 405 | s->soc[socket].num_harts; |
| 406 | imsic_regs[socket * 4 + 0] = 0; |
| 407 | imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr); |
| 408 | imsic_regs[socket * 4 + 2] = 0; |
| 409 | imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size); |
| 410 | if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { |
| 411 | imsic_max_hart_per_socket = s->soc[socket].num_harts; |
| 412 | } |
| 413 | } |
| 414 | |
| 415 | imsic_name = g_strdup_printf("/soc/interrupt-controller@%lx", |
| 416 | (unsigned long)base_addr); |
| 417 | qemu_fdt_add_subnode(ms->fdt, imsic_name); |
| 418 | qemu_fdt_setprop_string_array(ms->fdt, imsic_name, "compatible", |
| 419 | (char **)&imsic_compat, |
| 420 | ARRAY_SIZE(imsic_compat)); |
| 421 | |
| 422 | qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells", |
| 423 | FDT_IMSIC_INT_CELLS); |
| 424 | qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", NULL, 0); |
| 425 | qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", NULL, 0); |
| 426 | qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended", |
| 427 | imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2); |
| 428 | qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs, |
| 429 | socket_count * sizeof(uint32_t) * 4); |
| 430 | qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids", |
| 431 | VIRT_IRQCHIP_NUM_MSIS); |
| 432 | |
| 433 | if (imsic_guest_bits) { |
| 434 | qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,guest-index-bits", |
| 435 | imsic_guest_bits); |
| 436 | } |
| 437 | |
| 438 | if (socket_count > 1) { |
| 439 | qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits", |
| 440 | imsic_num_bits(imsic_max_hart_per_socket)); |
| 441 | qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits", |
| 442 | imsic_num_bits(socket_count)); |
| 443 | qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift", |
| 444 | IMSIC_MMIO_GROUP_MIN_SHIFT); |
| 445 | } |
| 446 | qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", msi_phandle); |
| 447 | } |
| 448 | |
| 449 | static void create_fdt_imsic(RISCVVirtState *s, |
| 450 | uint32_t *phandle, uint32_t *intc_phandles, |
| 451 | uint32_t *msi_m_phandle, uint32_t *msi_s_phandle) |
| 452 | { |
| 453 | *msi_m_phandle = (*phandle)++; |
| 454 | *msi_s_phandle = (*phandle)++; |
| 455 | |
| 456 | if (!kvm_enabled()) { |
| 457 | /* M-level IMSIC node */ |
| 458 | create_fdt_one_imsic(s, s->memmap[VIRT_IMSIC_M].base, intc_phandles, |
| 459 | *msi_m_phandle, true, 0); |
| 460 | } |
| 461 | |
| 462 | /* S-level IMSIC node */ |
| 463 | create_fdt_one_imsic(s, s->memmap[VIRT_IMSIC_S].base, intc_phandles, |
| 464 | *msi_s_phandle, false, |
| 465 | imsic_num_bits(s->aia_guests + 1)); |
| 466 | |
| 467 | } |
| 468 | |
| 469 | /* Caller must free string after use */ |
| 470 | static char *fdt_get_aplic_nodename(unsigned long aplic_addr) |
| 471 | { |
| 472 | return g_strdup_printf("/soc/interrupt-controller@%lx", aplic_addr); |
| 473 | } |
| 474 | |
| 475 | static void create_fdt_one_aplic(RISCVVirtState *s, int socket, |
| 476 | unsigned long aplic_addr, uint32_t aplic_size, |
| 477 | uint32_t msi_phandle, |
| 478 | uint32_t *intc_phandles, |
| 479 | uint32_t aplic_phandle, |
| 480 | uint32_t aplic_child_phandle, |
| 481 | bool m_mode, int num_harts) |
| 482 | { |
| 483 | int cpu; |
| 484 | g_autofree char *aplic_name = fdt_get_aplic_nodename(aplic_addr); |
| 485 | g_autofree uint32_t *aplic_cells = g_new0(uint32_t, num_harts * 2); |
| 486 | MachineState *ms = MACHINE(s); |
| 487 | static const char * const aplic_compat[2] = { |
| 488 | "qemu,aplic", "riscv,aplic" |
| 489 | }; |
| 490 | |
| 491 | for (cpu = 0; cpu < num_harts; cpu++) { |
| 492 | aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); |
| 493 | aplic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT); |
| 494 | } |
| 495 | |
| 496 | qemu_fdt_add_subnode(ms->fdt, aplic_name); |
| 497 | qemu_fdt_setprop_string_array(ms->fdt, aplic_name, "compatible", |
| 498 | (char **)&aplic_compat, |
| 499 | ARRAY_SIZE(aplic_compat)); |
| 500 | qemu_fdt_setprop_cell(ms->fdt, aplic_name, "#address-cells", |
| 501 | FDT_APLIC_ADDR_CELLS); |
| 502 | qemu_fdt_setprop_cell(ms->fdt, aplic_name, |
| 503 | "#interrupt-cells", FDT_APLIC_INT_CELLS); |
| 504 | qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0); |
| 505 | |
| 506 | if (s->aia_type == VIRT_AIA_TYPE_APLIC) { |
| 507 | qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended", |
| 508 | aplic_cells, num_harts * sizeof(uint32_t) * 2); |
| 509 | } else { |
| 510 | qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_phandle); |
| 511 | } |
| 512 | |
| 513 | qemu_fdt_setprop_sized_cells(ms->fdt, aplic_name, "reg", |
| 514 | 2, aplic_addr, 2, aplic_size); |
| 515 | qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources", |
| 516 | VIRT_IRQCHIP_NUM_SOURCES); |
| 517 | |
| 518 | if (aplic_child_phandle) { |
| 519 | qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children", |
| 520 | aplic_child_phandle); |
| 521 | qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegation", |
| 522 | aplic_child_phandle, 0x1, |
| 523 | VIRT_IRQCHIP_NUM_SOURCES); |
| 524 | } |
| 525 | |
| 526 | riscv_socket_fdt_write_id(ms, aplic_name, socket); |
| 527 | qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_phandle); |
| 528 | } |
| 529 | |
| 530 | static void create_fdt_socket_aplic(RISCVVirtState *s, |
| 531 | int socket, |
| 532 | uint32_t msi_m_phandle, |
| 533 | uint32_t msi_s_phandle, |
| 534 | uint32_t *phandle, |
| 535 | uint32_t *intc_phandles, |
| 536 | uint32_t *aplic_phandles, |
| 537 | int num_harts) |
| 538 | { |
| 539 | unsigned long aplic_addr; |
| 540 | MachineState *ms = MACHINE(s); |
| 541 | uint32_t aplic_m_phandle, aplic_s_phandle; |
| 542 | |
| 543 | aplic_m_phandle = (*phandle)++; |
| 544 | aplic_s_phandle = (*phandle)++; |
| 545 | |
| 546 | if (!kvm_enabled()) { |
| 547 | /* M-level APLIC node */ |
| 548 | aplic_addr = s->memmap[VIRT_APLIC_M].base + |
| 549 | (s->memmap[VIRT_APLIC_M].size * socket); |
| 550 | create_fdt_one_aplic(s, socket, aplic_addr, |
| 551 | s->memmap[VIRT_APLIC_M].size, |
| 552 | msi_m_phandle, intc_phandles, |
| 553 | aplic_m_phandle, aplic_s_phandle, |
| 554 | true, num_harts); |
| 555 | } |
| 556 | |
| 557 | /* S-level APLIC node */ |
| 558 | aplic_addr = s->memmap[VIRT_APLIC_S].base + |
| 559 | (s->memmap[VIRT_APLIC_S].size * socket); |
| 560 | create_fdt_one_aplic(s, socket, aplic_addr, s->memmap[VIRT_APLIC_S].size, |
| 561 | msi_s_phandle, intc_phandles, |
| 562 | aplic_s_phandle, 0, |
| 563 | false, num_harts); |
| 564 | |
| 565 | if (!socket) { |
| 566 | g_autofree char *aplic_name = fdt_get_aplic_nodename(aplic_addr); |
| 567 | platform_bus_add_all_fdt_nodes(ms->fdt, aplic_name, |
| 568 | s->memmap[VIRT_PLATFORM_BUS].base, |
| 569 | s->memmap[VIRT_PLATFORM_BUS].size, |
| 570 | VIRT_PLATFORM_BUS_IRQ); |
| 571 | } |
| 572 | |
| 573 | aplic_phandles[socket] = aplic_s_phandle; |
| 574 | } |
| 575 | |
| 576 | static void create_fdt_pmu(RISCVVirtState *s) |
| 577 | { |
| 578 | g_autofree char *pmu_name = g_strdup_printf("/pmu"); |
| 579 | MachineState *ms = MACHINE(s); |
| 580 | RISCVCPU *hart = &s->soc[0].harts[0]; |
| 581 | |
| 582 | qemu_fdt_add_subnode(ms->fdt, pmu_name); |
| 583 | qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu"); |
| 584 | riscv_pmu_generate_fdt_node(ms->fdt, hart->pmu_avail_ctrs, pmu_name); |
| 585 | } |
| 586 | |
| 587 | static void create_fdt_sockets(RISCVVirtState *s, |
| 588 | uint32_t *phandle, |
| 589 | uint32_t *irq_mmio_phandle, |
| 590 | uint32_t *irq_pcie_phandle, |
| 591 | uint32_t *irq_virtio_phandle, |
| 592 | uint32_t *msi_pcie_phandle) |
| 593 | { |
| 594 | int socket, phandle_pos; |
| 595 | MachineState *ms = MACHINE(s); |
| 596 | uint32_t msi_m_phandle = 0, msi_s_phandle = 0; |
| 597 | uint32_t xplic_phandles[MAX_NODES]; |
| 598 | g_autofree uint32_t *intc_phandles = NULL; |
| 599 | int socket_count = riscv_socket_count(ms); |
| 600 | bool numa_enabled = riscv_numa_enabled(ms); |
| 601 | bool is_32_bit = riscv_is_32bit(&s->soc[0]); |
| 602 | |
| 603 | fdt_create_cpu_socket_subnode(ms->fdt, |
| 604 | kvm_enabled() ? kvm_riscv_get_timebase_frequency(&s->soc->harts[0]) : |
| 605 | RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); |
| 606 | |
| 607 | intc_phandles = g_new0(uint32_t, ms->smp.cpus); |
| 608 | |
| 609 | phandle_pos = ms->smp.cpus; |
| 610 | for (socket = (socket_count - 1); socket >= 0; socket--) { |
| 611 | hwaddr memaddr = s->memmap[VIRT_DRAM].base + |
| 612 | riscv_socket_mem_offset(ms, socket); |
| 613 | uint64_t memsize = riscv_socket_mem_size(ms, socket); |
| 614 | |
| 615 | phandle_pos -= s->soc[socket].num_harts; |
| 616 | |
| 617 | create_fdt_socket_cpus(ms->fdt, (&s->soc[socket])->harts, socket, |
| 618 | s->soc[socket].num_harts, |
| 619 | s->soc[socket].hartid_base, |
| 620 | phandle, &intc_phandles[phandle_pos], |
| 621 | numa_enabled, is_32_bit); |
| 622 | |
| 623 | create_fdt_socket_memory(ms->fdt, memaddr, memsize, |
| 624 | socket, riscv_numa_enabled(ms)); |
| 625 | |
| 626 | if (virt_aclint_allowed() && s->have_aclint) { |
| 627 | create_fdt_socket_aclint(s, socket, |
| 628 | &intc_phandles[phandle_pos]); |
| 629 | } else if (tcg_enabled()) { |
| 630 | hwaddr clintaddr = s->memmap[VIRT_CLINT].base + |
| 631 | s->memmap[VIRT_CLINT].size * socket; |
| 632 | |
| 633 | create_fdt_socket_clint(ms->fdt, clintaddr, |
| 634 | s->memmap[VIRT_CLINT].size, |
| 635 | socket, &intc_phandles[phandle_pos], |
| 636 | s->soc[socket].num_harts, numa_enabled); |
| 637 | } |
| 638 | } |
| 639 | |
| 640 | if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { |
| 641 | create_fdt_imsic(s, phandle, intc_phandles, |
| 642 | &msi_m_phandle, &msi_s_phandle); |
| 643 | *msi_pcie_phandle = msi_s_phandle; |
| 644 | } |
| 645 | |
| 646 | /* |
| 647 | * With KVM AIA aplic-imsic, using an irqchip without split |
| 648 | * mode, we'll use only one APLIC instance. |
| 649 | */ |
| 650 | if (!virt_use_emulated_aplic(s->aia_type)) { |
| 651 | create_fdt_socket_aplic(s, 0, |
| 652 | msi_m_phandle, msi_s_phandle, phandle, |
| 653 | &intc_phandles[0], xplic_phandles, |
| 654 | ms->smp.cpus); |
| 655 | |
| 656 | *irq_mmio_phandle = xplic_phandles[0]; |
| 657 | *irq_virtio_phandle = xplic_phandles[0]; |
| 658 | *irq_pcie_phandle = xplic_phandles[0]; |
| 659 | } else { |
| 660 | phandle_pos = ms->smp.cpus; |
| 661 | for (socket = (socket_count - 1); socket >= 0; socket--) { |
| 662 | phandle_pos -= s->soc[socket].num_harts; |
| 663 | |
| 664 | if (s->aia_type == VIRT_AIA_TYPE_NONE) { |
| 665 | create_fdt_socket_plic(s, socket, phandle, |
| 666 | &intc_phandles[phandle_pos], |
| 667 | xplic_phandles); |
| 668 | } else { |
| 669 | create_fdt_socket_aplic(s, socket, |
| 670 | msi_m_phandle, msi_s_phandle, phandle, |
| 671 | &intc_phandles[phandle_pos], |
| 672 | xplic_phandles, |
| 673 | s->soc[socket].num_harts); |
| 674 | } |
| 675 | } |
| 676 | |
| 677 | for (socket = 0; socket < socket_count; socket++) { |
| 678 | if (socket == 0) { |
| 679 | *irq_mmio_phandle = xplic_phandles[socket]; |
| 680 | *irq_virtio_phandle = xplic_phandles[socket]; |
| 681 | *irq_pcie_phandle = xplic_phandles[socket]; |
| 682 | } |
| 683 | if (socket == 1) { |
| 684 | *irq_virtio_phandle = xplic_phandles[socket]; |
| 685 | *irq_pcie_phandle = xplic_phandles[socket]; |
| 686 | } |
| 687 | if (socket == 2) { |
| 688 | *irq_pcie_phandle = xplic_phandles[socket]; |
| 689 | } |
| 690 | } |
| 691 | } |
| 692 | |
| 693 | riscv_socket_fdt_write_distance_matrix(ms); |
| 694 | } |
| 695 | |
| 696 | static void create_fdt_virtio(RISCVVirtState *s, uint32_t irq_virtio_phandle) |
| 697 | { |
| 698 | int i; |
| 699 | MachineState *ms = MACHINE(s); |
| 700 | hwaddr virtio_base = s->memmap[VIRT_VIRTIO].base; |
| 701 | |
| 702 | for (i = 0; i < VIRTIO_COUNT; i++) { |
| 703 | g_autofree char *name = NULL; |
| 704 | uint64_t size = s->memmap[VIRT_VIRTIO].size; |
| 705 | hwaddr addr = virtio_base + i * size; |
| 706 | |
| 707 | name = g_strdup_printf("/soc/virtio_mmio@%"HWADDR_PRIx, addr); |
| 708 | |
| 709 | qemu_fdt_add_subnode(ms->fdt, name); |
| 710 | qemu_fdt_setprop_string(ms->fdt, name, "compatible", "virtio,mmio"); |
| 711 | qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", 2, addr, 2, size); |
| 712 | qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", |
| 713 | irq_virtio_phandle); |
| 714 | if (s->aia_type == VIRT_AIA_TYPE_NONE) { |
| 715 | qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", |
| 716 | VIRTIO_IRQ + i); |
| 717 | } else { |
| 718 | qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", |
| 719 | VIRTIO_IRQ + i, 0x4); |
| 720 | } |
| 721 | } |
| 722 | } |
| 723 | |
| 724 | static void create_fdt_pcie(RISCVVirtState *s, |
| 725 | uint32_t irq_pcie_phandle, |
| 726 | uint32_t msi_pcie_phandle, |
| 727 | uint32_t iommu_sys_phandle) |
| 728 | { |
| 729 | g_autofree char *name = NULL; |
| 730 | MachineState *ms = MACHINE(s); |
| 731 | |
| 732 | name = g_strdup_printf("/soc/pci@%"HWADDR_PRIx, |
| 733 | s->memmap[VIRT_PCIE_ECAM].base); |
| 734 | qemu_fdt_setprop_cell(ms->fdt, name, "#address-cells", |
| 735 | FDT_PCI_ADDR_CELLS); |
| 736 | qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", |
| 737 | FDT_PCI_INT_CELLS); |
| 738 | qemu_fdt_setprop_cell(ms->fdt, name, "#size-cells", 0x2); |
| 739 | qemu_fdt_setprop_string(ms->fdt, name, "compatible", |
| 740 | "pci-host-ecam-generic"); |
| 741 | qemu_fdt_setprop_string(ms->fdt, name, "device_type", "pci"); |
| 742 | qemu_fdt_setprop_cell(ms->fdt, name, "linux,pci-domain", 0); |
| 743 | qemu_fdt_setprop_cells(ms->fdt, name, "bus-range", 0, |
| 744 | s->memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); |
| 745 | qemu_fdt_setprop(ms->fdt, name, "dma-coherent", NULL, 0); |
| 746 | if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { |
| 747 | qemu_fdt_setprop_cell(ms->fdt, name, "msi-parent", msi_pcie_phandle); |
| 748 | } |
| 749 | qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", 2, |
| 750 | s->memmap[VIRT_PCIE_ECAM].base, 2, s->memmap[VIRT_PCIE_ECAM].size); |
| 751 | qemu_fdt_setprop_sized_cells(ms->fdt, name, "ranges", |
| 752 | 1, FDT_PCI_RANGE_IOPORT, 2, 0, |
| 753 | 2, s->memmap[VIRT_PCIE_PIO].base, 2, s->memmap[VIRT_PCIE_PIO].size, |
| 754 | 1, FDT_PCI_RANGE_MMIO, |
| 755 | 2, s->memmap[VIRT_PCIE_MMIO].base, |
| 756 | 2, s->memmap[VIRT_PCIE_MMIO].base, 2, s->memmap[VIRT_PCIE_MMIO].size, |
| 757 | 1, FDT_PCI_RANGE_MMIO_64BIT, |
| 758 | 2, virt_high_pcie_memmap.base, |
| 759 | 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); |
| 760 | |
| 761 | if (virt_is_iommu_sys_enabled(s)) { |
| 762 | qemu_fdt_setprop_cells(ms->fdt, name, "iommu-map", |
| 763 | 0, iommu_sys_phandle, 0, 0x10000); |
| 764 | } |
| 765 | |
| 766 | create_pcie_irq_map(s, ms->fdt, name, irq_pcie_phandle); |
| 767 | } |
| 768 | |
| 769 | static void create_fdt_reset(RISCVVirtState *s, uint32_t *phandle) |
| 770 | { |
| 771 | char *name; |
| 772 | uint32_t test_phandle; |
| 773 | MachineState *ms = MACHINE(s); |
| 774 | |
| 775 | test_phandle = (*phandle)++; |
| 776 | name = g_strdup_printf("/soc/test@%"HWADDR_PRIx, |
| 777 | s->memmap[VIRT_TEST].base); |
| 778 | qemu_fdt_add_subnode(ms->fdt, name); |
| 779 | { |
| 780 | static const char * const compat[3] = { |
| 781 | "sifive,test1", "sifive,test0", "syscon" |
| 782 | }; |
| 783 | qemu_fdt_setprop_string_array(ms->fdt, name, "compatible", |
| 784 | (char **)&compat, ARRAY_SIZE(compat)); |
| 785 | } |
| 786 | qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", |
| 787 | 2, s->memmap[VIRT_TEST].base, |
| 788 | 2, s->memmap[VIRT_TEST].size); |
| 789 | qemu_fdt_setprop_cell(ms->fdt, name, "phandle", test_phandle); |
| 790 | test_phandle = qemu_fdt_get_phandle(ms->fdt, name); |
| 791 | g_free(name); |
| 792 | |
| 793 | name = g_strdup_printf("/reboot"); |
| 794 | qemu_fdt_add_subnode(ms->fdt, name); |
| 795 | qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-reboot"); |
| 796 | qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); |
| 797 | qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); |
| 798 | qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_RESET); |
| 799 | g_free(name); |
| 800 | |
| 801 | name = g_strdup_printf("/poweroff"); |
| 802 | qemu_fdt_add_subnode(ms->fdt, name); |
| 803 | qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-poweroff"); |
| 804 | qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); |
| 805 | qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); |
| 806 | qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_PASS); |
| 807 | g_free(name); |
| 808 | } |
| 809 | |
| 810 | static void create_fdt_uart(RISCVVirtState *s, |
| 811 | uint32_t irq_mmio_phandle, int memId, int irqNo) |
| 812 | { |
| 813 | g_autofree char *name = NULL; |
| 814 | MachineState *ms = MACHINE(s); |
| 815 | |
| 816 | name = g_strdup_printf("/soc/serial@%"HWADDR_PRIx, |
| 817 | s->memmap[memId].base); |
| 818 | qemu_fdt_add_subnode(ms->fdt, name); |
| 819 | qemu_fdt_setprop_string(ms->fdt, name, "compatible", "ns16550a"); |
| 820 | qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", |
| 821 | 2, s->memmap[memId].base, |
| 822 | 2, s->memmap[memId].size); |
| 823 | qemu_fdt_setprop_cell(ms->fdt, name, "clock-frequency", 3686400); |
| 824 | qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phandle); |
| 825 | if (s->aia_type == VIRT_AIA_TYPE_NONE) { |
| 826 | qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", irqNo); |
| 827 | } else { |
| 828 | qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", irqNo, 0x4); |
| 829 | } |
| 830 | |
| 831 | if (VIRT_UART0 == memId) { |
| 832 | qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", name); |
| 833 | qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial0", name); |
| 834 | } |
| 835 | } |
| 836 | |
| 837 | static void create_fdt_uarts(RISCVVirtState *s, uint32_t irq_mmio_phandle) |
| 838 | { |
| 839 | if (s->uart1_present) { |
| 840 | create_fdt_uart(s, irq_mmio_phandle, VIRT_UART1, UART1_IRQ); |
| 841 | } |
| 842 | create_fdt_uart(s, irq_mmio_phandle, VIRT_UART0, UART0_IRQ); |
| 843 | } |
| 844 | |
| 845 | static void create_fdt_rtc(RISCVVirtState *s, |
| 846 | uint32_t irq_mmio_phandle) |
| 847 | { |
| 848 | g_autofree char *name = NULL; |
| 849 | MachineState *ms = MACHINE(s); |
| 850 | |
| 851 | name = g_strdup_printf("/soc/rtc@%"HWADDR_PRIx, |
| 852 | s->memmap[VIRT_RTC].base); |
| 853 | qemu_fdt_add_subnode(ms->fdt, name); |
| 854 | qemu_fdt_setprop_string(ms->fdt, name, "compatible", |
| 855 | "google,goldfish-rtc"); |
| 856 | qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", |
| 857 | 2, s->memmap[VIRT_RTC].base, |
| 858 | 2, s->memmap[VIRT_RTC].size); |
| 859 | qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", |
| 860 | irq_mmio_phandle); |
| 861 | if (s->aia_type == VIRT_AIA_TYPE_NONE) { |
| 862 | qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", RTC_IRQ); |
| 863 | } else { |
| 864 | qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", RTC_IRQ, 0x4); |
| 865 | } |
| 866 | } |
| 867 | |
| 868 | static void create_fdt_flash(RISCVVirtState *s) |
| 869 | { |
| 870 | MachineState *ms = MACHINE(s); |
| 871 | hwaddr flashsize = s->memmap[VIRT_FLASH].size / 2; |
| 872 | hwaddr flashbase = s->memmap[VIRT_FLASH].base; |
| 873 | g_autofree char *name = g_strdup_printf("/flash@%" PRIx64, flashbase); |
| 874 | |
| 875 | qemu_fdt_add_subnode(ms->fdt, name); |
| 876 | qemu_fdt_setprop_string(ms->fdt, name, "compatible", "cfi-flash"); |
| 877 | qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", |
| 878 | 2, flashbase, 2, flashsize, |
| 879 | 2, flashbase + flashsize, 2, flashsize); |
| 880 | qemu_fdt_setprop_cell(ms->fdt, name, "bank-width", 4); |
| 881 | } |
| 882 | |
| 883 | static void create_fdt_fw_cfg(RISCVVirtState *s) |
| 884 | { |
| 885 | MachineState *ms = MACHINE(s); |
| 886 | hwaddr base = s->memmap[VIRT_FW_CFG].base; |
| 887 | hwaddr size = s->memmap[VIRT_FW_CFG].size; |
| 888 | g_autofree char *nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); |
| 889 | |
| 890 | qemu_fdt_add_subnode(ms->fdt, nodename); |
| 891 | qemu_fdt_setprop_string(ms->fdt, nodename, |
| 892 | "compatible", "qemu,fw-cfg-mmio"); |
| 893 | qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", |
| 894 | 2, base, 2, size); |
| 895 | qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); |
| 896 | } |
| 897 | |
| 898 | static void create_fdt_virtio_iommu(RISCVVirtState *s, uint16_t bdf) |
| 899 | { |
| 900 | const char compat[] = "virtio,pci-iommu\0pci1af4,1057"; |
| 901 | void *fdt = MACHINE(s)->fdt; |
| 902 | uint32_t iommu_phandle; |
| 903 | g_autofree char *iommu_node = NULL; |
| 904 | g_autofree char *pci_node = NULL; |
| 905 | |
| 906 | pci_node = g_strdup_printf("/soc/pci@%"HWADDR_PRIx, |
| 907 | s->memmap[VIRT_PCIE_ECAM].base); |
| 908 | iommu_node = g_strdup_printf("%s/virtio_iommu@%x,%x", pci_node, |
| 909 | PCI_SLOT(bdf), PCI_FUNC(bdf)); |
| 910 | iommu_phandle = qemu_fdt_alloc_phandle(fdt); |
| 911 | |
| 912 | qemu_fdt_add_subnode(fdt, iommu_node); |
| 913 | |
| 914 | qemu_fdt_setprop(fdt, iommu_node, "compatible", compat, sizeof(compat)); |
| 915 | qemu_fdt_setprop_sized_cells(fdt, iommu_node, "reg", |
| 916 | 1, bdf << 8, 1, 0, 1, 0, |
| 917 | 1, 0, 1, 0); |
| 918 | qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1); |
| 919 | qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle); |
| 920 | |
| 921 | qemu_fdt_setprop_cells(fdt, pci_node, "iommu-map", |
| 922 | 0, iommu_phandle, 0, bdf, |
| 923 | bdf + 1, iommu_phandle, bdf + 1, 0xffff - bdf); |
| 924 | } |
| 925 | |
| 926 | static void create_fdt_iommu_sys(RISCVVirtState *s, uint32_t irq_chip, |
| 927 | uint32_t msi_phandle, |
| 928 | uint32_t *iommu_sys_phandle) |
| 929 | { |
| 930 | const char comp[] = "riscv,iommu"; |
| 931 | void *fdt = MACHINE(s)->fdt; |
| 932 | uint32_t iommu_phandle; |
| 933 | g_autofree char *iommu_node = NULL; |
| 934 | hwaddr addr = s->memmap[VIRT_IOMMU_SYS].base; |
| 935 | hwaddr size = s->memmap[VIRT_IOMMU_SYS].size; |
| 936 | uint32_t iommu_irq_map[RISCV_IOMMU_INTR_COUNT] = { |
| 937 | IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_CQ, |
| 938 | IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_FQ, |
| 939 | IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_PM, |
| 940 | IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_PQ, |
| 941 | }; |
| 942 | |
| 943 | iommu_node = g_strdup_printf("/soc/iommu@%x", |
| 944 | (unsigned int) s->memmap[VIRT_IOMMU_SYS].base); |
| 945 | iommu_phandle = qemu_fdt_alloc_phandle(fdt); |
| 946 | qemu_fdt_add_subnode(fdt, iommu_node); |
| 947 | |
| 948 | qemu_fdt_setprop(fdt, iommu_node, "compatible", comp, sizeof(comp)); |
| 949 | qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1); |
| 950 | qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle); |
| 951 | |
| 952 | qemu_fdt_setprop_sized_cells(fdt, iommu_node, "reg", 2, addr, 2, size); |
| 953 | qemu_fdt_setprop_cell(fdt, iommu_node, "interrupt-parent", irq_chip); |
| 954 | |
| 955 | qemu_fdt_setprop_cells(fdt, iommu_node, "interrupts", |
| 956 | iommu_irq_map[0], FDT_IRQ_TYPE_EDGE_LOW, |
| 957 | iommu_irq_map[1], FDT_IRQ_TYPE_EDGE_LOW, |
| 958 | iommu_irq_map[2], FDT_IRQ_TYPE_EDGE_LOW, |
| 959 | iommu_irq_map[3], FDT_IRQ_TYPE_EDGE_LOW); |
| 960 | |
| 961 | qemu_fdt_setprop_cell(fdt, iommu_node, "msi-parent", msi_phandle); |
| 962 | |
| 963 | *iommu_sys_phandle = iommu_phandle; |
| 964 | } |
| 965 | |
| 966 | static void create_fdt_iommu(RISCVVirtState *s, uint16_t bdf) |
| 967 | { |
| 968 | const char comp[] = "riscv,pci-iommu"; |
| 969 | void *fdt = MACHINE(s)->fdt; |
| 970 | uint32_t iommu_phandle; |
| 971 | g_autofree char *iommu_node = NULL; |
| 972 | g_autofree char *pci_node = NULL; |
| 973 | |
| 974 | pci_node = g_strdup_printf("/soc/pci@%"HWADDR_PRIx, |
| 975 | s->memmap[VIRT_PCIE_ECAM].base); |
| 976 | iommu_node = g_strdup_printf("%s/iommu@%x", pci_node, bdf); |
| 977 | iommu_phandle = qemu_fdt_alloc_phandle(fdt); |
| 978 | qemu_fdt_add_subnode(fdt, iommu_node); |
| 979 | |
| 980 | qemu_fdt_setprop(fdt, iommu_node, "compatible", comp, sizeof(comp)); |
| 981 | qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1); |
| 982 | qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle); |
| 983 | qemu_fdt_setprop_cells(fdt, iommu_node, "reg", |
| 984 | bdf << 8, 0, 0, 0, 0); |
| 985 | qemu_fdt_setprop_cells(fdt, pci_node, "iommu-map", |
| 986 | 0, iommu_phandle, 0, bdf, |
| 987 | bdf + 1, iommu_phandle, bdf + 1, 0xffff - bdf); |
| 988 | s->pci_iommu_bdf = bdf; |
| 989 | } |
| 990 | |
| 991 | static void finalize_fdt(RISCVVirtState *s) |
| 992 | { |
| 993 | uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1; |
| 994 | uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1; |
| 995 | uint32_t iommu_sys_phandle = 1; |
| 996 | |
| 997 | create_fdt_sockets(s, &phandle, &irq_mmio_phandle, |
| 998 | &irq_pcie_phandle, &irq_virtio_phandle, |
| 999 | &msi_pcie_phandle); |
| 1000 | |
| 1001 | create_fdt_virtio(s, irq_virtio_phandle); |
| 1002 | |
| 1003 | if (virt_is_iommu_sys_enabled(s)) { |
| 1004 | create_fdt_iommu_sys(s, irq_mmio_phandle, msi_pcie_phandle, |
| 1005 | &iommu_sys_phandle); |
| 1006 | } |
| 1007 | create_fdt_pcie(s, irq_pcie_phandle, msi_pcie_phandle, |
| 1008 | iommu_sys_phandle); |
| 1009 | |
| 1010 | create_fdt_reset(s, &phandle); |
| 1011 | |
| 1012 | create_fdt_uarts(s, irq_mmio_phandle); |
| 1013 | |
| 1014 | create_fdt_rtc(s, irq_mmio_phandle); |
| 1015 | } |
| 1016 | |
| 1017 | static void create_fdt(RISCVVirtState *s) |
| 1018 | { |
| 1019 | MachineState *ms = MACHINE(s); |
| 1020 | uint8_t rng_seed[32]; |
| 1021 | g_autofree char *name = NULL; |
| 1022 | |
| 1023 | ms->fdt = create_board_device_tree("riscv-virtio,qemu", "riscv-virtio", |
| 1024 | &s->fdt_size); |
| 1025 | |
| 1026 | /* |
| 1027 | * The "/soc/pci@..." node is needed for PCIE hotplugs |
| 1028 | * that might happen before finalize_fdt(). |
| 1029 | */ |
| 1030 | name = g_strdup_printf("/soc/pci@%"HWADDR_PRIx, |
| 1031 | s->memmap[VIRT_PCIE_ECAM].base); |
| 1032 | qemu_fdt_add_subnode(ms->fdt, name); |
| 1033 | |
| 1034 | qemu_fdt_add_subnode(ms->fdt, "/chosen"); |
| 1035 | |
| 1036 | /* Pass seed to RNG */ |
| 1037 | qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); |
| 1038 | qemu_fdt_setprop(ms->fdt, "/chosen", "rng-seed", |
| 1039 | rng_seed, sizeof(rng_seed)); |
| 1040 | |
| 1041 | qemu_fdt_add_subnode(ms->fdt, "/aliases"); |
| 1042 | |
| 1043 | create_fdt_flash(s); |
| 1044 | create_fdt_fw_cfg(s); |
| 1045 | create_fdt_pmu(s); |
| 1046 | } |
| 1047 | |
| 1048 | static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, |
| 1049 | DeviceState *irqchip, |
| 1050 | RISCVVirtState *s) |
| 1051 | { |
| 1052 | DeviceState *dev; |
| 1053 | MemoryRegion *ecam_alias, *ecam_reg; |
| 1054 | MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg; |
| 1055 | hwaddr ecam_base = s->memmap[VIRT_PCIE_ECAM].base; |
| 1056 | hwaddr ecam_size = s->memmap[VIRT_PCIE_ECAM].size; |
| 1057 | hwaddr mmio_base = s->memmap[VIRT_PCIE_MMIO].base; |
| 1058 | hwaddr mmio_size = s->memmap[VIRT_PCIE_MMIO].size; |
| 1059 | hwaddr high_mmio_base = virt_high_pcie_memmap.base; |
| 1060 | hwaddr high_mmio_size = virt_high_pcie_memmap.size; |
| 1061 | hwaddr pio_base = s->memmap[VIRT_PCIE_PIO].base; |
| 1062 | hwaddr pio_size = s->memmap[VIRT_PCIE_PIO].size; |
| 1063 | qemu_irq irq; |
| 1064 | int i; |
| 1065 | |
| 1066 | dev = qdev_new(TYPE_GPEX_HOST); |
| 1067 | |
| 1068 | /* Set GPEX object properties for the virt machine */ |
| 1069 | object_property_set_uint(OBJECT(dev), PCI_HOST_ECAM_BASE, |
| 1070 | ecam_base, NULL); |
| 1071 | object_property_set_int(OBJECT(dev), PCI_HOST_ECAM_SIZE, |
| 1072 | ecam_size, NULL); |
| 1073 | object_property_set_uint(OBJECT(dev), PCI_HOST_BELOW_4G_MMIO_BASE, |
| 1074 | mmio_base, NULL); |
| 1075 | object_property_set_int(OBJECT(dev), PCI_HOST_BELOW_4G_MMIO_SIZE, |
| 1076 | mmio_size, NULL); |
| 1077 | object_property_set_uint(OBJECT(dev), PCI_HOST_ABOVE_4G_MMIO_BASE, |
| 1078 | high_mmio_base, NULL); |
| 1079 | object_property_set_int(OBJECT(dev), PCI_HOST_ABOVE_4G_MMIO_SIZE, |
| 1080 | high_mmio_size, NULL); |
| 1081 | object_property_set_uint(OBJECT(dev), PCI_HOST_PIO_BASE, |
| 1082 | pio_base, NULL); |
| 1083 | object_property_set_int(OBJECT(dev), PCI_HOST_PIO_SIZE, |
| 1084 | pio_size, NULL); |
| 1085 | |
| 1086 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
| 1087 | |
| 1088 | ecam_alias = g_new0(MemoryRegion, 1); |
| 1089 | ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); |
| 1090 | memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", |
| 1091 | ecam_reg, 0, ecam_size); |
| 1092 | memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias); |
| 1093 | |
| 1094 | mmio_alias = g_new0(MemoryRegion, 1); |
| 1095 | mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); |
| 1096 | memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", |
| 1097 | mmio_reg, mmio_base, mmio_size); |
| 1098 | memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); |
| 1099 | |
| 1100 | /* Map high MMIO space */ |
| 1101 | high_mmio_alias = g_new0(MemoryRegion, 1); |
| 1102 | memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", |
| 1103 | mmio_reg, high_mmio_base, high_mmio_size); |
| 1104 | memory_region_add_subregion(get_system_memory(), high_mmio_base, |
| 1105 | high_mmio_alias); |
| 1106 | |
| 1107 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); |
| 1108 | |
| 1109 | for (i = 0; i < PCI_NUM_PINS; i++) { |
| 1110 | irq = qdev_get_gpio_in(irqchip, PCIE_IRQ + i); |
| 1111 | |
| 1112 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); |
| 1113 | gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); |
| 1114 | } |
| 1115 | |
| 1116 | GPEX_HOST(dev)->gpex_cfg.bus = PCI_HOST_BRIDGE(dev)->bus; |
| 1117 | return dev; |
| 1118 | } |
| 1119 | |
| 1120 | static FWCfgState *create_fw_cfg(const MachineState *ms, hwaddr base) |
| 1121 | { |
| 1122 | FWCfgState *fw_cfg; |
| 1123 | |
| 1124 | fw_cfg = fw_cfg_init_mem_dma(base, &address_space_memory); |
| 1125 | fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); |
| 1126 | |
| 1127 | return fw_cfg; |
| 1128 | } |
| 1129 | |
| 1130 | static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket, |
| 1131 | int base_hartid, int hart_count) |
| 1132 | { |
| 1133 | g_autofree char *plic_hart_config = NULL; |
| 1134 | |
| 1135 | /* Per-socket PLIC hart topology configuration string */ |
| 1136 | plic_hart_config = riscv_plic_hart_config_string(hart_count); |
| 1137 | |
| 1138 | /* Per-socket PLIC */ |
| 1139 | return sifive_plic_create( |
| 1140 | memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size, |
| 1141 | plic_hart_config, hart_count, base_hartid, |
| 1142 | VIRT_IRQCHIP_NUM_SOURCES, |
| 1143 | ((1U << VIRT_IRQCHIP_NUM_PRIO_BITS) - 1), |
| 1144 | VIRT_PLIC_PRIORITY_BASE, VIRT_PLIC_PENDING_BASE, |
| 1145 | VIRT_PLIC_ENABLE_BASE, VIRT_PLIC_ENABLE_STRIDE, |
| 1146 | VIRT_PLIC_CONTEXT_BASE, |
| 1147 | VIRT_PLIC_CONTEXT_STRIDE, |
| 1148 | memmap[VIRT_PLIC].size); |
| 1149 | } |
| 1150 | |
| 1151 | static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip) |
| 1152 | { |
| 1153 | DeviceState *dev; |
| 1154 | SysBusDevice *sysbus; |
| 1155 | int i; |
| 1156 | MemoryRegion *sysmem = get_system_memory(); |
| 1157 | |
| 1158 | dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); |
| 1159 | dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); |
| 1160 | qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); |
| 1161 | qdev_prop_set_uint32(dev, "mmio_size", s->memmap[VIRT_PLATFORM_BUS].size); |
| 1162 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
| 1163 | s->platform_bus_dev = dev; |
| 1164 | |
| 1165 | sysbus = SYS_BUS_DEVICE(dev); |
| 1166 | for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { |
| 1167 | int irq = VIRT_PLATFORM_BUS_IRQ + i; |
| 1168 | sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(irqchip, irq)); |
| 1169 | } |
| 1170 | |
| 1171 | memory_region_add_subregion(sysmem, |
| 1172 | s->memmap[VIRT_PLATFORM_BUS].base, |
| 1173 | sysbus_mmio_get_region(sysbus, 0)); |
| 1174 | } |
| 1175 | |
| 1176 | static void virt_build_smbios(RISCVVirtState *s) |
| 1177 | { |
| 1178 | MachineClass *mc = MACHINE_GET_CLASS(s); |
| 1179 | MachineState *ms = MACHINE(s); |
| 1180 | uint8_t *smbios_tables, *smbios_anchor; |
| 1181 | size_t smbios_tables_len, smbios_anchor_len; |
| 1182 | struct smbios_phys_mem_area mem_array; |
| 1183 | const char *product = "QEMU Virtual Machine"; |
| 1184 | |
| 1185 | if (kvm_enabled()) { |
| 1186 | product = "KVM Virtual Machine"; |
| 1187 | } |
| 1188 | |
| 1189 | smbios_set_defaults("QEMU", product, mc->name); |
| 1190 | |
| 1191 | if (riscv_is_32bit(&s->soc[0])) { |
| 1192 | smbios_set_default_processor_family(0x200); |
| 1193 | } else { |
| 1194 | smbios_set_default_processor_family(0x201); |
| 1195 | } |
| 1196 | |
| 1197 | /* build the array of physical mem area from base_memmap */ |
| 1198 | mem_array.address = s->memmap[VIRT_DRAM].base; |
| 1199 | mem_array.length = ms->ram_size; |
| 1200 | |
| 1201 | smbios_get_tables(ms, SMBIOS_ENTRY_POINT_TYPE_64, |
| 1202 | &mem_array, 1, |
| 1203 | &smbios_tables, &smbios_tables_len, |
| 1204 | &smbios_anchor, &smbios_anchor_len, |
| 1205 | &error_fatal); |
| 1206 | |
| 1207 | if (smbios_anchor) { |
| 1208 | fw_cfg_add_file(s->fw_cfg, "etc/smbios/smbios-tables", |
| 1209 | smbios_tables, smbios_tables_len); |
| 1210 | fw_cfg_add_file(s->fw_cfg, "etc/smbios/smbios-anchor", |
| 1211 | smbios_anchor, smbios_anchor_len); |
| 1212 | } |
| 1213 | } |
| 1214 | |
| 1215 | static void virt_machine_done(Notifier *notifier, void *data) |
| 1216 | { |
| 1217 | RISCVVirtState *s = container_of(notifier, RISCVVirtState, |
| 1218 | machine_done); |
| 1219 | MachineState *machine = MACHINE(s); |
| 1220 | hwaddr start_addr = s->memmap[VIRT_DRAM].base; |
| 1221 | hwaddr firmware_end_addr; |
| 1222 | vaddr kernel_start_addr; |
| 1223 | const char *firmware_name = riscv_default_firmware_name(&s->soc[0]); |
| 1224 | uint64_t fdt_load_addr; |
| 1225 | uint64_t kernel_entry = 0; |
| 1226 | BlockBackend *pflash_blk0; |
| 1227 | RISCVBootInfo boot_info; |
| 1228 | |
| 1229 | /* |
| 1230 | * An user provided dtb must include everything, including |
| 1231 | * dynamic sysbus devices. Our FDT needs to be finalized. |
| 1232 | */ |
| 1233 | if (machine->dtb == NULL) { |
| 1234 | finalize_fdt(s); |
| 1235 | } |
| 1236 | |
| 1237 | /* |
| 1238 | * Only direct boot kernel is currently supported for KVM VM, |
| 1239 | * so the "-bios" parameter is not supported when KVM is enabled. |
| 1240 | */ |
| 1241 | if (kvm_enabled()) { |
| 1242 | if (machine->firmware) { |
| 1243 | if (strcmp(machine->firmware, "none")) { |
| 1244 | error_report("Machine mode firmware is not supported in " |
| 1245 | "combination with KVM."); |
| 1246 | exit(1); |
| 1247 | } |
| 1248 | } else { |
| 1249 | machine->firmware = g_strdup("none"); |
| 1250 | } |
| 1251 | } |
| 1252 | |
| 1253 | riscv_boot_info_init(&boot_info, &s->soc[0]); |
| 1254 | |
| 1255 | firmware_end_addr = riscv_find_and_load_firmware(machine, &boot_info, |
| 1256 | firmware_name, |
| 1257 | &start_addr, NULL); |
| 1258 | |
| 1259 | pflash_blk0 = pflash_cfi01_get_blk(s->flash[0]); |
| 1260 | if (pflash_blk0) { |
| 1261 | if (machine->firmware && !strcmp(machine->firmware, "none") && |
| 1262 | !kvm_enabled()) { |
| 1263 | /* |
| 1264 | * Pflash was supplied but bios is none and not KVM guest, |
| 1265 | * let's overwrite the address we jump to after reset to |
| 1266 | * the base of the flash. |
| 1267 | */ |
| 1268 | start_addr = s->memmap[VIRT_FLASH].base; |
| 1269 | } else { |
| 1270 | /* |
| 1271 | * Pflash was supplied but either KVM guest or bios is not none. |
| 1272 | * In this case, base of the flash would contain S-mode payload. |
| 1273 | */ |
| 1274 | riscv_setup_firmware_boot(machine); |
| 1275 | kernel_entry = s->memmap[VIRT_FLASH].base; |
| 1276 | } |
| 1277 | } |
| 1278 | |
| 1279 | if (machine->kernel_filename && !kernel_entry) { |
| 1280 | kernel_start_addr = riscv_calc_kernel_start_addr(&boot_info, |
| 1281 | firmware_end_addr); |
| 1282 | riscv_load_kernel(machine, &boot_info, kernel_start_addr, |
| 1283 | true, NULL); |
| 1284 | kernel_entry = boot_info.image_low_addr; |
| 1285 | } |
| 1286 | |
| 1287 | fdt_load_addr = riscv_compute_fdt_addr(s->memmap[VIRT_DRAM].base, |
| 1288 | s->memmap[VIRT_DRAM].size, |
| 1289 | machine, &boot_info); |
| 1290 | riscv_load_fdt(fdt_load_addr, machine->fdt); |
| 1291 | |
| 1292 | /* load the reset vector */ |
| 1293 | riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, |
| 1294 | s->memmap[VIRT_MROM].base, |
| 1295 | s->memmap[VIRT_MROM].size, kernel_entry, |
| 1296 | fdt_load_addr); |
| 1297 | |
| 1298 | /* |
| 1299 | * Only direct boot kernel is currently supported for KVM VM, |
| 1300 | * So here setup kernel start address and fdt address. |
| 1301 | * TODO:Support firmware loading and integrate to TCG start |
| 1302 | */ |
| 1303 | if (kvm_enabled()) { |
| 1304 | riscv_setup_direct_kernel(kernel_entry, fdt_load_addr); |
| 1305 | } |
| 1306 | |
| 1307 | virt_build_smbios(s); |
| 1308 | |
| 1309 | if (virt_is_acpi_enabled(s)) { |
| 1310 | virt_acpi_setup(s); |
| 1311 | } |
| 1312 | } |
| 1313 | |
| 1314 | static void virt_machine_init(MachineState *machine) |
| 1315 | { |
| 1316 | RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); |
| 1317 | MemoryRegion *system_memory = get_system_memory(); |
| 1318 | MemoryRegion *mask_rom = g_new(MemoryRegion, 1); |
| 1319 | DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip; |
| 1320 | int i, base_hartid, hart_count; |
| 1321 | int socket_count = riscv_socket_count(machine); |
| 1322 | |
| 1323 | s->memmap = virt_memmap; |
| 1324 | |
| 1325 | /* Check socket count limit */ |
| 1326 | if (VIRT_SOCKETS_MAX < socket_count) { |
| 1327 | error_report("number of sockets/nodes should be less than %d", |
| 1328 | VIRT_SOCKETS_MAX); |
| 1329 | exit(1); |
| 1330 | } |
| 1331 | |
| 1332 | if (!virt_aclint_allowed() && s->have_aclint) { |
| 1333 | error_report("'aclint' is only available with TCG acceleration"); |
| 1334 | exit(1); |
| 1335 | } |
| 1336 | |
| 1337 | /* Initialize sockets */ |
| 1338 | mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL; |
| 1339 | for (i = 0; i < socket_count; i++) { |
| 1340 | g_autofree char *soc_name = g_strdup_printf("soc%d", i); |
| 1341 | |
| 1342 | if (!riscv_socket_check_hartids(machine, i)) { |
| 1343 | error_report("discontinuous hartids in socket%d", i); |
| 1344 | exit(1); |
| 1345 | } |
| 1346 | |
| 1347 | base_hartid = riscv_socket_first_hartid(machine, i); |
| 1348 | if (base_hartid < 0) { |
| 1349 | error_report("can't find hartid base for socket%d", i); |
| 1350 | exit(1); |
| 1351 | } |
| 1352 | |
| 1353 | hart_count = riscv_socket_hart_count(machine, i); |
| 1354 | if (hart_count < 0) { |
| 1355 | error_report("can't find hart count for socket%d", i); |
| 1356 | exit(1); |
| 1357 | } |
| 1358 | |
| 1359 | object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], |
| 1360 | TYPE_RISCV_HART_ARRAY); |
| 1361 | object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", |
| 1362 | machine->cpu_type, &error_abort); |
| 1363 | object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", |
| 1364 | base_hartid, &error_abort); |
| 1365 | object_property_set_int(OBJECT(&s->soc[i]), "num-harts", |
| 1366 | hart_count, &error_abort); |
| 1367 | sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal); |
| 1368 | |
| 1369 | if (virt_aclint_allowed() && s->have_aclint) { |
| 1370 | if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { |
| 1371 | /* Per-socket ACLINT MTIMER */ |
| 1372 | riscv_aclint_mtimer_create(s->memmap[VIRT_CLINT].base + |
| 1373 | i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE, |
| 1374 | RISCV_ACLINT_DEFAULT_MTIMER_SIZE, |
| 1375 | base_hartid, hart_count, |
| 1376 | RISCV_ACLINT_DEFAULT_MTIMECMP, |
| 1377 | RISCV_ACLINT_DEFAULT_MTIME, |
| 1378 | RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); |
| 1379 | } else { |
| 1380 | /* Per-socket ACLINT MSWI, MTIMER, and SSWI */ |
| 1381 | riscv_aclint_swi_create(s->memmap[VIRT_CLINT].base + |
| 1382 | i * s->memmap[VIRT_CLINT].size, |
| 1383 | base_hartid, hart_count, false); |
| 1384 | riscv_aclint_mtimer_create(s->memmap[VIRT_CLINT].base + |
| 1385 | i * s->memmap[VIRT_CLINT].size + |
| 1386 | RISCV_ACLINT_SWI_SIZE, |
| 1387 | RISCV_ACLINT_DEFAULT_MTIMER_SIZE, |
| 1388 | base_hartid, hart_count, |
| 1389 | RISCV_ACLINT_DEFAULT_MTIMECMP, |
| 1390 | RISCV_ACLINT_DEFAULT_MTIME, |
| 1391 | RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); |
| 1392 | riscv_aclint_swi_create(s->memmap[VIRT_ACLINT_SSWI].base + |
| 1393 | i * s->memmap[VIRT_ACLINT_SSWI].size, |
| 1394 | base_hartid, hart_count, true); |
| 1395 | } |
| 1396 | } else if (tcg_enabled()) { |
| 1397 | /* Per-socket SiFive CLINT */ |
| 1398 | riscv_aclint_swi_create( |
| 1399 | s->memmap[VIRT_CLINT].base + i * s->memmap[VIRT_CLINT].size, |
| 1400 | base_hartid, hart_count, false); |
| 1401 | riscv_aclint_mtimer_create(s->memmap[VIRT_CLINT].base + |
| 1402 | i * s->memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE, |
| 1403 | RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, |
| 1404 | RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, |
| 1405 | RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); |
| 1406 | } |
| 1407 | |
| 1408 | /* Per-socket interrupt controller */ |
| 1409 | if (s->aia_type == VIRT_AIA_TYPE_NONE) { |
| 1410 | s->irqchip[i] = virt_create_plic(s->memmap, i, |
| 1411 | base_hartid, hart_count); |
| 1412 | } else { |
| 1413 | s->irqchip[i] = riscv_create_aia(s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC, |
| 1414 | s->aia_guests, |
| 1415 | IMSIC_HART_SIZE(0), |
| 1416 | s->num_sources, |
| 1417 | &s->memmap[VIRT_APLIC_M], |
| 1418 | &s->memmap[VIRT_APLIC_S], |
| 1419 | &s->memmap[VIRT_IMSIC_M], |
| 1420 | &s->memmap[VIRT_IMSIC_S], |
| 1421 | i, base_hartid, hart_count, |
| 1422 | VIRT_IRQCHIP_NUM_MSIS, |
| 1423 | VIRT_IRQCHIP_NUM_PRIO_BITS); |
| 1424 | } |
| 1425 | |
| 1426 | /* Try to use different IRQCHIP instance based device type */ |
| 1427 | if (i == 0) { |
| 1428 | mmio_irqchip = s->irqchip[i]; |
| 1429 | virtio_irqchip = s->irqchip[i]; |
| 1430 | pcie_irqchip = s->irqchip[i]; |
| 1431 | } |
| 1432 | if (i == 1) { |
| 1433 | virtio_irqchip = s->irqchip[i]; |
| 1434 | pcie_irqchip = s->irqchip[i]; |
| 1435 | } |
| 1436 | if (i == 2) { |
| 1437 | pcie_irqchip = s->irqchip[i]; |
| 1438 | } |
| 1439 | } |
| 1440 | |
| 1441 | if (kvm_enabled() && virt_use_kvm_aia_aplic_imsic(s->aia_type)) { |
| 1442 | kvm_riscv_aia_create(machine, IMSIC_MMIO_GROUP_MIN_SHIFT, |
| 1443 | VIRT_IRQCHIP_NUM_SOURCES, VIRT_IRQCHIP_NUM_MSIS, |
| 1444 | s->memmap[VIRT_APLIC_S].base, |
| 1445 | s->memmap[VIRT_IMSIC_S].base, |
| 1446 | s->aia_guests); |
| 1447 | } |
| 1448 | |
| 1449 | if (riscv_is_32bit(&s->soc[0])) { |
| 1450 | #if HOST_LONG_BITS == 64 |
| 1451 | /* limit RAM size in a 32-bit system */ |
| 1452 | if (machine->ram_size > 10 * GiB) { |
| 1453 | machine->ram_size = 10 * GiB; |
| 1454 | error_report("Limiting RAM size to 10 GiB"); |
| 1455 | } |
| 1456 | #endif |
| 1457 | virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE; |
| 1458 | virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE; |
| 1459 | } else { |
| 1460 | virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE; |
| 1461 | virt_high_pcie_memmap.base = s->memmap[VIRT_DRAM].base + |
| 1462 | machine->ram_size; |
| 1463 | virt_high_pcie_memmap.base = |
| 1464 | ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size); |
| 1465 | } |
| 1466 | |
| 1467 | /* register system main memory (actual RAM) */ |
| 1468 | memory_region_add_subregion(system_memory, s->memmap[VIRT_DRAM].base, |
| 1469 | machine->ram); |
| 1470 | |
| 1471 | /* boot rom */ |
| 1472 | memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", |
| 1473 | s->memmap[VIRT_MROM].size, &error_fatal); |
| 1474 | memory_region_add_subregion(system_memory, s->memmap[VIRT_MROM].base, |
| 1475 | mask_rom); |
| 1476 | |
| 1477 | /* |
| 1478 | * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the |
| 1479 | * device tree cannot be altered and we get FDT_ERR_NOSPACE. |
| 1480 | */ |
| 1481 | s->fw_cfg = create_fw_cfg(machine, s->memmap[VIRT_FW_CFG].base); |
| 1482 | rom_set_fw(s->fw_cfg); |
| 1483 | |
| 1484 | /* SiFive Test MMIO device */ |
| 1485 | sifive_test_create(s->memmap[VIRT_TEST].base); |
| 1486 | |
| 1487 | /* VirtIO MMIO devices */ |
| 1488 | for (i = 0; i < VIRTIO_COUNT; i++) { |
| 1489 | sysbus_create_simple("virtio-mmio", |
| 1490 | s->memmap[VIRT_VIRTIO].base + i * s->memmap[VIRT_VIRTIO].size, |
| 1491 | qdev_get_gpio_in(virtio_irqchip, VIRTIO_IRQ + i)); |
| 1492 | } |
| 1493 | |
| 1494 | gpex_pcie_init(system_memory, pcie_irqchip, s); |
| 1495 | |
| 1496 | create_platform_bus(s, mmio_irqchip); |
| 1497 | |
| 1498 | serial_mm_init(system_memory, s->memmap[VIRT_UART0].base, |
| 1499 | 0, qdev_get_gpio_in(mmio_irqchip, UART0_IRQ), 399193, |
| 1500 | serial_hd(0), DEVICE_LITTLE_ENDIAN); |
| 1501 | |
| 1502 | if (serial_hd(1)) { |
| 1503 | serial_mm_init(system_memory, s->memmap[VIRT_UART1].base, |
| 1504 | 0, qdev_get_gpio_in(mmio_irqchip, UART1_IRQ), 399193, |
| 1505 | serial_hd(1), DEVICE_LITTLE_ENDIAN); |
| 1506 | s->uart1_present = true; |
| 1507 | } |
| 1508 | |
| 1509 | sysbus_create_simple("goldfish_rtc", s->memmap[VIRT_RTC].base, |
| 1510 | qdev_get_gpio_in(mmio_irqchip, RTC_IRQ)); |
| 1511 | |
| 1512 | for (i = 0; i < ARRAY_SIZE(s->flash); i++) { |
| 1513 | /* Map legacy -drive if=pflash to machine properties */ |
| 1514 | pflash_cfi01_legacy_drive(s->flash[i], |
| 1515 | drive_get(IF_PFLASH, 0, i)); |
| 1516 | } |
| 1517 | virt_flash_map(s, system_memory); |
| 1518 | |
| 1519 | /* load/create device tree */ |
| 1520 | if (machine->dtb) { |
| 1521 | machine->fdt = load_device_tree(machine->dtb, &s->fdt_size); |
| 1522 | if (!machine->fdt) { |
| 1523 | error_report("load_device_tree() failed"); |
| 1524 | exit(1); |
| 1525 | } |
| 1526 | } else { |
| 1527 | create_fdt(s); |
| 1528 | } |
| 1529 | |
| 1530 | if (virt_is_iommu_sys_enabled(s)) { |
| 1531 | DeviceState *iommu_sys = qdev_new(TYPE_RISCV_IOMMU_SYS); |
| 1532 | |
| 1533 | object_property_set_uint(OBJECT(iommu_sys), "addr", |
| 1534 | s->memmap[VIRT_IOMMU_SYS].base, |
| 1535 | &error_fatal); |
| 1536 | object_property_set_uint(OBJECT(iommu_sys), "base-irq", |
| 1537 | IOMMU_SYS_IRQ, |
| 1538 | &error_fatal); |
| 1539 | object_property_set_link(OBJECT(iommu_sys), "irqchip", |
| 1540 | OBJECT(mmio_irqchip), |
| 1541 | &error_fatal); |
| 1542 | /* |
| 1543 | * For riscv64 use a physical address size of 56 bits (44 bit PPN), |
| 1544 | * and for riscv32 use 34 bits (22 bit PPN). |
| 1545 | */ |
| 1546 | object_property_set_uint(OBJECT(iommu_sys), "pas-bits", |
| 1547 | riscv_is_32bit(&s->soc[0]) ? 34 : 56, |
| 1548 | &error_fatal); |
| 1549 | |
| 1550 | sysbus_realize_and_unref(SYS_BUS_DEVICE(iommu_sys), &error_fatal); |
| 1551 | } |
| 1552 | |
| 1553 | s->machine_done.notify = virt_machine_done; |
| 1554 | qemu_add_machine_init_done_notifier(&s->machine_done); |
| 1555 | } |
| 1556 | |
| 1557 | static void virt_machine_instance_finalize(Object *obj) |
| 1558 | { |
| 1559 | RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); |
| 1560 | |
| 1561 | for (int i = 0; i < ARRAY_SIZE(s->flash); i++) { |
| 1562 | if (s->flash[i] && !qdev_is_realized(DEVICE(s->flash[i]))) { |
| 1563 | object_unref(OBJECT(s->flash[i])); |
| 1564 | } |
| 1565 | } |
| 1566 | g_free(s->oem_id); |
| 1567 | g_free(s->oem_table_id); |
| 1568 | } |
| 1569 | |
| 1570 | static void virt_machine_instance_init(Object *obj) |
| 1571 | { |
| 1572 | RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); |
| 1573 | |
| 1574 | virt_flash_create(s); |
| 1575 | |
| 1576 | s->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); |
| 1577 | s->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); |
| 1578 | s->acpi = ON_OFF_AUTO_AUTO; |
| 1579 | s->iommu_sys = ON_OFF_AUTO_AUTO; |
| 1580 | s->num_sources = VIRT_IRQCHIP_NUM_SOURCES; |
| 1581 | } |
| 1582 | |
| 1583 | static char *virt_get_aia_guests(Object *obj, Error **errp) |
| 1584 | { |
| 1585 | RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); |
| 1586 | |
| 1587 | return g_strdup_printf("%d", s->aia_guests); |
| 1588 | } |
| 1589 | |
| 1590 | static void virt_set_aia_guests(Object *obj, const char *val, Error **errp) |
| 1591 | { |
| 1592 | RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); |
| 1593 | |
| 1594 | s->aia_guests = atoi(val); |
| 1595 | if (s->aia_guests < 0 || s->aia_guests > VIRT_IRQCHIP_MAX_GUESTS) { |
| 1596 | error_setg(errp, "Invalid number of AIA IMSIC guests"); |
| 1597 | error_append_hint(errp, "Valid values be between 0 and %d.\n", |
| 1598 | VIRT_IRQCHIP_MAX_GUESTS); |
| 1599 | } |
| 1600 | } |
| 1601 | |
| 1602 | static char *virt_get_aia(Object *obj, Error **errp) |
| 1603 | { |
| 1604 | RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); |
| 1605 | const char *val; |
| 1606 | |
| 1607 | switch (s->aia_type) { |
| 1608 | case VIRT_AIA_TYPE_APLIC: |
| 1609 | val = "aplic"; |
| 1610 | break; |
| 1611 | case VIRT_AIA_TYPE_APLIC_IMSIC: |
| 1612 | val = "aplic-imsic"; |
| 1613 | break; |
| 1614 | default: |
| 1615 | val = "none"; |
| 1616 | break; |
| 1617 | }; |
| 1618 | |
| 1619 | return g_strdup(val); |
| 1620 | } |
| 1621 | |
| 1622 | static void virt_set_aia(Object *obj, const char *val, Error **errp) |
| 1623 | { |
| 1624 | RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); |
| 1625 | |
| 1626 | if (!strcmp(val, "none")) { |
| 1627 | s->aia_type = VIRT_AIA_TYPE_NONE; |
| 1628 | } else if (!strcmp(val, "aplic")) { |
| 1629 | s->aia_type = VIRT_AIA_TYPE_APLIC; |
| 1630 | } else if (!strcmp(val, "aplic-imsic")) { |
| 1631 | s->aia_type = VIRT_AIA_TYPE_APLIC_IMSIC; |
| 1632 | } else { |
| 1633 | error_setg(errp, "Invalid AIA interrupt controller type"); |
| 1634 | error_append_hint(errp, "Valid values are none, aplic, and " |
| 1635 | "aplic-imsic.\n"); |
| 1636 | } |
| 1637 | } |
| 1638 | |
| 1639 | static bool virt_get_aclint(Object *obj, Error **errp) |
| 1640 | { |
| 1641 | RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); |
| 1642 | |
| 1643 | return s->have_aclint; |
| 1644 | } |
| 1645 | |
| 1646 | static void virt_set_aclint(Object *obj, bool value, Error **errp) |
| 1647 | { |
| 1648 | RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); |
| 1649 | |
| 1650 | s->have_aclint = value; |
| 1651 | } |
| 1652 | |
| 1653 | bool virt_is_iommu_sys_enabled(RISCVVirtState *s) |
| 1654 | { |
| 1655 | return s->iommu_sys == ON_OFF_AUTO_ON; |
| 1656 | } |
| 1657 | |
| 1658 | static void virt_get_iommu_sys(Object *obj, Visitor *v, const char *name, |
| 1659 | void *opaque, Error **errp) |
| 1660 | { |
| 1661 | RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); |
| 1662 | OnOffAuto iommu_sys = s->iommu_sys; |
| 1663 | |
| 1664 | visit_type_OnOffAuto(v, name, &iommu_sys, errp); |
| 1665 | } |
| 1666 | |
| 1667 | static void virt_set_iommu_sys(Object *obj, Visitor *v, const char *name, |
| 1668 | void *opaque, Error **errp) |
| 1669 | { |
| 1670 | RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); |
| 1671 | |
| 1672 | visit_type_OnOffAuto(v, name, &s->iommu_sys, errp); |
| 1673 | } |
| 1674 | |
| 1675 | bool virt_is_acpi_enabled(RISCVVirtState *s) |
| 1676 | { |
| 1677 | return s->acpi != ON_OFF_AUTO_OFF; |
| 1678 | } |
| 1679 | |
| 1680 | static void virt_get_acpi(Object *obj, Visitor *v, const char *name, |
| 1681 | void *opaque, Error **errp) |
| 1682 | { |
| 1683 | RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); |
| 1684 | OnOffAuto acpi = s->acpi; |
| 1685 | |
| 1686 | visit_type_OnOffAuto(v, name, &acpi, errp); |
| 1687 | } |
| 1688 | |
| 1689 | static void virt_set_acpi(Object *obj, Visitor *v, const char *name, |
| 1690 | void *opaque, Error **errp) |
| 1691 | { |
| 1692 | RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); |
| 1693 | |
| 1694 | visit_type_OnOffAuto(v, name, &s->acpi, errp); |
| 1695 | } |
| 1696 | |
| 1697 | static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, |
| 1698 | DeviceState *dev) |
| 1699 | { |
| 1700 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
| 1701 | RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); |
| 1702 | |
| 1703 | if (device_is_dynamic_sysbus(mc, dev) || |
| 1704 | object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || |
| 1705 | object_dynamic_cast(OBJECT(dev), TYPE_RISCV_IOMMU_PCI)) { |
| 1706 | s->iommu_sys = ON_OFF_AUTO_OFF; |
| 1707 | return HOTPLUG_HANDLER(machine); |
| 1708 | } |
| 1709 | |
| 1710 | return NULL; |
| 1711 | } |
| 1712 | |
| 1713 | static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, |
| 1714 | DeviceState *dev, Error **errp) |
| 1715 | { |
| 1716 | RISCVVirtState *s = RISCV_VIRT_MACHINE(hotplug_dev); |
| 1717 | |
| 1718 | if (s->platform_bus_dev) { |
| 1719 | MachineClass *mc = MACHINE_GET_CLASS(s); |
| 1720 | |
| 1721 | if (device_is_dynamic_sysbus(mc, dev)) { |
| 1722 | platform_bus_link_device(PLATFORM_BUS_DEVICE(s->platform_bus_dev), |
| 1723 | SYS_BUS_DEVICE(dev)); |
| 1724 | } |
| 1725 | } |
| 1726 | |
| 1727 | if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { |
| 1728 | create_fdt_virtio_iommu(s, pci_get_bdf(PCI_DEVICE(dev))); |
| 1729 | } |
| 1730 | |
| 1731 | if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_IOMMU_PCI)) { |
| 1732 | create_fdt_iommu(s, pci_get_bdf(PCI_DEVICE(dev))); |
| 1733 | s->iommu_sys = ON_OFF_AUTO_OFF; |
| 1734 | } |
| 1735 | } |
| 1736 | |
| 1737 | static void virt_machine_class_init(ObjectClass *oc, const void *data) |
| 1738 | { |
| 1739 | MachineClass *mc = MACHINE_CLASS(oc); |
| 1740 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); |
| 1741 | |
| 1742 | mc->desc = "RISC-V VirtIO board"; |
| 1743 | mc->init = virt_machine_init; |
| 1744 | mc->max_cpus = VIRT_CPUS_MAX; |
| 1745 | mc->default_cpu_type = TYPE_RISCV_CPU_BASE; |
| 1746 | mc->block_default_type = IF_VIRTIO; |
| 1747 | mc->no_cdrom = 1; |
| 1748 | mc->pci_allow_0_address = true; |
| 1749 | mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; |
| 1750 | mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; |
| 1751 | mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; |
| 1752 | mc->numa_mem_supported = true; |
| 1753 | /* platform instead of architectural choice */ |
| 1754 | mc->cpu_cluster_has_numa_boundary = true; |
| 1755 | mc->default_ram_id = "riscv_virt_board.ram"; |
| 1756 | assert(!mc->get_hotplug_handler); |
| 1757 | mc->get_hotplug_handler = virt_machine_get_hotplug_handler; |
| 1758 | |
| 1759 | hc->plug = virt_machine_device_plug_cb; |
| 1760 | |
| 1761 | machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); |
| 1762 | machine_class_allow_dynamic_sysbus_dev(mc, TYPE_UEFI_VARS_SYSBUS); |
| 1763 | #ifdef CONFIG_TPM |
| 1764 | machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); |
| 1765 | #endif |
| 1766 | |
| 1767 | object_class_property_add_bool(oc, "aclint", virt_get_aclint, |
| 1768 | virt_set_aclint); |
| 1769 | object_class_property_set_description(oc, "aclint", |
| 1770 | "(TCG only) Set on/off to " |
| 1771 | "enable/disable emulating " |
| 1772 | "ACLINT devices"); |
| 1773 | |
| 1774 | object_class_property_add_str(oc, "aia", virt_get_aia, |
| 1775 | virt_set_aia); |
| 1776 | object_class_property_set_description(oc, "aia", |
| 1777 | "Set type of AIA interrupt " |
| 1778 | "controller. Valid values are " |
| 1779 | "none, aplic, and aplic-imsic."); |
| 1780 | |
| 1781 | object_class_property_add_str(oc, "aia-guests", |
| 1782 | virt_get_aia_guests, |
| 1783 | virt_set_aia_guests); |
| 1784 | { |
| 1785 | g_autofree char *str = |
| 1786 | g_strdup_printf("Set number of guest MMIO pages for AIA IMSIC. " |
| 1787 | "Valid value should be between 0 and %d.", |
| 1788 | VIRT_IRQCHIP_MAX_GUESTS); |
| 1789 | object_class_property_set_description(oc, "aia-guests", str); |
| 1790 | } |
| 1791 | |
| 1792 | object_class_property_add(oc, "acpi", "OnOffAuto", |
| 1793 | virt_get_acpi, virt_set_acpi, |
| 1794 | NULL, NULL); |
| 1795 | object_class_property_set_description(oc, "acpi", |
| 1796 | "Enable ACPI"); |
| 1797 | |
| 1798 | object_class_property_add(oc, "iommu-sys", "OnOffAuto", |
| 1799 | virt_get_iommu_sys, virt_set_iommu_sys, |
| 1800 | NULL, NULL); |
| 1801 | object_class_property_set_description(oc, "iommu-sys", |
| 1802 | "Enable IOMMU platform device"); |
| 1803 | } |
| 1804 | |
| 1805 | static const TypeInfo virt_machine_typeinfo = { |
| 1806 | .name = MACHINE_TYPE_NAME("virt"), |
| 1807 | .parent = TYPE_MACHINE, |
| 1808 | .class_init = virt_machine_class_init, |
| 1809 | .instance_init = virt_machine_instance_init, |
| 1810 | .instance_finalize = virt_machine_instance_finalize, |
| 1811 | .instance_size = sizeof(RISCVVirtState), |
| 1812 | .interfaces = (const InterfaceInfo[]) { |
| 1813 | { TYPE_HOTPLUG_HANDLER }, |
| 1814 | { TYPE_TARGET_RISCV32_MACHINE }, |
| 1815 | { TYPE_TARGET_RISCV64_MACHINE }, |
| 1816 | { } |
| 1817 | }, |
| 1818 | }; |
| 1819 | |
| 1820 | static void virt_machine_init_register_types(void) |
| 1821 | { |
| 1822 | type_register_static(&virt_machine_typeinfo); |
| 1823 | } |
| 1824 | |
| 1825 | type_init(virt_machine_init_register_types) |