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1 /*
2 * QEMU RISC-V Board Compatible with the Xiangshan Kunminghu
3 * FPGA prototype platform
4 *
5 * Copyright (c) 2025 Beijing Institute of Open Source Chip (BOSC)
6 * SPDX-License-Identifier: GPL-2.0-or-later
7 *
8 * Provides a board compatible with the Xiangshan Kunminghu
9 * FPGA prototype platform:
10 *
11 * 0) UART (16550A)
12 * 1) CLINT (Core-Local Interruptor)
13 * 2) IMSIC (Incoming MSI Controller)
14 * 3) APLIC (Advanced Platform-Level Interrupt Controller)
15 *
16 * More information can be found in our Github repository:
17 * https://github.com/OpenXiangShan/XiangShan
18 *
19 * This program is free software; you can redistribute it and/or modify it
20 * under the terms and conditions of the GNU General Public License,
21 * version 2 or later, as published by the Free Software Foundation.
22 *
23 * This program is distributed in the hope it will be useful, but WITHOUT
24 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
25 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
26 * more details.
27 *
28 * You should have received a copy of the GNU General Public License along with
29 * this program. If not, see <http://www.gnu.org/licenses/>.
30 */
31
32 #include "qemu/osdep.h"
33 #include "qapi/error.h"
34 #include "system/address-spaces.h"
35 #include "hw/core/boards.h"
36 #include "hw/char/serial-mm.h"
37 #include "hw/intc/riscv_aclint.h"
38 #include "hw/intc/riscv_aplic.h"
39 #include "hw/intc/riscv_imsic.h"
40 #include "hw/core/qdev-properties.h"
41 #include "hw/riscv/boot.h"
42 #include "hw/riscv/xiangshan_kmh.h"
43 #include "hw/riscv/riscv_hart.h"
44 #include "hw/riscv/machines-qom.h"
45 #include "system/system.h"
46
47 static const MemMapEntry xiangshan_kmh_memmap[] = {
48 [XIANGSHAN_KMH_ROM] = { 0x1000, 0xF000 },
49 [XIANGSHAN_KMH_UART0] = { 0x310B0000, 0x10000 },
50 [XIANGSHAN_KMH_CLINT] = { 0x38000000, 0x10000 },
51 [XIANGSHAN_KMH_APLIC_M] = { 0x31100000, 0x4000 },
52 [XIANGSHAN_KMH_APLIC_S] = { 0x31120000, 0x4000 },
53 [XIANGSHAN_KMH_IMSIC_M] = { 0x3A800000, 0x10000 },
54 [XIANGSHAN_KMH_IMSIC_S] = { 0x3B000000, 0x80000 },
55 [XIANGSHAN_KMH_DRAM] = { 0x80000000, 0x0 },
56 };
57
58 static DeviceState *xiangshan_kmh_create_aia(uint32_t num_harts)
59 {
60 int i;
61 const MemMapEntry *memmap = xiangshan_kmh_memmap;
62 hwaddr addr = 0;
63 DeviceState *aplic_m = NULL;
64
65 /* M-level IMSICs */
66 addr = memmap[XIANGSHAN_KMH_IMSIC_M].base;
67 for (i = 0; i < num_harts; i++) {
68 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0), i, true,
69 1, XIANGSHAN_KMH_IMSIC_NUM_IDS);
70 }
71
72 /* S-level IMSICs */
73 addr = memmap[XIANGSHAN_KMH_IMSIC_S].base;
74 for (i = 0; i < num_harts; i++) {
75 riscv_imsic_create(addr +
76 i * IMSIC_HART_SIZE(XIANGSHAN_KMH_IMSIC_GUEST_BITS),
77 i, false, 1 + XIANGSHAN_KMH_IMSIC_GUEST_BITS,
78 XIANGSHAN_KMH_IMSIC_NUM_IDS);
79 }
80
81 /* M-level APLIC */
82 aplic_m = riscv_aplic_create(memmap[XIANGSHAN_KMH_APLIC_M].base,
83 memmap[XIANGSHAN_KMH_APLIC_M].size,
84 0, 0, XIANGSHAN_KMH_APLIC_NUM_SOURCES,
85 1, true, true, NULL);
86
87 /* S-level APLIC */
88 riscv_aplic_create(memmap[XIANGSHAN_KMH_APLIC_S].base,
89 memmap[XIANGSHAN_KMH_APLIC_S].size,
90 0, 0, XIANGSHAN_KMH_APLIC_NUM_SOURCES,
91 1, true, false, aplic_m);
92
93 return aplic_m;
94 }
95
96 static void xiangshan_kmh_soc_realize(DeviceState *dev, Error **errp)
97 {
98 MachineState *ms = MACHINE(qdev_get_machine());
99 XiangshanKmhSoCState *s = XIANGSHAN_KMH_SOC(dev);
100 const MemMapEntry *memmap = xiangshan_kmh_memmap;
101 MemoryRegion *system_memory = get_system_memory();
102 uint32_t num_harts = ms->smp.cpus;
103
104 qdev_prop_set_uint32(DEVICE(&s->cpus), "num-harts", num_harts);
105 qdev_prop_set_uint32(DEVICE(&s->cpus), "hartid-base", 0);
106 qdev_prop_set_string(DEVICE(&s->cpus), "cpu-type",
107 TYPE_RISCV_CPU_XIANGSHAN_KMH);
108 sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);
109
110 /* AIA */
111 s->irqchip = xiangshan_kmh_create_aia(num_harts);
112
113 /* UART */
114 serial_mm_init(system_memory, memmap[XIANGSHAN_KMH_UART0].base, 2,
115 qdev_get_gpio_in(s->irqchip, XIANGSHAN_KMH_UART0_IRQ),
116 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN);
117
118 /* CLINT */
119 riscv_aclint_swi_create(memmap[XIANGSHAN_KMH_CLINT].base,
120 0, num_harts, false);
121 riscv_aclint_mtimer_create(memmap[XIANGSHAN_KMH_CLINT].base +
122 RISCV_ACLINT_SWI_SIZE,
123 RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
124 0, num_harts, RISCV_ACLINT_DEFAULT_MTIMECMP,
125 RISCV_ACLINT_DEFAULT_MTIME,
126 XIANGSHAN_KMH_CLINT_TIMEBASE_FREQ, true);
127
128 /* ROM */
129 memory_region_init_rom(&s->rom, OBJECT(dev), "xiangshan.kunminghu.rom",
130 memmap[XIANGSHAN_KMH_ROM].size, &error_fatal);
131 memory_region_add_subregion(system_memory,
132 memmap[XIANGSHAN_KMH_ROM].base, &s->rom);
133 }
134
135 static void xiangshan_kmh_soc_class_init(ObjectClass *klass, const void *data)
136 {
137 DeviceClass *dc = DEVICE_CLASS(klass);
138
139 dc->realize = xiangshan_kmh_soc_realize;
140 dc->user_creatable = false;
141 }
142
143 static void xiangshan_kmh_soc_instance_init(Object *obj)
144 {
145 XiangshanKmhSoCState *s = XIANGSHAN_KMH_SOC(obj);
146
147 object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
148 }
149
150 static const TypeInfo xiangshan_kmh_soc_info = {
151 .name = TYPE_XIANGSHAN_KMH_SOC,
152 .parent = TYPE_DEVICE,
153 .instance_size = sizeof(XiangshanKmhSoCState),
154 .instance_init = xiangshan_kmh_soc_instance_init,
155 .class_init = xiangshan_kmh_soc_class_init,
156 };
157
158 static void xiangshan_kmh_soc_register_types(void)
159 {
160 type_register_static(&xiangshan_kmh_soc_info);
161 }
162 type_init(xiangshan_kmh_soc_register_types)
163
164 static void xiangshan_kmh_machine_init(MachineState *machine)
165 {
166 XiangshanKmhState *s = XIANGSHAN_KMH_MACHINE(machine);
167 const MemMapEntry *memmap = xiangshan_kmh_memmap;
168 MemoryRegion *system_memory = get_system_memory();
169 hwaddr start_addr = memmap[XIANGSHAN_KMH_DRAM].base;
170 RISCVBootInfo boot_info;
171
172 /* Initialize SoC */
173 object_initialize_child(OBJECT(machine), "soc", &s->soc,
174 TYPE_XIANGSHAN_KMH_SOC);
175 qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
176
177 /* Register RAM */
178 memory_region_add_subregion(system_memory,
179 memmap[XIANGSHAN_KMH_DRAM].base,
180 machine->ram);
181
182 riscv_boot_info_init(&boot_info, &s->soc.cpus);
183
184 /* ROM reset vector */
185 riscv_setup_rom_reset_vec(machine, &s->soc.cpus,
186 start_addr,
187 memmap[XIANGSHAN_KMH_ROM].base,
188 memmap[XIANGSHAN_KMH_ROM].size, 0, 0);
189 if (machine->firmware) {
190 riscv_load_firmware(machine, &boot_info, machine->firmware,
191 &start_addr, NULL);
192 }
193
194 /* Note: dtb has been integrated into firmware(OpenSBI) when compiling */
195 }
196
197 static void xiangshan_kmh_machine_class_init(ObjectClass *klass, const void *data)
198 {
199 MachineClass *mc = MACHINE_CLASS(klass);
200 static const char *const valid_cpu_types[] = {
201 TYPE_RISCV_CPU_XIANGSHAN_KMH,
202 NULL
203 };
204
205 mc->desc = "RISC-V Board compatible with the Xiangshan " \
206 "Kunminghu FPGA prototype platform";
207 mc->init = xiangshan_kmh_machine_init;
208 mc->max_cpus = XIANGSHAN_KMH_MAX_CPUS;
209 mc->default_cpu_type = TYPE_RISCV_CPU_XIANGSHAN_KMH;
210 mc->valid_cpu_types = valid_cpu_types;
211 mc->default_ram_id = "xiangshan.kunminghu.ram";
212 }
213
214 static const TypeInfo xiangshan_kmh_machine_info = {
215 .name = TYPE_XIANGSHAN_KMH_MACHINE,
216 .parent = TYPE_MACHINE,
217 .instance_size = sizeof(XiangshanKmhState),
218 .class_init = xiangshan_kmh_machine_class_init,
219 .interfaces = riscv64_machine_interfaces,
220 };
221
222 static void xiangshan_kmh_machine_register_types(void)
223 {
224 type_register_static(&xiangshan_kmh_machine_info);
225 }
226 type_init(xiangshan_kmh_machine_register_types)