| 1 | /* |
| 2 | * RX QEMU GDB simulator |
| 3 | * |
| 4 | * Copyright (c) 2019 Yoshinori Sato |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms and conditions of the GNU General Public License, |
| 8 | * version 2 or later, as published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | * more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License along with |
| 16 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 17 | */ |
| 18 | |
| 19 | #include "qemu/osdep.h" |
| 20 | #include "qemu/cutils.h" |
| 21 | #include "qemu/error-report.h" |
| 22 | #include "qemu/guest-random.h" |
| 23 | #include "qemu/units.h" |
| 24 | #include "qapi/error.h" |
| 25 | #include "hw/core/loader.h" |
| 26 | #include "hw/rx/rx62n.h" |
| 27 | #include "system/qtest.h" |
| 28 | #include "system/device_tree.h" |
| 29 | #include "system/reset.h" |
| 30 | #include "hw/core/boards.h" |
| 31 | #include "qom/object.h" |
| 32 | |
| 33 | /* Same address of GDB integrated simulator */ |
| 34 | #define SDRAM_BASE EXT_CS_BASE |
| 35 | |
| 36 | struct RxGdbSimMachineClass { |
| 37 | /*< private >*/ |
| 38 | MachineClass parent_class; |
| 39 | /*< public >*/ |
| 40 | const char *mcu_name; |
| 41 | uint32_t xtal_freq_hz; |
| 42 | }; |
| 43 | typedef struct RxGdbSimMachineClass RxGdbSimMachineClass; |
| 44 | |
| 45 | struct RxGdbSimMachineState { |
| 46 | /*< private >*/ |
| 47 | MachineState parent_obj; |
| 48 | /*< public >*/ |
| 49 | RX62NState mcu; |
| 50 | }; |
| 51 | typedef struct RxGdbSimMachineState RxGdbSimMachineState; |
| 52 | |
| 53 | #define TYPE_RX_GDBSIM_MACHINE MACHINE_TYPE_NAME("rx62n-common") |
| 54 | |
| 55 | DECLARE_OBJ_CHECKERS(RxGdbSimMachineState, RxGdbSimMachineClass, |
| 56 | RX_GDBSIM_MACHINE, TYPE_RX_GDBSIM_MACHINE) |
| 57 | |
| 58 | |
| 59 | static void rx_load_image(RXCPU *cpu, const char *filename, |
| 60 | uint32_t start, uint32_t size) |
| 61 | { |
| 62 | static uint32_t extable[32]; |
| 63 | long kernel_size; |
| 64 | int i; |
| 65 | |
| 66 | kernel_size = load_image_targphys(filename, start, size, NULL); |
| 67 | if (kernel_size < 0) { |
| 68 | fprintf(stderr, "qemu: could not load kernel '%s'\n", filename); |
| 69 | exit(1); |
| 70 | } |
| 71 | cpu->env.pc = start; |
| 72 | |
| 73 | /* setup exception trap trampoline */ |
| 74 | /* linux kernel only works little-endian mode */ |
| 75 | for (i = 0; i < ARRAY_SIZE(extable); i++) { |
| 76 | extable[i] = cpu_to_le32(0x10 + i * 4); |
| 77 | } |
| 78 | rom_add_blob_fixed("extable", extable, sizeof(extable), VECTOR_TABLE_BASE); |
| 79 | } |
| 80 | |
| 81 | static void rx_gdbsim_init(MachineState *machine) |
| 82 | { |
| 83 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
| 84 | RxGdbSimMachineState *s = RX_GDBSIM_MACHINE(machine); |
| 85 | RxGdbSimMachineClass *rxc = RX_GDBSIM_MACHINE_GET_CLASS(machine); |
| 86 | MemoryRegion *sysmem = get_system_memory(); |
| 87 | const char *kernel_filename = machine->kernel_filename; |
| 88 | const char *dtb_filename = machine->dtb; |
| 89 | uint8_t rng_seed[32]; |
| 90 | |
| 91 | if (machine->ram_size < mc->default_ram_size) { |
| 92 | char *sz = size_to_str(mc->default_ram_size); |
| 93 | error_report("Invalid RAM size, should be more than %s", sz); |
| 94 | g_free(sz); |
| 95 | exit(1); |
| 96 | } |
| 97 | |
| 98 | /* Allocate memory space */ |
| 99 | memory_region_add_subregion(sysmem, SDRAM_BASE, machine->ram); |
| 100 | |
| 101 | /* Initialize MCU */ |
| 102 | object_initialize_child(OBJECT(machine), "mcu", &s->mcu, rxc->mcu_name); |
| 103 | object_property_set_link(OBJECT(&s->mcu), "main-bus", OBJECT(sysmem), |
| 104 | &error_abort); |
| 105 | object_property_set_uint(OBJECT(&s->mcu), "xtal-frequency-hz", |
| 106 | rxc->xtal_freq_hz, &error_abort); |
| 107 | object_property_set_bool(OBJECT(&s->mcu), "load-kernel", |
| 108 | kernel_filename != NULL, &error_abort); |
| 109 | |
| 110 | if (!kernel_filename) { |
| 111 | if (machine->firmware) { |
| 112 | rom_add_file_fixed(machine->firmware, RX62N_CFLASH_BASE, 0); |
| 113 | } |
| 114 | } |
| 115 | |
| 116 | qdev_realize(DEVICE(&s->mcu), NULL, &error_abort); |
| 117 | |
| 118 | /* Load kernel and dtb */ |
| 119 | if (kernel_filename) { |
| 120 | ram_addr_t kernel_offset; |
| 121 | |
| 122 | /* |
| 123 | * The kernel image is loaded into |
| 124 | * the latter half of the SDRAM space. |
| 125 | */ |
| 126 | kernel_offset = machine->ram_size / 2; |
| 127 | rx_load_image(&s->mcu.cpu, kernel_filename, |
| 128 | SDRAM_BASE + kernel_offset, kernel_offset); |
| 129 | if (dtb_filename) { |
| 130 | ram_addr_t dtb_offset; |
| 131 | int dtb_size; |
| 132 | g_autofree void *dtb = load_device_tree(dtb_filename, &dtb_size); |
| 133 | |
| 134 | if (dtb == NULL) { |
| 135 | error_report("Couldn't open dtb file %s", dtb_filename); |
| 136 | exit(1); |
| 137 | } |
| 138 | if (machine->kernel_cmdline && |
| 139 | qemu_fdt_setprop_string(dtb, "/chosen", "bootargs", |
| 140 | machine->kernel_cmdline) < 0) { |
| 141 | error_report("Couldn't set /chosen/bootargs"); |
| 142 | exit(1); |
| 143 | } |
| 144 | qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); |
| 145 | qemu_fdt_setprop(dtb, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed)); |
| 146 | /* DTB is located at the end of SDRAM space. */ |
| 147 | dtb_offset = ROUND_DOWN(machine->ram_size - dtb_size, 16); |
| 148 | rom_add_blob_fixed("dtb", dtb, dtb_size, |
| 149 | SDRAM_BASE + dtb_offset); |
| 150 | qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds, |
| 151 | rom_ptr(SDRAM_BASE + dtb_offset, dtb_size)); |
| 152 | /* Set dtb address to R1 */ |
| 153 | s->mcu.cpu.env.regs[1] = SDRAM_BASE + dtb_offset; |
| 154 | } |
| 155 | } |
| 156 | } |
| 157 | |
| 158 | static void rx_gdbsim_class_init(ObjectClass *oc, const void *data) |
| 159 | { |
| 160 | MachineClass *mc = MACHINE_CLASS(oc); |
| 161 | |
| 162 | mc->init = rx_gdbsim_init; |
| 163 | mc->default_cpu_type = TYPE_RX62N_CPU; |
| 164 | mc->default_ram_size = 16 * MiB; |
| 165 | mc->default_ram_id = "ext-sdram"; |
| 166 | } |
| 167 | |
| 168 | static void rx62n7_class_init(ObjectClass *oc, const void *data) |
| 169 | { |
| 170 | RxGdbSimMachineClass *rxc = RX_GDBSIM_MACHINE_CLASS(oc); |
| 171 | MachineClass *mc = MACHINE_CLASS(oc); |
| 172 | |
| 173 | rxc->mcu_name = TYPE_R5F562N7_MCU; |
| 174 | rxc->xtal_freq_hz = 12 * 1000 * 1000; |
| 175 | mc->desc = "gdb simulator (R5F562N7 MCU and external RAM)"; |
| 176 | }; |
| 177 | |
| 178 | static void rx62n8_class_init(ObjectClass *oc, const void *data) |
| 179 | { |
| 180 | RxGdbSimMachineClass *rxc = RX_GDBSIM_MACHINE_CLASS(oc); |
| 181 | MachineClass *mc = MACHINE_CLASS(oc); |
| 182 | |
| 183 | rxc->mcu_name = TYPE_R5F562N8_MCU; |
| 184 | rxc->xtal_freq_hz = 12 * 1000 * 1000; |
| 185 | mc->desc = "gdb simulator (R5F562N8 MCU and external RAM)"; |
| 186 | }; |
| 187 | |
| 188 | static const TypeInfo rx_gdbsim_types[] = { |
| 189 | { |
| 190 | .name = MACHINE_TYPE_NAME("gdbsim-r5f562n7"), |
| 191 | .parent = TYPE_RX_GDBSIM_MACHINE, |
| 192 | .class_init = rx62n7_class_init, |
| 193 | }, { |
| 194 | .name = MACHINE_TYPE_NAME("gdbsim-r5f562n8"), |
| 195 | .parent = TYPE_RX_GDBSIM_MACHINE, |
| 196 | .class_init = rx62n8_class_init, |
| 197 | }, { |
| 198 | .name = TYPE_RX_GDBSIM_MACHINE, |
| 199 | .parent = TYPE_MACHINE, |
| 200 | .instance_size = sizeof(RxGdbSimMachineState), |
| 201 | .class_size = sizeof(RxGdbSimMachineClass), |
| 202 | .class_init = rx_gdbsim_class_init, |
| 203 | .abstract = true, |
| 204 | } |
| 205 | }; |
| 206 | |
| 207 | DEFINE_TYPES(rx_gdbsim_types) |