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1 /*
2 * Channel subsystem base support.
3 *
4 * Copyright 2012 IBM Corp.
5 * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com>
6 *
7 * This work is licensed under the terms of the GNU GPL, version 2 or (at
8 * your option) any later version. See the COPYING file in the top-level
9 * directory.
10 */
11
12 #include "qemu/osdep.h"
13 #include "qapi/error.h"
14 #include "qapi/visitor.h"
15 #include "qemu/bitops.h"
16 #include "qemu/error-report.h"
17 #include "system/address-spaces.h"
18 #include "system/physmem.h"
19 #include "hw/s390x/ioinst.h"
20 #include "hw/core/qdev-properties.h"
21 #include "hw/s390x/css.h"
22 #include "trace.h"
23 #include "hw/s390x/s390_flic.h"
24 #include "hw/s390x/s390-virtio-ccw.h"
25 #include "hw/s390x/s390-ccw.h"
26 #include "exec/cpu-common.h"
27
28 typedef struct CrwContainer {
29 CRW crw;
30 QTAILQ_ENTRY(CrwContainer) sibling;
31 } CrwContainer;
32
33 static const VMStateDescription vmstate_crw = {
34 .name = "s390_crw",
35 .version_id = 1,
36 .minimum_version_id = 1,
37 .fields = (const VMStateField[]) {
38 VMSTATE_UINT16(flags, CRW),
39 VMSTATE_UINT16(rsid, CRW),
40 VMSTATE_END_OF_LIST()
41 },
42 };
43
44 static const VMStateDescription vmstate_crw_container = {
45 .name = "s390_crw_container",
46 .version_id = 1,
47 .minimum_version_id = 1,
48 .fields = (const VMStateField[]) {
49 VMSTATE_STRUCT(crw, CrwContainer, 0, vmstate_crw, CRW),
50 VMSTATE_END_OF_LIST()
51 },
52 };
53
54 typedef struct ChpInfo {
55 uint8_t in_use;
56 uint8_t type;
57 uint8_t is_virtual;
58 } ChpInfo;
59
60 static const VMStateDescription vmstate_chp_info = {
61 .name = "s390_chp_info",
62 .version_id = 1,
63 .minimum_version_id = 1,
64 .fields = (const VMStateField[]) {
65 VMSTATE_UINT8(in_use, ChpInfo),
66 VMSTATE_UINT8(type, ChpInfo),
67 VMSTATE_UINT8(is_virtual, ChpInfo),
68 VMSTATE_END_OF_LIST()
69 }
70 };
71
72 typedef struct SubchSet {
73 SubchDev *sch[MAX_SCHID + 1];
74 unsigned long schids_used[BITS_TO_LONGS(MAX_SCHID + 1)];
75 unsigned long devnos_used[BITS_TO_LONGS(MAX_SCHID + 1)];
76 } SubchSet;
77
78 static const VMStateDescription vmstate_scsw = {
79 .name = "s390_scsw",
80 .version_id = 1,
81 .minimum_version_id = 1,
82 .fields = (const VMStateField[]) {
83 VMSTATE_UINT16(flags, SCSW),
84 VMSTATE_UINT16(ctrl, SCSW),
85 VMSTATE_UINT32(cpa, SCSW),
86 VMSTATE_UINT8(dstat, SCSW),
87 VMSTATE_UINT8(cstat, SCSW),
88 VMSTATE_UINT16(count, SCSW),
89 VMSTATE_END_OF_LIST()
90 }
91 };
92
93 static const VMStateDescription vmstate_pmcw = {
94 .name = "s390_pmcw",
95 .version_id = 1,
96 .minimum_version_id = 1,
97 .fields = (const VMStateField[]) {
98 VMSTATE_UINT32(intparm, PMCW),
99 VMSTATE_UINT16(flags, PMCW),
100 VMSTATE_UINT16(devno, PMCW),
101 VMSTATE_UINT8(lpm, PMCW),
102 VMSTATE_UINT8(pnom, PMCW),
103 VMSTATE_UINT8(lpum, PMCW),
104 VMSTATE_UINT8(pim, PMCW),
105 VMSTATE_UINT16(mbi, PMCW),
106 VMSTATE_UINT8(pom, PMCW),
107 VMSTATE_UINT8(pam, PMCW),
108 VMSTATE_UINT8_ARRAY(chpid, PMCW, 8),
109 VMSTATE_UINT32(chars, PMCW),
110 VMSTATE_END_OF_LIST()
111 }
112 };
113
114 static const VMStateDescription vmstate_schib = {
115 .name = "s390_schib",
116 .version_id = 1,
117 .minimum_version_id = 1,
118 .fields = (const VMStateField[]) {
119 VMSTATE_STRUCT(pmcw, SCHIB, 0, vmstate_pmcw, PMCW),
120 VMSTATE_STRUCT(scsw, SCHIB, 0, vmstate_scsw, SCSW),
121 VMSTATE_UINT64(mba, SCHIB),
122 VMSTATE_UINT8_ARRAY(mda, SCHIB, 4),
123 VMSTATE_END_OF_LIST()
124 }
125 };
126
127
128 static const VMStateDescription vmstate_ccw1 = {
129 .name = "s390_ccw1",
130 .version_id = 1,
131 .minimum_version_id = 1,
132 .fields = (const VMStateField[]) {
133 VMSTATE_UINT8(cmd_code, CCW1),
134 VMSTATE_UINT8(flags, CCW1),
135 VMSTATE_UINT16(count, CCW1),
136 VMSTATE_UINT32(cda, CCW1),
137 VMSTATE_END_OF_LIST()
138 }
139 };
140
141 static const VMStateDescription vmstate_ciw = {
142 .name = "s390_ciw",
143 .version_id = 1,
144 .minimum_version_id = 1,
145 .fields = (const VMStateField[]) {
146 VMSTATE_UINT8(type, CIW),
147 VMSTATE_UINT8(command, CIW),
148 VMSTATE_UINT16(count, CIW),
149 VMSTATE_END_OF_LIST()
150 }
151 };
152
153 static const VMStateDescription vmstate_sense_id = {
154 .name = "s390_sense_id",
155 .version_id = 1,
156 .minimum_version_id = 1,
157 .fields = (const VMStateField[]) {
158 VMSTATE_UINT8(reserved, SenseId),
159 VMSTATE_UINT16(cu_type, SenseId),
160 VMSTATE_UINT8(cu_model, SenseId),
161 VMSTATE_UINT16(dev_type, SenseId),
162 VMSTATE_UINT8(dev_model, SenseId),
163 VMSTATE_UINT8(unused, SenseId),
164 VMSTATE_STRUCT_ARRAY(ciw, SenseId, MAX_CIWS, 0, vmstate_ciw, CIW),
165 VMSTATE_END_OF_LIST()
166 }
167 };
168
169 static const VMStateDescription vmstate_orb = {
170 .name = "s390_orb",
171 .version_id = 1,
172 .minimum_version_id = 1,
173 .fields = (const VMStateField[]) {
174 VMSTATE_UINT32(intparm, ORB),
175 VMSTATE_UINT16(ctrl0, ORB),
176 VMSTATE_UINT8(lpm, ORB),
177 VMSTATE_UINT8(ctrl1, ORB),
178 VMSTATE_UINT32(cpa, ORB),
179 VMSTATE_END_OF_LIST()
180 }
181 };
182
183 static const VMStateDescription vmstate_schdev_orb = {
184 .name = "s390_subch_dev/orb",
185 .version_id = 1,
186 .minimum_version_id = 1,
187 .fields = (const VMStateField[]) {
188 VMSTATE_STRUCT(orb, SubchDev, 1, vmstate_orb, ORB),
189 VMSTATE_END_OF_LIST()
190 }
191 };
192
193 static int subch_dev_post_load(void *opaque, int version_id);
194 static int subch_dev_pre_save(void *opaque);
195
196 const VMStateDescription vmstate_subch_dev = {
197 .name = "s390_subch_dev",
198 .version_id = 1,
199 .minimum_version_id = 1,
200 .post_load = subch_dev_post_load,
201 .pre_save = subch_dev_pre_save,
202 .fields = (const VMStateField[]) {
203 VMSTATE_UINT8_EQUAL(cssid, SubchDev),
204 VMSTATE_UINT8_EQUAL(ssid, SubchDev),
205 VMSTATE_UINT16(migrated_schid, SubchDev),
206 /*
207 * If devno mismatch on target, it may be due to some
208 * sequences of plug and unplug breaks migration for
209 * machine versions prior to 2.7 (known design flaw).
210 */
211 VMSTATE_UINT16_EQUAL(devno, SubchDev),
212 VMSTATE_BOOL(thinint_active, SubchDev),
213 VMSTATE_STRUCT(curr_status, SubchDev, 0, vmstate_schib, SCHIB),
214 VMSTATE_UINT8_ARRAY(sense_data, SubchDev, 32),
215 VMSTATE_UINT64(channel_prog, SubchDev),
216 VMSTATE_STRUCT(last_cmd, SubchDev, 0, vmstate_ccw1, CCW1),
217 VMSTATE_BOOL(last_cmd_valid, SubchDev),
218 VMSTATE_STRUCT(id, SubchDev, 0, vmstate_sense_id, SenseId),
219 VMSTATE_BOOL(ccw_fmt_1, SubchDev),
220 VMSTATE_UINT8(ccw_no_data_cnt, SubchDev),
221 VMSTATE_END_OF_LIST()
222 },
223 .subsections = (const VMStateDescription * const []) {
224 &vmstate_schdev_orb,
225 NULL
226 }
227 };
228
229 typedef struct IndAddrPtrTmp {
230 IndAddr **parent;
231 uint64_t addr;
232 int32_t len;
233 } IndAddrPtrTmp;
234
235 static int post_load_ind_addr(void *opaque, int version_id)
236 {
237 IndAddrPtrTmp *ptmp = opaque;
238 IndAddr **ind_addr = ptmp->parent;
239
240 if (ptmp->len != 0) {
241 *ind_addr = get_indicator(ptmp->addr, ptmp->len);
242 } else {
243 *ind_addr = NULL;
244 }
245 return 0;
246 }
247
248 static int pre_save_ind_addr(void *opaque)
249 {
250 IndAddrPtrTmp *ptmp = opaque;
251 IndAddr *ind_addr = *(ptmp->parent);
252
253 if (ind_addr != NULL) {
254 ptmp->len = ind_addr->len;
255 ptmp->addr = ind_addr->addr;
256 } else {
257 ptmp->len = 0;
258 ptmp->addr = 0L;
259 }
260
261 return 0;
262 }
263
264 static const VMStateDescription vmstate_ind_addr_tmp = {
265 .name = "s390_ind_addr_tmp",
266 .pre_save = pre_save_ind_addr,
267 .post_load = post_load_ind_addr,
268
269 .fields = (const VMStateField[]) {
270 VMSTATE_INT32(len, IndAddrPtrTmp),
271 VMSTATE_UINT64(addr, IndAddrPtrTmp),
272 VMSTATE_END_OF_LIST()
273 }
274 };
275
276 const VMStateDescription vmstate_ind_addr = {
277 .name = "s390_ind_addr_tmp",
278 .fields = (const VMStateField[]) {
279 VMSTATE_WITH_TMP(IndAddr*, IndAddrPtrTmp, vmstate_ind_addr_tmp),
280 VMSTATE_END_OF_LIST()
281 }
282 };
283
284 typedef struct CssImage {
285 SubchSet *sch_set[MAX_SSID + 1];
286 ChpInfo chpids[MAX_CHPID + 1];
287 } CssImage;
288
289 static const VMStateDescription vmstate_css_img = {
290 .name = "s390_css_img",
291 .version_id = 1,
292 .minimum_version_id = 1,
293 .fields = (const VMStateField[]) {
294 /* Subchannel sets have no relevant state. */
295 VMSTATE_STRUCT_ARRAY(chpids, CssImage, MAX_CHPID + 1, 0,
296 vmstate_chp_info, ChpInfo),
297 VMSTATE_END_OF_LIST()
298 }
299
300 };
301
302 typedef struct IoAdapter {
303 uint32_t id;
304 uint8_t type;
305 uint8_t isc;
306 uint8_t flags;
307 } IoAdapter;
308
309 typedef struct ChannelSubSys {
310 QTAILQ_HEAD(, CrwContainer) pending_crws;
311 bool sei_pending;
312 bool do_crw_mchk;
313 bool crws_lost;
314 uint8_t max_cssid;
315 uint8_t max_ssid;
316 bool chnmon_active;
317 uint64_t chnmon_area;
318 CssImage *css[MAX_CSSID + 1];
319 uint8_t default_cssid;
320 /* don't migrate, see css_register_io_adapters */
321 IoAdapter *io_adapters[CSS_IO_ADAPTER_TYPE_NUMS][MAX_ISC + 1];
322 /* don't migrate, see get_indicator and IndAddrPtrTmp */
323 QTAILQ_HEAD(, IndAddr) indicator_addresses;
324 } ChannelSubSys;
325
326 static const VMStateDescription vmstate_css = {
327 .name = "s390_css",
328 .version_id = 1,
329 .minimum_version_id = 1,
330 .fields = (const VMStateField[]) {
331 VMSTATE_QTAILQ_V(pending_crws, ChannelSubSys, 1, vmstate_crw_container,
332 CrwContainer, sibling),
333 VMSTATE_BOOL(sei_pending, ChannelSubSys),
334 VMSTATE_BOOL(do_crw_mchk, ChannelSubSys),
335 VMSTATE_BOOL(crws_lost, ChannelSubSys),
336 /* These were kind of migrated by virtio */
337 VMSTATE_UINT8(max_cssid, ChannelSubSys),
338 VMSTATE_UINT8(max_ssid, ChannelSubSys),
339 VMSTATE_BOOL(chnmon_active, ChannelSubSys),
340 VMSTATE_UINT64(chnmon_area, ChannelSubSys),
341 VMSTATE_ARRAY_OF_POINTER_TO_STRUCT(css, ChannelSubSys, MAX_CSSID + 1,
342 0, vmstate_css_img, CssImage),
343 VMSTATE_UINT8(default_cssid, ChannelSubSys),
344 VMSTATE_END_OF_LIST()
345 }
346 };
347
348 static ChannelSubSys channel_subsys = {
349 .pending_crws = QTAILQ_HEAD_INITIALIZER(channel_subsys.pending_crws),
350 .do_crw_mchk = true,
351 .sei_pending = false,
352 .crws_lost = false,
353 .chnmon_active = false,
354 .indicator_addresses =
355 QTAILQ_HEAD_INITIALIZER(channel_subsys.indicator_addresses),
356 };
357
358 static int subch_dev_pre_save(void *opaque)
359 {
360 SubchDev *s = opaque;
361
362 /* Prepare remote_schid for save */
363 s->migrated_schid = s->schid;
364
365 return 0;
366 }
367
368 static int subch_dev_post_load(void *opaque, int version_id)
369 {
370
371 SubchDev *s = opaque;
372
373 /* Re-assign the subchannel to remote_schid if necessary */
374 if (s->migrated_schid != s->schid) {
375 if (css_find_subch(true, s->cssid, s->ssid, s->schid) == s) {
376 /*
377 * Cleanup the slot before moving to s->migrated_schid provided
378 * it still belongs to us, i.e. it was not changed by previous
379 * invocation of this function.
380 */
381 css_subch_assign(s->cssid, s->ssid, s->schid, s->devno, NULL);
382 }
383 /* It's OK to re-assign without a prior de-assign. */
384 s->schid = s->migrated_schid;
385 css_subch_assign(s->cssid, s->ssid, s->schid, s->devno, s);
386 }
387
388 return 0;
389 }
390
391 void css_register_vmstate(void)
392 {
393 vmstate_register(NULL, 0, &vmstate_css, &channel_subsys);
394 }
395
396 IndAddr *get_indicator(hwaddr ind_addr, int len)
397 {
398 IndAddr *indicator;
399
400 QTAILQ_FOREACH(indicator, &channel_subsys.indicator_addresses, sibling) {
401 if (indicator->addr == ind_addr) {
402 indicator->refcnt++;
403 return indicator;
404 }
405 }
406 indicator = g_new0(IndAddr, 1);
407 indicator->addr = ind_addr;
408 indicator->len = len;
409 indicator->refcnt = 1;
410 QTAILQ_INSERT_TAIL(&channel_subsys.indicator_addresses,
411 indicator, sibling);
412 return indicator;
413 }
414
415 static int s390_io_adapter_map(AdapterInfo *adapter, uint64_t map_addr,
416 bool do_map)
417 {
418 S390FLICState *fs = s390_get_flic();
419 S390FLICStateClass *fsc = s390_get_flic_class(fs);
420
421 return fsc->io_adapter_map(fs, adapter->adapter_id, map_addr, do_map);
422 }
423
424 void release_indicator(AdapterInfo *adapter, IndAddr *indicator)
425 {
426 assert(indicator->refcnt > 0);
427 indicator->refcnt--;
428 if (indicator->refcnt > 0) {
429 return;
430 }
431 QTAILQ_REMOVE(&channel_subsys.indicator_addresses, indicator, sibling);
432 if (indicator->map) {
433 s390_io_adapter_map(adapter, indicator->map, false);
434 }
435 g_free(indicator);
436 }
437
438 int map_indicator(AdapterInfo *adapter, IndAddr *indicator)
439 {
440 int ret;
441
442 if (indicator->map) {
443 return 0; /* already mapped is not an error */
444 }
445 indicator->map = indicator->addr;
446 ret = s390_io_adapter_map(adapter, indicator->map, true);
447 if ((ret != 0) && (ret != -ENOSYS)) {
448 goto out_err;
449 }
450 return 0;
451
452 out_err:
453 indicator->map = 0;
454 return ret;
455 }
456
457 int css_create_css_image(uint8_t cssid, bool default_image)
458 {
459 trace_css_new_image(cssid, default_image ? "(default)" : "");
460 /* 255 is reserved */
461 if (cssid == 255) {
462 return -EINVAL;
463 }
464 if (channel_subsys.css[cssid]) {
465 return -EBUSY;
466 }
467 channel_subsys.css[cssid] = g_new0(CssImage, 1);
468 if (default_image) {
469 channel_subsys.default_cssid = cssid;
470 }
471 return 0;
472 }
473
474 uint32_t css_get_adapter_id(CssIoAdapterType type, uint8_t isc)
475 {
476 if (type >= CSS_IO_ADAPTER_TYPE_NUMS || isc > MAX_ISC ||
477 !channel_subsys.io_adapters[type][isc]) {
478 return -1;
479 }
480
481 return channel_subsys.io_adapters[type][isc]->id;
482 }
483
484 /**
485 * css_register_io_adapters: Register I/O adapters per ISC during init
486 *
487 * @swap: an indication if byte swap is needed.
488 * @maskable: an indication if the adapter is subject to the mask operation.
489 * @flags: further characteristics of the adapter.
490 * e.g. suppressible, an indication if the adapter is subject to AIS.
491 * @errp: location to store error information.
492 */
493 void css_register_io_adapters(CssIoAdapterType type, bool swap, bool maskable,
494 uint8_t flags, Error **errp)
495 {
496 uint32_t id;
497 int ret, isc;
498 IoAdapter *adapter;
499 S390FLICState *fs = s390_get_flic();
500 S390FLICStateClass *fsc = s390_get_flic_class(fs);
501
502 /*
503 * Disallow multiple registrations for the same device type.
504 * Report an error if registering for an already registered type.
505 */
506 if (channel_subsys.io_adapters[type][0]) {
507 error_setg(errp, "Adapters for type %d already registered", type);
508 }
509
510 for (isc = 0; isc <= MAX_ISC; isc++) {
511 id = (type << 3) | isc;
512 ret = fsc->register_io_adapter(fs, id, isc, swap, maskable, flags);
513 if (ret == 0) {
514 adapter = g_new0(IoAdapter, 1);
515 adapter->id = id;
516 adapter->isc = isc;
517 adapter->type = type;
518 adapter->flags = flags;
519 channel_subsys.io_adapters[type][isc] = adapter;
520 } else {
521 error_setg_errno(errp, -ret, "Unexpected error %d when "
522 "registering adapter %d", ret, id);
523 break;
524 }
525 }
526
527 /*
528 * No need to free registered adapters in kvm: kvm will clean up
529 * when the machine goes away.
530 */
531 if (ret) {
532 for (isc--; isc >= 0; isc--) {
533 g_free(channel_subsys.io_adapters[type][isc]);
534 channel_subsys.io_adapters[type][isc] = NULL;
535 }
536 }
537
538 }
539
540 static void css_clear_io_interrupt(uint16_t subchannel_id,
541 uint16_t subchannel_nr)
542 {
543 Error *err = NULL;
544 static bool no_clear_irq;
545 S390FLICState *fs = s390_get_flic();
546 S390FLICStateClass *fsc = s390_get_flic_class(fs);
547 int r;
548
549 if (unlikely(no_clear_irq)) {
550 return;
551 }
552 r = fsc->clear_io_irq(fs, subchannel_id, subchannel_nr);
553 switch (r) {
554 case 0:
555 break;
556 case -ENOSYS:
557 no_clear_irq = true;
558 /*
559 * Ignore unavailability, as the user can't do anything
560 * about it anyway.
561 */
562 break;
563 default:
564 error_setg_errno(&err, -r, "unexpected error condition");
565 error_propagate(&error_abort, err);
566 }
567 }
568
569 static inline uint16_t css_do_build_subchannel_id(uint8_t cssid, uint8_t ssid)
570 {
571 if (channel_subsys.max_cssid > 0) {
572 return (cssid << 8) | (1 << 3) | (ssid << 1) | 1;
573 }
574 return (ssid << 1) | 1;
575 }
576
577 uint16_t css_build_subchannel_id(SubchDev *sch)
578 {
579 return css_do_build_subchannel_id(sch->cssid, sch->ssid);
580 }
581
582 void css_inject_io_interrupt(SubchDev *sch)
583 {
584 uint8_t isc = (sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ISC) >> 11;
585
586 trace_css_io_interrupt(sch->cssid, sch->ssid, sch->schid,
587 sch->curr_status.pmcw.intparm, isc, "");
588 s390_io_interrupt(css_build_subchannel_id(sch),
589 sch->schid,
590 sch->curr_status.pmcw.intparm,
591 isc << 27);
592 }
593
594 void css_conditional_io_interrupt(SubchDev *sch)
595 {
596 /*
597 * If the subchannel is not enabled, it is not made status pending
598 * (see PoP p. 16-17, "Status Control").
599 */
600 if (!(sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ENA)) {
601 return;
602 }
603
604 /*
605 * If the subchannel is not currently status pending, make it pending
606 * with alert status.
607 */
608 if (!(sch->curr_status.scsw.ctrl & SCSW_STCTL_STATUS_PEND)) {
609 uint8_t isc = (sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ISC) >> 11;
610
611 trace_css_io_interrupt(sch->cssid, sch->ssid, sch->schid,
612 sch->curr_status.pmcw.intparm, isc,
613 "(unsolicited)");
614 sch->curr_status.scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL;
615 sch->curr_status.scsw.ctrl |=
616 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND;
617 /* Inject an I/O interrupt. */
618 s390_io_interrupt(css_build_subchannel_id(sch),
619 sch->schid,
620 sch->curr_status.pmcw.intparm,
621 isc << 27);
622 }
623 }
624
625 int css_do_sic(S390CPU *cpu, uint8_t isc, uint16_t mode)
626 {
627 CPUS390XState *env = &cpu->env;
628 S390FLICState *fs = s390_get_flic();
629 S390FLICStateClass *fsc = s390_get_flic_class(fs);
630 int r;
631
632 if (env->psw.mask & PSW_MASK_PSTATE) {
633 r = -PGM_PRIVILEGED;
634 goto out;
635 }
636
637 trace_css_do_sic(mode, isc);
638 switch (mode) {
639 case SIC_IRQ_MODE_ALL:
640 case SIC_IRQ_MODE_SINGLE:
641 break;
642 default:
643 r = -PGM_OPERAND;
644 goto out;
645 }
646
647 r = fsc->modify_ais_mode(fs, isc, mode) ? -PGM_OPERATION : 0;
648 out:
649 return r;
650 }
651
652 void css_adapter_interrupt(CssIoAdapterType type, uint8_t isc)
653 {
654 S390FLICState *fs = s390_get_flic();
655 S390FLICStateClass *fsc = s390_get_flic_class(fs);
656 uint32_t io_int_word = (isc << 27) | IO_INT_WORD_AI;
657 IoAdapter *adapter = channel_subsys.io_adapters[type][isc];
658
659 if (!adapter) {
660 return;
661 }
662
663 trace_css_adapter_interrupt(isc);
664 if (fs->ais_supported) {
665 if (fsc->inject_airq(fs, type, isc, adapter->flags)) {
666 error_report("Failed to inject airq with AIS supported");
667 exit(1);
668 }
669 } else {
670 s390_io_interrupt(0, 0, 0, io_int_word);
671 }
672 }
673
674 static void sch_handle_clear_func(SubchDev *sch)
675 {
676 SCHIB *schib = &sch->curr_status;
677 int path;
678
679 /* Path management: In our simple css, we always choose the only path. */
680 path = 0x80;
681
682 /* Reset values prior to 'issuing the clear signal'. */
683 schib->pmcw.lpum = 0;
684 schib->pmcw.pom = 0xff;
685 schib->scsw.flags &= ~SCSW_FLAGS_MASK_PNO;
686
687 /* We always 'attempt to issue the clear signal', and we always succeed. */
688 sch->channel_prog = 0x0;
689 sch->last_cmd_valid = false;
690 schib->scsw.ctrl &= ~SCSW_ACTL_CLEAR_PEND;
691 schib->scsw.ctrl |= SCSW_STCTL_STATUS_PEND;
692
693 schib->scsw.dstat = 0;
694 schib->scsw.cstat = 0;
695 schib->pmcw.lpum = path;
696
697 }
698
699 static void sch_handle_halt_func(SubchDev *sch)
700 {
701 SCHIB *schib = &sch->curr_status;
702 hwaddr curr_ccw = sch->channel_prog;
703 int path;
704
705 /* Path management: In our simple css, we always choose the only path. */
706 path = 0x80;
707
708 /* We always 'attempt to issue the halt signal', and we always succeed. */
709 sch->channel_prog = 0x0;
710 sch->last_cmd_valid = false;
711 schib->scsw.ctrl &= ~SCSW_ACTL_HALT_PEND;
712 schib->scsw.ctrl |= SCSW_STCTL_STATUS_PEND;
713
714 if ((schib->scsw.ctrl & (SCSW_ACTL_SUBCH_ACTIVE |
715 SCSW_ACTL_DEVICE_ACTIVE)) ||
716 !((schib->scsw.ctrl & SCSW_ACTL_START_PEND) ||
717 (schib->scsw.ctrl & SCSW_ACTL_SUSP))) {
718 schib->scsw.dstat = SCSW_DSTAT_DEVICE_END;
719 }
720 if ((schib->scsw.ctrl & (SCSW_ACTL_SUBCH_ACTIVE |
721 SCSW_ACTL_DEVICE_ACTIVE)) ||
722 (schib->scsw.ctrl & SCSW_ACTL_SUSP)) {
723 schib->scsw.cpa = curr_ccw + 8;
724 }
725 schib->scsw.cstat = 0;
726 schib->pmcw.lpum = path;
727
728 }
729
730 /*
731 * As the SenseId struct cannot be packed (would cause unaligned accesses), we
732 * have to copy the individual fields to an unstructured area using the correct
733 * layout (see SA22-7204-01 "Common I/O-Device Commands").
734 */
735 static void copy_sense_id_to_guest(uint8_t *dest, SenseId *src)
736 {
737 int i;
738
739 dest[0] = src->reserved;
740 stw_be_p(dest + 1, src->cu_type);
741 dest[3] = src->cu_model;
742 stw_be_p(dest + 4, src->dev_type);
743 dest[6] = src->dev_model;
744 dest[7] = src->unused;
745 for (i = 0; i < ARRAY_SIZE(src->ciw); i++) {
746 dest[8 + i * 4] = src->ciw[i].type;
747 dest[9 + i * 4] = src->ciw[i].command;
748 stw_be_p(dest + 10 + i * 4, src->ciw[i].count);
749 }
750 }
751
752 static CCW1 copy_ccw_from_guest(hwaddr addr, bool fmt1)
753 {
754 CCW0 tmp0;
755 CCW1 tmp1;
756 CCW1 ret;
757
758 if (fmt1) {
759 physical_memory_read(addr, &tmp1, sizeof(tmp1));
760 ret.cmd_code = tmp1.cmd_code;
761 ret.flags = tmp1.flags;
762 ret.count = be16_to_cpu(tmp1.count);
763 ret.cda = be32_to_cpu(tmp1.cda);
764 } else {
765 physical_memory_read(addr, &tmp0, sizeof(tmp0));
766 if ((tmp0.cmd_code & 0x0f) == CCW_CMD_TIC) {
767 ret.cmd_code = CCW_CMD_TIC;
768 ret.flags = 0;
769 ret.count = 0;
770 } else {
771 ret.cmd_code = tmp0.cmd_code;
772 ret.flags = tmp0.flags;
773 ret.count = be16_to_cpu(tmp0.count);
774 }
775 ret.cda = be16_to_cpu(tmp0.cda1) | (tmp0.cda0 << 16);
776 }
777 return ret;
778 }
779 /**
780 * If out of bounds marks the stream broken. If broken returns -EINVAL,
781 * otherwise the requested length (may be zero)
782 */
783 static inline int cds_check_len(CcwDataStream *cds, int len)
784 {
785 if (cds->at_byte + len > cds->count) {
786 cds->flags |= CDS_F_STREAM_BROKEN;
787 }
788 return cds->flags & CDS_F_STREAM_BROKEN ? -EINVAL : len;
789 }
790
791 static inline bool cds_ccw_addrs_ok(hwaddr addr, int len, bool ccw_fmt1)
792 {
793 return (addr + len) < (ccw_fmt1 ? (1UL << 31) : (1UL << 24));
794 }
795
796 static int ccw_dstream_rw_noflags(CcwDataStream *cds, void *buff, int len,
797 CcwDataStreamOp op)
798 {
799 int ret;
800
801 ret = cds_check_len(cds, len);
802 if (ret <= 0) {
803 return ret;
804 }
805 if (!cds_ccw_addrs_ok(cds->cda, len, cds->flags & CDS_F_FMT)) {
806 return -EINVAL; /* channel program check */
807 }
808 if (op == CDS_OP_A) {
809 goto incr;
810 }
811 if (!cds->do_skip) {
812 ret = address_space_rw(&address_space_memory, cds->cda,
813 MEMTXATTRS_UNSPECIFIED, buff, len, op);
814 } else {
815 ret = MEMTX_OK;
816 }
817 if (ret != MEMTX_OK) {
818 cds->flags |= CDS_F_STREAM_BROKEN;
819 return -EINVAL;
820 }
821 incr:
822 cds->at_byte += len;
823 cds->cda += len;
824 return 0;
825 }
826
827 /* returns values between 1 and bsz, where bsz is a power of 2 */
828 static inline uint16_t ida_continuous_left(hwaddr cda, uint64_t bsz)
829 {
830 return bsz - (cda & (bsz - 1));
831 }
832
833 static inline uint64_t ccw_ida_block_size(uint8_t flags)
834 {
835 if ((flags & CDS_F_C64) && !(flags & CDS_F_I2K)) {
836 return 1ULL << 12;
837 }
838 return 1ULL << 11;
839 }
840
841 static inline int ida_read_next_idaw(CcwDataStream *cds)
842 {
843 union {uint64_t fmt2; uint32_t fmt1; } idaw;
844 int ret;
845 hwaddr idaw_addr;
846 bool idaw_fmt2 = cds->flags & CDS_F_C64;
847 bool ccw_fmt1 = cds->flags & CDS_F_FMT;
848
849 if (idaw_fmt2) {
850 idaw_addr = cds->cda_orig + sizeof(idaw.fmt2) * cds->at_idaw;
851 if (idaw_addr & 0x07 || !cds_ccw_addrs_ok(idaw_addr, 0, ccw_fmt1)) {
852 return -EINVAL; /* channel program check */
853 }
854 ret = address_space_read(&address_space_memory, idaw_addr,
855 MEMTXATTRS_UNSPECIFIED, &idaw.fmt2,
856 sizeof(idaw.fmt2));
857 cds->cda = be64_to_cpu(idaw.fmt2);
858 } else {
859 idaw_addr = cds->cda_orig + sizeof(idaw.fmt1) * cds->at_idaw;
860 if (idaw_addr & 0x03 || !cds_ccw_addrs_ok(idaw_addr, 0, ccw_fmt1)) {
861 return -EINVAL; /* channel program check */
862 }
863 ret = address_space_read(&address_space_memory, idaw_addr,
864 MEMTXATTRS_UNSPECIFIED, &idaw.fmt1,
865 sizeof(idaw.fmt1));
866 cds->cda = be64_to_cpu(idaw.fmt1);
867 if (cds->cda & 0x80000000) {
868 return -EINVAL; /* channel program check */
869 }
870 }
871 ++(cds->at_idaw);
872 if (ret != MEMTX_OK) {
873 /* assume inaccessible address */
874 return -EINVAL; /* channel program check */
875 }
876 return 0;
877 }
878
879 static int ccw_dstream_rw_ida(CcwDataStream *cds, void *buff, int len,
880 CcwDataStreamOp op)
881 {
882 uint64_t bsz = ccw_ida_block_size(cds->flags);
883 int ret = 0;
884 uint16_t cont_left, iter_len;
885
886 ret = cds_check_len(cds, len);
887 if (ret <= 0) {
888 return ret;
889 }
890 if (!cds->at_idaw) {
891 /* read first idaw */
892 ret = ida_read_next_idaw(cds);
893 if (ret) {
894 goto err;
895 }
896 cont_left = ida_continuous_left(cds->cda, bsz);
897 } else {
898 cont_left = ida_continuous_left(cds->cda, bsz);
899 if (cont_left == bsz) {
900 ret = ida_read_next_idaw(cds);
901 if (ret) {
902 goto err;
903 }
904 if (cds->cda & (bsz - 1)) {
905 ret = -EINVAL; /* channel program check */
906 goto err;
907 }
908 }
909 }
910 do {
911 iter_len = MIN(len, cont_left);
912 if (op != CDS_OP_A) {
913 if (!cds->do_skip) {
914 ret = address_space_rw(&address_space_memory, cds->cda,
915 MEMTXATTRS_UNSPECIFIED, buff, iter_len,
916 op);
917 } else {
918 ret = MEMTX_OK;
919 }
920 if (ret != MEMTX_OK) {
921 /* assume inaccessible address */
922 ret = -EINVAL; /* channel program check */
923 goto err;
924 }
925 }
926 cds->at_byte += iter_len;
927 cds->cda += iter_len;
928 len -= iter_len;
929 if (!len) {
930 break;
931 }
932 ret = ida_read_next_idaw(cds);
933 if (ret) {
934 goto err;
935 }
936 cont_left = bsz;
937 } while (true);
938 return ret;
939 err:
940 cds->flags |= CDS_F_STREAM_BROKEN;
941 return ret;
942 }
943
944 void ccw_dstream_init(CcwDataStream *cds, CCW1 const *ccw, ORB const *orb)
945 {
946 /*
947 * We don't support MIDA (an optional facility) yet and we
948 * catch this earlier. Just for expressing the precondition.
949 */
950 g_assert(!(orb->ctrl1 & ORB_CTRL1_MASK_MIDAW));
951 cds->flags = (orb->ctrl0 & ORB_CTRL0_MASK_I2K ? CDS_F_I2K : 0) |
952 (orb->ctrl0 & ORB_CTRL0_MASK_C64 ? CDS_F_C64 : 0) |
953 (orb->ctrl0 & ORB_CTRL0_MASK_FMT ? CDS_F_FMT : 0) |
954 (ccw->flags & CCW_FLAG_IDA ? CDS_F_IDA : 0);
955
956 cds->count = ccw->count;
957 cds->cda_orig = ccw->cda;
958 /* skip is only effective for read, read backwards, or sense commands */
959 cds->do_skip = (ccw->flags & CCW_FLAG_SKIP) &&
960 ((ccw->cmd_code & 0x0f) == CCW_CMD_BASIC_SENSE ||
961 (ccw->cmd_code & 0x03) == 0x02 /* read */ ||
962 (ccw->cmd_code & 0x0f) == 0x0c /* read backwards */);
963 ccw_dstream_rewind(cds);
964 if (!(cds->flags & CDS_F_IDA)) {
965 cds->op_handler = ccw_dstream_rw_noflags;
966 } else {
967 cds->op_handler = ccw_dstream_rw_ida;
968 }
969 }
970
971 static int css_interpret_ccw(SubchDev *sch, hwaddr ccw_addr,
972 bool suspend_allowed)
973 {
974 int ret;
975 bool check_len;
976 int len;
977 CCW1 ccw;
978
979 if (!ccw_addr) {
980 return -EINVAL; /* channel-program check */
981 }
982 /* Check doubleword aligned and 31 or 24 (fmt 0) bit addressable. */
983 if (ccw_addr & (sch->ccw_fmt_1 ? 0x80000007 : 0xff000007)) {
984 return -EINVAL;
985 }
986
987 /* Translate everything to format-1 ccws - the information is the same. */
988 ccw = copy_ccw_from_guest(ccw_addr, sch->ccw_fmt_1);
989
990 /* Check for invalid command codes. */
991 if ((ccw.cmd_code & 0x0f) == 0) {
992 return -EINVAL;
993 }
994 if (((ccw.cmd_code & 0x0f) == CCW_CMD_TIC) &&
995 ((ccw.cmd_code & 0xf0) != 0)) {
996 return -EINVAL;
997 }
998 if (!sch->ccw_fmt_1 && (ccw.count == 0) &&
999 (ccw.cmd_code != CCW_CMD_TIC)) {
1000 return -EINVAL;
1001 }
1002
1003 /* We don't support MIDA. */
1004 if (ccw.flags & CCW_FLAG_MIDA) {
1005 return -EINVAL;
1006 }
1007
1008 if (ccw.flags & CCW_FLAG_SUSPEND) {
1009 return suspend_allowed ? -EINPROGRESS : -EINVAL;
1010 }
1011
1012 check_len = !((ccw.flags & CCW_FLAG_SLI) && !(ccw.flags & CCW_FLAG_DC));
1013
1014 if (!ccw.cda) {
1015 if (sch->ccw_no_data_cnt == 255) {
1016 return -EINVAL;
1017 }
1018 sch->ccw_no_data_cnt++;
1019 }
1020
1021 /* Look at the command. */
1022 ccw_dstream_init(&sch->cds, &ccw, &(sch->orb));
1023 switch (ccw.cmd_code) {
1024 case CCW_CMD_NOOP:
1025 /* Nothing to do. */
1026 ret = 0;
1027 break;
1028 case CCW_CMD_BASIC_SENSE:
1029 if (check_len) {
1030 if (ccw.count != sizeof(sch->sense_data)) {
1031 ret = -EINVAL;
1032 break;
1033 }
1034 }
1035 len = MIN(ccw.count, sizeof(sch->sense_data));
1036 ret = ccw_dstream_write_buf(&sch->cds, sch->sense_data, len);
1037 sch->curr_status.scsw.count = ccw_dstream_residual_count(&sch->cds);
1038 if (!ret) {
1039 memset(sch->sense_data, 0, sizeof(sch->sense_data));
1040 }
1041 break;
1042 case CCW_CMD_SENSE_ID:
1043 {
1044 /* According to SA22-7204-01, Sense-ID can store up to 256 bytes */
1045 uint8_t sense_id[256];
1046
1047 copy_sense_id_to_guest(sense_id, &sch->id);
1048 /* Sense ID information is device specific. */
1049 if (check_len) {
1050 if (ccw.count != sizeof(sense_id)) {
1051 ret = -EINVAL;
1052 break;
1053 }
1054 }
1055 len = MIN(ccw.count, sizeof(sense_id));
1056 /*
1057 * Only indicate 0xff in the first sense byte if we actually
1058 * have enough place to store at least bytes 0-3.
1059 */
1060 if (len >= 4) {
1061 sense_id[0] = 0xff;
1062 } else {
1063 sense_id[0] = 0;
1064 }
1065 ret = ccw_dstream_write_buf(&sch->cds, sense_id, len);
1066 if (!ret) {
1067 sch->curr_status.scsw.count = ccw_dstream_residual_count(&sch->cds);
1068 }
1069 break;
1070 }
1071 case CCW_CMD_TIC:
1072 if (sch->last_cmd_valid && (sch->last_cmd.cmd_code == CCW_CMD_TIC)) {
1073 ret = -EINVAL;
1074 break;
1075 }
1076 if (ccw.flags || ccw.count) {
1077 /* We have already sanitized these if converted from fmt 0. */
1078 ret = -EINVAL;
1079 break;
1080 }
1081 /* Limit the number of TICs in a given channel program */
1082 if (sch->ccw_tic_cnt == 255) {
1083 ret = -EINVAL;
1084 break;
1085 }
1086 sch->ccw_tic_cnt++;
1087 sch->channel_prog = ccw.cda;
1088 ret = -EAGAIN;
1089 break;
1090 default:
1091 if (sch->ccw_cb) {
1092 /* Handle device specific commands. */
1093 ret = sch->ccw_cb(sch, ccw);
1094 } else {
1095 ret = -ENOSYS;
1096 }
1097 break;
1098 }
1099 sch->last_cmd = ccw;
1100 sch->last_cmd_valid = true;
1101 if (ret == 0) {
1102 if (ccw.flags & CCW_FLAG_CC) {
1103 sch->channel_prog += 8;
1104 ret = -EAGAIN;
1105 }
1106 }
1107
1108 return ret;
1109 }
1110
1111 static void sch_handle_start_func_virtual(SubchDev *sch)
1112 {
1113 SCHIB *schib = &sch->curr_status;
1114 int path;
1115 int ret;
1116 bool suspend_allowed;
1117
1118 /* Path management: In our simple css, we always choose the only path. */
1119 path = 0x80;
1120
1121 if (!(schib->scsw.ctrl & SCSW_ACTL_SUSP)) {
1122 /* Start Function triggered via ssch, i.e. we have an ORB */
1123 ORB *orb = &sch->orb;
1124 schib->scsw.cstat = 0;
1125 schib->scsw.dstat = 0;
1126 /* Look at the orb and try to execute the channel program. */
1127 schib->pmcw.intparm = orb->intparm;
1128 if (!(orb->lpm & path)) {
1129 /* Generate a deferred cc 3 condition. */
1130 schib->scsw.flags |= SCSW_FLAGS_MASK_CC;
1131 schib->scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL;
1132 schib->scsw.ctrl |= (SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND);
1133 return;
1134 }
1135 sch->ccw_fmt_1 = !!(orb->ctrl0 & ORB_CTRL0_MASK_FMT);
1136 schib->scsw.flags |= (sch->ccw_fmt_1) ? SCSW_FLAGS_MASK_FMT : 0;
1137 sch->ccw_no_data_cnt = 0;
1138 sch->ccw_tic_cnt = 0;
1139 suspend_allowed = !!(orb->ctrl0 & ORB_CTRL0_MASK_SPND);
1140 } else {
1141 /* Start Function resumed via rsch */
1142 schib->scsw.ctrl &= ~(SCSW_ACTL_SUSP | SCSW_ACTL_RESUME_PEND);
1143 /* The channel program had been suspended before. */
1144 suspend_allowed = true;
1145 }
1146 sch->last_cmd_valid = false;
1147 do {
1148 ret = css_interpret_ccw(sch, sch->channel_prog, suspend_allowed);
1149 switch (ret) {
1150 case -EAGAIN:
1151 /* ccw chain, continue processing */
1152 break;
1153 case 0:
1154 /* success */
1155 schib->scsw.ctrl &= ~SCSW_ACTL_START_PEND;
1156 schib->scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL;
1157 schib->scsw.ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY |
1158 SCSW_STCTL_STATUS_PEND;
1159 schib->scsw.dstat = SCSW_DSTAT_CHANNEL_END | SCSW_DSTAT_DEVICE_END;
1160 schib->scsw.cpa = sch->channel_prog + 8;
1161 break;
1162 case -EIO:
1163 /* I/O errors, status depends on specific devices */
1164 break;
1165 case -ENOSYS:
1166 /* unsupported command, generate unit check (command reject) */
1167 schib->scsw.ctrl &= ~SCSW_ACTL_START_PEND;
1168 schib->scsw.dstat = SCSW_DSTAT_UNIT_CHECK;
1169 /* Set sense bit 0 in ecw0. */
1170 sch->sense_data[0] = 0x80;
1171 schib->scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL;
1172 schib->scsw.ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY |
1173 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND;
1174 schib->scsw.cpa = sch->channel_prog + 8;
1175 break;
1176 case -EINPROGRESS:
1177 /* channel program has been suspended */
1178 schib->scsw.ctrl &= ~SCSW_ACTL_START_PEND;
1179 schib->scsw.ctrl |= SCSW_ACTL_SUSP;
1180 break;
1181 default:
1182 /* error, generate channel program check */
1183 schib->scsw.ctrl &= ~SCSW_ACTL_START_PEND;
1184 schib->scsw.cstat = SCSW_CSTAT_PROG_CHECK;
1185 schib->scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL;
1186 schib->scsw.ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY |
1187 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND;
1188 schib->scsw.cpa = sch->channel_prog + 8;
1189 break;
1190 }
1191 } while (ret == -EAGAIN);
1192
1193 }
1194
1195 static IOInstEnding sch_handle_halt_func_passthrough(SubchDev *sch)
1196 {
1197 int ret;
1198
1199 ret = s390_ccw_halt(sch);
1200 if (ret == -ENOSYS) {
1201 sch_handle_halt_func(sch);
1202 return IOINST_CC_EXPECTED;
1203 }
1204 /*
1205 * Some conditions may have been detected prior to starting the halt
1206 * function; map them to the correct cc.
1207 * Note that we map both -ENODEV and -EACCES to cc 3 (there's not really
1208 * anything else we can do.)
1209 */
1210 switch (ret) {
1211 case -EBUSY:
1212 return IOINST_CC_BUSY;
1213 case -ENODEV:
1214 case -EACCES:
1215 return IOINST_CC_NOT_OPERATIONAL;
1216 default:
1217 return IOINST_CC_EXPECTED;
1218 }
1219 }
1220
1221 static IOInstEnding sch_handle_clear_func_passthrough(SubchDev *sch)
1222 {
1223 int ret;
1224
1225 ret = s390_ccw_clear(sch);
1226 if (ret == -ENOSYS) {
1227 sch_handle_clear_func(sch);
1228 return IOINST_CC_EXPECTED;
1229 }
1230 /*
1231 * Some conditions may have been detected prior to starting the clear
1232 * function; map them to the correct cc.
1233 * Note that we map both -ENODEV and -EACCES to cc 3 (there's not really
1234 * anything else we can do.)
1235 */
1236 switch (ret) {
1237 case -ENODEV:
1238 case -EACCES:
1239 return IOINST_CC_NOT_OPERATIONAL;
1240 default:
1241 return IOINST_CC_EXPECTED;
1242 }
1243 }
1244
1245 static IOInstEnding sch_handle_start_func_passthrough(SubchDev *sch)
1246 {
1247 SCHIB *schib = &sch->curr_status;
1248 ORB *orb = &sch->orb;
1249 if (!(schib->scsw.ctrl & SCSW_ACTL_SUSP)) {
1250 assert(orb != NULL);
1251 schib->pmcw.intparm = orb->intparm;
1252 }
1253 return s390_ccw_cmd_request(sch);
1254 }
1255
1256 /*
1257 * On real machines, this would run asynchronously to the main vcpus.
1258 * We might want to make some parts of the ssch handling (interpreting
1259 * read/writes) asynchronous later on if we start supporting more than
1260 * our current very simple devices.
1261 */
1262 IOInstEnding do_subchannel_work_virtual(SubchDev *sch)
1263 {
1264 SCHIB *schib = &sch->curr_status;
1265
1266 if (schib->scsw.ctrl & SCSW_FCTL_CLEAR_FUNC) {
1267 sch_handle_clear_func(sch);
1268 } else if (schib->scsw.ctrl & SCSW_FCTL_HALT_FUNC) {
1269 sch_handle_halt_func(sch);
1270 } else if (schib->scsw.ctrl & SCSW_FCTL_START_FUNC) {
1271 /* Triggered by both ssch and rsch. */
1272 sch_handle_start_func_virtual(sch);
1273 }
1274 css_inject_io_interrupt(sch);
1275 /* inst must succeed if this func is called */
1276 return IOINST_CC_EXPECTED;
1277 }
1278
1279 IOInstEnding do_subchannel_work_passthrough(SubchDev *sch)
1280 {
1281 SCHIB *schib = &sch->curr_status;
1282
1283 if (schib->scsw.ctrl & SCSW_FCTL_CLEAR_FUNC) {
1284 return sch_handle_clear_func_passthrough(sch);
1285 } else if (schib->scsw.ctrl & SCSW_FCTL_HALT_FUNC) {
1286 return sch_handle_halt_func_passthrough(sch);
1287 } else if (schib->scsw.ctrl & SCSW_FCTL_START_FUNC) {
1288 return sch_handle_start_func_passthrough(sch);
1289 }
1290 return IOINST_CC_EXPECTED;
1291 }
1292
1293 static IOInstEnding do_subchannel_work(SubchDev *sch)
1294 {
1295 if (!sch->do_subchannel_work) {
1296 return IOINST_CC_STATUS_PRESENT;
1297 }
1298 g_assert(sch->curr_status.scsw.ctrl & SCSW_CTRL_MASK_FCTL);
1299 return sch->do_subchannel_work(sch);
1300 }
1301
1302 static void copy_pmcw_to_guest(PMCW *dest, const PMCW *src)
1303 {
1304 int i;
1305
1306 dest->intparm = cpu_to_be32(src->intparm);
1307 dest->flags = cpu_to_be16(src->flags);
1308 dest->devno = cpu_to_be16(src->devno);
1309 dest->lpm = src->lpm;
1310 dest->pnom = src->pnom;
1311 dest->lpum = src->lpum;
1312 dest->pim = src->pim;
1313 dest->mbi = cpu_to_be16(src->mbi);
1314 dest->pom = src->pom;
1315 dest->pam = src->pam;
1316 for (i = 0; i < ARRAY_SIZE(dest->chpid); i++) {
1317 dest->chpid[i] = src->chpid[i];
1318 }
1319 dest->chars = cpu_to_be32(src->chars);
1320 }
1321
1322 void copy_scsw_to_guest(SCSW *dest, const SCSW *src)
1323 {
1324 dest->flags = cpu_to_be16(src->flags);
1325 dest->ctrl = cpu_to_be16(src->ctrl);
1326 dest->cpa = cpu_to_be32(src->cpa);
1327 dest->dstat = src->dstat;
1328 dest->cstat = src->cstat;
1329 dest->count = cpu_to_be16(src->count);
1330 }
1331
1332 static void copy_schib_to_guest(SCHIB *dest, const SCHIB *src)
1333 {
1334 int i;
1335 /*
1336 * We copy the PMCW and SCSW in and out of local variables to
1337 * avoid taking the address of members of a packed struct.
1338 */
1339 PMCW src_pmcw, dest_pmcw;
1340 SCSW src_scsw, dest_scsw;
1341
1342 src_pmcw = src->pmcw;
1343 copy_pmcw_to_guest(&dest_pmcw, &src_pmcw);
1344 dest->pmcw = dest_pmcw;
1345 src_scsw = src->scsw;
1346 copy_scsw_to_guest(&dest_scsw, &src_scsw);
1347 dest->scsw = dest_scsw;
1348 dest->mba = cpu_to_be64(src->mba);
1349 for (i = 0; i < ARRAY_SIZE(dest->mda); i++) {
1350 dest->mda[i] = src->mda[i];
1351 }
1352 }
1353
1354 void copy_esw_to_guest(ESW *dest, const ESW *src)
1355 {
1356 dest->word0 = cpu_to_be32(src->word0);
1357 dest->erw = cpu_to_be32(src->erw);
1358 dest->word2 = cpu_to_be64(src->word2);
1359 dest->word4 = cpu_to_be32(src->word4);
1360 }
1361
1362 IOInstEnding css_do_stsch(SubchDev *sch, SCHIB *schib)
1363 {
1364 int ret;
1365
1366 /*
1367 * For some subchannels, we may want to update parts of
1368 * the schib (e.g., update path masks from the host device
1369 * for passthrough subchannels).
1370 */
1371 ret = s390_ccw_store(sch);
1372
1373 /* Use current status. */
1374 copy_schib_to_guest(schib, &sch->curr_status);
1375 return ret;
1376 }
1377
1378 static void copy_pmcw_from_guest(PMCW *dest, const PMCW *src)
1379 {
1380 int i;
1381
1382 dest->intparm = be32_to_cpu(src->intparm);
1383 dest->flags = be16_to_cpu(src->flags);
1384 dest->devno = be16_to_cpu(src->devno);
1385 dest->lpm = src->lpm;
1386 dest->pnom = src->pnom;
1387 dest->lpum = src->lpum;
1388 dest->pim = src->pim;
1389 dest->mbi = be16_to_cpu(src->mbi);
1390 dest->pom = src->pom;
1391 dest->pam = src->pam;
1392 for (i = 0; i < ARRAY_SIZE(dest->chpid); i++) {
1393 dest->chpid[i] = src->chpid[i];
1394 }
1395 dest->chars = be32_to_cpu(src->chars);
1396 }
1397
1398 static void copy_scsw_from_guest(SCSW *dest, const SCSW *src)
1399 {
1400 dest->flags = be16_to_cpu(src->flags);
1401 dest->ctrl = be16_to_cpu(src->ctrl);
1402 dest->cpa = be32_to_cpu(src->cpa);
1403 dest->dstat = src->dstat;
1404 dest->cstat = src->cstat;
1405 dest->count = be16_to_cpu(src->count);
1406 }
1407
1408 static void copy_schib_from_guest(SCHIB *dest, const SCHIB *src)
1409 {
1410 int i;
1411 /*
1412 * We copy the PMCW and SCSW in and out of local variables to
1413 * avoid taking the address of members of a packed struct.
1414 */
1415 PMCW src_pmcw, dest_pmcw;
1416 SCSW src_scsw, dest_scsw;
1417
1418 src_pmcw = src->pmcw;
1419 copy_pmcw_from_guest(&dest_pmcw, &src_pmcw);
1420 dest->pmcw = dest_pmcw;
1421 src_scsw = src->scsw;
1422 copy_scsw_from_guest(&dest_scsw, &src_scsw);
1423 dest->scsw = dest_scsw;
1424 dest->mba = be64_to_cpu(src->mba);
1425 for (i = 0; i < ARRAY_SIZE(dest->mda); i++) {
1426 dest->mda[i] = src->mda[i];
1427 }
1428 }
1429
1430 IOInstEnding css_do_msch(SubchDev *sch, const SCHIB *orig_schib)
1431 {
1432 SCHIB *schib = &sch->curr_status;
1433 uint16_t oldflags;
1434 SCHIB schib_copy;
1435
1436 if (!(schib->pmcw.flags & PMCW_FLAGS_MASK_DNV)) {
1437 return IOINST_CC_EXPECTED;
1438 }
1439
1440 if (schib->scsw.ctrl & SCSW_STCTL_STATUS_PEND) {
1441 return IOINST_CC_STATUS_PRESENT;
1442 }
1443
1444 if (schib->scsw.ctrl &
1445 (SCSW_FCTL_START_FUNC|SCSW_FCTL_HALT_FUNC|SCSW_FCTL_CLEAR_FUNC)) {
1446 return IOINST_CC_BUSY;
1447 }
1448
1449 copy_schib_from_guest(&schib_copy, orig_schib);
1450 /* Only update the program-modifiable fields. */
1451 schib->pmcw.intparm = schib_copy.pmcw.intparm;
1452 oldflags = schib->pmcw.flags;
1453 schib->pmcw.flags &= ~(PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA |
1454 PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME |
1455 PMCW_FLAGS_MASK_MP);
1456 schib->pmcw.flags |= schib_copy.pmcw.flags &
1457 (PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA |
1458 PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME |
1459 PMCW_FLAGS_MASK_MP);
1460 schib->pmcw.lpm = schib_copy.pmcw.lpm;
1461 schib->pmcw.mbi = schib_copy.pmcw.mbi;
1462 schib->pmcw.pom = schib_copy.pmcw.pom;
1463 schib->pmcw.chars &= ~(PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_CSENSE);
1464 schib->pmcw.chars |= schib_copy.pmcw.chars &
1465 (PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_CSENSE);
1466 schib->mba = schib_copy.mba;
1467
1468 /* Has the channel been disabled? */
1469 if (sch->disable_cb && (oldflags & PMCW_FLAGS_MASK_ENA) != 0
1470 && (schib->pmcw.flags & PMCW_FLAGS_MASK_ENA) == 0) {
1471 sch->disable_cb(sch);
1472 }
1473 return IOINST_CC_EXPECTED;
1474 }
1475
1476 IOInstEnding css_do_xsch(SubchDev *sch)
1477 {
1478 SCHIB *schib = &sch->curr_status;
1479
1480 if (~(schib->pmcw.flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) {
1481 return IOINST_CC_NOT_OPERATIONAL;
1482 }
1483
1484 if (schib->scsw.ctrl & SCSW_CTRL_MASK_STCTL) {
1485 return IOINST_CC_STATUS_PRESENT;
1486 }
1487
1488 if (!(schib->scsw.ctrl & SCSW_CTRL_MASK_FCTL) ||
1489 ((schib->scsw.ctrl & SCSW_CTRL_MASK_FCTL) != SCSW_FCTL_START_FUNC) ||
1490 (!(schib->scsw.ctrl &
1491 (SCSW_ACTL_RESUME_PEND | SCSW_ACTL_START_PEND | SCSW_ACTL_SUSP))) ||
1492 (schib->scsw.ctrl & SCSW_ACTL_SUBCH_ACTIVE)) {
1493 return IOINST_CC_BUSY;
1494 }
1495
1496 /* Cancel the current operation. */
1497 schib->scsw.ctrl &= ~(SCSW_FCTL_START_FUNC |
1498 SCSW_ACTL_RESUME_PEND |
1499 SCSW_ACTL_START_PEND |
1500 SCSW_ACTL_SUSP);
1501 sch->channel_prog = 0x0;
1502 sch->last_cmd_valid = false;
1503 schib->scsw.dstat = 0;
1504 schib->scsw.cstat = 0;
1505 return IOINST_CC_EXPECTED;
1506 }
1507
1508 IOInstEnding css_do_csch(SubchDev *sch)
1509 {
1510 SCHIB *schib = &sch->curr_status;
1511 uint16_t old_scsw_ctrl;
1512 IOInstEnding ccode;
1513
1514 if (~(schib->pmcw.flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) {
1515 return IOINST_CC_NOT_OPERATIONAL;
1516 }
1517
1518 /*
1519 * Save the current scsw.ctrl in case CSCH fails and we need
1520 * to revert the scsw to the status quo ante.
1521 */
1522 old_scsw_ctrl = schib->scsw.ctrl;
1523
1524 /* Trigger the clear function. */
1525 schib->scsw.ctrl &= ~(SCSW_CTRL_MASK_FCTL | SCSW_CTRL_MASK_ACTL);
1526 schib->scsw.ctrl |= SCSW_FCTL_CLEAR_FUNC | SCSW_ACTL_CLEAR_PEND;
1527
1528 ccode = do_subchannel_work(sch);
1529
1530 if (ccode != IOINST_CC_EXPECTED) {
1531 schib->scsw.ctrl = old_scsw_ctrl;
1532 }
1533
1534 return ccode;
1535 }
1536
1537 IOInstEnding css_do_hsch(SubchDev *sch)
1538 {
1539 SCHIB *schib = &sch->curr_status;
1540 uint16_t old_scsw_ctrl;
1541 IOInstEnding ccode;
1542
1543 if (~(schib->pmcw.flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) {
1544 return IOINST_CC_NOT_OPERATIONAL;
1545 }
1546
1547 if (((schib->scsw.ctrl & SCSW_CTRL_MASK_STCTL) == SCSW_STCTL_STATUS_PEND) ||
1548 (schib->scsw.ctrl & (SCSW_STCTL_PRIMARY |
1549 SCSW_STCTL_SECONDARY |
1550 SCSW_STCTL_ALERT))) {
1551 return IOINST_CC_STATUS_PRESENT;
1552 }
1553
1554 if (schib->scsw.ctrl & (SCSW_FCTL_HALT_FUNC | SCSW_FCTL_CLEAR_FUNC)) {
1555 return IOINST_CC_BUSY;
1556 }
1557
1558 /*
1559 * Save the current scsw.ctrl in case HSCH fails and we need
1560 * to revert the scsw to the status quo ante.
1561 */
1562 old_scsw_ctrl = schib->scsw.ctrl;
1563
1564 /* Trigger the halt function. */
1565 schib->scsw.ctrl |= SCSW_FCTL_HALT_FUNC;
1566 schib->scsw.ctrl &= ~SCSW_FCTL_START_FUNC;
1567 if (((schib->scsw.ctrl & SCSW_CTRL_MASK_ACTL) ==
1568 (SCSW_ACTL_SUBCH_ACTIVE | SCSW_ACTL_DEVICE_ACTIVE)) &&
1569 ((schib->scsw.ctrl & SCSW_CTRL_MASK_STCTL) ==
1570 SCSW_STCTL_INTERMEDIATE)) {
1571 schib->scsw.ctrl &= ~SCSW_STCTL_STATUS_PEND;
1572 }
1573 schib->scsw.ctrl |= SCSW_ACTL_HALT_PEND;
1574
1575 ccode = do_subchannel_work(sch);
1576
1577 if (ccode != IOINST_CC_EXPECTED) {
1578 schib->scsw.ctrl = old_scsw_ctrl;
1579 }
1580
1581 return ccode;
1582 }
1583
1584 static void css_update_chnmon(SubchDev *sch)
1585 {
1586 if (!(sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_MME)) {
1587 /* Not active. */
1588 return;
1589 }
1590 /* The counter is conveniently located at the beginning of the struct. */
1591 if (sch->curr_status.pmcw.chars & PMCW_CHARS_MASK_MBFC) {
1592 /* Format 1, per-subchannel area. */
1593 uint32_t count;
1594
1595 count = address_space_ldl_be(&address_space_memory,
1596 sch->curr_status.mba,
1597 MEMTXATTRS_UNSPECIFIED, NULL);
1598 count++;
1599 address_space_stl_be(&address_space_memory, sch->curr_status.mba, count,
1600 MEMTXATTRS_UNSPECIFIED, NULL);
1601 } else {
1602 /* Format 0, global area. */
1603 uint32_t offset;
1604 uint16_t count;
1605
1606 offset = sch->curr_status.pmcw.mbi << 5;
1607 count = address_space_lduw_be(&address_space_memory,
1608 channel_subsys.chnmon_area + offset,
1609 MEMTXATTRS_UNSPECIFIED, NULL);
1610 count++;
1611 address_space_stw_be(&address_space_memory,
1612 channel_subsys.chnmon_area + offset, count,
1613 MEMTXATTRS_UNSPECIFIED, NULL);
1614 }
1615 }
1616
1617 IOInstEnding css_do_ssch(SubchDev *sch, ORB *orb)
1618 {
1619 SCHIB *schib = &sch->curr_status;
1620 uint16_t old_scsw_ctrl, old_scsw_flags;
1621 IOInstEnding ccode;
1622
1623 if (~(schib->pmcw.flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) {
1624 return IOINST_CC_NOT_OPERATIONAL;
1625 }
1626
1627 if (schib->scsw.ctrl & SCSW_STCTL_STATUS_PEND) {
1628 return IOINST_CC_STATUS_PRESENT;
1629 }
1630
1631 if (schib->scsw.ctrl & (SCSW_FCTL_START_FUNC |
1632 SCSW_FCTL_HALT_FUNC |
1633 SCSW_FCTL_CLEAR_FUNC)) {
1634 return IOINST_CC_BUSY;
1635 }
1636
1637 /* If monitoring is active, update counter. */
1638 if (channel_subsys.chnmon_active) {
1639 css_update_chnmon(sch);
1640 }
1641 sch->orb = *orb;
1642 sch->channel_prog = orb->cpa;
1643
1644 /*
1645 * Save the current scsw.ctrl and scsw.flags in case SSCH fails and we need
1646 * to revert the scsw to the status quo ante.
1647 */
1648 old_scsw_ctrl = schib->scsw.ctrl;
1649 old_scsw_flags = schib->scsw.flags;
1650
1651 /* Trigger the start function. */
1652 schib->scsw.ctrl |= (SCSW_FCTL_START_FUNC | SCSW_ACTL_START_PEND);
1653 schib->scsw.flags &= ~SCSW_FLAGS_MASK_PNO;
1654
1655 ccode = do_subchannel_work(sch);
1656
1657 if (ccode != IOINST_CC_EXPECTED) {
1658 schib->scsw.ctrl = old_scsw_ctrl;
1659 schib->scsw.flags = old_scsw_flags;
1660 }
1661
1662 return ccode;
1663 }
1664
1665 static void copy_irb_to_guest(IRB *dest, const IRB *src, const PMCW *pmcw,
1666 int *irb_len)
1667 {
1668 int i;
1669 uint16_t stctl = src->scsw.ctrl & SCSW_CTRL_MASK_STCTL;
1670 uint16_t actl = src->scsw.ctrl & SCSW_CTRL_MASK_ACTL;
1671
1672 copy_scsw_to_guest(&dest->scsw, &src->scsw);
1673
1674 copy_esw_to_guest(&dest->esw, &src->esw);
1675
1676 for (i = 0; i < ARRAY_SIZE(dest->ecw); i++) {
1677 dest->ecw[i] = cpu_to_be32(src->ecw[i]);
1678 }
1679 *irb_len = sizeof(*dest) - sizeof(dest->emw);
1680
1681 /* extended measurements enabled? */
1682 if ((src->scsw.flags & SCSW_FLAGS_MASK_ESWF) ||
1683 !(pmcw->flags & PMCW_FLAGS_MASK_TF) ||
1684 !(pmcw->chars & PMCW_CHARS_MASK_XMWME)) {
1685 return;
1686 }
1687 /* extended measurements pending? */
1688 if (!(stctl & SCSW_STCTL_STATUS_PEND)) {
1689 return;
1690 }
1691 if ((stctl & SCSW_STCTL_PRIMARY) ||
1692 (stctl == SCSW_STCTL_SECONDARY) ||
1693 ((stctl & SCSW_STCTL_INTERMEDIATE) && (actl & SCSW_ACTL_SUSP))) {
1694 for (i = 0; i < ARRAY_SIZE(dest->emw); i++) {
1695 dest->emw[i] = cpu_to_be32(src->emw[i]);
1696 }
1697 }
1698 *irb_len = sizeof(*dest);
1699 }
1700
1701 static void build_irb_sense_data(SubchDev *sch, IRB *irb)
1702 {
1703 int i;
1704
1705 /* Attention: sense_data is already BE! */
1706 memcpy(irb->ecw, sch->sense_data, sizeof(sch->sense_data));
1707 for (i = 0; i < ARRAY_SIZE(irb->ecw); i++) {
1708 irb->ecw[i] = be32_to_cpu(irb->ecw[i]);
1709 }
1710 }
1711
1712 void build_irb_passthrough(SubchDev *sch, IRB *irb)
1713 {
1714 /* Copy ESW from hardware */
1715 irb->esw = sch->esw;
1716
1717 /*
1718 * If (irb->esw.erw & ESW_ERW_SENSE) is true, then the contents
1719 * of the ECW is sense data. If false, then it is model-dependent
1720 * information. Either way, copy it into the IRB for the guest to
1721 * read/decide what to do with.
1722 */
1723 build_irb_sense_data(sch, irb);
1724 }
1725
1726 void build_irb_virtual(SubchDev *sch, IRB *irb)
1727 {
1728 SCHIB *schib = &sch->curr_status;
1729 uint16_t stctl = schib->scsw.ctrl & SCSW_CTRL_MASK_STCTL;
1730
1731 if (stctl & SCSW_STCTL_STATUS_PEND) {
1732 if (schib->scsw.cstat & (SCSW_CSTAT_DATA_CHECK |
1733 SCSW_CSTAT_CHN_CTRL_CHK |
1734 SCSW_CSTAT_INTF_CTRL_CHK)) {
1735 irb->scsw.flags |= SCSW_FLAGS_MASK_ESWF;
1736 irb->esw.word0 = 0x04804000;
1737 } else {
1738 irb->esw.word0 = 0x00800000;
1739 }
1740 /* If a unit check is pending, copy sense data. */
1741 if ((schib->scsw.dstat & SCSW_DSTAT_UNIT_CHECK) &&
1742 (schib->pmcw.chars & PMCW_CHARS_MASK_CSENSE)) {
1743 irb->scsw.flags |= SCSW_FLAGS_MASK_ESWF | SCSW_FLAGS_MASK_ECTL;
1744 build_irb_sense_data(sch, irb);
1745 irb->esw.erw = ESW_ERW_SENSE | (sizeof(sch->sense_data) << 8);
1746 }
1747 }
1748 }
1749
1750 int css_do_tsch_get_irb(SubchDev *sch, IRB *target_irb, int *irb_len)
1751 {
1752 SCHIB *schib = &sch->curr_status;
1753 PMCW p;
1754 uint16_t stctl;
1755 IRB irb;
1756
1757 if (~(schib->pmcw.flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) {
1758 return 3;
1759 }
1760
1761 stctl = schib->scsw.ctrl & SCSW_CTRL_MASK_STCTL;
1762
1763 /* Prepare the irb for the guest. */
1764 memset(&irb, 0, sizeof(IRB));
1765
1766 /* Copy scsw from current status. */
1767 irb.scsw = schib->scsw;
1768
1769 /* Build other IRB data, if necessary */
1770 if (sch->irb_cb) {
1771 sch->irb_cb(sch, &irb);
1772 }
1773
1774 /* Store the irb to the guest. */
1775 p = schib->pmcw;
1776 copy_irb_to_guest(target_irb, &irb, &p, irb_len);
1777
1778 return ((stctl & SCSW_STCTL_STATUS_PEND) == 0);
1779 }
1780
1781 void css_do_tsch_update_subch(SubchDev *sch)
1782 {
1783 SCHIB *schib = &sch->curr_status;
1784 uint16_t stctl;
1785 uint16_t fctl;
1786 uint16_t actl;
1787
1788 stctl = schib->scsw.ctrl & SCSW_CTRL_MASK_STCTL;
1789 fctl = schib->scsw.ctrl & SCSW_CTRL_MASK_FCTL;
1790 actl = schib->scsw.ctrl & SCSW_CTRL_MASK_ACTL;
1791
1792 /* Clear conditions on subchannel, if applicable. */
1793 if (stctl & SCSW_STCTL_STATUS_PEND) {
1794 schib->scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL;
1795 if ((stctl != (SCSW_STCTL_INTERMEDIATE | SCSW_STCTL_STATUS_PEND)) ||
1796 ((fctl & SCSW_FCTL_HALT_FUNC) &&
1797 (actl & SCSW_ACTL_SUSP))) {
1798 schib->scsw.ctrl &= ~SCSW_CTRL_MASK_FCTL;
1799 }
1800 if (stctl != (SCSW_STCTL_INTERMEDIATE | SCSW_STCTL_STATUS_PEND)) {
1801 schib->scsw.flags &= ~SCSW_FLAGS_MASK_PNO;
1802 schib->scsw.ctrl &= ~(SCSW_ACTL_RESUME_PEND |
1803 SCSW_ACTL_START_PEND |
1804 SCSW_ACTL_HALT_PEND |
1805 SCSW_ACTL_CLEAR_PEND |
1806 SCSW_ACTL_SUSP);
1807 } else {
1808 if ((actl & SCSW_ACTL_SUSP) &&
1809 (fctl & SCSW_FCTL_START_FUNC)) {
1810 schib->scsw.flags &= ~SCSW_FLAGS_MASK_PNO;
1811 if (fctl & SCSW_FCTL_HALT_FUNC) {
1812 schib->scsw.ctrl &= ~(SCSW_ACTL_RESUME_PEND |
1813 SCSW_ACTL_START_PEND |
1814 SCSW_ACTL_HALT_PEND |
1815 SCSW_ACTL_CLEAR_PEND |
1816 SCSW_ACTL_SUSP);
1817 } else {
1818 schib->scsw.ctrl &= ~SCSW_ACTL_RESUME_PEND;
1819 }
1820 }
1821 }
1822 /* Clear pending sense data. */
1823 if (schib->pmcw.chars & PMCW_CHARS_MASK_CSENSE) {
1824 memset(sch->sense_data, 0 , sizeof(sch->sense_data));
1825 }
1826 }
1827 }
1828
1829 static void copy_crw_to_guest(CRW *dest, const CRW *src)
1830 {
1831 dest->flags = cpu_to_be16(src->flags);
1832 dest->rsid = cpu_to_be16(src->rsid);
1833 }
1834
1835 int css_do_stcrw(CRW *crw)
1836 {
1837 CrwContainer *crw_cont;
1838 int ret;
1839
1840 crw_cont = QTAILQ_FIRST(&channel_subsys.pending_crws);
1841 if (crw_cont) {
1842 QTAILQ_REMOVE(&channel_subsys.pending_crws, crw_cont, sibling);
1843 copy_crw_to_guest(crw, &crw_cont->crw);
1844 g_free(crw_cont);
1845 ret = 0;
1846 } else {
1847 /* List was empty, turn crw machine checks on again. */
1848 memset(crw, 0, sizeof(*crw));
1849 channel_subsys.do_crw_mchk = true;
1850 ret = 1;
1851 }
1852
1853 return ret;
1854 }
1855
1856 static void copy_crw_from_guest(CRW *dest, const CRW *src)
1857 {
1858 dest->flags = be16_to_cpu(src->flags);
1859 dest->rsid = be16_to_cpu(src->rsid);
1860 }
1861
1862 void css_undo_stcrw(CRW *crw)
1863 {
1864 CrwContainer *crw_cont;
1865
1866 crw_cont = g_try_new0(CrwContainer, 1);
1867 if (!crw_cont) {
1868 channel_subsys.crws_lost = true;
1869 return;
1870 }
1871 copy_crw_from_guest(&crw_cont->crw, crw);
1872
1873 QTAILQ_INSERT_HEAD(&channel_subsys.pending_crws, crw_cont, sibling);
1874 }
1875
1876 int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid,
1877 int rfmt, void *buf)
1878 {
1879 int i, desc_size;
1880 uint32_t words[8];
1881 uint32_t chpid_type_word;
1882 uint32_t max_chpids, chpid_count = 0;
1883 CssImage *css;
1884
1885 if (!m && !cssid) {
1886 css = channel_subsys.css[channel_subsys.default_cssid];
1887 } else {
1888 css = channel_subsys.css[cssid];
1889 }
1890 if (!css) {
1891 return 0;
1892 }
1893
1894 if (rfmt == 0) {
1895 max_chpids = 256;
1896 } else if (rfmt == 1) {
1897 max_chpids = 127;
1898 } else {
1899 /* Should be rejected by caller */
1900 return 0;
1901 }
1902
1903 desc_size = 0;
1904 for (i = f_chpid; i <= l_chpid; i++) {
1905 if (css->chpids[i].in_use) {
1906 /* Limit number of CHPIDs sent back */
1907 if (chpid_count == max_chpids) {
1908 break;
1909 }
1910
1911 chpid_count++;
1912 chpid_type_word = 0x80000000 | (css->chpids[i].type << 8) | i;
1913 if (rfmt == 0) {
1914 words[0] = cpu_to_be32(chpid_type_word);
1915 words[1] = 0;
1916 memcpy(buf + desc_size, words, 8);
1917 desc_size += 8;
1918 } else if (rfmt == 1) {
1919 words[0] = cpu_to_be32(chpid_type_word);
1920 words[1] = 0;
1921 words[2] = 0;
1922 words[3] = 0;
1923 words[4] = 0;
1924 words[5] = 0;
1925 words[6] = 0;
1926 words[7] = 0;
1927 memcpy(buf + desc_size, words, 32);
1928 desc_size += 32;
1929 }
1930 }
1931 }
1932 return desc_size;
1933 }
1934
1935 void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo)
1936 {
1937 /* dct is currently ignored (not really meaningful for our devices) */
1938 /* TODO: Don't ignore mbk. */
1939 if (update && !channel_subsys.chnmon_active) {
1940 /* Enable measuring. */
1941 channel_subsys.chnmon_area = mbo;
1942 channel_subsys.chnmon_active = true;
1943 }
1944 if (!update && channel_subsys.chnmon_active) {
1945 /* Disable measuring. */
1946 channel_subsys.chnmon_area = 0;
1947 channel_subsys.chnmon_active = false;
1948 }
1949 }
1950
1951 IOInstEnding css_do_rsch(SubchDev *sch)
1952 {
1953 SCHIB *schib = &sch->curr_status;
1954
1955 if (~(schib->pmcw.flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) {
1956 return IOINST_CC_NOT_OPERATIONAL;
1957 }
1958
1959 if (schib->scsw.ctrl & SCSW_STCTL_STATUS_PEND) {
1960 return IOINST_CC_STATUS_PRESENT;
1961 }
1962
1963 if (((schib->scsw.ctrl & SCSW_CTRL_MASK_FCTL) != SCSW_FCTL_START_FUNC) ||
1964 (schib->scsw.ctrl & SCSW_ACTL_RESUME_PEND) ||
1965 (!(schib->scsw.ctrl & SCSW_ACTL_SUSP))) {
1966 return IOINST_CC_BUSY;
1967 }
1968
1969 /* If monitoring is active, update counter. */
1970 if (channel_subsys.chnmon_active) {
1971 css_update_chnmon(sch);
1972 }
1973
1974 schib->scsw.ctrl |= SCSW_ACTL_RESUME_PEND;
1975 return do_subchannel_work(sch);
1976 }
1977
1978 int css_do_rchp(uint8_t cssid, uint8_t chpid)
1979 {
1980 uint8_t real_cssid;
1981
1982 if (cssid > channel_subsys.max_cssid) {
1983 return -EINVAL;
1984 }
1985 if (channel_subsys.max_cssid == 0) {
1986 real_cssid = channel_subsys.default_cssid;
1987 } else {
1988 real_cssid = cssid;
1989 }
1990 if (!channel_subsys.css[real_cssid]) {
1991 return -EINVAL;
1992 }
1993
1994 if (!channel_subsys.css[real_cssid]->chpids[chpid].in_use) {
1995 return -ENODEV;
1996 }
1997
1998 if (!channel_subsys.css[real_cssid]->chpids[chpid].is_virtual) {
1999 fprintf(stderr,
2000 "rchp unsupported for non-virtual chpid %x.%02x!\n",
2001 real_cssid, chpid);
2002 return -ENODEV;
2003 }
2004
2005 /* We don't really use a channel path, so we're done here. */
2006 css_queue_crw(CRW_RSC_CHP, CRW_ERC_INIT, 1,
2007 channel_subsys.max_cssid > 0 ? 1 : 0, chpid);
2008 if (channel_subsys.max_cssid > 0) {
2009 css_queue_crw(CRW_RSC_CHP, CRW_ERC_INIT, 1, 0, real_cssid << 8);
2010 }
2011 return 0;
2012 }
2013
2014 bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid)
2015 {
2016 SubchSet *set;
2017 uint8_t real_cssid;
2018
2019 real_cssid = (!m && (cssid == 0)) ? channel_subsys.default_cssid : cssid;
2020 if (ssid > MAX_SSID ||
2021 !channel_subsys.css[real_cssid] ||
2022 !channel_subsys.css[real_cssid]->sch_set[ssid]) {
2023 return true;
2024 }
2025 set = channel_subsys.css[real_cssid]->sch_set[ssid];
2026 return schid > find_last_bit(set->schids_used, (MAX_SCHID + 1));
2027 }
2028
2029 unsigned int css_find_free_chpid(uint8_t cssid)
2030 {
2031 CssImage *css = channel_subsys.css[cssid];
2032 unsigned int chpid;
2033
2034 if (!css) {
2035 return MAX_CHPID + 1;
2036 }
2037
2038 for (chpid = 0; chpid <= MAX_CHPID; chpid++) {
2039 /* skip reserved chpid */
2040 if (chpid == VIRTIO_CCW_CHPID) {
2041 continue;
2042 }
2043 if (!css->chpids[chpid].in_use) {
2044 return chpid;
2045 }
2046 }
2047 return MAX_CHPID + 1;
2048 }
2049
2050 static int css_add_chpid(uint8_t cssid, uint8_t chpid, uint8_t type,
2051 bool is_virt)
2052 {
2053 CssImage *css;
2054
2055 trace_css_chpid_add(cssid, chpid, type);
2056 css = channel_subsys.css[cssid];
2057 if (!css) {
2058 return -EINVAL;
2059 }
2060 if (css->chpids[chpid].in_use) {
2061 return -EEXIST;
2062 }
2063 css->chpids[chpid].in_use = 1;
2064 css->chpids[chpid].type = type;
2065 css->chpids[chpid].is_virtual = is_virt;
2066
2067 css_generate_chp_crws(cssid, chpid);
2068
2069 return 0;
2070 }
2071
2072 void css_sch_build_virtual_schib(SubchDev *sch, uint8_t chpid, uint8_t type)
2073 {
2074 SCHIB *schib = &sch->curr_status;
2075 int i;
2076 CssImage *css = channel_subsys.css[sch->cssid];
2077
2078 assert(css != NULL);
2079 memset(&schib->pmcw, 0, sizeof(PMCW));
2080 schib->pmcw.flags |= PMCW_FLAGS_MASK_DNV;
2081 schib->pmcw.devno = sch->devno;
2082 /* single path */
2083 schib->pmcw.pim = 0x80;
2084 schib->pmcw.pom = 0xff;
2085 schib->pmcw.pam = 0x80;
2086 schib->pmcw.chpid[0] = chpid;
2087 if (!css->chpids[chpid].in_use) {
2088 css_add_chpid(sch->cssid, chpid, type, true);
2089 }
2090
2091 memset(&schib->scsw, 0, sizeof(SCSW));
2092 schib->mba = 0;
2093 for (i = 0; i < ARRAY_SIZE(schib->mda); i++) {
2094 schib->mda[i] = 0;
2095 }
2096 }
2097
2098 SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid, uint16_t schid)
2099 {
2100 uint8_t real_cssid;
2101
2102 real_cssid = (!m && (cssid == 0)) ? channel_subsys.default_cssid : cssid;
2103
2104 if (!channel_subsys.css[real_cssid]) {
2105 return NULL;
2106 }
2107
2108 if (!channel_subsys.css[real_cssid]->sch_set[ssid]) {
2109 return NULL;
2110 }
2111
2112 return channel_subsys.css[real_cssid]->sch_set[ssid]->sch[schid];
2113 }
2114
2115 /**
2116 * Return free device number in subchannel set.
2117 *
2118 * Return index of the first free device number in the subchannel set
2119 * identified by @p cssid and @p ssid, beginning the search at @p
2120 * start and wrapping around at MAX_DEVNO. Return a value exceeding
2121 * MAX_SCHID if there are no free device numbers in the subchannel
2122 * set.
2123 */
2124 static uint32_t css_find_free_devno(uint8_t cssid, uint8_t ssid,
2125 uint16_t start)
2126 {
2127 uint32_t round;
2128
2129 for (round = 0; round <= MAX_DEVNO; round++) {
2130 uint16_t devno = (start + round) % MAX_DEVNO;
2131
2132 if (!css_devno_used(cssid, ssid, devno)) {
2133 return devno;
2134 }
2135 }
2136 return MAX_DEVNO + 1;
2137 }
2138
2139 /**
2140 * Return first free subchannel (id) in subchannel set.
2141 *
2142 * Return index of the first free subchannel in the subchannel set
2143 * identified by @p cssid and @p ssid, if there is any. Return a value
2144 * exceeding MAX_SCHID if there are no free subchannels in the
2145 * subchannel set.
2146 */
2147 static uint32_t css_find_free_subch(uint8_t cssid, uint8_t ssid)
2148 {
2149 uint32_t schid;
2150
2151 for (schid = 0; schid <= MAX_SCHID; schid++) {
2152 if (!css_find_subch(1, cssid, ssid, schid)) {
2153 return schid;
2154 }
2155 }
2156 return MAX_SCHID + 1;
2157 }
2158
2159 /**
2160 * Return first free subchannel (id) in subchannel set for a device number
2161 *
2162 * Verify the device number @p devno is not used yet in the subchannel
2163 * set identified by @p cssid and @p ssid. Set @p schid to the index
2164 * of the first free subchannel in the subchannel set, if there is
2165 * any. Return true if everything succeeded and false otherwise.
2166 */
2167 static bool css_find_free_subch_for_devno(uint8_t cssid, uint8_t ssid,
2168 uint16_t devno, uint16_t *schid,
2169 Error **errp)
2170 {
2171 uint32_t free_schid;
2172
2173 assert(schid);
2174 if (css_devno_used(cssid, ssid, devno)) {
2175 error_setg(errp, "Device %x.%x.%04x already exists",
2176 cssid, ssid, devno);
2177 return false;
2178 }
2179 free_schid = css_find_free_subch(cssid, ssid);
2180 if (free_schid > MAX_SCHID) {
2181 error_setg(errp, "No free subchannel found for %x.%x.%04x",
2182 cssid, ssid, devno);
2183 return false;
2184 }
2185 *schid = free_schid;
2186 return true;
2187 }
2188
2189 /**
2190 * Return first free subchannel (id) and device number
2191 *
2192 * Locate the first free subchannel and first free device number in
2193 * any of the subchannel sets of the channel subsystem identified by
2194 * @p cssid. Return false if no free subchannel / device number could
2195 * be found. Otherwise set @p ssid, @p devno and @p schid to identify
2196 * the available subchannel and device number and return true.
2197 *
2198 * May modify @p ssid, @p devno and / or @p schid even if no free
2199 * subchannel / device number could be found.
2200 */
2201 static bool css_find_free_subch_and_devno(uint8_t cssid, uint8_t *ssid,
2202 uint16_t *devno, uint16_t *schid,
2203 Error **errp)
2204 {
2205 uint32_t free_schid, free_devno;
2206
2207 assert(ssid && devno && schid);
2208 for (*ssid = 0; *ssid <= MAX_SSID; (*ssid)++) {
2209 free_schid = css_find_free_subch(cssid, *ssid);
2210 if (free_schid > MAX_SCHID) {
2211 continue;
2212 }
2213 free_devno = css_find_free_devno(cssid, *ssid, free_schid);
2214 if (free_devno > MAX_DEVNO) {
2215 continue;
2216 }
2217 *schid = free_schid;
2218 *devno = free_devno;
2219 return true;
2220 }
2221 error_setg(errp, "Virtual channel subsystem is full!");
2222 return false;
2223 }
2224
2225 bool css_subch_visible(SubchDev *sch)
2226 {
2227 if (sch->ssid > channel_subsys.max_ssid) {
2228 return false;
2229 }
2230
2231 if (sch->cssid != channel_subsys.default_cssid) {
2232 return (channel_subsys.max_cssid > 0);
2233 }
2234
2235 return true;
2236 }
2237
2238 bool css_present(uint8_t cssid)
2239 {
2240 return (channel_subsys.css[cssid] != NULL);
2241 }
2242
2243 bool css_devno_used(uint8_t cssid, uint8_t ssid, uint16_t devno)
2244 {
2245 if (!channel_subsys.css[cssid]) {
2246 return false;
2247 }
2248 if (!channel_subsys.css[cssid]->sch_set[ssid]) {
2249 return false;
2250 }
2251
2252 return !!test_bit(devno,
2253 channel_subsys.css[cssid]->sch_set[ssid]->devnos_used);
2254 }
2255
2256 void css_subch_assign(uint8_t cssid, uint8_t ssid, uint16_t schid,
2257 uint16_t devno, SubchDev *sch)
2258 {
2259 CssImage *css;
2260 SubchSet *s_set;
2261
2262 trace_css_assign_subch(sch ? "assign" : "deassign", cssid, ssid, schid,
2263 devno);
2264 if (!channel_subsys.css[cssid]) {
2265 fprintf(stderr,
2266 "Suspicious call to %s (%x.%x.%04x) for non-existing css!\n",
2267 __func__, cssid, ssid, schid);
2268 return;
2269 }
2270 css = channel_subsys.css[cssid];
2271
2272 if (!css->sch_set[ssid]) {
2273 css->sch_set[ssid] = g_new0(SubchSet, 1);
2274 }
2275 s_set = css->sch_set[ssid];
2276
2277 s_set->sch[schid] = sch;
2278 if (sch) {
2279 set_bit(schid, s_set->schids_used);
2280 set_bit(devno, s_set->devnos_used);
2281 } else {
2282 clear_bit(schid, s_set->schids_used);
2283 clear_bit(devno, s_set->devnos_used);
2284 }
2285 }
2286
2287 void css_crw_add_to_queue(CRW crw)
2288 {
2289 CrwContainer *crw_cont;
2290
2291 trace_css_crw((crw.flags & CRW_FLAGS_MASK_RSC) >> 8,
2292 crw.flags & CRW_FLAGS_MASK_ERC,
2293 crw.rsid,
2294 (crw.flags & CRW_FLAGS_MASK_C) ? "(chained)" : "");
2295
2296 /* TODO: Maybe use a static crw pool? */
2297 crw_cont = g_try_new0(CrwContainer, 1);
2298 if (!crw_cont) {
2299 channel_subsys.crws_lost = true;
2300 return;
2301 }
2302
2303 crw_cont->crw = crw;
2304
2305 QTAILQ_INSERT_TAIL(&channel_subsys.pending_crws, crw_cont, sibling);
2306
2307 if (channel_subsys.do_crw_mchk) {
2308 channel_subsys.do_crw_mchk = false;
2309 /* Inject crw pending machine check. */
2310 s390_crw_mchk();
2311 }
2312 }
2313
2314 void css_queue_crw(uint8_t rsc, uint8_t erc, int solicited,
2315 int chain, uint16_t rsid)
2316 {
2317 CRW crw;
2318
2319 crw.flags = (rsc << 8) | erc;
2320 if (solicited) {
2321 crw.flags |= CRW_FLAGS_MASK_S;
2322 }
2323 if (chain) {
2324 crw.flags |= CRW_FLAGS_MASK_C;
2325 }
2326 crw.rsid = rsid;
2327 if (channel_subsys.crws_lost) {
2328 crw.flags |= CRW_FLAGS_MASK_R;
2329 channel_subsys.crws_lost = false;
2330 }
2331
2332 css_crw_add_to_queue(crw);
2333 }
2334
2335 void css_generate_sch_crws(uint8_t cssid, uint8_t ssid, uint16_t schid,
2336 int hotplugged, int add)
2337 {
2338 uint8_t guest_cssid;
2339 bool chain_crw;
2340
2341 if (add && !hotplugged) {
2342 return;
2343 }
2344 if (channel_subsys.max_cssid == 0) {
2345 /* Default cssid shows up as 0. */
2346 guest_cssid = (cssid == channel_subsys.default_cssid) ? 0 : cssid;
2347 } else {
2348 /* Show real cssid to the guest. */
2349 guest_cssid = cssid;
2350 }
2351 /*
2352 * Only notify for higher subchannel sets/channel subsystems if the
2353 * guest has enabled it.
2354 */
2355 if ((ssid > channel_subsys.max_ssid) ||
2356 (guest_cssid > channel_subsys.max_cssid) ||
2357 ((channel_subsys.max_cssid == 0) &&
2358 (cssid != channel_subsys.default_cssid))) {
2359 return;
2360 }
2361 chain_crw = (channel_subsys.max_ssid > 0) ||
2362 (channel_subsys.max_cssid > 0);
2363 css_queue_crw(CRW_RSC_SUBCH, CRW_ERC_IPI, 0, chain_crw ? 1 : 0, schid);
2364 if (chain_crw) {
2365 css_queue_crw(CRW_RSC_SUBCH, CRW_ERC_IPI, 0, 0,
2366 (guest_cssid << 8) | (ssid << 4));
2367 }
2368 /* RW_ERC_IPI --> clear pending interrupts */
2369 css_clear_io_interrupt(css_do_build_subchannel_id(cssid, ssid), schid);
2370 }
2371
2372 void css_generate_chp_crws(uint8_t cssid, uint8_t chpid)
2373 {
2374 /* TODO */
2375 }
2376
2377 void css_generate_css_crws(uint8_t cssid)
2378 {
2379 if (!channel_subsys.sei_pending) {
2380 css_queue_crw(CRW_RSC_CSS, CRW_ERC_EVENT, 0, 0, cssid);
2381 }
2382 channel_subsys.sei_pending = true;
2383 }
2384
2385 void css_clear_sei_pending(void)
2386 {
2387 channel_subsys.sei_pending = false;
2388 }
2389
2390 int css_enable_mcsse(void)
2391 {
2392 trace_css_enable_facility("mcsse");
2393 channel_subsys.max_cssid = MAX_CSSID;
2394 return 0;
2395 }
2396
2397 int css_enable_mss(void)
2398 {
2399 trace_css_enable_facility("mss");
2400 channel_subsys.max_ssid = MAX_SSID;
2401 return 0;
2402 }
2403
2404 void css_reset_sch(SubchDev *sch)
2405 {
2406 SCHIB *schib = &sch->curr_status;
2407
2408 if ((schib->pmcw.flags & PMCW_FLAGS_MASK_ENA) != 0 && sch->disable_cb) {
2409 sch->disable_cb(sch);
2410 }
2411
2412 schib->pmcw.intparm = 0;
2413 schib->pmcw.flags &= ~(PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA |
2414 PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME |
2415 PMCW_FLAGS_MASK_MP | PMCW_FLAGS_MASK_TF);
2416 schib->pmcw.flags |= PMCW_FLAGS_MASK_DNV;
2417 schib->pmcw.devno = sch->devno;
2418 schib->pmcw.pim = 0x80;
2419 schib->pmcw.lpm = schib->pmcw.pim;
2420 schib->pmcw.pnom = 0;
2421 schib->pmcw.lpum = 0;
2422 schib->pmcw.mbi = 0;
2423 schib->pmcw.pom = 0xff;
2424 schib->pmcw.pam = 0x80;
2425 schib->pmcw.chars &= ~(PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_XMWME |
2426 PMCW_CHARS_MASK_CSENSE);
2427
2428 memset(&schib->scsw, 0, sizeof(schib->scsw));
2429 schib->mba = 0;
2430
2431 sch->channel_prog = 0x0;
2432 sch->last_cmd_valid = false;
2433 sch->thinint_active = false;
2434 }
2435
2436 void css_reset(void)
2437 {
2438 CrwContainer *crw_cont;
2439
2440 /* Clean up monitoring. */
2441 channel_subsys.chnmon_active = false;
2442 channel_subsys.chnmon_area = 0;
2443
2444 /* Clear pending CRWs. */
2445 while ((crw_cont = QTAILQ_FIRST(&channel_subsys.pending_crws))) {
2446 QTAILQ_REMOVE(&channel_subsys.pending_crws, crw_cont, sibling);
2447 g_free(crw_cont);
2448 }
2449 channel_subsys.sei_pending = false;
2450 channel_subsys.do_crw_mchk = true;
2451 channel_subsys.crws_lost = false;
2452
2453 /* Reset maximum ids. */
2454 channel_subsys.max_cssid = 0;
2455 channel_subsys.max_ssid = 0;
2456 }
2457
2458 static void get_css_devid(Object *obj, Visitor *v, const char *name,
2459 void *opaque, Error **errp)
2460 {
2461 const Property *prop = opaque;
2462 CssDevId *dev_id = object_field_prop_ptr(obj, prop);
2463 char buffer[] = "xx.x.xxxx";
2464 char *p = buffer;
2465 int r;
2466
2467 if (dev_id->valid) {
2468
2469 r = snprintf(buffer, sizeof(buffer), "%02x.%1x.%04x", dev_id->cssid,
2470 dev_id->ssid, dev_id->devid);
2471 assert(r == sizeof(buffer) - 1);
2472
2473 /* drop leading zero */
2474 if (dev_id->cssid <= 0xf) {
2475 p++;
2476 }
2477 } else {
2478 snprintf(buffer, sizeof(buffer), "<unset>");
2479 }
2480
2481 visit_type_str(v, name, &p, errp);
2482 }
2483
2484 /*
2485 * parse <cssid>.<ssid>.<devid> and assert valid range for cssid/ssid
2486 */
2487 static void set_css_devid(Object *obj, Visitor *v, const char *name,
2488 void *opaque, Error **errp)
2489 {
2490 const Property *prop = opaque;
2491 CssDevId *dev_id = object_field_prop_ptr(obj, prop);
2492 char *str;
2493 int num, n1, n2;
2494 unsigned int cssid, ssid, devid;
2495
2496 if (!visit_type_str(v, name, &str, errp)) {
2497 return;
2498 }
2499
2500 num = sscanf(str, "%2x.%1x%n.%4x%n", &cssid, &ssid, &n1, &devid, &n2);
2501 if (num != 3 || (n2 - n1) != 5 || strlen(str) != n2) {
2502 error_set_from_qdev_prop_error(errp, EINVAL, obj, name, str);
2503 goto out;
2504 }
2505 if ((cssid > MAX_CSSID) || (ssid > MAX_SSID)) {
2506 error_setg(errp, "Invalid cssid or ssid: cssid %x, ssid %x",
2507 cssid, ssid);
2508 goto out;
2509 }
2510
2511 dev_id->cssid = cssid;
2512 dev_id->ssid = ssid;
2513 dev_id->devid = devid;
2514 dev_id->valid = true;
2515
2516 out:
2517 g_free(str);
2518 }
2519
2520 const PropertyInfo css_devid_propinfo = {
2521 .type = "str",
2522 .description = "Identifier of an I/O device in the channel "
2523 "subsystem, example: fe.1.23ab",
2524 .get = get_css_devid,
2525 .set = set_css_devid,
2526 };
2527
2528 const PropertyInfo css_devid_ro_propinfo = {
2529 .type = "str",
2530 .description = "Read-only identifier of an I/O device in the channel "
2531 "subsystem, example: fe.1.23ab",
2532 .get = get_css_devid,
2533 };
2534
2535 SubchDev *css_create_sch(CssDevId bus_id, Error **errp)
2536 {
2537 uint16_t schid = 0;
2538 SubchDev *sch;
2539
2540 if (bus_id.valid) {
2541 if (!channel_subsys.css[bus_id.cssid]) {
2542 css_create_css_image(bus_id.cssid, false);
2543 }
2544
2545 if (!css_find_free_subch_for_devno(bus_id.cssid, bus_id.ssid,
2546 bus_id.devid, &schid, errp)) {
2547 return NULL;
2548 }
2549 } else {
2550 for (bus_id.cssid = channel_subsys.default_cssid;;) {
2551 if (!channel_subsys.css[bus_id.cssid]) {
2552 css_create_css_image(bus_id.cssid, false);
2553 }
2554
2555 if (css_find_free_subch_and_devno(bus_id.cssid, &bus_id.ssid,
2556 &bus_id.devid, &schid,
2557 NULL)) {
2558 break;
2559 }
2560 bus_id.cssid = (bus_id.cssid + 1) % MAX_CSSID;
2561 if (bus_id.cssid == channel_subsys.default_cssid) {
2562 error_setg(errp, "Virtual channel subsystem is full!");
2563 return NULL;
2564 }
2565 }
2566 }
2567
2568 sch = g_new0(SubchDev, 1);
2569 sch->cssid = bus_id.cssid;
2570 sch->ssid = bus_id.ssid;
2571 sch->devno = bus_id.devid;
2572 sch->schid = schid;
2573 css_subch_assign(sch->cssid, sch->ssid, schid, sch->devno, sch);
2574 return sch;
2575 }
2576
2577 static int css_sch_get_chpids(SubchDev *sch, CssDevId *dev_id)
2578 {
2579 char *fid_path;
2580 FILE *fd;
2581 uint32_t chpid[8];
2582 int i;
2583 SCHIB *schib = &sch->curr_status;
2584
2585 fid_path = g_strdup_printf("/sys/bus/css/devices/%x.%x.%04x/chpids",
2586 dev_id->cssid, dev_id->ssid, dev_id->devid);
2587 fd = fopen(fid_path, "r");
2588 if (fd == NULL) {
2589 error_report("%s: open %s failed", __func__, fid_path);
2590 g_free(fid_path);
2591 return -EINVAL;
2592 }
2593
2594 if (fscanf(fd, "%x %x %x %x %x %x %x %x",
2595 &chpid[0], &chpid[1], &chpid[2], &chpid[3],
2596 &chpid[4], &chpid[5], &chpid[6], &chpid[7]) != 8) {
2597 fclose(fd);
2598 g_free(fid_path);
2599 return -EINVAL;
2600 }
2601
2602 for (i = 0; i < ARRAY_SIZE(schib->pmcw.chpid); i++) {
2603 schib->pmcw.chpid[i] = chpid[i];
2604 }
2605
2606 fclose(fd);
2607 g_free(fid_path);
2608
2609 return 0;
2610 }
2611
2612 static int css_sch_get_path_masks(SubchDev *sch, CssDevId *dev_id)
2613 {
2614 char *fid_path;
2615 FILE *fd;
2616 uint32_t pim, pam, pom;
2617 SCHIB *schib = &sch->curr_status;
2618
2619 fid_path = g_strdup_printf("/sys/bus/css/devices/%x.%x.%04x/pimpampom",
2620 dev_id->cssid, dev_id->ssid, dev_id->devid);
2621 fd = fopen(fid_path, "r");
2622 if (fd == NULL) {
2623 error_report("%s: open %s failed", __func__, fid_path);
2624 g_free(fid_path);
2625 return -EINVAL;
2626 }
2627
2628 if (fscanf(fd, "%x %x %x", &pim, &pam, &pom) != 3) {
2629 fclose(fd);
2630 g_free(fid_path);
2631 return -EINVAL;
2632 }
2633
2634 schib->pmcw.pim = pim;
2635 schib->pmcw.pam = pam;
2636 schib->pmcw.pom = pom;
2637 fclose(fd);
2638 g_free(fid_path);
2639
2640 return 0;
2641 }
2642
2643 static int css_sch_get_chpid_type(uint8_t chpid, uint32_t *type,
2644 CssDevId *dev_id)
2645 {
2646 char *fid_path;
2647 FILE *fd;
2648
2649 fid_path = g_strdup_printf("/sys/devices/css%x/chp0.%02x/type",
2650 dev_id->cssid, chpid);
2651 fd = fopen(fid_path, "r");
2652 if (fd == NULL) {
2653 error_report("%s: open %s failed", __func__, fid_path);
2654 g_free(fid_path);
2655 return -EINVAL;
2656 }
2657
2658 if (fscanf(fd, "%x", type) != 1) {
2659 fclose(fd);
2660 g_free(fid_path);
2661 return -EINVAL;
2662 }
2663
2664 fclose(fd);
2665 g_free(fid_path);
2666
2667 return 0;
2668 }
2669
2670 /*
2671 * We currently retrieve the real device information from sysfs to build the
2672 * guest subchannel information block without considering the migration feature.
2673 * We need to revisit this problem when we want to add migration support.
2674 */
2675 int css_sch_build_schib(SubchDev *sch, CssDevId *dev_id)
2676 {
2677 CssImage *css = channel_subsys.css[sch->cssid];
2678 SCHIB *schib = &sch->curr_status;
2679 uint32_t type;
2680 int i, ret;
2681
2682 assert(css != NULL);
2683 memset(&schib->pmcw, 0, sizeof(PMCW));
2684 schib->pmcw.flags |= PMCW_FLAGS_MASK_DNV;
2685 /* We are dealing with I/O subchannels only. */
2686 schib->pmcw.devno = sch->devno;
2687
2688 /* Grab path mask from sysfs. */
2689 ret = css_sch_get_path_masks(sch, dev_id);
2690 if (ret) {
2691 return ret;
2692 }
2693
2694 /* Grab chpids from sysfs. */
2695 ret = css_sch_get_chpids(sch, dev_id);
2696 if (ret) {
2697 return ret;
2698 }
2699
2700 /* Build chpid type. */
2701 for (i = 0; i < ARRAY_SIZE(schib->pmcw.chpid); i++) {
2702 if (schib->pmcw.chpid[i] && !css->chpids[schib->pmcw.chpid[i]].in_use) {
2703 ret = css_sch_get_chpid_type(schib->pmcw.chpid[i], &type, dev_id);
2704 if (ret) {
2705 return ret;
2706 }
2707 css_add_chpid(sch->cssid, schib->pmcw.chpid[i], type, false);
2708 }
2709 }
2710
2711 memset(&schib->scsw, 0, sizeof(SCSW));
2712 schib->mba = 0;
2713 for (i = 0; i < ARRAY_SIZE(schib->mda); i++) {
2714 schib->mda[i] = 0;
2715 }
2716
2717 return 0;
2718 }