| 1 | /* |
| 2 | * QEMU LSI53C895A SCSI Host Bus Adapter emulation |
| 3 | * |
| 4 | * Copyright (c) 2006 CodeSourcery. |
| 5 | * Written by Paul Brook |
| 6 | * |
| 7 | * This code is licensed under the LGPL. |
| 8 | */ |
| 9 | |
| 10 | /* Note: |
| 11 | * LSI53C810 emulation is incorrect, in the sense that it supports |
| 12 | * features added in later evolutions. This should not be a problem, |
| 13 | * as well-behaved operating systems will not try to use them. |
| 14 | */ |
| 15 | |
| 16 | #include "qemu/osdep.h" |
| 17 | |
| 18 | #include "hw/core/irq.h" |
| 19 | #include "hw/pci/pci_device.h" |
| 20 | #include "hw/scsi/scsi.h" |
| 21 | #include "migration/vmstate.h" |
| 22 | #include "system/dma.h" |
| 23 | #include "qemu/log.h" |
| 24 | #include "qemu/module.h" |
| 25 | #include "trace.h" |
| 26 | #include "qom/object.h" |
| 27 | |
| 28 | static const char *names[] = { |
| 29 | "SCNTL0", "SCNTL1", "SCNTL2", "SCNTL3", "SCID", "SXFER", "SDID", "GPREG", |
| 30 | "SFBR", "SOCL", "SSID", "SBCL", "DSTAT", "SSTAT0", "SSTAT1", "SSTAT2", |
| 31 | "DSA0", "DSA1", "DSA2", "DSA3", "ISTAT", "0x15", "0x16", "0x17", |
| 32 | "CTEST0", "CTEST1", "CTEST2", "CTEST3", "TEMP0", "TEMP1", "TEMP2", "TEMP3", |
| 33 | "DFIFO", "CTEST4", "CTEST5", "CTEST6", "DBC0", "DBC1", "DBC2", "DCMD", |
| 34 | "DNAD0", "DNAD1", "DNAD2", "DNAD3", "DSP0", "DSP1", "DSP2", "DSP3", |
| 35 | "DSPS0", "DSPS1", "DSPS2", "DSPS3", "SCRATCHA0", "SCRATCHA1", "SCRATCHA2", "SCRATCHA3", |
| 36 | "DMODE", "DIEN", "SBR", "DCNTL", "ADDER0", "ADDER1", "ADDER2", "ADDER3", |
| 37 | "SIEN0", "SIEN1", "SIST0", "SIST1", "SLPAR", "0x45", "MACNTL", "GPCNTL", |
| 38 | "STIME0", "STIME1", "RESPID", "0x4b", "STEST0", "STEST1", "STEST2", "STEST3", |
| 39 | "SIDL", "0x51", "0x52", "0x53", "SODL", "0x55", "0x56", "0x57", |
| 40 | "SBDL", "0x59", "0x5a", "0x5b", "SCRATCHB0", "SCRATCHB1", "SCRATCHB2", "SCRATCHB3", |
| 41 | }; |
| 42 | |
| 43 | #define LSI_MAX_DEVS 7 |
| 44 | |
| 45 | #define LSI_SCNTL0_TRG 0x01 |
| 46 | #define LSI_SCNTL0_AAP 0x02 |
| 47 | #define LSI_SCNTL0_EPC 0x08 |
| 48 | #define LSI_SCNTL0_WATN 0x10 |
| 49 | #define LSI_SCNTL0_START 0x20 |
| 50 | |
| 51 | #define LSI_SCNTL1_SST 0x01 |
| 52 | #define LSI_SCNTL1_IARB 0x02 |
| 53 | #define LSI_SCNTL1_AESP 0x04 |
| 54 | #define LSI_SCNTL1_RST 0x08 |
| 55 | #define LSI_SCNTL1_CON 0x10 |
| 56 | #define LSI_SCNTL1_DHP 0x20 |
| 57 | #define LSI_SCNTL1_ADB 0x40 |
| 58 | #define LSI_SCNTL1_EXC 0x80 |
| 59 | |
| 60 | #define LSI_SCNTL2_WSR 0x01 |
| 61 | #define LSI_SCNTL2_VUE0 0x02 |
| 62 | #define LSI_SCNTL2_VUE1 0x04 |
| 63 | #define LSI_SCNTL2_WSS 0x08 |
| 64 | #define LSI_SCNTL2_SLPHBEN 0x10 |
| 65 | #define LSI_SCNTL2_SLPMD 0x20 |
| 66 | #define LSI_SCNTL2_CHM 0x40 |
| 67 | #define LSI_SCNTL2_SDU 0x80 |
| 68 | |
| 69 | #define LSI_ISTAT0_DIP 0x01 |
| 70 | #define LSI_ISTAT0_SIP 0x02 |
| 71 | #define LSI_ISTAT0_INTF 0x04 |
| 72 | #define LSI_ISTAT0_CON 0x08 |
| 73 | #define LSI_ISTAT0_SEM 0x10 |
| 74 | #define LSI_ISTAT0_SIGP 0x20 |
| 75 | #define LSI_ISTAT0_SRST 0x40 |
| 76 | #define LSI_ISTAT0_ABRT 0x80 |
| 77 | |
| 78 | #define LSI_ISTAT1_SI 0x01 |
| 79 | #define LSI_ISTAT1_SRUN 0x02 |
| 80 | #define LSI_ISTAT1_FLSH 0x04 |
| 81 | |
| 82 | #define LSI_SSTAT0_SDP0 0x01 |
| 83 | #define LSI_SSTAT0_RST 0x02 |
| 84 | #define LSI_SSTAT0_WOA 0x04 |
| 85 | #define LSI_SSTAT0_LOA 0x08 |
| 86 | #define LSI_SSTAT0_AIP 0x10 |
| 87 | #define LSI_SSTAT0_OLF 0x20 |
| 88 | #define LSI_SSTAT0_ORF 0x40 |
| 89 | #define LSI_SSTAT0_ILF 0x80 |
| 90 | |
| 91 | #define LSI_SIST0_PAR 0x01 |
| 92 | #define LSI_SIST0_RST 0x02 |
| 93 | #define LSI_SIST0_UDC 0x04 |
| 94 | #define LSI_SIST0_SGE 0x08 |
| 95 | #define LSI_SIST0_RSL 0x10 |
| 96 | #define LSI_SIST0_SEL 0x20 |
| 97 | #define LSI_SIST0_CMP 0x40 |
| 98 | #define LSI_SIST0_MA 0x80 |
| 99 | |
| 100 | #define LSI_SIST1_HTH 0x01 |
| 101 | #define LSI_SIST1_GEN 0x02 |
| 102 | #define LSI_SIST1_STO 0x04 |
| 103 | #define LSI_SIST1_SBMC 0x10 |
| 104 | |
| 105 | #define LSI_SOCL_IO 0x01 |
| 106 | #define LSI_SOCL_CD 0x02 |
| 107 | #define LSI_SOCL_MSG 0x04 |
| 108 | #define LSI_SOCL_ATN 0x08 |
| 109 | #define LSI_SOCL_SEL 0x10 |
| 110 | #define LSI_SOCL_BSY 0x20 |
| 111 | #define LSI_SOCL_ACK 0x40 |
| 112 | #define LSI_SOCL_REQ 0x80 |
| 113 | |
| 114 | #define LSI_DSTAT_IID 0x01 |
| 115 | #define LSI_DSTAT_SIR 0x04 |
| 116 | #define LSI_DSTAT_SSI 0x08 |
| 117 | #define LSI_DSTAT_ABRT 0x10 |
| 118 | #define LSI_DSTAT_BF 0x20 |
| 119 | #define LSI_DSTAT_MDPE 0x40 |
| 120 | #define LSI_DSTAT_DFE 0x80 |
| 121 | |
| 122 | #define LSI_DCNTL_COM 0x01 |
| 123 | #define LSI_DCNTL_IRQD 0x02 |
| 124 | #define LSI_DCNTL_STD 0x04 |
| 125 | #define LSI_DCNTL_IRQM 0x08 |
| 126 | #define LSI_DCNTL_SSM 0x10 |
| 127 | #define LSI_DCNTL_PFEN 0x20 |
| 128 | #define LSI_DCNTL_PFF 0x40 |
| 129 | #define LSI_DCNTL_CLSE 0x80 |
| 130 | |
| 131 | #define LSI_DMODE_MAN 0x01 |
| 132 | #define LSI_DMODE_BOF 0x02 |
| 133 | #define LSI_DMODE_ERMP 0x04 |
| 134 | #define LSI_DMODE_ERL 0x08 |
| 135 | #define LSI_DMODE_DIOM 0x10 |
| 136 | #define LSI_DMODE_SIOM 0x20 |
| 137 | |
| 138 | #define LSI_CTEST2_DACK 0x01 |
| 139 | #define LSI_CTEST2_DREQ 0x02 |
| 140 | #define LSI_CTEST2_TEOP 0x04 |
| 141 | #define LSI_CTEST2_PCICIE 0x08 |
| 142 | #define LSI_CTEST2_CM 0x10 |
| 143 | #define LSI_CTEST2_CIO 0x20 |
| 144 | #define LSI_CTEST2_SIGP 0x40 |
| 145 | #define LSI_CTEST2_DDIR 0x80 |
| 146 | |
| 147 | #define LSI_CTEST5_BL2 0x04 |
| 148 | #define LSI_CTEST5_DDIR 0x08 |
| 149 | #define LSI_CTEST5_MASR 0x10 |
| 150 | #define LSI_CTEST5_DFSN 0x20 |
| 151 | #define LSI_CTEST5_BBCK 0x40 |
| 152 | #define LSI_CTEST5_ADCK 0x80 |
| 153 | |
| 154 | #define LSI_CCNTL0_DILS 0x01 |
| 155 | #define LSI_CCNTL0_DISFC 0x10 |
| 156 | #define LSI_CCNTL0_ENNDJ 0x20 |
| 157 | #define LSI_CCNTL0_PMJCTL 0x40 |
| 158 | #define LSI_CCNTL0_ENPMJ 0x80 |
| 159 | |
| 160 | #define LSI_CCNTL1_EN64DBMV 0x01 |
| 161 | #define LSI_CCNTL1_EN64TIBMV 0x02 |
| 162 | #define LSI_CCNTL1_64TIMOD 0x04 |
| 163 | #define LSI_CCNTL1_DDAC 0x08 |
| 164 | #define LSI_CCNTL1_ZMOD 0x80 |
| 165 | |
| 166 | #define LSI_SBCL_ATN 0x08 |
| 167 | #define LSI_SBCL_BSY 0x20 |
| 168 | #define LSI_SBCL_ACK 0x40 |
| 169 | #define LSI_SBCL_REQ 0x80 |
| 170 | |
| 171 | /* Enable Response to Reselection */ |
| 172 | #define LSI_SCID_RRE 0x60 |
| 173 | |
| 174 | #define LSI_CCNTL1_40BIT (LSI_CCNTL1_EN64TIBMV|LSI_CCNTL1_64TIMOD) |
| 175 | |
| 176 | #define PHASE_DO 0 |
| 177 | #define PHASE_DI 1 |
| 178 | #define PHASE_CMD 2 |
| 179 | #define PHASE_ST 3 |
| 180 | #define PHASE_MO 6 |
| 181 | #define PHASE_MI 7 |
| 182 | #define PHASE_MASK 7 |
| 183 | |
| 184 | /* Maximum length of MSG IN data. */ |
| 185 | #define LSI_MAX_MSGIN_LEN 8 |
| 186 | |
| 187 | /* Flag set if this is a tagged command. */ |
| 188 | #define LSI_TAG_VALID (1 << 16) |
| 189 | |
| 190 | /* Maximum instructions to process. */ |
| 191 | #define LSI_MAX_INSN 500 |
| 192 | |
| 193 | typedef struct lsi_request { |
| 194 | SCSIRequest *req; |
| 195 | uint32_t tag; |
| 196 | uint32_t dma_len; |
| 197 | uint8_t *dma_buf; |
| 198 | uint32_t pending; |
| 199 | int out; |
| 200 | bool orphan; |
| 201 | QTAILQ_ENTRY(lsi_request) next; |
| 202 | } lsi_request; |
| 203 | |
| 204 | enum { |
| 205 | LSI_NOWAIT, /* SCRIPTS are running or stopped */ |
| 206 | LSI_WAIT_RESELECT, /* Wait Reselect instruction has been issued */ |
| 207 | LSI_DMA_SCRIPTS, /* processing DMA from lsi_execute_script */ |
| 208 | LSI_DMA_IN_PROGRESS, /* DMA operation is in progress */ |
| 209 | LSI_WAIT_SCRIPTS, /* SCRIPTS stopped because of instruction count limit */ |
| 210 | }; |
| 211 | |
| 212 | enum { |
| 213 | LSI_MSG_ACTION_COMMAND = 0, |
| 214 | LSI_MSG_ACTION_DISCONNECT = 1, |
| 215 | LSI_MSG_ACTION_DOUT = 2, |
| 216 | LSI_MSG_ACTION_DIN = 3, |
| 217 | }; |
| 218 | |
| 219 | struct LSIState { |
| 220 | /*< private >*/ |
| 221 | PCIDevice parent_obj; |
| 222 | /*< public >*/ |
| 223 | |
| 224 | qemu_irq ext_irq; |
| 225 | MemoryRegion mmio_io; |
| 226 | MemoryRegion ram_io; |
| 227 | MemoryRegion io_io; |
| 228 | AddressSpace pci_io_as; |
| 229 | QEMUTimer *scripts_timer; |
| 230 | |
| 231 | int carry; /* ??? Should this be in a visible register somewhere? */ |
| 232 | int status; |
| 233 | int msg_action; |
| 234 | int msg_len; |
| 235 | uint8_t msg[LSI_MAX_MSGIN_LEN]; |
| 236 | int waiting; |
| 237 | SCSIBus bus; |
| 238 | int current_lun; |
| 239 | /* The tag is a combination of the device ID and the SCSI tag. */ |
| 240 | uint32_t select_tag; |
| 241 | int command_complete; |
| 242 | QTAILQ_HEAD(, lsi_request) queue; |
| 243 | lsi_request *current; |
| 244 | |
| 245 | uint32_t dsa; |
| 246 | uint32_t temp; |
| 247 | uint32_t dnad; |
| 248 | uint32_t dbc; |
| 249 | uint8_t istat0; |
| 250 | uint8_t istat1; |
| 251 | uint8_t dcmd; |
| 252 | uint8_t dstat; |
| 253 | uint8_t dien; |
| 254 | uint8_t sist0; |
| 255 | uint8_t sist1; |
| 256 | uint8_t sien0; |
| 257 | uint8_t sien1; |
| 258 | uint8_t mbox0; |
| 259 | uint8_t mbox1; |
| 260 | uint8_t dfifo; |
| 261 | uint8_t ctest2; |
| 262 | uint8_t ctest3; |
| 263 | uint8_t ctest4; |
| 264 | uint8_t ctest5; |
| 265 | uint8_t ccntl0; |
| 266 | uint8_t ccntl1; |
| 267 | uint32_t dsp; |
| 268 | uint32_t dsps; |
| 269 | uint8_t dmode; |
| 270 | uint8_t dcntl; |
| 271 | uint8_t scntl0; |
| 272 | uint8_t scntl1; |
| 273 | uint8_t scntl2; |
| 274 | uint8_t scntl3; |
| 275 | uint8_t sstat0; |
| 276 | uint8_t sstat1; |
| 277 | uint8_t scid; |
| 278 | uint8_t sxfer; |
| 279 | uint8_t socl; |
| 280 | uint8_t sdid; |
| 281 | uint8_t ssid; |
| 282 | uint8_t sfbr; |
| 283 | uint8_t sbcl; |
| 284 | uint8_t stest1; |
| 285 | uint8_t stest2; |
| 286 | uint8_t stest3; |
| 287 | uint8_t sidl; |
| 288 | uint8_t stime0; |
| 289 | uint8_t respid0; |
| 290 | uint8_t respid1; |
| 291 | uint32_t mmrs; |
| 292 | uint32_t mmws; |
| 293 | uint32_t sfs; |
| 294 | uint32_t drs; |
| 295 | uint32_t sbms; |
| 296 | uint32_t dbms; |
| 297 | uint32_t dnad64; |
| 298 | uint32_t pmjad1; |
| 299 | uint32_t pmjad2; |
| 300 | uint32_t rbc; |
| 301 | uint32_t ua; |
| 302 | uint32_t ia; |
| 303 | uint32_t sbc; |
| 304 | uint32_t csbc; |
| 305 | uint32_t scratch[18]; /* SCRATCHA-SCRATCHR */ |
| 306 | uint8_t sbr; |
| 307 | uint32_t adder; |
| 308 | |
| 309 | uint8_t script_ram[2048 * sizeof(uint32_t)]; |
| 310 | }; |
| 311 | |
| 312 | #define TYPE_LSI53C810 "lsi53c810" |
| 313 | #define TYPE_LSI53C895A "lsi53c895a" |
| 314 | |
| 315 | OBJECT_DECLARE_SIMPLE_TYPE(LSIState, LSI53C895A) |
| 316 | |
| 317 | static const char *scsi_phases[] = { |
| 318 | "DOUT", |
| 319 | "DIN", |
| 320 | "CMD", |
| 321 | "STATUS", |
| 322 | "RSVOUT", |
| 323 | "RSVIN", |
| 324 | "MSGOUT", |
| 325 | "MSGIN" |
| 326 | }; |
| 327 | |
| 328 | static const char *scsi_phase_name(int phase) |
| 329 | { |
| 330 | return scsi_phases[phase & PHASE_MASK]; |
| 331 | } |
| 332 | |
| 333 | static inline int lsi_irq_on_rsl(LSIState *s) |
| 334 | { |
| 335 | return (s->sien0 & LSI_SIST0_RSL) && (s->scid & LSI_SCID_RRE); |
| 336 | } |
| 337 | |
| 338 | static lsi_request *get_pending_req(LSIState *s) |
| 339 | { |
| 340 | lsi_request *p; |
| 341 | |
| 342 | QTAILQ_FOREACH(p, &s->queue, next) { |
| 343 | if (p->pending) { |
| 344 | return p; |
| 345 | } |
| 346 | } |
| 347 | return NULL; |
| 348 | } |
| 349 | |
| 350 | static void lsi_soft_reset(LSIState *s) |
| 351 | { |
| 352 | trace_lsi_reset(); |
| 353 | s->carry = 0; |
| 354 | |
| 355 | s->msg_action = LSI_MSG_ACTION_COMMAND; |
| 356 | s->msg_len = 0; |
| 357 | s->waiting = LSI_NOWAIT; |
| 358 | s->dsa = 0; |
| 359 | s->dnad = 0; |
| 360 | s->dbc = 0; |
| 361 | s->temp = 0; |
| 362 | memset(s->scratch, 0, sizeof(s->scratch)); |
| 363 | s->istat0 = 0; |
| 364 | s->istat1 = 0; |
| 365 | s->dcmd = 0x40; |
| 366 | s->dstat = 0; |
| 367 | s->dien = 0; |
| 368 | s->sist0 = 0; |
| 369 | s->sist1 = 0; |
| 370 | s->sien0 = 0; |
| 371 | s->sien1 = 0; |
| 372 | s->mbox0 = 0; |
| 373 | s->mbox1 = 0; |
| 374 | s->dfifo = 0; |
| 375 | s->ctest2 = LSI_CTEST2_DACK; |
| 376 | s->ctest3 = 0; |
| 377 | s->ctest4 = 0; |
| 378 | s->ctest5 = 0; |
| 379 | s->ccntl0 = 0; |
| 380 | s->ccntl1 = 0; |
| 381 | s->dsp = 0; |
| 382 | s->dsps = 0; |
| 383 | s->dmode = 0; |
| 384 | s->dcntl = 0; |
| 385 | s->scntl0 = 0xc0; |
| 386 | s->scntl1 = 0; |
| 387 | s->scntl2 = 0; |
| 388 | s->scntl3 = 0; |
| 389 | s->sstat0 = 0; |
| 390 | s->sstat1 = 0; |
| 391 | s->scid = 7; |
| 392 | s->sxfer = 0; |
| 393 | s->socl = 0; |
| 394 | s->sdid = 0; |
| 395 | s->ssid = 0; |
| 396 | s->sbcl = 0; |
| 397 | s->stest1 = 0; |
| 398 | s->stest2 = 0; |
| 399 | s->stest3 = 0; |
| 400 | s->sidl = 0; |
| 401 | s->stime0 = 0; |
| 402 | s->respid0 = 0x80; |
| 403 | s->respid1 = 0; |
| 404 | s->mmrs = 0; |
| 405 | s->mmws = 0; |
| 406 | s->sfs = 0; |
| 407 | s->drs = 0; |
| 408 | s->sbms = 0; |
| 409 | s->dbms = 0; |
| 410 | s->dnad64 = 0; |
| 411 | s->pmjad1 = 0; |
| 412 | s->pmjad2 = 0; |
| 413 | s->rbc = 0; |
| 414 | s->ua = 0; |
| 415 | s->ia = 0; |
| 416 | s->sbc = 0; |
| 417 | s->csbc = 0; |
| 418 | s->sbr = 0; |
| 419 | assert(QTAILQ_EMPTY(&s->queue)); |
| 420 | assert(!s->current); |
| 421 | timer_del(s->scripts_timer); |
| 422 | } |
| 423 | |
| 424 | static int lsi_dma_40bit(LSIState *s) |
| 425 | { |
| 426 | if ((s->ccntl1 & LSI_CCNTL1_40BIT) == LSI_CCNTL1_40BIT) |
| 427 | return 1; |
| 428 | return 0; |
| 429 | } |
| 430 | |
| 431 | static int lsi_dma_ti64bit(LSIState *s) |
| 432 | { |
| 433 | if ((s->ccntl1 & LSI_CCNTL1_EN64TIBMV) == LSI_CCNTL1_EN64TIBMV) |
| 434 | return 1; |
| 435 | return 0; |
| 436 | } |
| 437 | |
| 438 | static int lsi_dma_64bit(LSIState *s) |
| 439 | { |
| 440 | if ((s->ccntl1 & LSI_CCNTL1_EN64DBMV) == LSI_CCNTL1_EN64DBMV) |
| 441 | return 1; |
| 442 | return 0; |
| 443 | } |
| 444 | |
| 445 | static uint8_t lsi_reg_readb(LSIState *s, int offset); |
| 446 | static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val); |
| 447 | static void lsi_execute_script(LSIState *s); |
| 448 | static void lsi_reselect(LSIState *s, lsi_request *p); |
| 449 | |
| 450 | static inline void lsi_mem_read(LSIState *s, dma_addr_t addr, |
| 451 | void *buf, dma_addr_t len) |
| 452 | { |
| 453 | if (s->dmode & LSI_DMODE_SIOM) { |
| 454 | address_space_read(&s->pci_io_as, addr, MEMTXATTRS_UNSPECIFIED, |
| 455 | buf, len); |
| 456 | } else { |
| 457 | pci_dma_read(PCI_DEVICE(s), addr, buf, len); |
| 458 | } |
| 459 | } |
| 460 | |
| 461 | static inline void lsi_mem_write(LSIState *s, dma_addr_t addr, |
| 462 | const void *buf, dma_addr_t len) |
| 463 | { |
| 464 | if (s->dmode & LSI_DMODE_DIOM) { |
| 465 | address_space_write(&s->pci_io_as, addr, MEMTXATTRS_UNSPECIFIED, |
| 466 | buf, len); |
| 467 | } else { |
| 468 | pci_dma_write(PCI_DEVICE(s), addr, buf, len); |
| 469 | } |
| 470 | } |
| 471 | |
| 472 | static inline uint32_t read_dword(LSIState *s, uint32_t addr) |
| 473 | { |
| 474 | uint32_t buf; |
| 475 | |
| 476 | pci_dma_read(PCI_DEVICE(s), addr, &buf, 4); |
| 477 | return cpu_to_le32(buf); |
| 478 | } |
| 479 | |
| 480 | static void lsi_stop_script(LSIState *s) |
| 481 | { |
| 482 | s->istat1 &= ~LSI_ISTAT1_SRUN; |
| 483 | } |
| 484 | |
| 485 | static void lsi_set_irq(LSIState *s, int level) |
| 486 | { |
| 487 | PCIDevice *d = PCI_DEVICE(s); |
| 488 | |
| 489 | if (s->ext_irq) { |
| 490 | qemu_set_irq(s->ext_irq, level); |
| 491 | } else { |
| 492 | pci_set_irq(d, level); |
| 493 | } |
| 494 | } |
| 495 | |
| 496 | static void lsi_update_irq(LSIState *s) |
| 497 | { |
| 498 | int level; |
| 499 | static int last_level; |
| 500 | |
| 501 | /* It's unclear whether the DIP/SIP bits should be cleared when the |
| 502 | Interrupt Status Registers are cleared or when istat0 is read. |
| 503 | We currently do the formwer, which seems to work. */ |
| 504 | level = 0; |
| 505 | if (s->dstat) { |
| 506 | if (s->dstat & s->dien) |
| 507 | level = 1; |
| 508 | s->istat0 |= LSI_ISTAT0_DIP; |
| 509 | } else { |
| 510 | s->istat0 &= ~LSI_ISTAT0_DIP; |
| 511 | } |
| 512 | |
| 513 | if (s->sist0 || s->sist1) { |
| 514 | if ((s->sist0 & s->sien0) || (s->sist1 & s->sien1)) |
| 515 | level = 1; |
| 516 | s->istat0 |= LSI_ISTAT0_SIP; |
| 517 | } else { |
| 518 | s->istat0 &= ~LSI_ISTAT0_SIP; |
| 519 | } |
| 520 | if (s->istat0 & LSI_ISTAT0_INTF) |
| 521 | level = 1; |
| 522 | |
| 523 | if (level != last_level) { |
| 524 | trace_lsi_update_irq(level, s->dstat, s->sist1, s->sist0); |
| 525 | last_level = level; |
| 526 | } |
| 527 | lsi_set_irq(s, level); |
| 528 | |
| 529 | if (!s->current && !level && lsi_irq_on_rsl(s) && !(s->scntl1 & LSI_SCNTL1_CON)) { |
| 530 | lsi_request *p; |
| 531 | |
| 532 | trace_lsi_update_irq_disconnected(); |
| 533 | p = get_pending_req(s); |
| 534 | if (p) { |
| 535 | lsi_reselect(s, p); |
| 536 | } |
| 537 | } |
| 538 | } |
| 539 | |
| 540 | /* Stop SCRIPTS execution and raise a SCSI interrupt. */ |
| 541 | static void lsi_script_scsi_interrupt(LSIState *s, int stat0, int stat1) |
| 542 | { |
| 543 | uint32_t mask0; |
| 544 | uint32_t mask1; |
| 545 | |
| 546 | trace_lsi_script_scsi_interrupt(stat1, stat0, s->sist1, s->sist0); |
| 547 | s->sist0 |= stat0; |
| 548 | s->sist1 |= stat1; |
| 549 | /* Stop processor on fatal or unmasked interrupt. As a special hack |
| 550 | we don't stop processing when raising STO. Instead continue |
| 551 | execution and stop at the next insn that accesses the SCSI bus. */ |
| 552 | mask0 = s->sien0 | ~(LSI_SIST0_CMP | LSI_SIST0_SEL | LSI_SIST0_RSL); |
| 553 | mask1 = s->sien1 | ~(LSI_SIST1_GEN | LSI_SIST1_HTH); |
| 554 | mask1 &= ~LSI_SIST1_STO; |
| 555 | if (s->sist0 & mask0 || s->sist1 & mask1) { |
| 556 | lsi_stop_script(s); |
| 557 | } |
| 558 | lsi_update_irq(s); |
| 559 | } |
| 560 | |
| 561 | /* Stop SCRIPTS execution and raise a DMA interrupt. */ |
| 562 | static void lsi_script_dma_interrupt(LSIState *s, int stat) |
| 563 | { |
| 564 | trace_lsi_script_dma_interrupt(stat, s->dstat); |
| 565 | s->dstat |= stat; |
| 566 | lsi_update_irq(s); |
| 567 | lsi_stop_script(s); |
| 568 | } |
| 569 | |
| 570 | static inline void lsi_set_phase(LSIState *s, int phase) |
| 571 | { |
| 572 | s->sbcl &= ~PHASE_MASK; |
| 573 | s->sbcl |= phase | LSI_SBCL_REQ; |
| 574 | s->sstat1 = (s->sstat1 & ~PHASE_MASK) | phase; |
| 575 | } |
| 576 | |
| 577 | static int lsi_bad_phase(LSIState *s, int out, int new_phase) |
| 578 | { |
| 579 | int ret = 0; |
| 580 | /* Trigger a phase mismatch. */ |
| 581 | if (s->ccntl0 & LSI_CCNTL0_ENPMJ) { |
| 582 | if ((s->ccntl0 & LSI_CCNTL0_PMJCTL)) { |
| 583 | s->dsp = out ? s->pmjad1 : s->pmjad2; |
| 584 | } else { |
| 585 | s->dsp = (s->scntl2 & LSI_SCNTL2_WSR ? s->pmjad2 : s->pmjad1); |
| 586 | } |
| 587 | trace_lsi_bad_phase_jump(s->dsp); |
| 588 | } else { |
| 589 | trace_lsi_bad_phase_interrupt(); |
| 590 | lsi_script_scsi_interrupt(s, LSI_SIST0_MA, 0); |
| 591 | lsi_stop_script(s); |
| 592 | ret = 1; |
| 593 | } |
| 594 | lsi_set_phase(s, new_phase); |
| 595 | return ret; |
| 596 | } |
| 597 | |
| 598 | |
| 599 | /* Resume SCRIPTS execution after a DMA operation. */ |
| 600 | static void lsi_resume_script(LSIState *s) |
| 601 | { |
| 602 | if (s->waiting != 2) { |
| 603 | s->waiting = LSI_NOWAIT; |
| 604 | lsi_execute_script(s); |
| 605 | } else { |
| 606 | s->waiting = LSI_NOWAIT; |
| 607 | } |
| 608 | } |
| 609 | |
| 610 | static void lsi_disconnect(LSIState *s) |
| 611 | { |
| 612 | s->scntl1 &= ~LSI_SCNTL1_CON; |
| 613 | s->sstat1 &= ~PHASE_MASK; |
| 614 | s->sbcl = 0; |
| 615 | } |
| 616 | |
| 617 | static void lsi_bad_selection(LSIState *s, uint32_t id) |
| 618 | { |
| 619 | trace_lsi_bad_selection(id); |
| 620 | lsi_script_scsi_interrupt(s, 0, LSI_SIST1_STO); |
| 621 | lsi_disconnect(s); |
| 622 | } |
| 623 | |
| 624 | /* Initiate a SCSI layer data transfer. */ |
| 625 | static void lsi_do_dma(LSIState *s, int out) |
| 626 | { |
| 627 | uint32_t count; |
| 628 | dma_addr_t addr; |
| 629 | SCSIDevice *dev; |
| 630 | SCSIRequest *req; |
| 631 | lsi_request *p; |
| 632 | |
| 633 | if (!s->current || !s->current->dma_len) { |
| 634 | /* Wait until data is available. */ |
| 635 | trace_lsi_do_dma_unavailable(); |
| 636 | return; |
| 637 | } |
| 638 | |
| 639 | p = s->current; |
| 640 | req = scsi_req_ref(s->current->req); |
| 641 | dev = req->dev; |
| 642 | assert(dev); |
| 643 | |
| 644 | count = s->dbc; |
| 645 | if (count > p->dma_len) |
| 646 | count = p->dma_len; |
| 647 | |
| 648 | addr = s->dnad; |
| 649 | /* both 40 and Table Indirect 64-bit DMAs store upper bits in dnad64 */ |
| 650 | if (lsi_dma_40bit(s) || lsi_dma_ti64bit(s)) |
| 651 | addr |= ((uint64_t)s->dnad64 << 32); |
| 652 | else if (s->dbms) |
| 653 | addr |= ((uint64_t)s->dbms << 32); |
| 654 | else if (s->sbms) |
| 655 | addr |= ((uint64_t)s->sbms << 32); |
| 656 | |
| 657 | trace_lsi_do_dma(addr, count); |
| 658 | s->csbc += count; |
| 659 | s->dnad += count; |
| 660 | s->dbc -= count; |
| 661 | if (p->dma_buf == NULL) { |
| 662 | p->dma_buf = scsi_req_get_buf(req); |
| 663 | } |
| 664 | /* ??? Set SFBR to first data byte. */ |
| 665 | if (out) { |
| 666 | lsi_mem_read(s, addr, p->dma_buf, count); |
| 667 | } else { |
| 668 | lsi_mem_write(s, addr, p->dma_buf, count); |
| 669 | } |
| 670 | if (p->orphan) { |
| 671 | scsi_req_unref(req); |
| 672 | return; |
| 673 | } |
| 674 | scsi_req_unref(req); |
| 675 | |
| 676 | p->dma_len -= count; |
| 677 | if (p->dma_len == 0) { |
| 678 | p->dma_buf = NULL; |
| 679 | scsi_req_continue(req); |
| 680 | } else { |
| 681 | p->dma_buf += count; |
| 682 | lsi_resume_script(s); |
| 683 | } |
| 684 | } |
| 685 | |
| 686 | |
| 687 | /* Add a command to the queue. */ |
| 688 | static void lsi_queue_command(LSIState *s) |
| 689 | { |
| 690 | lsi_request *p = s->current; |
| 691 | |
| 692 | trace_lsi_queue_command(p->tag); |
| 693 | assert(s->current != NULL); |
| 694 | assert(s->current->dma_len == 0); |
| 695 | QTAILQ_INSERT_TAIL(&s->queue, s->current, next); |
| 696 | s->current = NULL; |
| 697 | |
| 698 | p->pending = 0; |
| 699 | p->out = (s->sstat1 & PHASE_MASK) == PHASE_DO; |
| 700 | } |
| 701 | |
| 702 | /* Queue a byte for a MSG IN phase. */ |
| 703 | static void lsi_add_msg_byte(LSIState *s, uint8_t data) |
| 704 | { |
| 705 | if (s->msg_len >= LSI_MAX_MSGIN_LEN) { |
| 706 | trace_lsi_add_msg_byte_error(); |
| 707 | } else { |
| 708 | trace_lsi_add_msg_byte(data); |
| 709 | s->msg[s->msg_len++] = data; |
| 710 | } |
| 711 | } |
| 712 | |
| 713 | /* Perform reselection to continue a command. */ |
| 714 | static void lsi_reselect(LSIState *s, lsi_request *p) |
| 715 | { |
| 716 | int id; |
| 717 | |
| 718 | assert(s->current == NULL); |
| 719 | QTAILQ_REMOVE(&s->queue, p, next); |
| 720 | s->current = p; |
| 721 | |
| 722 | id = (p->tag >> 8) & 0xf; |
| 723 | s->ssid = id | 0x80; |
| 724 | /* LSI53C700 Family Compatibility, see LSI53C895A 4-73 */ |
| 725 | if (!(s->dcntl & LSI_DCNTL_COM)) { |
| 726 | s->sfbr = 1 << (id & 0x7); |
| 727 | } |
| 728 | trace_lsi_reselect(id); |
| 729 | s->scntl1 |= LSI_SCNTL1_CON; |
| 730 | lsi_set_phase(s, PHASE_MI); |
| 731 | s->msg_action = p->out ? LSI_MSG_ACTION_DOUT : LSI_MSG_ACTION_DIN; |
| 732 | s->current->dma_len = p->pending; |
| 733 | lsi_add_msg_byte(s, 0x80); |
| 734 | if (s->current->tag & LSI_TAG_VALID) { |
| 735 | lsi_add_msg_byte(s, 0x20); |
| 736 | lsi_add_msg_byte(s, p->tag & 0xff); |
| 737 | } |
| 738 | |
| 739 | if (lsi_irq_on_rsl(s)) { |
| 740 | lsi_script_scsi_interrupt(s, LSI_SIST0_RSL, 0); |
| 741 | } |
| 742 | } |
| 743 | |
| 744 | static lsi_request *lsi_find_by_tag(LSIState *s, uint32_t tag) |
| 745 | { |
| 746 | lsi_request *p; |
| 747 | |
| 748 | QTAILQ_FOREACH(p, &s->queue, next) { |
| 749 | if (p->tag == tag) { |
| 750 | return p; |
| 751 | } |
| 752 | } |
| 753 | |
| 754 | return NULL; |
| 755 | } |
| 756 | |
| 757 | static void lsi_request_orphan(LSIState *s, lsi_request *p) |
| 758 | { |
| 759 | p->orphan = true; |
| 760 | if (p == s->current) { |
| 761 | s->current = NULL; |
| 762 | } else { |
| 763 | QTAILQ_REMOVE(&s->queue, p, next); |
| 764 | } |
| 765 | scsi_req_unref(p->req); |
| 766 | } |
| 767 | |
| 768 | static void lsi_free_request(SCSIBus *bus, void *priv) |
| 769 | { |
| 770 | g_free(priv); |
| 771 | } |
| 772 | |
| 773 | static void lsi_request_cancelled(SCSIRequest *req) |
| 774 | { |
| 775 | LSIState *s = LSI53C895A(req->bus->qbus.parent); |
| 776 | lsi_request *p = req->hba_private; |
| 777 | |
| 778 | lsi_request_orphan(s, p); |
| 779 | } |
| 780 | |
| 781 | /* Record that data is available for a queued command. Returns zero if |
| 782 | the device was reselected, nonzero if the IO is deferred. */ |
| 783 | static int lsi_queue_req(LSIState *s, SCSIRequest *req, uint32_t len) |
| 784 | { |
| 785 | lsi_request *p = req->hba_private; |
| 786 | |
| 787 | if (p->pending) { |
| 788 | trace_lsi_queue_req_error(p); |
| 789 | } |
| 790 | p->pending = len; |
| 791 | /* Reselect if waiting for it, or if reselection triggers an IRQ |
| 792 | and the bus is free. |
| 793 | Since no interrupt stacking is implemented in the emulation, it |
| 794 | is also required that there are no pending interrupts waiting |
| 795 | for service from the device driver. */ |
| 796 | if (s->waiting == LSI_WAIT_RESELECT || |
| 797 | (lsi_irq_on_rsl(s) && !(s->scntl1 & LSI_SCNTL1_CON) && |
| 798 | !(s->istat0 & (LSI_ISTAT0_SIP | LSI_ISTAT0_DIP)))) { |
| 799 | /* Reselect device. */ |
| 800 | lsi_reselect(s, p); |
| 801 | return 0; |
| 802 | } else { |
| 803 | trace_lsi_queue_req(p->tag); |
| 804 | p->pending = len; |
| 805 | return 1; |
| 806 | } |
| 807 | } |
| 808 | |
| 809 | /* Callback to indicate that the SCSI layer has completed a command. */ |
| 810 | static void lsi_command_complete(SCSIRequest *req, size_t resid) |
| 811 | { |
| 812 | LSIState *s = LSI53C895A(req->bus->qbus.parent); |
| 813 | int out, stop = 0; |
| 814 | |
| 815 | out = (s->sstat1 & PHASE_MASK) == PHASE_DO; |
| 816 | trace_lsi_command_complete(req->status); |
| 817 | s->status = req->status; |
| 818 | s->command_complete = 2; |
| 819 | if (s->waiting && s->dbc != 0) { |
| 820 | /* Raise phase mismatch for short transfers. */ |
| 821 | stop = lsi_bad_phase(s, out, PHASE_ST); |
| 822 | if (stop) { |
| 823 | s->waiting = 0; |
| 824 | } |
| 825 | } else { |
| 826 | lsi_set_phase(s, PHASE_ST); |
| 827 | } |
| 828 | |
| 829 | if (req->hba_private == s->current) { |
| 830 | lsi_request_orphan(s, s->current); |
| 831 | } |
| 832 | if (!stop) { |
| 833 | lsi_resume_script(s); |
| 834 | } |
| 835 | } |
| 836 | |
| 837 | /* Callback to indicate that the SCSI layer has completed a transfer. */ |
| 838 | static void lsi_transfer_data(SCSIRequest *req, uint32_t len) |
| 839 | { |
| 840 | LSIState *s = LSI53C895A(req->bus->qbus.parent); |
| 841 | lsi_request *p = req->hba_private; |
| 842 | int out; |
| 843 | |
| 844 | assert(!p->orphan); |
| 845 | if (s->waiting == LSI_WAIT_RESELECT || p != s->current || |
| 846 | (lsi_irq_on_rsl(s) && !(s->scntl1 & LSI_SCNTL1_CON))) { |
| 847 | if (lsi_queue_req(s, req, len)) { |
| 848 | return; |
| 849 | } |
| 850 | } |
| 851 | |
| 852 | out = (s->sstat1 & PHASE_MASK) == PHASE_DO; |
| 853 | |
| 854 | /* host adapter (re)connected */ |
| 855 | trace_lsi_transfer_data(req->tag, len); |
| 856 | s->current->dma_len = len; |
| 857 | s->command_complete = 1; |
| 858 | if (s->waiting) { |
| 859 | if (s->waiting == LSI_WAIT_RESELECT || s->dbc == 0) { |
| 860 | lsi_resume_script(s); |
| 861 | } else { |
| 862 | lsi_do_dma(s, out); |
| 863 | } |
| 864 | } |
| 865 | } |
| 866 | |
| 867 | static void lsi_do_command(LSIState *s) |
| 868 | { |
| 869 | SCSIDevice *dev; |
| 870 | uint8_t buf[16]; |
| 871 | uint32_t id; |
| 872 | int n; |
| 873 | |
| 874 | trace_lsi_do_command(s->dbc); |
| 875 | if (s->dbc > 16) |
| 876 | s->dbc = 16; |
| 877 | pci_dma_read(PCI_DEVICE(s), s->dnad, buf, s->dbc); |
| 878 | s->sfbr = buf[0]; |
| 879 | s->command_complete = 0; |
| 880 | |
| 881 | id = (s->select_tag >> 8) & 0xf; |
| 882 | dev = scsi_device_find(&s->bus, 0, id, s->current_lun); |
| 883 | if (!dev) { |
| 884 | lsi_bad_selection(s, id); |
| 885 | return; |
| 886 | } |
| 887 | |
| 888 | assert(s->current == NULL); |
| 889 | s->current = g_new0(lsi_request, 1); |
| 890 | s->current->tag = s->select_tag; |
| 891 | s->current->req = scsi_req_new(dev, s->current->tag, s->current_lun, buf, |
| 892 | s->dbc, s->current); |
| 893 | |
| 894 | n = scsi_req_enqueue(s->current->req); |
| 895 | if (n) { |
| 896 | if (n > 0) { |
| 897 | lsi_set_phase(s, PHASE_DI); |
| 898 | } else if (n < 0) { |
| 899 | lsi_set_phase(s, PHASE_DO); |
| 900 | } |
| 901 | scsi_req_continue(s->current->req); |
| 902 | } |
| 903 | if (!s->command_complete) { |
| 904 | if (n) { |
| 905 | /* Command did not complete immediately so disconnect. */ |
| 906 | lsi_add_msg_byte(s, 2); /* SAVE DATA POINTER */ |
| 907 | lsi_add_msg_byte(s, 4); /* DISCONNECT */ |
| 908 | /* wait data */ |
| 909 | lsi_set_phase(s, PHASE_MI); |
| 910 | s->msg_action = LSI_MSG_ACTION_DISCONNECT; |
| 911 | lsi_queue_command(s); |
| 912 | } else { |
| 913 | /* wait command complete */ |
| 914 | lsi_set_phase(s, PHASE_DI); |
| 915 | } |
| 916 | } |
| 917 | } |
| 918 | |
| 919 | static void lsi_do_status(LSIState *s) |
| 920 | { |
| 921 | uint8_t status; |
| 922 | trace_lsi_do_status(s->dbc, s->status); |
| 923 | if (s->dbc != 1) { |
| 924 | trace_lsi_do_status_error(); |
| 925 | } |
| 926 | s->dbc = 1; |
| 927 | status = s->status; |
| 928 | s->sfbr = status; |
| 929 | pci_dma_write(PCI_DEVICE(s), s->dnad, &status, 1); |
| 930 | lsi_set_phase(s, PHASE_MI); |
| 931 | s->msg_action = LSI_MSG_ACTION_DISCONNECT; |
| 932 | lsi_add_msg_byte(s, 0); /* COMMAND COMPLETE */ |
| 933 | } |
| 934 | |
| 935 | static void lsi_do_msgin(LSIState *s) |
| 936 | { |
| 937 | uint8_t len; |
| 938 | trace_lsi_do_msgin(s->dbc, s->msg_len); |
| 939 | s->sfbr = s->msg[0]; |
| 940 | len = s->msg_len; |
| 941 | assert(len > 0 && len <= LSI_MAX_MSGIN_LEN); |
| 942 | if (len > s->dbc) |
| 943 | len = s->dbc; |
| 944 | |
| 945 | if (len) { |
| 946 | pci_dma_write(PCI_DEVICE(s), s->dnad, s->msg, len); |
| 947 | /* Linux drivers rely on the last byte being in the SIDL. */ |
| 948 | s->sidl = s->msg[len - 1]; |
| 949 | s->msg_len -= len; |
| 950 | if (s->msg_len) { |
| 951 | memmove(s->msg, s->msg + len, s->msg_len); |
| 952 | } |
| 953 | } |
| 954 | |
| 955 | if (!s->msg_len) { |
| 956 | /* ??? Check if ATN (not yet implemented) is asserted and maybe |
| 957 | switch to PHASE_MO. */ |
| 958 | switch (s->msg_action) { |
| 959 | case LSI_MSG_ACTION_COMMAND: |
| 960 | lsi_set_phase(s, PHASE_CMD); |
| 961 | break; |
| 962 | case LSI_MSG_ACTION_DISCONNECT: |
| 963 | lsi_disconnect(s); |
| 964 | break; |
| 965 | case LSI_MSG_ACTION_DOUT: |
| 966 | lsi_set_phase(s, PHASE_DO); |
| 967 | break; |
| 968 | case LSI_MSG_ACTION_DIN: |
| 969 | lsi_set_phase(s, PHASE_DI); |
| 970 | break; |
| 971 | default: |
| 972 | abort(); |
| 973 | } |
| 974 | } |
| 975 | } |
| 976 | |
| 977 | /* Read the next byte during a MSGOUT phase. */ |
| 978 | static uint8_t lsi_get_msgbyte(LSIState *s) |
| 979 | { |
| 980 | uint8_t data; |
| 981 | pci_dma_read(PCI_DEVICE(s), s->dnad, &data, 1); |
| 982 | s->dnad++; |
| 983 | s->dbc--; |
| 984 | return data; |
| 985 | } |
| 986 | |
| 987 | /* Skip the next n bytes during a MSGOUT phase. */ |
| 988 | static void lsi_skip_msgbytes(LSIState *s, unsigned int n) |
| 989 | { |
| 990 | s->dnad += n; |
| 991 | s->dbc -= n; |
| 992 | } |
| 993 | |
| 994 | static void lsi_do_msgout(LSIState *s) |
| 995 | { |
| 996 | uint8_t msg; |
| 997 | int len; |
| 998 | uint32_t current_tag; |
| 999 | lsi_request *current_req, *p, *p_next; |
| 1000 | |
| 1001 | if (s->current) { |
| 1002 | current_tag = s->current->tag; |
| 1003 | } else { |
| 1004 | current_tag = s->select_tag; |
| 1005 | } |
| 1006 | |
| 1007 | trace_lsi_do_msgout(s->dbc); |
| 1008 | while (s->dbc) { |
| 1009 | msg = lsi_get_msgbyte(s); |
| 1010 | s->sfbr = msg; |
| 1011 | |
| 1012 | switch (msg) { |
| 1013 | case 0x04: |
| 1014 | trace_lsi_do_msgout_disconnect(); |
| 1015 | lsi_disconnect(s); |
| 1016 | break; |
| 1017 | case 0x08: |
| 1018 | trace_lsi_do_msgout_noop(); |
| 1019 | lsi_set_phase(s, PHASE_CMD); |
| 1020 | break; |
| 1021 | case 0x01: |
| 1022 | len = lsi_get_msgbyte(s); |
| 1023 | msg = lsi_get_msgbyte(s); |
| 1024 | (void)len; /* avoid a warning about unused variable*/ |
| 1025 | trace_lsi_do_msgout_extended(msg, len); |
| 1026 | switch (msg) { |
| 1027 | case 1: |
| 1028 | trace_lsi_do_msgout_ignored("SDTR"); |
| 1029 | lsi_skip_msgbytes(s, 2); |
| 1030 | break; |
| 1031 | case 3: |
| 1032 | trace_lsi_do_msgout_ignored("WDTR"); |
| 1033 | lsi_skip_msgbytes(s, 1); |
| 1034 | break; |
| 1035 | case 4: |
| 1036 | trace_lsi_do_msgout_ignored("PPR"); |
| 1037 | lsi_skip_msgbytes(s, 5); |
| 1038 | break; |
| 1039 | default: |
| 1040 | goto bad; |
| 1041 | } |
| 1042 | break; |
| 1043 | case 0x20: /* SIMPLE queue */ |
| 1044 | s->select_tag &= ~0xff; |
| 1045 | s->select_tag |= lsi_get_msgbyte(s) | LSI_TAG_VALID; |
| 1046 | trace_lsi_do_msgout_simplequeue(s->select_tag & 0xff); |
| 1047 | break; |
| 1048 | case 0x21: /* HEAD of queue */ |
| 1049 | qemu_log_mask(LOG_UNIMP, "lsi_scsi: HEAD queue not implemented\n"); |
| 1050 | s->select_tag &= ~0xff; |
| 1051 | s->select_tag |= lsi_get_msgbyte(s) | LSI_TAG_VALID; |
| 1052 | break; |
| 1053 | case 0x22: /* ORDERED queue */ |
| 1054 | qemu_log_mask(LOG_UNIMP, |
| 1055 | "lsi_scsi: ORDERED queue not implemented\n"); |
| 1056 | s->select_tag &= ~0xff; |
| 1057 | s->select_tag |= lsi_get_msgbyte(s) | LSI_TAG_VALID; |
| 1058 | break; |
| 1059 | case 0x0d: |
| 1060 | /* The ABORT TAG message clears the current I/O process only. */ |
| 1061 | trace_lsi_do_msgout_abort(current_tag); |
| 1062 | if (s->current) { |
| 1063 | current_req = s->current; |
| 1064 | } else { |
| 1065 | current_req = lsi_find_by_tag(s, current_tag); |
| 1066 | } |
| 1067 | if (current_req && current_req->req) { |
| 1068 | scsi_req_cancel(current_req->req); |
| 1069 | } |
| 1070 | lsi_disconnect(s); |
| 1071 | break; |
| 1072 | case 0x06: |
| 1073 | case 0x0e: |
| 1074 | case 0x0c: |
| 1075 | /* The ABORT message clears all I/O processes for the selecting |
| 1076 | initiator on the specified logical unit of the target. */ |
| 1077 | if (msg == 0x06) { |
| 1078 | trace_lsi_do_msgout_abort(current_tag); |
| 1079 | } |
| 1080 | /* The CLEAR QUEUE message clears all I/O processes for all |
| 1081 | initiators on the specified logical unit of the target. */ |
| 1082 | if (msg == 0x0e) { |
| 1083 | trace_lsi_do_msgout_clearqueue(current_tag); |
| 1084 | } |
| 1085 | /* The BUS DEVICE RESET message clears all I/O processes for all |
| 1086 | initiators on all logical units of the target. */ |
| 1087 | if (msg == 0x0c) { |
| 1088 | trace_lsi_do_msgout_busdevicereset(current_tag); |
| 1089 | } |
| 1090 | |
| 1091 | /* clear the current I/O process */ |
| 1092 | if (s->current) { |
| 1093 | scsi_req_cancel(s->current->req); |
| 1094 | } |
| 1095 | |
| 1096 | /* As the current implemented devices scsi_disk and scsi_generic |
| 1097 | only support one LUN, we don't need to keep track of LUNs. |
| 1098 | Clearing I/O processes for other initiators could be possible |
| 1099 | for scsi_generic by sending a SG_SCSI_RESET to the /dev/sgX |
| 1100 | device, but this is currently not implemented (and seems not |
| 1101 | to be really necessary). So let's simply clear all queued |
| 1102 | commands for the current device: */ |
| 1103 | QTAILQ_FOREACH_SAFE(p, &s->queue, next, p_next) { |
| 1104 | if ((p->tag & 0x0000ff00) == (current_tag & 0x0000ff00)) { |
| 1105 | scsi_req_cancel(p->req); |
| 1106 | } |
| 1107 | } |
| 1108 | |
| 1109 | lsi_disconnect(s); |
| 1110 | break; |
| 1111 | default: |
| 1112 | if ((msg & 0x80) == 0) { |
| 1113 | goto bad; |
| 1114 | } |
| 1115 | s->current_lun = msg & 7; |
| 1116 | trace_lsi_do_msgout_select(s->current_lun); |
| 1117 | lsi_set_phase(s, PHASE_CMD); |
| 1118 | break; |
| 1119 | } |
| 1120 | } |
| 1121 | return; |
| 1122 | bad: |
| 1123 | qemu_log_mask(LOG_UNIMP, "Unimplemented message 0x%02x\n", msg); |
| 1124 | lsi_set_phase(s, PHASE_MI); |
| 1125 | lsi_add_msg_byte(s, 7); /* MESSAGE REJECT */ |
| 1126 | s->msg_action = LSI_MSG_ACTION_COMMAND; |
| 1127 | } |
| 1128 | |
| 1129 | #define LSI_BUF_SIZE 4096 |
| 1130 | static void lsi_memcpy(LSIState *s, uint32_t dest, uint32_t src, int count) |
| 1131 | { |
| 1132 | int n; |
| 1133 | QEMU_UNINITIALIZED uint8_t buf[LSI_BUF_SIZE]; |
| 1134 | |
| 1135 | trace_lsi_memcpy(dest, src, count); |
| 1136 | while (count) { |
| 1137 | n = (count > LSI_BUF_SIZE) ? LSI_BUF_SIZE : count; |
| 1138 | lsi_mem_read(s, src, buf, n); |
| 1139 | lsi_mem_write(s, dest, buf, n); |
| 1140 | src += n; |
| 1141 | dest += n; |
| 1142 | count -= n; |
| 1143 | } |
| 1144 | } |
| 1145 | |
| 1146 | static void lsi_wait_reselect(LSIState *s) |
| 1147 | { |
| 1148 | lsi_request *p; |
| 1149 | |
| 1150 | trace_lsi_wait_reselect(); |
| 1151 | |
| 1152 | if (s->current) { |
| 1153 | return; |
| 1154 | } |
| 1155 | p = get_pending_req(s); |
| 1156 | if (p) { |
| 1157 | lsi_reselect(s, p); |
| 1158 | } |
| 1159 | if (s->current == NULL) { |
| 1160 | s->waiting = LSI_WAIT_RESELECT; |
| 1161 | } |
| 1162 | } |
| 1163 | |
| 1164 | static void lsi_scripts_timer_start(LSIState *s) |
| 1165 | { |
| 1166 | trace_lsi_scripts_timer_start(); |
| 1167 | timer_mod(s->scripts_timer, qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) + 500); |
| 1168 | } |
| 1169 | |
| 1170 | static void lsi_execute_script(LSIState *s) |
| 1171 | { |
| 1172 | PCIDevice *pci_dev = PCI_DEVICE(s); |
| 1173 | uint32_t insn; |
| 1174 | uint32_t addr, addr_high; |
| 1175 | int opcode; |
| 1176 | int insn_processed = 0; |
| 1177 | static int reentrancy_level; |
| 1178 | |
| 1179 | if (s->waiting == LSI_WAIT_SCRIPTS) { |
| 1180 | timer_del(s->scripts_timer); |
| 1181 | s->waiting = LSI_NOWAIT; |
| 1182 | } |
| 1183 | |
| 1184 | object_ref(s); |
| 1185 | reentrancy_level++; |
| 1186 | |
| 1187 | s->istat1 |= LSI_ISTAT1_SRUN; |
| 1188 | again: |
| 1189 | /* |
| 1190 | * Some windows drivers make the device spin waiting for a memory location |
| 1191 | * to change. If we have executed more than LSI_MAX_INSN instructions then |
| 1192 | * assume this is the case and start a timer. Until the timer fires, the |
| 1193 | * host CPU has a chance to run and change the memory location. |
| 1194 | * |
| 1195 | * Another issue (CVE-2023-0330) can occur if the script is programmed to |
| 1196 | * trigger itself again and again. Avoid this problem by stopping after |
| 1197 | * being called multiple times in a reentrant way (8 is an arbitrary value |
| 1198 | * which should be enough for all valid use cases). |
| 1199 | */ |
| 1200 | if (++insn_processed > LSI_MAX_INSN || reentrancy_level > 8) { |
| 1201 | s->waiting = LSI_WAIT_SCRIPTS; |
| 1202 | lsi_scripts_timer_start(s); |
| 1203 | reentrancy_level--; |
| 1204 | object_unref(s); |
| 1205 | return; |
| 1206 | } |
| 1207 | insn = read_dword(s, s->dsp); |
| 1208 | if (!insn) { |
| 1209 | /* If we receive an empty opcode increment the DSP by 4 bytes |
| 1210 | instead of 8 and execute the next opcode at that location */ |
| 1211 | s->dsp += 4; |
| 1212 | goto again; |
| 1213 | } |
| 1214 | addr = read_dword(s, s->dsp + 4); |
| 1215 | addr_high = 0; |
| 1216 | trace_lsi_execute_script(s->dsp, insn, addr); |
| 1217 | s->dsps = addr; |
| 1218 | s->dcmd = insn >> 24; |
| 1219 | s->dsp += 8; |
| 1220 | switch (insn >> 30) { |
| 1221 | case 0: /* Block move. */ |
| 1222 | if (s->sist1 & LSI_SIST1_STO) { |
| 1223 | trace_lsi_execute_script_blockmove_delayed(); |
| 1224 | lsi_stop_script(s); |
| 1225 | break; |
| 1226 | } |
| 1227 | s->dbc = insn & 0xffffff; |
| 1228 | s->rbc = s->dbc; |
| 1229 | /* ??? Set ESA. */ |
| 1230 | s->ia = s->dsp - 8; |
| 1231 | if (insn & (1 << 29)) { |
| 1232 | /* Indirect addressing. */ |
| 1233 | addr = read_dword(s, addr); |
| 1234 | } else if (insn & (1 << 28)) { |
| 1235 | uint32_t buf[2]; |
| 1236 | int32_t offset; |
| 1237 | /* Table indirect addressing. */ |
| 1238 | |
| 1239 | /* 32-bit Table indirect */ |
| 1240 | offset = sextract32(addr, 0, 24); |
| 1241 | pci_dma_read(pci_dev, s->dsa + offset, buf, 8); |
| 1242 | /* byte count is stored in bits 0:23 only */ |
| 1243 | s->dbc = cpu_to_le32(buf[0]) & 0xffffff; |
| 1244 | s->rbc = s->dbc; |
| 1245 | addr = cpu_to_le32(buf[1]); |
| 1246 | |
| 1247 | /* 40-bit DMA, upper addr bits [39:32] stored in first DWORD of |
| 1248 | * table, bits [31:24] */ |
| 1249 | if (lsi_dma_40bit(s)) |
| 1250 | addr_high = cpu_to_le32(buf[0]) >> 24; |
| 1251 | else if (lsi_dma_ti64bit(s)) { |
| 1252 | int selector = (cpu_to_le32(buf[0]) >> 24) & 0x1f; |
| 1253 | switch (selector) { |
| 1254 | case 0 ... 0x0f: |
| 1255 | /* offset index into scratch registers since |
| 1256 | * TI64 mode can use registers C to R */ |
| 1257 | addr_high = s->scratch[2 + selector]; |
| 1258 | break; |
| 1259 | case 0x10: |
| 1260 | addr_high = s->mmrs; |
| 1261 | break; |
| 1262 | case 0x11: |
| 1263 | addr_high = s->mmws; |
| 1264 | break; |
| 1265 | case 0x12: |
| 1266 | addr_high = s->sfs; |
| 1267 | break; |
| 1268 | case 0x13: |
| 1269 | addr_high = s->drs; |
| 1270 | break; |
| 1271 | case 0x14: |
| 1272 | addr_high = s->sbms; |
| 1273 | break; |
| 1274 | case 0x15: |
| 1275 | addr_high = s->dbms; |
| 1276 | break; |
| 1277 | default: |
| 1278 | qemu_log_mask(LOG_GUEST_ERROR, |
| 1279 | "lsi_scsi: Illegal selector specified (0x%x > 0x15) " |
| 1280 | "for 64-bit DMA block move", selector); |
| 1281 | break; |
| 1282 | } |
| 1283 | } |
| 1284 | } else if (lsi_dma_64bit(s)) { |
| 1285 | /* fetch a 3rd dword if 64-bit direct move is enabled and |
| 1286 | only if we're not doing table indirect or indirect addressing */ |
| 1287 | s->dbms = read_dword(s, s->dsp); |
| 1288 | s->dsp += 4; |
| 1289 | s->ia = s->dsp - 12; |
| 1290 | } |
| 1291 | if ((s->sstat1 & PHASE_MASK) != ((insn >> 24) & 7)) { |
| 1292 | trace_lsi_execute_script_blockmove_badphase( |
| 1293 | scsi_phase_name(s->sstat1), |
| 1294 | scsi_phase_name(insn >> 24)); |
| 1295 | lsi_script_scsi_interrupt(s, LSI_SIST0_MA, 0); |
| 1296 | break; |
| 1297 | } |
| 1298 | s->dnad = addr; |
| 1299 | s->dnad64 = addr_high; |
| 1300 | switch (s->sstat1 & 0x7) { |
| 1301 | case PHASE_DO: |
| 1302 | s->waiting = LSI_DMA_SCRIPTS; |
| 1303 | lsi_do_dma(s, 1); |
| 1304 | if (s->waiting) |
| 1305 | s->waiting = LSI_DMA_IN_PROGRESS; |
| 1306 | break; |
| 1307 | case PHASE_DI: |
| 1308 | s->waiting = LSI_DMA_SCRIPTS; |
| 1309 | lsi_do_dma(s, 0); |
| 1310 | if (s->waiting) |
| 1311 | s->waiting = LSI_DMA_IN_PROGRESS; |
| 1312 | break; |
| 1313 | case PHASE_CMD: |
| 1314 | lsi_do_command(s); |
| 1315 | break; |
| 1316 | case PHASE_ST: |
| 1317 | lsi_do_status(s); |
| 1318 | break; |
| 1319 | case PHASE_MO: |
| 1320 | lsi_do_msgout(s); |
| 1321 | break; |
| 1322 | case PHASE_MI: |
| 1323 | lsi_do_msgin(s); |
| 1324 | break; |
| 1325 | default: |
| 1326 | qemu_log_mask(LOG_UNIMP, "lsi_scsi: Unimplemented phase %s\n", |
| 1327 | scsi_phase_name(s->sstat1)); |
| 1328 | } |
| 1329 | s->dfifo = s->dbc & 0xff; |
| 1330 | s->ctest5 = (s->ctest5 & 0xfc) | ((s->dbc >> 8) & 3); |
| 1331 | s->sbc = s->dbc; |
| 1332 | s->rbc -= s->dbc; |
| 1333 | s->ua = addr + s->dbc; |
| 1334 | break; |
| 1335 | |
| 1336 | case 1: /* IO or Read/Write instruction. */ |
| 1337 | opcode = (insn >> 27) & 7; |
| 1338 | if (opcode < 5) { |
| 1339 | uint32_t id; |
| 1340 | |
| 1341 | if (insn & (1 << 25)) { |
| 1342 | id = read_dword(s, s->dsa + sextract32(insn, 0, 24)); |
| 1343 | } else { |
| 1344 | id = insn; |
| 1345 | } |
| 1346 | id = (id >> 16) & 0xf; |
| 1347 | if (insn & (1 << 26)) { |
| 1348 | addr = s->dsp + sextract32(addr, 0, 24); |
| 1349 | } |
| 1350 | s->dnad = addr; |
| 1351 | switch (opcode) { |
| 1352 | case 0: /* Select */ |
| 1353 | s->sdid = id; |
| 1354 | if (s->scntl1 & LSI_SCNTL1_CON) { |
| 1355 | trace_lsi_execute_script_io_alreadyreselected(); |
| 1356 | s->dsp = s->dnad; |
| 1357 | break; |
| 1358 | } |
| 1359 | s->sstat0 |= LSI_SSTAT0_WOA; |
| 1360 | s->scntl1 &= ~LSI_SCNTL1_IARB; |
| 1361 | if (!scsi_device_find(&s->bus, 0, id, 0)) { |
| 1362 | lsi_bad_selection(s, id); |
| 1363 | break; |
| 1364 | } |
| 1365 | trace_lsi_execute_script_io_selected(id, |
| 1366 | insn & (1 << 3) ? " ATN" : ""); |
| 1367 | /* ??? Linux drivers complain when this is set. Maybe |
| 1368 | it only applies in low-level mode (unimplemented). |
| 1369 | lsi_script_scsi_interrupt(s, LSI_SIST0_CMP, 0); */ |
| 1370 | s->select_tag = id << 8; |
| 1371 | s->scntl1 |= LSI_SCNTL1_CON; |
| 1372 | if (insn & (1 << 3)) { |
| 1373 | s->socl |= LSI_SOCL_ATN; |
| 1374 | s->sbcl |= LSI_SBCL_ATN; |
| 1375 | } |
| 1376 | s->sbcl |= LSI_SBCL_BSY; |
| 1377 | lsi_set_phase(s, PHASE_MO); |
| 1378 | s->waiting = LSI_NOWAIT; |
| 1379 | break; |
| 1380 | case 1: /* Disconnect */ |
| 1381 | trace_lsi_execute_script_io_disconnect(); |
| 1382 | s->scntl1 &= ~LSI_SCNTL1_CON; |
| 1383 | /* FIXME: this is not entirely correct; the target need not ask |
| 1384 | * for reselection until it has to send data, while here we force a |
| 1385 | * reselection as soon as the bus is free. The correct flow would |
| 1386 | * reselect before lsi_transfer_data and disconnect as soon as |
| 1387 | * DMA ends. |
| 1388 | */ |
| 1389 | if (!s->current) { |
| 1390 | lsi_request *p = get_pending_req(s); |
| 1391 | if (p) { |
| 1392 | lsi_reselect(s, p); |
| 1393 | } |
| 1394 | } |
| 1395 | break; |
| 1396 | case 2: /* Wait Reselect */ |
| 1397 | if (s->istat0 & LSI_ISTAT0_SIGP) { |
| 1398 | s->dsp = s->dnad; |
| 1399 | } else if (!lsi_irq_on_rsl(s)) { |
| 1400 | lsi_wait_reselect(s); |
| 1401 | } |
| 1402 | break; |
| 1403 | case 3: /* Set */ |
| 1404 | trace_lsi_execute_script_io_set( |
| 1405 | insn & (1 << 3) ? " ATN" : "", |
| 1406 | insn & (1 << 6) ? " ACK" : "", |
| 1407 | insn & (1 << 9) ? " TM" : "", |
| 1408 | insn & (1 << 10) ? " CC" : ""); |
| 1409 | if (insn & (1 << 3)) { |
| 1410 | s->socl |= LSI_SOCL_ATN; |
| 1411 | s->sbcl |= LSI_SBCL_ATN; |
| 1412 | lsi_set_phase(s, PHASE_MO); |
| 1413 | } |
| 1414 | |
| 1415 | if (insn & (1 << 6)) { |
| 1416 | s->sbcl |= LSI_SBCL_ACK; |
| 1417 | } |
| 1418 | |
| 1419 | if (insn & (1 << 9)) { |
| 1420 | qemu_log_mask(LOG_UNIMP, |
| 1421 | "lsi_scsi: Target mode not implemented\n"); |
| 1422 | } |
| 1423 | if (insn & (1 << 10)) |
| 1424 | s->carry = 1; |
| 1425 | break; |
| 1426 | case 4: /* Clear */ |
| 1427 | trace_lsi_execute_script_io_clear( |
| 1428 | insn & (1 << 3) ? " ATN" : "", |
| 1429 | insn & (1 << 6) ? " ACK" : "", |
| 1430 | insn & (1 << 9) ? " TM" : "", |
| 1431 | insn & (1 << 10) ? " CC" : ""); |
| 1432 | if (insn & (1 << 3)) { |
| 1433 | s->socl &= ~LSI_SOCL_ATN; |
| 1434 | s->sbcl &= ~LSI_SBCL_ATN; |
| 1435 | } |
| 1436 | |
| 1437 | if (insn & (1 << 6)) { |
| 1438 | s->sbcl &= ~LSI_SBCL_ACK; |
| 1439 | } |
| 1440 | |
| 1441 | if (insn & (1 << 10)) |
| 1442 | s->carry = 0; |
| 1443 | break; |
| 1444 | } |
| 1445 | } else { |
| 1446 | uint8_t op0; |
| 1447 | uint8_t op1; |
| 1448 | uint8_t data8; |
| 1449 | int reg; |
| 1450 | int operator; |
| 1451 | |
| 1452 | static const char *opcode_names[3] = |
| 1453 | {"Write", "Read", "Read-Modify-Write"}; |
| 1454 | static const char *operator_names[8] = |
| 1455 | {"MOV", "SHL", "OR", "XOR", "AND", "SHR", "ADD", "ADC"}; |
| 1456 | |
| 1457 | reg = ((insn >> 16) & 0x7f) | (insn & 0x80); |
| 1458 | data8 = (insn >> 8) & 0xff; |
| 1459 | opcode = (insn >> 27) & 7; |
| 1460 | operator = (insn >> 24) & 7; |
| 1461 | trace_lsi_execute_script_io_opcode( |
| 1462 | opcode_names[opcode - 5], reg, |
| 1463 | operator_names[operator], data8, s->sfbr, |
| 1464 | (insn & (1 << 23)) ? " SFBR" : ""); |
| 1465 | op0 = op1 = 0; |
| 1466 | switch (opcode) { |
| 1467 | case 5: /* From SFBR */ |
| 1468 | op0 = s->sfbr; |
| 1469 | op1 = data8; |
| 1470 | break; |
| 1471 | case 6: /* To SFBR */ |
| 1472 | if (operator) |
| 1473 | op0 = lsi_reg_readb(s, reg); |
| 1474 | op1 = data8; |
| 1475 | break; |
| 1476 | case 7: /* Read-modify-write */ |
| 1477 | if (operator) |
| 1478 | op0 = lsi_reg_readb(s, reg); |
| 1479 | if (insn & (1 << 23)) { |
| 1480 | op1 = s->sfbr; |
| 1481 | } else { |
| 1482 | op1 = data8; |
| 1483 | } |
| 1484 | break; |
| 1485 | } |
| 1486 | |
| 1487 | switch (operator) { |
| 1488 | case 0: /* move */ |
| 1489 | op0 = op1; |
| 1490 | break; |
| 1491 | case 1: /* Shift left */ |
| 1492 | op1 = op0 >> 7; |
| 1493 | op0 = (op0 << 1) | s->carry; |
| 1494 | s->carry = op1; |
| 1495 | break; |
| 1496 | case 2: /* OR */ |
| 1497 | op0 |= op1; |
| 1498 | break; |
| 1499 | case 3: /* XOR */ |
| 1500 | op0 ^= op1; |
| 1501 | break; |
| 1502 | case 4: /* AND */ |
| 1503 | op0 &= op1; |
| 1504 | break; |
| 1505 | case 5: /* SHR */ |
| 1506 | op1 = op0 & 1; |
| 1507 | op0 = (op0 >> 1) | (s->carry << 7); |
| 1508 | s->carry = op1; |
| 1509 | break; |
| 1510 | case 6: /* ADD */ |
| 1511 | op0 += op1; |
| 1512 | s->carry = op0 < op1; |
| 1513 | break; |
| 1514 | case 7: /* ADC */ |
| 1515 | op0 += op1 + s->carry; |
| 1516 | if (s->carry) |
| 1517 | s->carry = op0 <= op1; |
| 1518 | else |
| 1519 | s->carry = op0 < op1; |
| 1520 | break; |
| 1521 | } |
| 1522 | |
| 1523 | switch (opcode) { |
| 1524 | case 5: /* From SFBR */ |
| 1525 | case 7: /* Read-modify-write */ |
| 1526 | lsi_reg_writeb(s, reg, op0); |
| 1527 | break; |
| 1528 | case 6: /* To SFBR */ |
| 1529 | s->sfbr = op0; |
| 1530 | break; |
| 1531 | } |
| 1532 | } |
| 1533 | break; |
| 1534 | |
| 1535 | case 2: /* Transfer Control. */ |
| 1536 | { |
| 1537 | int cond; |
| 1538 | int jmp; |
| 1539 | |
| 1540 | if ((insn & 0x002e0000) == 0) { |
| 1541 | trace_lsi_execute_script_tc_nop(); |
| 1542 | break; |
| 1543 | } |
| 1544 | if (s->sist1 & LSI_SIST1_STO) { |
| 1545 | trace_lsi_execute_script_tc_delayedselect_timeout(); |
| 1546 | lsi_stop_script(s); |
| 1547 | break; |
| 1548 | } |
| 1549 | cond = jmp = (insn & (1 << 19)) != 0; |
| 1550 | if (cond == jmp && (insn & (1 << 21))) { |
| 1551 | trace_lsi_execute_script_tc_compc(s->carry == jmp); |
| 1552 | cond = s->carry != 0; |
| 1553 | } |
| 1554 | if (cond == jmp && (insn & (1 << 17))) { |
| 1555 | trace_lsi_execute_script_tc_compp(scsi_phase_name(s->sstat1), |
| 1556 | jmp ? '=' : '!', scsi_phase_name(insn >> 24)); |
| 1557 | cond = (s->sstat1 & PHASE_MASK) == ((insn >> 24) & 7); |
| 1558 | } |
| 1559 | if (cond == jmp && (insn & (1 << 18))) { |
| 1560 | uint8_t mask; |
| 1561 | |
| 1562 | mask = (~insn >> 8) & 0xff; |
| 1563 | trace_lsi_execute_script_tc_compd( |
| 1564 | s->sfbr, mask, jmp ? '=' : '!', insn & mask); |
| 1565 | cond = (s->sfbr & mask) == (insn & mask); |
| 1566 | } |
| 1567 | if (cond == jmp) { |
| 1568 | if (insn & (1 << 23)) { |
| 1569 | /* Relative address. */ |
| 1570 | addr = s->dsp + sextract32(addr, 0, 24); |
| 1571 | } |
| 1572 | switch ((insn >> 27) & 7) { |
| 1573 | case 0: /* Jump */ |
| 1574 | trace_lsi_execute_script_tc_jump(addr); |
| 1575 | s->adder = addr; |
| 1576 | s->dsp = addr; |
| 1577 | break; |
| 1578 | case 1: /* Call */ |
| 1579 | trace_lsi_execute_script_tc_call(addr); |
| 1580 | s->temp = s->dsp; |
| 1581 | s->dsp = addr; |
| 1582 | break; |
| 1583 | case 2: /* Return */ |
| 1584 | trace_lsi_execute_script_tc_return(s->temp); |
| 1585 | s->dsp = s->temp; |
| 1586 | break; |
| 1587 | case 3: /* Interrupt */ |
| 1588 | trace_lsi_execute_script_tc_interrupt(s->dsps); |
| 1589 | if ((insn & (1 << 20)) != 0) { |
| 1590 | s->istat0 |= LSI_ISTAT0_INTF; |
| 1591 | lsi_update_irq(s); |
| 1592 | } else { |
| 1593 | lsi_script_dma_interrupt(s, LSI_DSTAT_SIR); |
| 1594 | } |
| 1595 | break; |
| 1596 | default: |
| 1597 | trace_lsi_execute_script_tc_illegal(); |
| 1598 | lsi_script_dma_interrupt(s, LSI_DSTAT_IID); |
| 1599 | break; |
| 1600 | } |
| 1601 | } else { |
| 1602 | trace_lsi_execute_script_tc_cc_failed(); |
| 1603 | } |
| 1604 | } |
| 1605 | break; |
| 1606 | |
| 1607 | case 3: |
| 1608 | if ((insn & (1 << 29)) == 0) { |
| 1609 | /* Memory move. */ |
| 1610 | uint32_t dest; |
| 1611 | /* ??? The docs imply the destination address is loaded into |
| 1612 | the TEMP register. However the Linux drivers rely on |
| 1613 | the value being presrved. */ |
| 1614 | dest = read_dword(s, s->dsp); |
| 1615 | s->dsp += 4; |
| 1616 | lsi_memcpy(s, dest, addr, insn & 0xffffff); |
| 1617 | } else { |
| 1618 | uint8_t data[7]; |
| 1619 | int reg; |
| 1620 | int n; |
| 1621 | int i; |
| 1622 | |
| 1623 | if (insn & (1 << 28)) { |
| 1624 | addr = s->dsa + sextract32(addr, 0, 24); |
| 1625 | } |
| 1626 | n = (insn & 7); |
| 1627 | reg = (insn >> 16) & 0xff; |
| 1628 | if (insn & (1 << 24)) { |
| 1629 | pci_dma_read(pci_dev, addr, data, n); |
| 1630 | trace_lsi_execute_script_mm_load(reg, n, addr, *(int *)data); |
| 1631 | for (i = 0; i < n; i++) { |
| 1632 | lsi_reg_writeb(s, reg + i, data[i]); |
| 1633 | } |
| 1634 | } else { |
| 1635 | trace_lsi_execute_script_mm_store(reg, n, addr); |
| 1636 | for (i = 0; i < n; i++) { |
| 1637 | data[i] = lsi_reg_readb(s, reg + i); |
| 1638 | } |
| 1639 | pci_dma_write(pci_dev, addr, data, n); |
| 1640 | } |
| 1641 | } |
| 1642 | } |
| 1643 | if (s->istat1 & LSI_ISTAT1_SRUN && s->waiting == LSI_NOWAIT) { |
| 1644 | if (s->dcntl & LSI_DCNTL_SSM) { |
| 1645 | lsi_script_dma_interrupt(s, LSI_DSTAT_SSI); |
| 1646 | } else { |
| 1647 | goto again; |
| 1648 | } |
| 1649 | } |
| 1650 | trace_lsi_execute_script_stop(); |
| 1651 | |
| 1652 | reentrancy_level--; |
| 1653 | object_unref(s); |
| 1654 | } |
| 1655 | |
| 1656 | static uint8_t lsi_reg_readb(LSIState *s, int offset) |
| 1657 | { |
| 1658 | uint8_t ret; |
| 1659 | |
| 1660 | #define CASE_GET_REG24(name, addr) \ |
| 1661 | case addr: ret = s->name & 0xff; break; \ |
| 1662 | case addr + 1: ret = (s->name >> 8) & 0xff; break; \ |
| 1663 | case addr + 2: ret = (s->name >> 16) & 0xff; break; |
| 1664 | |
| 1665 | #define CASE_GET_REG32(name, addr) \ |
| 1666 | case addr: ret = s->name & 0xff; break; \ |
| 1667 | case addr + 1: ret = (s->name >> 8) & 0xff; break; \ |
| 1668 | case addr + 2: ret = (s->name >> 16) & 0xff; break; \ |
| 1669 | case addr + 3: ret = (s->name >> 24) & 0xff; break; |
| 1670 | |
| 1671 | switch (offset) { |
| 1672 | case 0x00: /* SCNTL0 */ |
| 1673 | ret = s->scntl0; |
| 1674 | break; |
| 1675 | case 0x01: /* SCNTL1 */ |
| 1676 | ret = s->scntl1; |
| 1677 | break; |
| 1678 | case 0x02: /* SCNTL2 */ |
| 1679 | ret = s->scntl2; |
| 1680 | break; |
| 1681 | case 0x03: /* SCNTL3 */ |
| 1682 | ret = s->scntl3; |
| 1683 | break; |
| 1684 | case 0x04: /* SCID */ |
| 1685 | ret = s->scid; |
| 1686 | break; |
| 1687 | case 0x05: /* SXFER */ |
| 1688 | ret = s->sxfer; |
| 1689 | break; |
| 1690 | case 0x06: /* SDID */ |
| 1691 | ret = s->sdid; |
| 1692 | break; |
| 1693 | case 0x07: /* GPREG0 */ |
| 1694 | ret = 0x7f; |
| 1695 | break; |
| 1696 | case 0x08: /* Revision ID */ |
| 1697 | ret = 0x00; |
| 1698 | break; |
| 1699 | case 0x09: /* SOCL */ |
| 1700 | ret = s->socl; |
| 1701 | break; |
| 1702 | case 0xa: /* SSID */ |
| 1703 | ret = s->ssid; |
| 1704 | break; |
| 1705 | case 0xb: /* SBCL */ |
| 1706 | ret = s->sbcl; |
| 1707 | break; |
| 1708 | case 0xc: /* DSTAT */ |
| 1709 | ret = s->dstat | LSI_DSTAT_DFE; |
| 1710 | if ((s->istat0 & LSI_ISTAT0_INTF) == 0) |
| 1711 | s->dstat = 0; |
| 1712 | lsi_update_irq(s); |
| 1713 | break; |
| 1714 | case 0x0d: /* SSTAT0 */ |
| 1715 | ret = s->sstat0; |
| 1716 | break; |
| 1717 | case 0x0e: /* SSTAT1 */ |
| 1718 | ret = s->sstat1; |
| 1719 | break; |
| 1720 | case 0x0f: /* SSTAT2 */ |
| 1721 | ret = s->scntl1 & LSI_SCNTL1_CON ? 0 : 2; |
| 1722 | break; |
| 1723 | CASE_GET_REG32(dsa, 0x10) |
| 1724 | case 0x14: /* ISTAT0 */ |
| 1725 | ret = s->istat0; |
| 1726 | break; |
| 1727 | case 0x15: /* ISTAT1 */ |
| 1728 | ret = s->istat1; |
| 1729 | break; |
| 1730 | case 0x16: /* MBOX0 */ |
| 1731 | ret = s->mbox0; |
| 1732 | break; |
| 1733 | case 0x17: /* MBOX1 */ |
| 1734 | ret = s->mbox1; |
| 1735 | break; |
| 1736 | case 0x18: /* CTEST0 */ |
| 1737 | ret = 0xff; |
| 1738 | break; |
| 1739 | case 0x19: /* CTEST1 */ |
| 1740 | ret = 0; |
| 1741 | break; |
| 1742 | case 0x1a: /* CTEST2 */ |
| 1743 | ret = s->ctest2 | LSI_CTEST2_DACK | LSI_CTEST2_CM; |
| 1744 | if (s->istat0 & LSI_ISTAT0_SIGP) { |
| 1745 | s->istat0 &= ~LSI_ISTAT0_SIGP; |
| 1746 | ret |= LSI_CTEST2_SIGP; |
| 1747 | } |
| 1748 | break; |
| 1749 | case 0x1b: /* CTEST3 */ |
| 1750 | ret = s->ctest3; |
| 1751 | break; |
| 1752 | CASE_GET_REG32(temp, 0x1c) |
| 1753 | case 0x20: /* DFIFO */ |
| 1754 | ret = s->dfifo; |
| 1755 | break; |
| 1756 | case 0x21: /* CTEST4 */ |
| 1757 | ret = s->ctest4; |
| 1758 | break; |
| 1759 | case 0x22: /* CTEST5 */ |
| 1760 | ret = s->ctest5; |
| 1761 | break; |
| 1762 | case 0x23: /* CTEST6 */ |
| 1763 | ret = 0; |
| 1764 | break; |
| 1765 | CASE_GET_REG24(dbc, 0x24) |
| 1766 | case 0x27: /* DCMD */ |
| 1767 | ret = s->dcmd; |
| 1768 | break; |
| 1769 | CASE_GET_REG32(dnad, 0x28) |
| 1770 | CASE_GET_REG32(dsp, 0x2c) |
| 1771 | CASE_GET_REG32(dsps, 0x30) |
| 1772 | CASE_GET_REG32(scratch[0], 0x34) |
| 1773 | case 0x38: /* DMODE */ |
| 1774 | ret = s->dmode; |
| 1775 | break; |
| 1776 | case 0x39: /* DIEN */ |
| 1777 | ret = s->dien; |
| 1778 | break; |
| 1779 | case 0x3a: /* SBR */ |
| 1780 | ret = s->sbr; |
| 1781 | break; |
| 1782 | case 0x3b: /* DCNTL */ |
| 1783 | ret = s->dcntl; |
| 1784 | break; |
| 1785 | /* ADDER Output (Debug of relative jump address) */ |
| 1786 | CASE_GET_REG32(adder, 0x3c) |
| 1787 | case 0x40: /* SIEN0 */ |
| 1788 | ret = s->sien0; |
| 1789 | break; |
| 1790 | case 0x41: /* SIEN1 */ |
| 1791 | ret = s->sien1; |
| 1792 | break; |
| 1793 | case 0x42: /* SIST0 */ |
| 1794 | ret = s->sist0; |
| 1795 | s->sist0 = 0; |
| 1796 | lsi_update_irq(s); |
| 1797 | break; |
| 1798 | case 0x43: /* SIST1 */ |
| 1799 | ret = s->sist1; |
| 1800 | s->sist1 = 0; |
| 1801 | lsi_update_irq(s); |
| 1802 | break; |
| 1803 | case 0x46: /* MACNTL */ |
| 1804 | ret = 0x0f; |
| 1805 | break; |
| 1806 | case 0x47: /* GPCNTL0 */ |
| 1807 | ret = 0x0f; |
| 1808 | break; |
| 1809 | case 0x48: /* STIME0 */ |
| 1810 | ret = s->stime0; |
| 1811 | break; |
| 1812 | case 0x4a: /* RESPID0 */ |
| 1813 | ret = s->respid0; |
| 1814 | break; |
| 1815 | case 0x4b: /* RESPID1 */ |
| 1816 | ret = s->respid1; |
| 1817 | break; |
| 1818 | case 0x4d: /* STEST1 */ |
| 1819 | ret = s->stest1; |
| 1820 | break; |
| 1821 | case 0x4e: /* STEST2 */ |
| 1822 | ret = s->stest2; |
| 1823 | break; |
| 1824 | case 0x4f: /* STEST3 */ |
| 1825 | ret = s->stest3; |
| 1826 | break; |
| 1827 | case 0x50: /* SIDL */ |
| 1828 | /* This is needed by the linux drivers. We currently only update it |
| 1829 | during the MSG IN phase. */ |
| 1830 | ret = s->sidl; |
| 1831 | break; |
| 1832 | case 0x52: /* STEST4 */ |
| 1833 | ret = 0xe0; |
| 1834 | break; |
| 1835 | case 0x56: /* CCNTL0 */ |
| 1836 | ret = s->ccntl0; |
| 1837 | break; |
| 1838 | case 0x57: /* CCNTL1 */ |
| 1839 | ret = s->ccntl1; |
| 1840 | break; |
| 1841 | case 0x58: /* SBDL */ |
| 1842 | /* Some drivers peek at the data bus during the MSG IN phase. */ |
| 1843 | if ((s->sstat1 & PHASE_MASK) == PHASE_MI) { |
| 1844 | assert(s->msg_len > 0); |
| 1845 | return s->msg[0]; |
| 1846 | } |
| 1847 | ret = 0; |
| 1848 | break; |
| 1849 | case 0x59: /* SBDL high */ |
| 1850 | ret = 0; |
| 1851 | break; |
| 1852 | CASE_GET_REG32(mmrs, 0xa0) |
| 1853 | CASE_GET_REG32(mmws, 0xa4) |
| 1854 | CASE_GET_REG32(sfs, 0xa8) |
| 1855 | CASE_GET_REG32(drs, 0xac) |
| 1856 | CASE_GET_REG32(sbms, 0xb0) |
| 1857 | CASE_GET_REG32(dbms, 0xb4) |
| 1858 | CASE_GET_REG32(dnad64, 0xb8) |
| 1859 | CASE_GET_REG32(pmjad1, 0xc0) |
| 1860 | CASE_GET_REG32(pmjad2, 0xc4) |
| 1861 | CASE_GET_REG32(rbc, 0xc8) |
| 1862 | CASE_GET_REG32(ua, 0xcc) |
| 1863 | CASE_GET_REG32(ia, 0xd4) |
| 1864 | CASE_GET_REG32(sbc, 0xd8) |
| 1865 | CASE_GET_REG32(csbc, 0xdc) |
| 1866 | case 0x5c ... 0x9f: |
| 1867 | { |
| 1868 | int n; |
| 1869 | int shift; |
| 1870 | n = (offset - 0x58) >> 2; |
| 1871 | shift = (offset & 3) * 8; |
| 1872 | ret = (s->scratch[n] >> shift) & 0xff; |
| 1873 | break; |
| 1874 | } |
| 1875 | default: |
| 1876 | { |
| 1877 | qemu_log_mask(LOG_GUEST_ERROR, |
| 1878 | "lsi_scsi: invalid read from reg %s %x\n", |
| 1879 | offset < ARRAY_SIZE(names) ? names[offset] : "???", |
| 1880 | offset); |
| 1881 | ret = 0xff; |
| 1882 | break; |
| 1883 | } |
| 1884 | } |
| 1885 | #undef CASE_GET_REG24 |
| 1886 | #undef CASE_GET_REG32 |
| 1887 | |
| 1888 | trace_lsi_reg_read(offset < ARRAY_SIZE(names) ? names[offset] : "???", |
| 1889 | offset, ret); |
| 1890 | |
| 1891 | return ret; |
| 1892 | } |
| 1893 | |
| 1894 | static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val) |
| 1895 | { |
| 1896 | #define CASE_SET_REG24(name, addr) \ |
| 1897 | case addr : s->name &= 0xffffff00; s->name |= val; break; \ |
| 1898 | case addr + 1: s->name &= 0xffff00ff; s->name |= val << 8; break; \ |
| 1899 | case addr + 2: s->name &= 0xff00ffff; s->name |= val << 16; break; |
| 1900 | |
| 1901 | #define CASE_SET_REG32(name, addr) \ |
| 1902 | case addr : s->name &= 0xffffff00; s->name |= val; break; \ |
| 1903 | case addr + 1: s->name &= 0xffff00ff; s->name |= val << 8; break; \ |
| 1904 | case addr + 2: s->name &= 0xff00ffff; s->name |= val << 16; break; \ |
| 1905 | case addr + 3: s->name &= 0x00ffffff; s->name |= val << 24; break; |
| 1906 | |
| 1907 | trace_lsi_reg_write(offset < ARRAY_SIZE(names) ? names[offset] : "???", |
| 1908 | offset, val); |
| 1909 | |
| 1910 | switch (offset) { |
| 1911 | case 0x00: /* SCNTL0 */ |
| 1912 | s->scntl0 = val; |
| 1913 | if (val & LSI_SCNTL0_START) { |
| 1914 | qemu_log_mask(LOG_UNIMP, |
| 1915 | "lsi_scsi: Start sequence not implemented\n"); |
| 1916 | } |
| 1917 | break; |
| 1918 | case 0x01: /* SCNTL1 */ |
| 1919 | s->scntl1 = val & ~LSI_SCNTL1_SST; |
| 1920 | if (val & LSI_SCNTL1_IARB) { |
| 1921 | qemu_log_mask(LOG_UNIMP, |
| 1922 | "lsi_scsi: Immediate Arbritration not implemented\n"); |
| 1923 | } |
| 1924 | if (val & LSI_SCNTL1_RST) { |
| 1925 | if (!(s->sstat0 & LSI_SSTAT0_RST)) { |
| 1926 | bus_cold_reset(BUS(&s->bus)); |
| 1927 | s->sstat0 |= LSI_SSTAT0_RST; |
| 1928 | lsi_script_scsi_interrupt(s, LSI_SIST0_RST, 0); |
| 1929 | } |
| 1930 | } else { |
| 1931 | s->sstat0 &= ~LSI_SSTAT0_RST; |
| 1932 | } |
| 1933 | break; |
| 1934 | case 0x02: /* SCNTL2 */ |
| 1935 | val &= ~(LSI_SCNTL2_WSR | LSI_SCNTL2_WSS); |
| 1936 | s->scntl2 = val; |
| 1937 | break; |
| 1938 | case 0x03: /* SCNTL3 */ |
| 1939 | s->scntl3 = val; |
| 1940 | break; |
| 1941 | case 0x04: /* SCID */ |
| 1942 | s->scid = val; |
| 1943 | break; |
| 1944 | case 0x05: /* SXFER */ |
| 1945 | s->sxfer = val; |
| 1946 | break; |
| 1947 | case 0x06: /* SDID */ |
| 1948 | if ((s->ssid & 0x80) && (val & 0xf) != (s->ssid & 0xf)) { |
| 1949 | qemu_log_mask(LOG_GUEST_ERROR, |
| 1950 | "lsi_scsi: Destination ID does not match SSID\n"); |
| 1951 | } |
| 1952 | s->sdid = val & 0xf; |
| 1953 | break; |
| 1954 | case 0x07: /* GPREG0 */ |
| 1955 | break; |
| 1956 | case 0x08: /* SFBR */ |
| 1957 | /* The CPU is not allowed to write to this register. However the |
| 1958 | SCRIPTS register move instructions are. */ |
| 1959 | s->sfbr = val; |
| 1960 | break; |
| 1961 | case 0x0a: case 0x0b: |
| 1962 | /* Openserver writes to these readonly registers on startup */ |
| 1963 | return; |
| 1964 | case 0x0c: case 0x0d: case 0x0e: case 0x0f: |
| 1965 | /* Linux writes to these readonly registers on startup. */ |
| 1966 | return; |
| 1967 | CASE_SET_REG32(dsa, 0x10) |
| 1968 | case 0x14: /* ISTAT0 */ |
| 1969 | s->istat0 = (s->istat0 & 0x0f) | (val & 0xf0); |
| 1970 | if (val & LSI_ISTAT0_SRST) { |
| 1971 | device_cold_reset(DEVICE(s)); |
| 1972 | return; |
| 1973 | } |
| 1974 | if (val & LSI_ISTAT0_ABRT) { |
| 1975 | lsi_script_dma_interrupt(s, LSI_DSTAT_ABRT); |
| 1976 | } |
| 1977 | if (val & LSI_ISTAT0_INTF) { |
| 1978 | s->istat0 &= ~LSI_ISTAT0_INTF; |
| 1979 | lsi_update_irq(s); |
| 1980 | } |
| 1981 | if (s->waiting == LSI_WAIT_RESELECT && val & LSI_ISTAT0_SIGP) { |
| 1982 | trace_lsi_awoken(); |
| 1983 | s->waiting = LSI_NOWAIT; |
| 1984 | s->dsp = s->dnad; |
| 1985 | lsi_execute_script(s); |
| 1986 | } |
| 1987 | break; |
| 1988 | case 0x16: /* MBOX0 */ |
| 1989 | s->mbox0 = val; |
| 1990 | break; |
| 1991 | case 0x17: /* MBOX1 */ |
| 1992 | s->mbox1 = val; |
| 1993 | break; |
| 1994 | case 0x18: /* CTEST0 */ |
| 1995 | /* nothing to do */ |
| 1996 | break; |
| 1997 | case 0x1a: /* CTEST2 */ |
| 1998 | s->ctest2 = val & LSI_CTEST2_PCICIE; |
| 1999 | break; |
| 2000 | case 0x1b: /* CTEST3 */ |
| 2001 | s->ctest3 = val & 0x0f; |
| 2002 | break; |
| 2003 | CASE_SET_REG32(temp, 0x1c) |
| 2004 | case 0x21: /* CTEST4 */ |
| 2005 | if (val & 7) { |
| 2006 | qemu_log_mask(LOG_UNIMP, |
| 2007 | "lsi_scsi: Unimplemented CTEST4-FBL 0x%x\n", val); |
| 2008 | } |
| 2009 | s->ctest4 = val; |
| 2010 | break; |
| 2011 | case 0x22: /* CTEST5 */ |
| 2012 | if (val & (LSI_CTEST5_ADCK | LSI_CTEST5_BBCK)) { |
| 2013 | qemu_log_mask(LOG_UNIMP, |
| 2014 | "lsi_scsi: CTEST5 DMA increment not implemented\n"); |
| 2015 | } |
| 2016 | s->ctest5 = val; |
| 2017 | break; |
| 2018 | CASE_SET_REG24(dbc, 0x24) |
| 2019 | CASE_SET_REG32(dnad, 0x28) |
| 2020 | case 0x2c: /* DSP[0:7] */ |
| 2021 | s->dsp &= 0xffffff00; |
| 2022 | s->dsp |= val; |
| 2023 | break; |
| 2024 | case 0x2d: /* DSP[8:15] */ |
| 2025 | s->dsp &= 0xffff00ff; |
| 2026 | s->dsp |= val << 8; |
| 2027 | break; |
| 2028 | case 0x2e: /* DSP[16:23] */ |
| 2029 | s->dsp &= 0xff00ffff; |
| 2030 | s->dsp |= val << 16; |
| 2031 | break; |
| 2032 | case 0x2f: /* DSP[24:31] */ |
| 2033 | s->dsp &= 0x00ffffff; |
| 2034 | s->dsp |= val << 24; |
| 2035 | /* |
| 2036 | * FIXME: if s->waiting != LSI_NOWAIT, this will only execute one |
| 2037 | * instruction. Is this correct? |
| 2038 | */ |
| 2039 | if ((s->dmode & LSI_DMODE_MAN) == 0 |
| 2040 | && (s->istat1 & LSI_ISTAT1_SRUN) == 0) |
| 2041 | lsi_execute_script(s); |
| 2042 | break; |
| 2043 | CASE_SET_REG32(dsps, 0x30) |
| 2044 | CASE_SET_REG32(scratch[0], 0x34) |
| 2045 | case 0x38: /* DMODE */ |
| 2046 | s->dmode = val; |
| 2047 | break; |
| 2048 | case 0x39: /* DIEN */ |
| 2049 | s->dien = val; |
| 2050 | lsi_update_irq(s); |
| 2051 | break; |
| 2052 | case 0x3a: /* SBR */ |
| 2053 | s->sbr = val; |
| 2054 | break; |
| 2055 | case 0x3b: /* DCNTL */ |
| 2056 | s->dcntl = val & ~(LSI_DCNTL_PFF | LSI_DCNTL_STD); |
| 2057 | /* |
| 2058 | * FIXME: if s->waiting != LSI_NOWAIT, this will only execute one |
| 2059 | * instruction. Is this correct? |
| 2060 | */ |
| 2061 | if ((val & LSI_DCNTL_STD) && (s->istat1 & LSI_ISTAT1_SRUN) == 0) |
| 2062 | lsi_execute_script(s); |
| 2063 | break; |
| 2064 | case 0x40: /* SIEN0 */ |
| 2065 | s->sien0 = val; |
| 2066 | lsi_update_irq(s); |
| 2067 | break; |
| 2068 | case 0x41: /* SIEN1 */ |
| 2069 | s->sien1 = val; |
| 2070 | lsi_update_irq(s); |
| 2071 | break; |
| 2072 | case 0x47: /* GPCNTL0 */ |
| 2073 | break; |
| 2074 | case 0x48: /* STIME0 */ |
| 2075 | s->stime0 = val; |
| 2076 | break; |
| 2077 | case 0x49: /* STIME1 */ |
| 2078 | if (val & 0xf) { |
| 2079 | qemu_log_mask(LOG_UNIMP, |
| 2080 | "lsi_scsi: General purpose timer not implemented\n"); |
| 2081 | /* ??? Raising the interrupt immediately seems to be sufficient |
| 2082 | to keep the FreeBSD driver happy. */ |
| 2083 | lsi_script_scsi_interrupt(s, 0, LSI_SIST1_GEN); |
| 2084 | } |
| 2085 | break; |
| 2086 | case 0x4a: /* RESPID0 */ |
| 2087 | s->respid0 = val; |
| 2088 | break; |
| 2089 | case 0x4b: /* RESPID1 */ |
| 2090 | s->respid1 = val; |
| 2091 | break; |
| 2092 | case 0x4d: /* STEST1 */ |
| 2093 | s->stest1 = val; |
| 2094 | break; |
| 2095 | case 0x4e: /* STEST2 */ |
| 2096 | if (val & 1) { |
| 2097 | qemu_log_mask(LOG_UNIMP, |
| 2098 | "lsi_scsi: Low level mode not implemented\n"); |
| 2099 | } |
| 2100 | s->stest2 = val; |
| 2101 | break; |
| 2102 | case 0x4f: /* STEST3 */ |
| 2103 | if (val & 0x41) { |
| 2104 | qemu_log_mask(LOG_UNIMP, |
| 2105 | "lsi_scsi: SCSI FIFO test mode not implemented\n"); |
| 2106 | } |
| 2107 | s->stest3 = val; |
| 2108 | break; |
| 2109 | case 0x56: /* CCNTL0 */ |
| 2110 | s->ccntl0 = val; |
| 2111 | break; |
| 2112 | case 0x57: /* CCNTL1 */ |
| 2113 | s->ccntl1 = val; |
| 2114 | break; |
| 2115 | CASE_SET_REG32(mmrs, 0xa0) |
| 2116 | CASE_SET_REG32(mmws, 0xa4) |
| 2117 | CASE_SET_REG32(sfs, 0xa8) |
| 2118 | CASE_SET_REG32(drs, 0xac) |
| 2119 | CASE_SET_REG32(sbms, 0xb0) |
| 2120 | CASE_SET_REG32(dbms, 0xb4) |
| 2121 | CASE_SET_REG32(dnad64, 0xb8) |
| 2122 | CASE_SET_REG32(pmjad1, 0xc0) |
| 2123 | CASE_SET_REG32(pmjad2, 0xc4) |
| 2124 | CASE_SET_REG32(rbc, 0xc8) |
| 2125 | CASE_SET_REG32(ua, 0xcc) |
| 2126 | CASE_SET_REG32(ia, 0xd4) |
| 2127 | CASE_SET_REG32(sbc, 0xd8) |
| 2128 | CASE_SET_REG32(csbc, 0xdc) |
| 2129 | default: |
| 2130 | if (offset >= 0x5c && offset < 0xa0) { |
| 2131 | int n; |
| 2132 | int shift; |
| 2133 | n = (offset - 0x58) >> 2; |
| 2134 | shift = (offset & 3) * 8; |
| 2135 | s->scratch[n] = deposit32(s->scratch[n], shift, 8, val); |
| 2136 | } else { |
| 2137 | qemu_log_mask(LOG_GUEST_ERROR, |
| 2138 | "lsi_scsi: invalid write to reg %s %x (0x%02x)\n", |
| 2139 | offset < ARRAY_SIZE(names) ? names[offset] : "???", |
| 2140 | offset, val); |
| 2141 | } |
| 2142 | } |
| 2143 | #undef CASE_SET_REG24 |
| 2144 | #undef CASE_SET_REG32 |
| 2145 | } |
| 2146 | |
| 2147 | static void lsi_mmio_write(void *opaque, hwaddr addr, |
| 2148 | uint64_t val, unsigned size) |
| 2149 | { |
| 2150 | LSIState *s = opaque; |
| 2151 | |
| 2152 | lsi_reg_writeb(s, addr & 0xff, val); |
| 2153 | } |
| 2154 | |
| 2155 | static uint64_t lsi_mmio_read(void *opaque, hwaddr addr, |
| 2156 | unsigned size) |
| 2157 | { |
| 2158 | LSIState *s = opaque; |
| 2159 | return lsi_reg_readb(s, addr & 0xff); |
| 2160 | } |
| 2161 | |
| 2162 | static const MemoryRegionOps lsi_mmio_ops = { |
| 2163 | .read = lsi_mmio_read, |
| 2164 | .write = lsi_mmio_write, |
| 2165 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 2166 | .impl = { |
| 2167 | .min_access_size = 1, |
| 2168 | .max_access_size = 1, |
| 2169 | }, |
| 2170 | }; |
| 2171 | |
| 2172 | static void lsi_ram_write(void *opaque, hwaddr addr, |
| 2173 | uint64_t val, unsigned size) |
| 2174 | { |
| 2175 | LSIState *s = opaque; |
| 2176 | stn_le_p(s->script_ram + addr, size, val); |
| 2177 | } |
| 2178 | |
| 2179 | static uint64_t lsi_ram_read(void *opaque, hwaddr addr, |
| 2180 | unsigned size) |
| 2181 | { |
| 2182 | LSIState *s = opaque; |
| 2183 | return ldn_le_p(s->script_ram + addr, size); |
| 2184 | } |
| 2185 | |
| 2186 | static const MemoryRegionOps lsi_ram_ops = { |
| 2187 | .read = lsi_ram_read, |
| 2188 | .write = lsi_ram_write, |
| 2189 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 2190 | }; |
| 2191 | |
| 2192 | static uint64_t lsi_io_read(void *opaque, hwaddr addr, |
| 2193 | unsigned size) |
| 2194 | { |
| 2195 | LSIState *s = opaque; |
| 2196 | return lsi_reg_readb(s, addr & 0xff); |
| 2197 | } |
| 2198 | |
| 2199 | static void lsi_io_write(void *opaque, hwaddr addr, |
| 2200 | uint64_t val, unsigned size) |
| 2201 | { |
| 2202 | LSIState *s = opaque; |
| 2203 | lsi_reg_writeb(s, addr & 0xff, val); |
| 2204 | } |
| 2205 | |
| 2206 | static const MemoryRegionOps lsi_io_ops = { |
| 2207 | .read = lsi_io_read, |
| 2208 | .write = lsi_io_write, |
| 2209 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 2210 | .impl = { |
| 2211 | .min_access_size = 1, |
| 2212 | .max_access_size = 1, |
| 2213 | }, |
| 2214 | }; |
| 2215 | |
| 2216 | static void lsi_scsi_reset(DeviceState *dev) |
| 2217 | { |
| 2218 | LSIState *s = LSI53C895A(dev); |
| 2219 | |
| 2220 | lsi_soft_reset(s); |
| 2221 | } |
| 2222 | |
| 2223 | static int lsi_pre_save(void *opaque) |
| 2224 | { |
| 2225 | LSIState *s = opaque; |
| 2226 | |
| 2227 | if (s->current) { |
| 2228 | assert(s->current->dma_buf == NULL); |
| 2229 | assert(s->current->dma_len == 0); |
| 2230 | } |
| 2231 | assert(QTAILQ_EMPTY(&s->queue)); |
| 2232 | |
| 2233 | return 0; |
| 2234 | } |
| 2235 | |
| 2236 | static int lsi_post_load(void *opaque, int version_id) |
| 2237 | { |
| 2238 | LSIState *s = opaque; |
| 2239 | |
| 2240 | if (s->msg_len < 0 || s->msg_len > LSI_MAX_MSGIN_LEN) { |
| 2241 | return -EINVAL; |
| 2242 | } |
| 2243 | |
| 2244 | if (s->waiting == LSI_WAIT_SCRIPTS) { |
| 2245 | lsi_scripts_timer_start(s); |
| 2246 | } |
| 2247 | return 0; |
| 2248 | } |
| 2249 | |
| 2250 | static const VMStateDescription vmstate_lsi_scsi = { |
| 2251 | .name = "lsiscsi", |
| 2252 | .version_id = 1, |
| 2253 | .minimum_version_id = 0, |
| 2254 | .pre_save = lsi_pre_save, |
| 2255 | .post_load = lsi_post_load, |
| 2256 | .fields = (const VMStateField[]) { |
| 2257 | VMSTATE_PCI_DEVICE(parent_obj, LSIState), |
| 2258 | |
| 2259 | VMSTATE_INT32(carry, LSIState), |
| 2260 | VMSTATE_INT32(status, LSIState), |
| 2261 | VMSTATE_INT32(msg_action, LSIState), |
| 2262 | VMSTATE_INT32(msg_len, LSIState), |
| 2263 | VMSTATE_BUFFER(msg, LSIState), |
| 2264 | VMSTATE_INT32(waiting, LSIState), |
| 2265 | |
| 2266 | VMSTATE_UINT32(dsa, LSIState), |
| 2267 | VMSTATE_UINT32(temp, LSIState), |
| 2268 | VMSTATE_UINT32(dnad, LSIState), |
| 2269 | VMSTATE_UINT32(dbc, LSIState), |
| 2270 | VMSTATE_UINT8(istat0, LSIState), |
| 2271 | VMSTATE_UINT8(istat1, LSIState), |
| 2272 | VMSTATE_UINT8(dcmd, LSIState), |
| 2273 | VMSTATE_UINT8(dstat, LSIState), |
| 2274 | VMSTATE_UINT8(dien, LSIState), |
| 2275 | VMSTATE_UINT8(sist0, LSIState), |
| 2276 | VMSTATE_UINT8(sist1, LSIState), |
| 2277 | VMSTATE_UINT8(sien0, LSIState), |
| 2278 | VMSTATE_UINT8(sien1, LSIState), |
| 2279 | VMSTATE_UINT8(mbox0, LSIState), |
| 2280 | VMSTATE_UINT8(mbox1, LSIState), |
| 2281 | VMSTATE_UINT8(dfifo, LSIState), |
| 2282 | VMSTATE_UINT8(ctest2, LSIState), |
| 2283 | VMSTATE_UINT8(ctest3, LSIState), |
| 2284 | VMSTATE_UINT8(ctest4, LSIState), |
| 2285 | VMSTATE_UINT8(ctest5, LSIState), |
| 2286 | VMSTATE_UINT8(ccntl0, LSIState), |
| 2287 | VMSTATE_UINT8(ccntl1, LSIState), |
| 2288 | VMSTATE_UINT32(dsp, LSIState), |
| 2289 | VMSTATE_UINT32(dsps, LSIState), |
| 2290 | VMSTATE_UINT8(dmode, LSIState), |
| 2291 | VMSTATE_UINT8(dcntl, LSIState), |
| 2292 | VMSTATE_UINT8(scntl0, LSIState), |
| 2293 | VMSTATE_UINT8(scntl1, LSIState), |
| 2294 | VMSTATE_UINT8(scntl2, LSIState), |
| 2295 | VMSTATE_UINT8(scntl3, LSIState), |
| 2296 | VMSTATE_UINT8(sstat0, LSIState), |
| 2297 | VMSTATE_UINT8(sstat1, LSIState), |
| 2298 | VMSTATE_UINT8(scid, LSIState), |
| 2299 | VMSTATE_UINT8(sxfer, LSIState), |
| 2300 | VMSTATE_UINT8(socl, LSIState), |
| 2301 | VMSTATE_UINT8(sdid, LSIState), |
| 2302 | VMSTATE_UINT8(ssid, LSIState), |
| 2303 | VMSTATE_UINT8(sfbr, LSIState), |
| 2304 | VMSTATE_UINT8(stest1, LSIState), |
| 2305 | VMSTATE_UINT8(stest2, LSIState), |
| 2306 | VMSTATE_UINT8(stest3, LSIState), |
| 2307 | VMSTATE_UINT8(sidl, LSIState), |
| 2308 | VMSTATE_UINT8(stime0, LSIState), |
| 2309 | VMSTATE_UINT8(respid0, LSIState), |
| 2310 | VMSTATE_UINT8(respid1, LSIState), |
| 2311 | VMSTATE_UINT8_V(sbcl, LSIState, 1), |
| 2312 | VMSTATE_UINT32(mmrs, LSIState), |
| 2313 | VMSTATE_UINT32(mmws, LSIState), |
| 2314 | VMSTATE_UINT32(sfs, LSIState), |
| 2315 | VMSTATE_UINT32(drs, LSIState), |
| 2316 | VMSTATE_UINT32(sbms, LSIState), |
| 2317 | VMSTATE_UINT32(dbms, LSIState), |
| 2318 | VMSTATE_UINT32(dnad64, LSIState), |
| 2319 | VMSTATE_UINT32(pmjad1, LSIState), |
| 2320 | VMSTATE_UINT32(pmjad2, LSIState), |
| 2321 | VMSTATE_UINT32(rbc, LSIState), |
| 2322 | VMSTATE_UINT32(ua, LSIState), |
| 2323 | VMSTATE_UINT32(ia, LSIState), |
| 2324 | VMSTATE_UINT32(sbc, LSIState), |
| 2325 | VMSTATE_UINT32(csbc, LSIState), |
| 2326 | VMSTATE_BUFFER_UNSAFE(scratch, LSIState, 0, 18 * sizeof(uint32_t)), |
| 2327 | VMSTATE_UINT8(sbr, LSIState), |
| 2328 | |
| 2329 | VMSTATE_BUFFER_UNSAFE(script_ram, LSIState, 0, 8192), |
| 2330 | VMSTATE_END_OF_LIST() |
| 2331 | } |
| 2332 | }; |
| 2333 | |
| 2334 | static const struct SCSIBusInfo lsi_scsi_info = { |
| 2335 | .tcq = true, |
| 2336 | .max_target = LSI_MAX_DEVS, |
| 2337 | .max_lun = 0, /* LUN support is buggy */ |
| 2338 | |
| 2339 | .transfer_data = lsi_transfer_data, |
| 2340 | .complete = lsi_command_complete, |
| 2341 | .cancel = lsi_request_cancelled, |
| 2342 | .free_request = lsi_free_request, |
| 2343 | }; |
| 2344 | |
| 2345 | static void scripts_timer_cb(void *opaque) |
| 2346 | { |
| 2347 | LSIState *s = opaque; |
| 2348 | |
| 2349 | trace_lsi_scripts_timer_triggered(); |
| 2350 | s->waiting = LSI_NOWAIT; |
| 2351 | lsi_execute_script(s); |
| 2352 | } |
| 2353 | |
| 2354 | static void lsi_scsi_realize(PCIDevice *dev, Error **errp) |
| 2355 | { |
| 2356 | LSIState *s = LSI53C895A(dev); |
| 2357 | DeviceState *d = DEVICE(dev); |
| 2358 | uint8_t *pci_conf; |
| 2359 | |
| 2360 | pci_conf = dev->config; |
| 2361 | |
| 2362 | /* PCI latency timer = 255 */ |
| 2363 | pci_conf[PCI_LATENCY_TIMER] = 0xff; |
| 2364 | /* Interrupt pin A */ |
| 2365 | pci_conf[PCI_INTERRUPT_PIN] = 0x01; |
| 2366 | |
| 2367 | memory_region_init_io(&s->mmio_io, OBJECT(s), &lsi_mmio_ops, s, |
| 2368 | "lsi-mmio", 0x400); |
| 2369 | memory_region_init_io(&s->ram_io, OBJECT(s), &lsi_ram_ops, s, |
| 2370 | "lsi-ram", 0x2000); |
| 2371 | memory_region_init_io(&s->io_io, OBJECT(s), &lsi_io_ops, s, |
| 2372 | "lsi-io", 256); |
| 2373 | s->scripts_timer = timer_new_us(QEMU_CLOCK_VIRTUAL, scripts_timer_cb, s); |
| 2374 | |
| 2375 | /* |
| 2376 | * Since we use the address-space API to interact with ram_io, disable the |
| 2377 | * re-entrancy guard. |
| 2378 | */ |
| 2379 | s->ram_io.disable_reentrancy_guard = true; |
| 2380 | s->mmio_io.disable_reentrancy_guard = true; |
| 2381 | |
| 2382 | address_space_init(&s->pci_io_as, pci_address_space_io(dev), "lsi-pci-io"); |
| 2383 | qdev_init_gpio_out(d, &s->ext_irq, 1); |
| 2384 | |
| 2385 | pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_io); |
| 2386 | pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mmio_io); |
| 2387 | pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->ram_io); |
| 2388 | QTAILQ_INIT(&s->queue); |
| 2389 | |
| 2390 | scsi_bus_init(&s->bus, sizeof(s->bus), d, &lsi_scsi_info); |
| 2391 | } |
| 2392 | |
| 2393 | static void lsi_scsi_exit(PCIDevice *dev) |
| 2394 | { |
| 2395 | LSIState *s = LSI53C895A(dev); |
| 2396 | |
| 2397 | address_space_destroy(&s->pci_io_as); |
| 2398 | timer_free(s->scripts_timer); |
| 2399 | } |
| 2400 | |
| 2401 | static void lsi_class_init(ObjectClass *klass, const void *data) |
| 2402 | { |
| 2403 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 2404 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
| 2405 | |
| 2406 | k->realize = lsi_scsi_realize; |
| 2407 | k->exit = lsi_scsi_exit; |
| 2408 | k->vendor_id = PCI_VENDOR_ID_LSI_LOGIC; |
| 2409 | k->device_id = PCI_DEVICE_ID_LSI_53C895A; |
| 2410 | k->class_id = PCI_CLASS_STORAGE_SCSI; |
| 2411 | k->subsystem_id = 0x1000; |
| 2412 | device_class_set_legacy_reset(dc, lsi_scsi_reset); |
| 2413 | dc->vmsd = &vmstate_lsi_scsi; |
| 2414 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); |
| 2415 | } |
| 2416 | |
| 2417 | static const TypeInfo lsi_info = { |
| 2418 | .name = TYPE_LSI53C895A, |
| 2419 | .parent = TYPE_PCI_DEVICE, |
| 2420 | .instance_size = sizeof(LSIState), |
| 2421 | .class_init = lsi_class_init, |
| 2422 | .interfaces = (const InterfaceInfo[]) { |
| 2423 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, |
| 2424 | { }, |
| 2425 | }, |
| 2426 | }; |
| 2427 | |
| 2428 | static void lsi53c810_class_init(ObjectClass *klass, const void *data) |
| 2429 | { |
| 2430 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
| 2431 | |
| 2432 | k->device_id = PCI_DEVICE_ID_LSI_53C810; |
| 2433 | } |
| 2434 | |
| 2435 | static const TypeInfo lsi53c810_info = { |
| 2436 | .name = TYPE_LSI53C810, |
| 2437 | .parent = TYPE_LSI53C895A, |
| 2438 | .class_init = lsi53c810_class_init, |
| 2439 | }; |
| 2440 | |
| 2441 | static void lsi53c895a_register_types(void) |
| 2442 | { |
| 2443 | type_register_static(&lsi_info); |
| 2444 | type_register_static(&lsi53c810_info); |
| 2445 | } |
| 2446 | |
| 2447 | type_init(lsi53c895a_register_types) |
| 2448 | |
| 2449 | void lsi53c8xx_handle_legacy_cmdline(DeviceState *lsi_dev) |
| 2450 | { |
| 2451 | LSIState *s = LSI53C895A(lsi_dev); |
| 2452 | |
| 2453 | scsi_bus_legacy_handle_cmdline(&s->bus); |
| 2454 | } |