@samitouri / QOSamiQemu
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1 /*
2 * QEMU MegaRAID SAS 8708EM2 Host Bus Adapter emulation
3 * Based on the linux driver code at drivers/scsi/megaraid
4 *
5 * Copyright (c) 2009-2012 Hannes Reinecke, SUSE Labs
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "hw/pci/pci.h"
23 #include "hw/core/qdev-properties.h"
24 #include "system/dma.h"
25 #include "system/block-backend.h"
26 #include "system/rtc.h"
27 #include "hw/pci/msi.h"
28 #include "hw/pci/msix.h"
29 #include "qemu/iov.h"
30 #include "qemu/module.h"
31 #include "qemu/hw-version.h"
32 #include "hw/scsi/scsi.h"
33 #include "scsi/constants.h"
34 #include "trace.h"
35 #include "qapi/error.h"
36 #include "mfi.h"
37 #include "migration/vmstate.h"
38 #include "qom/object.h"
39
40 #define MEGASAS_VERSION_GEN1 "1.70"
41 #define MEGASAS_VERSION_GEN2 "1.80"
42 #define MEGASAS_MAX_FRAMES 2048 /* Firmware limit at 65535 */
43 #define MEGASAS_DEFAULT_FRAMES 1000 /* Windows requires this */
44 #define MEGASAS_GEN2_DEFAULT_FRAMES 1008 /* Windows requires this */
45 #define MEGASAS_MIN_SGE 64
46 #define MEGASAS_MAX_SGE 128 /* Firmware limit */
47 #define MEGASAS_DEFAULT_SGE 80
48 #define MEGASAS_MAX_SECTORS 0xFFFF /* No real limit */
49 #define MEGASAS_MAX_ARRAYS 128
50
51 #define MEGASAS_HBA_SERIAL "QEMU123456"
52 #define NAA_LOCALLY_ASSIGNED_ID 0x3ULL
53 #define IEEE_COMPANY_LOCALLY_ASSIGNED 0x525400
54
55 #define MEGASAS_FLAG_USE_JBOD 0
56 #define MEGASAS_MASK_USE_JBOD (1 << MEGASAS_FLAG_USE_JBOD)
57 #define MEGASAS_FLAG_USE_QUEUE64 1
58 #define MEGASAS_MASK_USE_QUEUE64 (1 << MEGASAS_FLAG_USE_QUEUE64)
59
60 typedef struct MegasasCmd {
61 uint32_t index;
62 uint16_t flags;
63 uint16_t count;
64 uint64_t context;
65
66 hwaddr pa;
67 hwaddr pa_size;
68 uint32_t dcmd_opcode;
69 union mfi_frame *frame;
70 SCSIRequest *req;
71 QEMUSGList qsg;
72 void *iov_buf;
73 size_t iov_size;
74 size_t iov_offset;
75 struct MegasasState *state;
76 } MegasasCmd;
77
78 struct MegasasState {
79 /*< private >*/
80 PCIDevice parent_obj;
81 /*< public >*/
82
83 MemoryRegion mmio_io;
84 MemoryRegion port_io;
85 MemoryRegion queue_io;
86 uint32_t frame_hi;
87
88 uint32_t fw_state;
89 uint32_t fw_sge;
90 uint32_t fw_cmds;
91 uint32_t flags;
92 uint32_t fw_luns;
93 uint32_t intr_mask;
94 uint32_t doorbell;
95 uint32_t busy;
96 uint32_t diag;
97 uint32_t adp_reset;
98 OnOffAuto msi;
99 OnOffAuto msix;
100
101 MegasasCmd *event_cmd;
102 uint16_t event_locale;
103 int event_class;
104 uint32_t event_count;
105 uint32_t shutdown_event;
106 uint32_t boot_event;
107
108 uint64_t sas_addr;
109 char *hba_serial;
110
111 uint64_t reply_queue_pa;
112 void *reply_queue;
113 uint16_t reply_queue_len;
114 uint32_t reply_queue_head;
115 uint32_t reply_queue_tail;
116 uint64_t consumer_pa;
117 uint64_t producer_pa;
118
119 MegasasCmd frames[MEGASAS_MAX_FRAMES];
120 DECLARE_BITMAP(frame_map, MEGASAS_MAX_FRAMES);
121 SCSIBus bus;
122 };
123 typedef struct MegasasState MegasasState;
124
125 struct MegasasBaseClass {
126 PCIDeviceClass parent_class;
127 const char *product_name;
128 const char *product_version;
129 int mmio_bar;
130 int ioport_bar;
131 int osts;
132 };
133 typedef struct MegasasBaseClass MegasasBaseClass;
134
135 #define TYPE_MEGASAS_BASE "megasas-base"
136 #define TYPE_MEGASAS_GEN1 "megasas"
137 #define TYPE_MEGASAS_GEN2 "megasas-gen2"
138
139 DECLARE_OBJ_CHECKERS(MegasasState, MegasasBaseClass,
140 MEGASAS, TYPE_MEGASAS_BASE)
141
142
143 #define MEGASAS_INTR_DISABLED_MASK 0xFFFFFFFF
144
145 static bool megasas_intr_enabled(MegasasState *s)
146 {
147 if ((s->intr_mask & MEGASAS_INTR_DISABLED_MASK) !=
148 MEGASAS_INTR_DISABLED_MASK) {
149 return true;
150 }
151 return false;
152 }
153
154 static bool megasas_use_queue64(MegasasState *s)
155 {
156 return s->flags & MEGASAS_MASK_USE_QUEUE64;
157 }
158
159 static bool megasas_use_msix(MegasasState *s)
160 {
161 return s->msix != ON_OFF_AUTO_OFF;
162 }
163
164 static bool megasas_is_jbod(MegasasState *s)
165 {
166 return s->flags & MEGASAS_MASK_USE_JBOD;
167 }
168
169 static void megasas_frame_set_cmd_status(MegasasState *s,
170 unsigned long frame, uint8_t v)
171 {
172 PCIDevice *pci = &s->parent_obj;
173 stb_pci_dma(pci, frame + offsetof(struct mfi_frame_header, cmd_status),
174 v, MEMTXATTRS_UNSPECIFIED);
175 }
176
177 static void megasas_frame_set_scsi_status(MegasasState *s,
178 unsigned long frame, uint8_t v)
179 {
180 PCIDevice *pci = &s->parent_obj;
181 stb_pci_dma(pci, frame + offsetof(struct mfi_frame_header, scsi_status),
182 v, MEMTXATTRS_UNSPECIFIED);
183 }
184
185 static inline const char *mfi_frame_desc(unsigned int cmd)
186 {
187 static const char *mfi_frame_descs[] = {
188 "MFI init", "LD Read", "LD Write", "LD SCSI", "PD SCSI",
189 "MFI Doorbell", "MFI Abort", "MFI SMP", "MFI Stop"
190 };
191
192 if (cmd < ARRAY_SIZE(mfi_frame_descs)) {
193 return mfi_frame_descs[cmd];
194 }
195
196 return "Unknown";
197 }
198
199 /*
200 * Context is considered opaque, but the HBA firmware is running
201 * in little endian mode. So convert it to little endian, too.
202 */
203 static uint64_t megasas_frame_get_context(MegasasState *s,
204 unsigned long frame)
205 {
206 PCIDevice *pci = &s->parent_obj;
207 uint64_t val;
208
209 ldq_le_pci_dma(pci, frame + offsetof(struct mfi_frame_header, context),
210 &val, MEMTXATTRS_UNSPECIFIED);
211
212 return val;
213 }
214
215 static bool megasas_frame_is_ieee_sgl(MegasasCmd *cmd)
216 {
217 return cmd->flags & MFI_FRAME_IEEE_SGL;
218 }
219
220 static bool megasas_frame_is_sgl64(MegasasCmd *cmd)
221 {
222 return cmd->flags & MFI_FRAME_SGL64;
223 }
224
225 static bool megasas_frame_is_sense64(MegasasCmd *cmd)
226 {
227 return cmd->flags & MFI_FRAME_SENSE64;
228 }
229
230 static uint64_t megasas_sgl_get_addr(MegasasCmd *cmd,
231 union mfi_sgl *sgl)
232 {
233 uint64_t addr;
234
235 if (megasas_frame_is_ieee_sgl(cmd)) {
236 addr = le64_to_cpu(sgl->sg_skinny->addr);
237 } else if (megasas_frame_is_sgl64(cmd)) {
238 addr = le64_to_cpu(sgl->sg64->addr);
239 } else {
240 addr = le32_to_cpu(sgl->sg32->addr);
241 }
242 return addr;
243 }
244
245 static uint32_t megasas_sgl_get_len(MegasasCmd *cmd,
246 union mfi_sgl *sgl)
247 {
248 uint32_t len;
249
250 if (megasas_frame_is_ieee_sgl(cmd)) {
251 len = le32_to_cpu(sgl->sg_skinny->len);
252 } else if (megasas_frame_is_sgl64(cmd)) {
253 len = le32_to_cpu(sgl->sg64->len);
254 } else {
255 len = le32_to_cpu(sgl->sg32->len);
256 }
257 return len;
258 }
259
260 static union mfi_sgl *megasas_sgl_next(MegasasCmd *cmd,
261 union mfi_sgl *sgl)
262 {
263 uint8_t *next = (uint8_t *)sgl;
264
265 if (megasas_frame_is_ieee_sgl(cmd)) {
266 next += sizeof(struct mfi_sg_skinny);
267 } else if (megasas_frame_is_sgl64(cmd)) {
268 next += sizeof(struct mfi_sg64);
269 } else {
270 next += sizeof(struct mfi_sg32);
271 }
272
273 if (next >= (uint8_t *)cmd->frame + cmd->pa_size) {
274 return NULL;
275 }
276 return (union mfi_sgl *)next;
277 }
278
279 static void megasas_soft_reset(MegasasState *s);
280
281 static int megasas_map_sgl(MegasasState *s, MegasasCmd *cmd, union mfi_sgl *sgl)
282 {
283 int i;
284 int iov_count = 0;
285 size_t iov_size = 0;
286
287 cmd->flags = le16_to_cpu(cmd->frame->header.flags);
288 iov_count = cmd->frame->header.sge_count;
289 if (!iov_count || iov_count > MEGASAS_MAX_SGE) {
290 trace_megasas_iovec_sgl_overflow(cmd->index, iov_count,
291 MEGASAS_MAX_SGE);
292 return -1;
293 }
294 pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), iov_count);
295 for (i = 0; i < iov_count; i++) {
296 dma_addr_t iov_pa, iov_size_p;
297
298 if (!sgl) {
299 trace_megasas_iovec_sgl_underflow(cmd->index, i);
300 goto unmap;
301 }
302 iov_pa = megasas_sgl_get_addr(cmd, sgl);
303 iov_size_p = megasas_sgl_get_len(cmd, sgl);
304 if (!iov_pa || !iov_size_p) {
305 trace_megasas_iovec_sgl_invalid(cmd->index, i,
306 iov_pa, iov_size_p);
307 goto unmap;
308 }
309 qemu_sglist_add(&cmd->qsg, iov_pa, iov_size_p);
310 sgl = megasas_sgl_next(cmd, sgl);
311 iov_size += (size_t)iov_size_p;
312 }
313 if (cmd->iov_size > iov_size) {
314 trace_megasas_iovec_overflow(cmd->index, iov_size, cmd->iov_size);
315 goto unmap;
316 } else if (cmd->iov_size < iov_size) {
317 trace_megasas_iovec_underflow(cmd->index, iov_size, cmd->iov_size);
318 }
319 cmd->iov_offset = 0;
320 return 0;
321 unmap:
322 qemu_sglist_destroy(&cmd->qsg);
323 return -1;
324 }
325
326 /*
327 * passthrough sense and io sense are at the same offset
328 */
329 static int megasas_build_sense(MegasasCmd *cmd, uint8_t *sense_ptr,
330 uint8_t sense_len)
331 {
332 PCIDevice *pcid = PCI_DEVICE(cmd->state);
333 uint32_t pa_hi = 0, pa_lo;
334 hwaddr pa;
335 int frame_sense_len;
336
337 frame_sense_len = cmd->frame->header.sense_len;
338 if (sense_len > frame_sense_len) {
339 sense_len = frame_sense_len;
340 }
341 if (sense_len) {
342 pa_lo = le32_to_cpu(cmd->frame->pass.sense_addr_lo);
343 if (megasas_frame_is_sense64(cmd)) {
344 pa_hi = le32_to_cpu(cmd->frame->pass.sense_addr_hi);
345 }
346 pa = ((uint64_t) pa_hi << 32) | pa_lo;
347 pci_dma_write(pcid, pa, sense_ptr, sense_len);
348 cmd->frame->header.sense_len = sense_len;
349 }
350 return sense_len;
351 }
352
353 static void megasas_write_sense(MegasasCmd *cmd, SCSISense sense)
354 {
355 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE];
356 uint8_t sense_len = 18;
357
358 memset(sense_buf, 0, sense_len);
359 sense_buf[0] = 0xf0;
360 sense_buf[2] = sense.key;
361 sense_buf[7] = 10;
362 sense_buf[12] = sense.asc;
363 sense_buf[13] = sense.ascq;
364 megasas_build_sense(cmd, sense_buf, sense_len);
365 }
366
367 static void megasas_copy_sense(MegasasCmd *cmd)
368 {
369 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE];
370 uint8_t sense_len;
371
372 sense_len = scsi_req_get_sense(cmd->req, sense_buf,
373 SCSI_SENSE_BUF_SIZE);
374 megasas_build_sense(cmd, sense_buf, sense_len);
375 }
376
377 /*
378 * Format an INQUIRY CDB
379 */
380 static int megasas_setup_inquiry(uint8_t *cdb, int pg, int len)
381 {
382 memset(cdb, 0, 6);
383 cdb[0] = INQUIRY;
384 if (pg > 0) {
385 cdb[1] = 0x1;
386 cdb[2] = pg;
387 }
388 stw_be_p(&cdb[3], len);
389 return len;
390 }
391
392 /*
393 * Encode lba and len into a READ_16/WRITE_16 CDB
394 */
395 static void megasas_encode_lba(uint8_t *cdb, uint64_t lba,
396 uint32_t len, bool is_write)
397 {
398 memset(cdb, 0x0, 16);
399 if (is_write) {
400 cdb[0] = WRITE_16;
401 } else {
402 cdb[0] = READ_16;
403 }
404 stq_be_p(&cdb[2], lba);
405 stl_be_p(&cdb[2 + 8], len);
406 }
407
408 /*
409 * Utility functions
410 */
411 static uint64_t megasas_fw_time(void)
412 {
413 struct tm curtime;
414
415 qemu_get_timedate(&curtime, 0);
416 return ((uint64_t)curtime.tm_sec & 0xff) << 48 |
417 ((uint64_t)curtime.tm_min & 0xff) << 40 |
418 ((uint64_t)curtime.tm_hour & 0xff) << 32 |
419 ((uint64_t)curtime.tm_mday & 0xff) << 24 |
420 ((uint64_t)curtime.tm_mon & 0xff) << 16 |
421 ((uint64_t)(curtime.tm_year + 1900) & 0xffff);
422 }
423
424 /*
425 * Default disk sata address
426 * 0x1221 is the magic number as
427 * present in real hardware,
428 * so use it here, too.
429 */
430 static uint64_t megasas_get_sata_addr(uint16_t id)
431 {
432 uint64_t addr = (0x1221ULL << 48);
433 return addr | ((uint64_t)id << 24);
434 }
435
436 /*
437 * Frame handling
438 */
439 static int megasas_next_index(MegasasState *s, int index, int limit)
440 {
441 index++;
442 if (index == limit) {
443 index = 0;
444 }
445 return index;
446 }
447
448 static MegasasCmd *megasas_lookup_frame(MegasasState *s,
449 hwaddr frame)
450 {
451 MegasasCmd *cmd = NULL;
452 int num = 0, index;
453
454 index = s->reply_queue_head;
455
456 while (num < s->fw_cmds && index < MEGASAS_MAX_FRAMES) {
457 if (s->frames[index].pa && s->frames[index].pa == frame) {
458 cmd = &s->frames[index];
459 break;
460 }
461 index = megasas_next_index(s, index, s->fw_cmds);
462 num++;
463 }
464
465 return cmd;
466 }
467
468 static void megasas_unmap_frame(MegasasState *s, MegasasCmd *cmd)
469 {
470 PCIDevice *p = PCI_DEVICE(s);
471
472 if (cmd->pa_size) {
473 pci_dma_unmap(p, cmd->frame, cmd->pa_size, 0, 0);
474 }
475 cmd->frame = NULL;
476 cmd->pa = 0;
477 cmd->pa_size = 0;
478 qemu_sglist_destroy(&cmd->qsg);
479 clear_bit(cmd->index, s->frame_map);
480 }
481
482 /*
483 * This absolutely needs to be locked if
484 * qemu ever goes multithreaded.
485 */
486 static MegasasCmd *megasas_enqueue_frame(MegasasState *s,
487 hwaddr frame, uint64_t context, int count)
488 {
489 PCIDevice *pcid = PCI_DEVICE(s);
490 MegasasCmd *cmd = NULL;
491 int frame_size = MEGASAS_MAX_SGE * sizeof(union mfi_sgl);
492 hwaddr frame_size_p = frame_size;
493 unsigned long index;
494
495 index = 0;
496 while (index < s->fw_cmds) {
497 index = find_next_zero_bit(s->frame_map, s->fw_cmds, index);
498 if (!s->frames[index].pa)
499 break;
500 /* Busy frame found */
501 trace_megasas_qf_mapped(index);
502 }
503 if (index >= s->fw_cmds) {
504 /* All frames busy */
505 trace_megasas_qf_busy(frame);
506 return NULL;
507 }
508 cmd = &s->frames[index];
509 set_bit(index, s->frame_map);
510 trace_megasas_qf_new(index, frame);
511
512 cmd->pa = frame;
513 /* Map all possible frames */
514 cmd->frame = pci_dma_map(pcid, frame, &frame_size_p, 0);
515 if (!cmd->frame || frame_size_p != frame_size) {
516 trace_megasas_qf_map_failed(cmd->index, (unsigned long)frame);
517 if (cmd->frame) {
518 megasas_unmap_frame(s, cmd);
519 }
520 s->event_count++;
521 return NULL;
522 }
523 cmd->pa_size = frame_size_p;
524 cmd->context = context;
525 if (!megasas_use_queue64(s)) {
526 cmd->context &= (uint64_t)0xFFFFFFFF;
527 }
528 cmd->count = count;
529 cmd->dcmd_opcode = -1;
530 s->busy++;
531
532 if (s->consumer_pa) {
533 ldl_le_pci_dma(pcid, s->consumer_pa, &s->reply_queue_tail,
534 MEMTXATTRS_UNSPECIFIED);
535 }
536 trace_megasas_qf_enqueue(cmd->index, cmd->count, cmd->context,
537 s->reply_queue_head, s->reply_queue_tail, s->busy);
538
539 return cmd;
540 }
541
542 static void megasas_complete_frame(MegasasState *s, uint64_t context)
543 {
544 const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
545 PCIDevice *pci_dev = PCI_DEVICE(s);
546 int tail, queue_offset;
547
548 /* Decrement busy count */
549 s->busy--;
550 if (s->reply_queue_pa) {
551 /*
552 * Put command on the reply queue.
553 * Context is opaque, but emulation is running in
554 * little endian. So convert it.
555 */
556 if (megasas_use_queue64(s)) {
557 queue_offset = s->reply_queue_head * sizeof(uint64_t);
558 stq_le_pci_dma(pci_dev, s->reply_queue_pa + queue_offset,
559 context, attrs);
560 } else {
561 queue_offset = s->reply_queue_head * sizeof(uint32_t);
562 stl_le_pci_dma(pci_dev, s->reply_queue_pa + queue_offset,
563 context, attrs);
564 }
565 ldl_le_pci_dma(pci_dev, s->consumer_pa, &s->reply_queue_tail, attrs);
566 trace_megasas_qf_complete(context, s->reply_queue_head,
567 s->reply_queue_tail, s->busy);
568 }
569
570 if (megasas_intr_enabled(s)) {
571 /* Update reply queue pointer */
572 ldl_le_pci_dma(pci_dev, s->consumer_pa, &s->reply_queue_tail, attrs);
573 tail = s->reply_queue_head;
574 s->reply_queue_head = megasas_next_index(s, tail, s->fw_cmds);
575 trace_megasas_qf_update(s->reply_queue_head, s->reply_queue_tail,
576 s->busy);
577 stl_le_pci_dma(pci_dev, s->producer_pa, s->reply_queue_head, attrs);
578 /* Notify HBA */
579 if (msix_enabled(pci_dev)) {
580 trace_megasas_msix_raise(0);
581 msix_notify(pci_dev, 0);
582 } else if (msi_enabled(pci_dev)) {
583 trace_megasas_msi_raise(0);
584 msi_notify(pci_dev, 0);
585 } else {
586 s->doorbell++;
587 if (s->doorbell == 1) {
588 trace_megasas_irq_raise();
589 pci_irq_assert(pci_dev);
590 }
591 }
592 } else {
593 trace_megasas_qf_complete_noirq(context);
594 }
595 }
596
597 static void megasas_complete_command(MegasasCmd *cmd)
598 {
599 cmd->iov_size = 0;
600 cmd->iov_offset = 0;
601
602 cmd->req->hba_private = NULL;
603 scsi_req_unref(cmd->req);
604 cmd->req = NULL;
605
606 megasas_unmap_frame(cmd->state, cmd);
607 megasas_complete_frame(cmd->state, cmd->context);
608 }
609
610 static void megasas_reset_frames(MegasasState *s)
611 {
612 int i;
613 MegasasCmd *cmd;
614
615 for (i = 0; i < s->fw_cmds; i++) {
616 cmd = &s->frames[i];
617 if (cmd->pa) {
618 megasas_unmap_frame(s, cmd);
619 }
620 }
621 bitmap_zero(s->frame_map, MEGASAS_MAX_FRAMES);
622 }
623
624 static void megasas_abort_command(MegasasCmd *cmd)
625 {
626 /* Never abort internal commands. */
627 if (cmd->dcmd_opcode != -1) {
628 return;
629 }
630 if (cmd->req != NULL) {
631 scsi_req_cancel(cmd->req);
632 }
633 }
634
635 static int megasas_init_firmware(MegasasState *s, MegasasCmd *cmd)
636 {
637 const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
638 PCIDevice *pcid = PCI_DEVICE(s);
639 uint32_t pa_hi, pa_lo;
640 hwaddr iq_pa, initq_size = sizeof(struct mfi_init_qinfo);
641 struct mfi_init_qinfo *initq = NULL;
642 uint32_t flags;
643 int ret = MFI_STAT_OK;
644
645 if (s->reply_queue_pa) {
646 trace_megasas_initq_mapped(s->reply_queue_pa);
647 goto out;
648 }
649 pa_lo = le32_to_cpu(cmd->frame->init.qinfo_new_addr_lo);
650 pa_hi = le32_to_cpu(cmd->frame->init.qinfo_new_addr_hi);
651 iq_pa = (((uint64_t) pa_hi << 32) | pa_lo);
652 trace_megasas_init_firmware((uint64_t)iq_pa);
653 initq = pci_dma_map(pcid, iq_pa, &initq_size, 0);
654 if (!initq || initq_size != sizeof(*initq)) {
655 trace_megasas_initq_map_failed(cmd->index);
656 s->event_count++;
657 ret = MFI_STAT_MEMORY_NOT_AVAILABLE;
658 goto out;
659 }
660 s->reply_queue_len = le32_to_cpu(initq->rq_entries) & 0xFFFF;
661 if (s->reply_queue_len > s->fw_cmds) {
662 trace_megasas_initq_mismatch(s->reply_queue_len, s->fw_cmds);
663 s->event_count++;
664 ret = MFI_STAT_INVALID_PARAMETER;
665 goto out;
666 }
667 pa_lo = le32_to_cpu(initq->rq_addr_lo);
668 pa_hi = le32_to_cpu(initq->rq_addr_hi);
669 s->reply_queue_pa = ((uint64_t) pa_hi << 32) | pa_lo;
670 pa_lo = le32_to_cpu(initq->ci_addr_lo);
671 pa_hi = le32_to_cpu(initq->ci_addr_hi);
672 s->consumer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
673 pa_lo = le32_to_cpu(initq->pi_addr_lo);
674 pa_hi = le32_to_cpu(initq->pi_addr_hi);
675 s->producer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
676 ldl_le_pci_dma(pcid, s->producer_pa, &s->reply_queue_head, attrs);
677 s->reply_queue_head %= MEGASAS_MAX_FRAMES;
678 ldl_le_pci_dma(pcid, s->consumer_pa, &s->reply_queue_tail, attrs);
679 s->reply_queue_tail %= MEGASAS_MAX_FRAMES;
680 flags = le32_to_cpu(initq->flags);
681 if (flags & MFI_QUEUE_FLAG_CONTEXT64) {
682 s->flags |= MEGASAS_MASK_USE_QUEUE64;
683 }
684 trace_megasas_init_queue((unsigned long)s->reply_queue_pa,
685 s->reply_queue_len, s->reply_queue_head,
686 s->reply_queue_tail, flags);
687 megasas_reset_frames(s);
688 s->fw_state = MFI_FWSTATE_OPERATIONAL;
689 out:
690 if (initq) {
691 pci_dma_unmap(pcid, initq, initq_size, 0, 0);
692 }
693 return ret;
694 }
695
696 static int megasas_map_dcmd(MegasasState *s, MegasasCmd *cmd)
697 {
698 dma_addr_t iov_pa, iov_size;
699 int iov_count;
700
701 cmd->flags = le16_to_cpu(cmd->frame->header.flags);
702 iov_count = cmd->frame->header.sge_count;
703 if (!iov_count) {
704 trace_megasas_dcmd_zero_sge(cmd->index);
705 cmd->iov_size = 0;
706 return 0;
707 } else if (iov_count > 1) {
708 trace_megasas_dcmd_invalid_sge(cmd->index, iov_count);
709 cmd->iov_size = 0;
710 return -EINVAL;
711 }
712 iov_pa = megasas_sgl_get_addr(cmd, &cmd->frame->dcmd.sgl);
713 iov_size = megasas_sgl_get_len(cmd, &cmd->frame->dcmd.sgl);
714 pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), 1);
715 qemu_sglist_add(&cmd->qsg, iov_pa, iov_size);
716 cmd->iov_size = iov_size;
717 return 0;
718 }
719
720 static void megasas_finish_dcmd(MegasasCmd *cmd, uint32_t iov_size)
721 {
722 trace_megasas_finish_dcmd(cmd->index, iov_size);
723
724 if (iov_size > cmd->iov_size) {
725 if (megasas_frame_is_ieee_sgl(cmd)) {
726 cmd->frame->dcmd.sgl.sg_skinny->len = cpu_to_le32(iov_size);
727 } else if (megasas_frame_is_sgl64(cmd)) {
728 cmd->frame->dcmd.sgl.sg64->len = cpu_to_le32(iov_size);
729 } else {
730 cmd->frame->dcmd.sgl.sg32->len = cpu_to_le32(iov_size);
731 }
732 }
733 }
734
735 static int megasas_ctrl_get_info(MegasasState *s, MegasasCmd *cmd)
736 {
737 PCIDevice *pci_dev = PCI_DEVICE(s);
738 PCIDeviceClass *pci_class = PCI_DEVICE_GET_CLASS(pci_dev);
739 MegasasBaseClass *base_class = MEGASAS_GET_CLASS(s);
740 struct mfi_ctrl_info info;
741 size_t dcmd_size = sizeof(info);
742 BusChild *kid;
743 int num_pd_disks = 0;
744 dma_addr_t residual;
745
746 memset(&info, 0x0, dcmd_size);
747 if (cmd->iov_size < dcmd_size) {
748 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
749 dcmd_size);
750 return MFI_STAT_INVALID_PARAMETER;
751 }
752
753 info.pci.vendor = cpu_to_le16(pci_class->vendor_id);
754 info.pci.device = cpu_to_le16(pci_class->device_id);
755 info.pci.subvendor = cpu_to_le16(pci_class->subsystem_vendor_id);
756 info.pci.subdevice = cpu_to_le16(pci_class->subsystem_id);
757
758 /*
759 * For some reason the firmware supports
760 * only up to 8 device ports.
761 * Despite supporting a far larger number
762 * of devices for the physical devices.
763 * So just display the first 8 devices
764 * in the device port list, independent
765 * of how many logical devices are actually
766 * present.
767 */
768 info.host.type = MFI_INFO_HOST_PCIE;
769 info.device.type = MFI_INFO_DEV_SAS3G;
770 info.device.port_count = 8;
771 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
772 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
773 uint16_t pd_id;
774
775 if (num_pd_disks < 8) {
776 pd_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
777 info.device.port_addr[num_pd_disks] =
778 cpu_to_le64(megasas_get_sata_addr(pd_id));
779 }
780 num_pd_disks++;
781 }
782
783 memcpy(info.product_name, base_class->product_name, 24);
784 snprintf(info.serial_number, 32, "%s", s->hba_serial);
785 snprintf(info.package_version, 0x60, "%s-QEMU", QEMU_HW_VERSION);
786 memcpy(info.image_component[0].name, "APP", 3);
787 snprintf(info.image_component[0].version, 10, "%s-QEMU",
788 base_class->product_version);
789 memcpy(info.image_component[0].build_date, "Apr 1 2014", 11);
790 memcpy(info.image_component[0].build_time, "12:34:56", 8);
791 info.image_component_count = 1;
792 if (pci_dev->has_rom) {
793 uint8_t biosver[32];
794 uint8_t *ptr;
795
796 ptr = memory_region_get_ram_ptr(&pci_dev->rom);
797 memcpy(biosver, ptr + 0x41, 31);
798 biosver[31] = 0;
799 memcpy(info.image_component[1].name, "BIOS", 4);
800 memcpy(info.image_component[1].version, biosver,
801 strlen((const char *)biosver));
802 info.image_component_count++;
803 }
804 info.current_fw_time = cpu_to_le32(megasas_fw_time());
805 info.max_arms = 32;
806 info.max_spans = 8;
807 info.max_arrays = MEGASAS_MAX_ARRAYS;
808 info.max_lds = MFI_MAX_LD;
809 info.max_cmds = cpu_to_le16(s->fw_cmds);
810 info.max_sg_elements = cpu_to_le16(s->fw_sge);
811 info.max_request_size = cpu_to_le32(MEGASAS_MAX_SECTORS);
812 if (!megasas_is_jbod(s))
813 info.lds_present = cpu_to_le16(num_pd_disks);
814 info.pd_present = cpu_to_le16(num_pd_disks);
815 info.pd_disks_present = cpu_to_le16(num_pd_disks);
816 info.hw_present = cpu_to_le32(MFI_INFO_HW_NVRAM |
817 MFI_INFO_HW_MEM |
818 MFI_INFO_HW_FLASH);
819 info.memory_size = cpu_to_le16(512);
820 info.nvram_size = cpu_to_le16(32);
821 info.flash_size = cpu_to_le16(16);
822 info.raid_levels = cpu_to_le32(MFI_INFO_RAID_0);
823 info.adapter_ops = cpu_to_le32(MFI_INFO_AOPS_RBLD_RATE |
824 MFI_INFO_AOPS_SELF_DIAGNOSTIC |
825 MFI_INFO_AOPS_MIXED_ARRAY);
826 info.ld_ops = cpu_to_le32(MFI_INFO_LDOPS_DISK_CACHE_POLICY |
827 MFI_INFO_LDOPS_ACCESS_POLICY |
828 MFI_INFO_LDOPS_IO_POLICY |
829 MFI_INFO_LDOPS_WRITE_POLICY |
830 MFI_INFO_LDOPS_READ_POLICY);
831 info.max_strips_per_io = cpu_to_le16(s->fw_sge);
832 info.stripe_sz_ops.min = 3;
833 info.stripe_sz_ops.max = ctz32(MEGASAS_MAX_SECTORS + 1);
834 info.properties.pred_fail_poll_interval = cpu_to_le16(300);
835 info.properties.intr_throttle_cnt = cpu_to_le16(16);
836 info.properties.intr_throttle_timeout = cpu_to_le16(50);
837 info.properties.rebuild_rate = 30;
838 info.properties.patrol_read_rate = 30;
839 info.properties.bgi_rate = 30;
840 info.properties.cc_rate = 30;
841 info.properties.recon_rate = 30;
842 info.properties.cache_flush_interval = 4;
843 info.properties.spinup_drv_cnt = 2;
844 info.properties.spinup_delay = 6;
845 info.properties.ecc_bucket_size = 15;
846 info.properties.ecc_bucket_leak_rate = cpu_to_le16(1440);
847 info.properties.expose_encl_devices = 1;
848 info.properties.OnOffProperties = cpu_to_le32(MFI_CTRL_PROP_EnableJBOD);
849 info.pd_ops = cpu_to_le32(MFI_INFO_PDOPS_FORCE_ONLINE |
850 MFI_INFO_PDOPS_FORCE_OFFLINE);
851 info.pd_mix_support = cpu_to_le32(MFI_INFO_PDMIX_SAS |
852 MFI_INFO_PDMIX_SATA |
853 MFI_INFO_PDMIX_LD);
854
855 dma_buf_read(&info, dcmd_size, &residual, &cmd->qsg,
856 MEMTXATTRS_UNSPECIFIED);
857 cmd->iov_size -= residual;
858 return MFI_STAT_OK;
859 }
860
861 static int megasas_mfc_get_defaults(MegasasState *s, MegasasCmd *cmd)
862 {
863 struct mfi_defaults info;
864 size_t dcmd_size = sizeof(struct mfi_defaults);
865 dma_addr_t residual;
866
867 memset(&info, 0x0, dcmd_size);
868 if (cmd->iov_size < dcmd_size) {
869 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
870 dcmd_size);
871 return MFI_STAT_INVALID_PARAMETER;
872 }
873
874 info.sas_addr = cpu_to_le64(s->sas_addr);
875 info.stripe_size = 3;
876 info.flush_time = 4;
877 info.background_rate = 30;
878 info.allow_mix_in_enclosure = 1;
879 info.allow_mix_in_ld = 1;
880 info.direct_pd_mapping = 1;
881 /* Enable for BIOS support */
882 info.bios_enumerate_lds = 1;
883 info.disable_ctrl_r = 1;
884 info.expose_enclosure_devices = 1;
885 info.disable_preboot_cli = 1;
886 info.cluster_disable = 1;
887
888 dma_buf_read(&info, dcmd_size, &residual, &cmd->qsg,
889 MEMTXATTRS_UNSPECIFIED);
890 cmd->iov_size -= residual;
891 return MFI_STAT_OK;
892 }
893
894 static int megasas_dcmd_get_bios_info(MegasasState *s, MegasasCmd *cmd)
895 {
896 struct mfi_bios_data info;
897 size_t dcmd_size = sizeof(info);
898 dma_addr_t residual;
899
900 memset(&info, 0x0, dcmd_size);
901 if (cmd->iov_size < dcmd_size) {
902 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
903 dcmd_size);
904 return MFI_STAT_INVALID_PARAMETER;
905 }
906 info.continue_on_error = 1;
907 info.verbose = 1;
908 if (megasas_is_jbod(s)) {
909 info.expose_all_drives = 1;
910 }
911
912 dma_buf_read(&info, dcmd_size, &residual, &cmd->qsg,
913 MEMTXATTRS_UNSPECIFIED);
914 cmd->iov_size -= residual;
915 return MFI_STAT_OK;
916 }
917
918 static int megasas_dcmd_get_fw_time(MegasasState *s, MegasasCmd *cmd)
919 {
920 uint64_t fw_time;
921 size_t dcmd_size = sizeof(fw_time);
922 dma_addr_t residual;
923
924 fw_time = cpu_to_le64(megasas_fw_time());
925
926 dma_buf_read(&fw_time, dcmd_size, &residual, &cmd->qsg,
927 MEMTXATTRS_UNSPECIFIED);
928 cmd->iov_size -= residual;
929 return MFI_STAT_OK;
930 }
931
932 static int megasas_dcmd_set_fw_time(MegasasState *s, MegasasCmd *cmd)
933 {
934 uint64_t fw_time;
935
936 /* This is a dummy; setting of firmware time is not allowed */
937 memcpy(&fw_time, cmd->frame->dcmd.mbox, sizeof(fw_time));
938
939 trace_megasas_dcmd_set_fw_time(cmd->index, fw_time);
940 fw_time = cpu_to_le64(megasas_fw_time());
941 return MFI_STAT_OK;
942 }
943
944 static int megasas_event_info(MegasasState *s, MegasasCmd *cmd)
945 {
946 struct mfi_evt_log_state info;
947 size_t dcmd_size = sizeof(info);
948 dma_addr_t residual;
949
950 memset(&info, 0, dcmd_size);
951
952 info.newest_seq_num = cpu_to_le32(s->event_count);
953 info.shutdown_seq_num = cpu_to_le32(s->shutdown_event);
954 info.boot_seq_num = cpu_to_le32(s->boot_event);
955
956 dma_buf_read(&info, dcmd_size, &residual, &cmd->qsg,
957 MEMTXATTRS_UNSPECIFIED);
958 cmd->iov_size -= residual;
959 return MFI_STAT_OK;
960 }
961
962 static int megasas_event_wait(MegasasState *s, MegasasCmd *cmd)
963 {
964 union mfi_evt event;
965
966 if (cmd->iov_size < sizeof(struct mfi_evt_detail)) {
967 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
968 sizeof(struct mfi_evt_detail));
969 return MFI_STAT_INVALID_PARAMETER;
970 }
971 s->event_count = cpu_to_le32(cmd->frame->dcmd.mbox[0]);
972 event.word = cpu_to_le32(cmd->frame->dcmd.mbox[4]);
973 s->event_locale = event.members.locale;
974 s->event_class = event.members.class;
975 s->event_cmd = cmd;
976 /* Decrease busy count; event frame doesn't count here */
977 s->busy--;
978 cmd->iov_size = sizeof(struct mfi_evt_detail);
979 return MFI_STAT_INVALID_STATUS;
980 }
981
982 static int megasas_dcmd_pd_get_list(MegasasState *s, MegasasCmd *cmd)
983 {
984 struct mfi_pd_list info = {};
985 BusChild *kid;
986 uint32_t offset, dcmd_limit, num_pd_disks = 0, max_pd_disks;
987 dma_addr_t residual;
988
989 offset = 8;
990 dcmd_limit = offset + sizeof(struct mfi_pd_address);
991 if (cmd->iov_size < dcmd_limit) {
992 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
993 dcmd_limit);
994 return MFI_STAT_INVALID_PARAMETER;
995 }
996
997 max_pd_disks = (cmd->iov_size - offset) / sizeof(struct mfi_pd_address);
998 if (max_pd_disks > MFI_MAX_SYS_PDS) {
999 max_pd_disks = MFI_MAX_SYS_PDS;
1000 }
1001 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1002 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
1003 uint16_t pd_id;
1004
1005 if (num_pd_disks >= max_pd_disks)
1006 break;
1007
1008 pd_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
1009 info.addr[num_pd_disks].device_id = cpu_to_le16(pd_id);
1010 info.addr[num_pd_disks].encl_device_id = 0xFFFF;
1011 info.addr[num_pd_disks].encl_index = 0;
1012 info.addr[num_pd_disks].slot_number = sdev->id & 0xFF;
1013 info.addr[num_pd_disks].scsi_dev_type = sdev->type;
1014 info.addr[num_pd_disks].connect_port_bitmap = 0x1;
1015 info.addr[num_pd_disks].sas_addr[0] =
1016 cpu_to_le64(megasas_get_sata_addr(pd_id));
1017 num_pd_disks++;
1018 offset += sizeof(struct mfi_pd_address);
1019 }
1020 trace_megasas_dcmd_pd_get_list(cmd->index, num_pd_disks,
1021 max_pd_disks, offset);
1022
1023 info.size = cpu_to_le32(offset);
1024 info.count = cpu_to_le32(num_pd_disks);
1025
1026 dma_buf_read(&info, offset, &residual, &cmd->qsg,
1027 MEMTXATTRS_UNSPECIFIED);
1028 cmd->iov_size -= residual;
1029 return MFI_STAT_OK;
1030 }
1031
1032 static int megasas_dcmd_pd_list_query(MegasasState *s, MegasasCmd *cmd)
1033 {
1034 uint16_t flags;
1035
1036 /* mbox0 contains flags */
1037 flags = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1038 trace_megasas_dcmd_pd_list_query(cmd->index, flags);
1039 if (flags == MR_PD_QUERY_TYPE_ALL ||
1040 megasas_is_jbod(s)) {
1041 return megasas_dcmd_pd_get_list(s, cmd);
1042 }
1043
1044 return MFI_STAT_OK;
1045 }
1046
1047 static int megasas_pd_get_info_submit(SCSIDevice *sdev, int lun,
1048 MegasasCmd *cmd)
1049 {
1050 struct mfi_pd_info *info = cmd->iov_buf;
1051 size_t dcmd_size = sizeof(struct mfi_pd_info);
1052 uint64_t pd_size;
1053 uint16_t pd_id = ((sdev->id & 0xFF) << 8) | (lun & 0xFF);
1054 uint8_t cmdbuf[6];
1055 size_t len;
1056 dma_addr_t residual;
1057
1058 if (!cmd->iov_buf) {
1059 cmd->iov_buf = g_malloc0(dcmd_size);
1060 info = cmd->iov_buf;
1061 info->inquiry_data[0] = 0x7f; /* Force PQual 0x3, PType 0x1f */
1062 info->vpd_page83[0] = 0x7f;
1063 megasas_setup_inquiry(cmdbuf, 0, sizeof(info->inquiry_data));
1064 cmd->req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, sizeof(cmdbuf), cmd);
1065 if (!cmd->req) {
1066 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1067 "PD get info std inquiry");
1068 g_free(cmd->iov_buf);
1069 cmd->iov_buf = NULL;
1070 return MFI_STAT_FLASH_ALLOC_FAIL;
1071 }
1072 trace_megasas_dcmd_internal_submit(cmd->index,
1073 "PD get info std inquiry", lun);
1074 len = scsi_req_enqueue(cmd->req);
1075 if (len > 0) {
1076 cmd->iov_size = len;
1077 scsi_req_continue(cmd->req);
1078 }
1079 return MFI_STAT_INVALID_STATUS;
1080 } else if (info->inquiry_data[0] != 0x7f && info->vpd_page83[0] == 0x7f) {
1081 megasas_setup_inquiry(cmdbuf, 0x83, sizeof(info->vpd_page83));
1082 cmd->req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, sizeof(cmdbuf), cmd);
1083 if (!cmd->req) {
1084 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1085 "PD get info vpd inquiry");
1086 return MFI_STAT_FLASH_ALLOC_FAIL;
1087 }
1088 trace_megasas_dcmd_internal_submit(cmd->index,
1089 "PD get info vpd inquiry", lun);
1090 len = scsi_req_enqueue(cmd->req);
1091 if (len > 0) {
1092 cmd->iov_size = len;
1093 scsi_req_continue(cmd->req);
1094 }
1095 return MFI_STAT_INVALID_STATUS;
1096 }
1097 /* Finished, set FW state */
1098 if ((info->inquiry_data[0] >> 5) == 0) {
1099 if (megasas_is_jbod(cmd->state)) {
1100 info->fw_state = cpu_to_le16(MFI_PD_STATE_SYSTEM);
1101 } else {
1102 info->fw_state = cpu_to_le16(MFI_PD_STATE_ONLINE);
1103 }
1104 } else {
1105 info->fw_state = cpu_to_le16(MFI_PD_STATE_OFFLINE);
1106 }
1107
1108 info->ref.v.device_id = cpu_to_le16(pd_id);
1109 info->state.ddf.pd_type = cpu_to_le16(MFI_PD_DDF_TYPE_IN_VD|
1110 MFI_PD_DDF_TYPE_INTF_SAS);
1111 blk_get_geometry(sdev->conf.blk, &pd_size);
1112 info->raw_size = cpu_to_le64(pd_size);
1113 info->non_coerced_size = cpu_to_le64(pd_size);
1114 info->coerced_size = cpu_to_le64(pd_size);
1115 info->encl_device_id = 0xFFFF;
1116 info->slot_number = (sdev->id & 0xFF);
1117 info->path_info.count = 1;
1118 info->path_info.sas_addr[0] =
1119 cpu_to_le64(megasas_get_sata_addr(pd_id));
1120 info->connected_port_bitmap = 0x1;
1121 info->device_speed = 1;
1122 info->link_speed = 1;
1123 dma_buf_read(cmd->iov_buf, dcmd_size, &residual, &cmd->qsg,
1124 MEMTXATTRS_UNSPECIFIED);
1125 cmd->iov_size -= residual;
1126 g_free(cmd->iov_buf);
1127 cmd->iov_size = dcmd_size - residual;
1128 cmd->iov_buf = NULL;
1129 return MFI_STAT_OK;
1130 }
1131
1132 static int megasas_dcmd_pd_get_info(MegasasState *s, MegasasCmd *cmd)
1133 {
1134 size_t dcmd_size = sizeof(struct mfi_pd_info);
1135 uint16_t pd_id;
1136 uint8_t target_id, lun_id;
1137 SCSIDevice *sdev = NULL;
1138 int retval = MFI_STAT_DEVICE_NOT_FOUND;
1139
1140 if (cmd->iov_size < dcmd_size) {
1141 return MFI_STAT_INVALID_PARAMETER;
1142 }
1143
1144 /* mbox0 has the ID */
1145 pd_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1146 target_id = (pd_id >> 8) & 0xFF;
1147 lun_id = pd_id & 0xFF;
1148 sdev = scsi_device_find(&s->bus, 0, target_id, lun_id);
1149 trace_megasas_dcmd_pd_get_info(cmd->index, pd_id);
1150
1151 if (sdev) {
1152 /* Submit inquiry */
1153 retval = megasas_pd_get_info_submit(sdev, pd_id, cmd);
1154 }
1155
1156 return retval;
1157 }
1158
1159 static int megasas_dcmd_ld_get_list(MegasasState *s, MegasasCmd *cmd)
1160 {
1161 struct mfi_ld_list info;
1162 size_t dcmd_size = sizeof(info);
1163 dma_addr_t residual;
1164 uint32_t num_ld_disks = 0, max_ld_disks;
1165 uint64_t ld_size;
1166 BusChild *kid;
1167
1168 memset(&info, 0, dcmd_size);
1169 if (cmd->iov_size > dcmd_size) {
1170 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1171 dcmd_size);
1172 return MFI_STAT_INVALID_PARAMETER;
1173 }
1174
1175 max_ld_disks = (cmd->iov_size - 8) / 16;
1176 if (megasas_is_jbod(s)) {
1177 max_ld_disks = 0;
1178 }
1179 if (max_ld_disks > MFI_MAX_LD) {
1180 max_ld_disks = MFI_MAX_LD;
1181 }
1182 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1183 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
1184
1185 if (num_ld_disks >= max_ld_disks) {
1186 break;
1187 }
1188 /* Logical device size is in blocks */
1189 blk_get_geometry(sdev->conf.blk, &ld_size);
1190 info.ld_list[num_ld_disks].ld.v.target_id = sdev->id;
1191 info.ld_list[num_ld_disks].state = MFI_LD_STATE_OPTIMAL;
1192 info.ld_list[num_ld_disks].size = cpu_to_le64(ld_size);
1193 num_ld_disks++;
1194 }
1195 info.ld_count = cpu_to_le32(num_ld_disks);
1196 trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks);
1197
1198 dma_buf_read(&info, dcmd_size, &residual, &cmd->qsg,
1199 MEMTXATTRS_UNSPECIFIED);
1200 cmd->iov_size = dcmd_size - residual;
1201 return MFI_STAT_OK;
1202 }
1203
1204 static int megasas_dcmd_ld_list_query(MegasasState *s, MegasasCmd *cmd)
1205 {
1206 uint16_t flags;
1207 struct mfi_ld_targetid_list info;
1208 size_t dcmd_size = sizeof(info);
1209 dma_addr_t residual;
1210 uint32_t num_ld_disks = 0, max_ld_disks = s->fw_luns;
1211 BusChild *kid;
1212
1213 /* mbox0 contains flags */
1214 flags = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1215 trace_megasas_dcmd_ld_list_query(cmd->index, flags);
1216 if (flags != MR_LD_QUERY_TYPE_ALL &&
1217 flags != MR_LD_QUERY_TYPE_EXPOSED_TO_HOST) {
1218 max_ld_disks = 0;
1219 }
1220
1221 memset(&info, 0, dcmd_size);
1222 if (cmd->iov_size < 12) {
1223 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1224 dcmd_size);
1225 return MFI_STAT_INVALID_PARAMETER;
1226 }
1227 dcmd_size = sizeof(uint32_t) * 2 + 3;
1228 max_ld_disks = cmd->iov_size - dcmd_size;
1229 if (megasas_is_jbod(s)) {
1230 max_ld_disks = 0;
1231 }
1232 if (max_ld_disks > MFI_MAX_LD) {
1233 max_ld_disks = MFI_MAX_LD;
1234 }
1235 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1236 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
1237
1238 if (num_ld_disks >= max_ld_disks) {
1239 break;
1240 }
1241 info.targetid[num_ld_disks] = sdev->lun;
1242 num_ld_disks++;
1243 dcmd_size++;
1244 }
1245 info.ld_count = cpu_to_le32(num_ld_disks);
1246 info.size = dcmd_size;
1247 trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks);
1248
1249 dma_buf_read(&info, dcmd_size, &residual, &cmd->qsg,
1250 MEMTXATTRS_UNSPECIFIED);
1251 cmd->iov_size = dcmd_size - residual;
1252 return MFI_STAT_OK;
1253 }
1254
1255 static int megasas_ld_get_info_submit(SCSIDevice *sdev, int lun,
1256 MegasasCmd *cmd)
1257 {
1258 struct mfi_ld_info *info = cmd->iov_buf;
1259 size_t dcmd_size = sizeof(struct mfi_ld_info);
1260 uint8_t cdb[6];
1261 ssize_t len;
1262 dma_addr_t residual;
1263 uint16_t sdev_id = ((sdev->id & 0xFF) << 8) | (lun & 0xFF);
1264 uint64_t ld_size;
1265
1266 if (!cmd->iov_buf) {
1267 cmd->iov_buf = g_malloc0(dcmd_size);
1268 info = cmd->iov_buf;
1269 megasas_setup_inquiry(cdb, 0x83, sizeof(info->vpd_page83));
1270 cmd->req = scsi_req_new(sdev, cmd->index, lun, cdb, sizeof(cdb), cmd);
1271 if (!cmd->req) {
1272 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1273 "LD get info vpd inquiry");
1274 g_free(cmd->iov_buf);
1275 cmd->iov_buf = NULL;
1276 return MFI_STAT_FLASH_ALLOC_FAIL;
1277 }
1278 trace_megasas_dcmd_internal_submit(cmd->index,
1279 "LD get info vpd inquiry", lun);
1280 len = scsi_req_enqueue(cmd->req);
1281 if (len > 0) {
1282 cmd->iov_size = len;
1283 scsi_req_continue(cmd->req);
1284 }
1285 return MFI_STAT_INVALID_STATUS;
1286 }
1287
1288 info->ld_config.params.state = MFI_LD_STATE_OPTIMAL;
1289 info->ld_config.properties.ld.v.target_id = lun;
1290 info->ld_config.params.stripe_size = 3;
1291 info->ld_config.params.num_drives = 1;
1292 info->ld_config.params.is_consistent = 1;
1293 /* Logical device size is in blocks */
1294 blk_get_geometry(sdev->conf.blk, &ld_size);
1295 info->size = cpu_to_le64(ld_size);
1296 memset(info->ld_config.span, 0, sizeof(info->ld_config.span));
1297 info->ld_config.span[0].start_block = 0;
1298 info->ld_config.span[0].num_blocks = info->size;
1299 info->ld_config.span[0].array_ref = cpu_to_le16(sdev_id);
1300
1301 dma_buf_read(cmd->iov_buf, dcmd_size, &residual, &cmd->qsg,
1302 MEMTXATTRS_UNSPECIFIED);
1303 g_free(cmd->iov_buf);
1304 cmd->iov_size = dcmd_size - residual;
1305 cmd->iov_buf = NULL;
1306 return MFI_STAT_OK;
1307 }
1308
1309 static int megasas_dcmd_ld_get_info(MegasasState *s, MegasasCmd *cmd)
1310 {
1311 struct mfi_ld_info info;
1312 size_t dcmd_size = sizeof(info);
1313 uint16_t ld_id;
1314 uint32_t max_ld_disks = s->fw_luns;
1315 SCSIDevice *sdev = NULL;
1316 int retval = MFI_STAT_DEVICE_NOT_FOUND;
1317
1318 if (cmd->iov_size < dcmd_size) {
1319 return MFI_STAT_INVALID_PARAMETER;
1320 }
1321
1322 /* mbox0 has the ID */
1323 ld_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1324 trace_megasas_dcmd_ld_get_info(cmd->index, ld_id);
1325
1326 if (megasas_is_jbod(s)) {
1327 return MFI_STAT_DEVICE_NOT_FOUND;
1328 }
1329
1330 if (ld_id < max_ld_disks) {
1331 sdev = scsi_device_find(&s->bus, 0, ld_id, 0);
1332 }
1333
1334 if (sdev) {
1335 retval = megasas_ld_get_info_submit(sdev, ld_id, cmd);
1336 }
1337
1338 return retval;
1339 }
1340
1341 static int megasas_dcmd_cfg_read(MegasasState *s, MegasasCmd *cmd)
1342 {
1343 uint8_t data[4096] = { 0 };
1344 struct mfi_config_data *info;
1345 int num_pd_disks = 0, array_offset, ld_offset;
1346 BusChild *kid;
1347 dma_addr_t residual;
1348
1349 if (cmd->iov_size > 4096) {
1350 return MFI_STAT_INVALID_PARAMETER;
1351 }
1352
1353 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1354 num_pd_disks++;
1355 }
1356 info = (struct mfi_config_data *)&data;
1357 /*
1358 * Array mapping:
1359 * - One array per SCSI device
1360 * - One logical drive per SCSI device
1361 * spanning the entire device
1362 */
1363 info->array_count = num_pd_disks;
1364 info->array_size = sizeof(struct mfi_array) * num_pd_disks;
1365 info->log_drv_count = num_pd_disks;
1366 info->log_drv_size = sizeof(struct mfi_ld_config) * num_pd_disks;
1367 info->spares_count = 0;
1368 info->spares_size = sizeof(struct mfi_spare);
1369 info->size = sizeof(struct mfi_config_data) + info->array_size +
1370 info->log_drv_size;
1371 if (info->size > 4096) {
1372 return MFI_STAT_INVALID_PARAMETER;
1373 }
1374
1375 array_offset = sizeof(struct mfi_config_data);
1376 ld_offset = array_offset + sizeof(struct mfi_array) * num_pd_disks;
1377
1378 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1379 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
1380 uint16_t sdev_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
1381 struct mfi_array *array;
1382 struct mfi_ld_config *ld;
1383 uint64_t pd_size;
1384 int i;
1385
1386 array = (struct mfi_array *)(data + array_offset);
1387 blk_get_geometry(sdev->conf.blk, &pd_size);
1388 array->size = cpu_to_le64(pd_size);
1389 array->num_drives = 1;
1390 array->array_ref = cpu_to_le16(sdev_id);
1391 array->pd[0].ref.v.device_id = cpu_to_le16(sdev_id);
1392 array->pd[0].ref.v.seq_num = 0;
1393 array->pd[0].fw_state = MFI_PD_STATE_ONLINE;
1394 array->pd[0].encl.pd = 0xFF;
1395 array->pd[0].encl.slot = (sdev->id & 0xFF);
1396 for (i = 1; i < MFI_MAX_ROW_SIZE; i++) {
1397 array->pd[i].ref.v.device_id = 0xFFFF;
1398 array->pd[i].ref.v.seq_num = 0;
1399 array->pd[i].fw_state = MFI_PD_STATE_UNCONFIGURED_GOOD;
1400 array->pd[i].encl.pd = 0xFF;
1401 array->pd[i].encl.slot = 0xFF;
1402 }
1403 array_offset += sizeof(struct mfi_array);
1404 ld = (struct mfi_ld_config *)(data + ld_offset);
1405 memset(ld, 0, sizeof(struct mfi_ld_config));
1406 ld->properties.ld.v.target_id = sdev->id;
1407 ld->properties.default_cache_policy = MR_LD_CACHE_READ_AHEAD |
1408 MR_LD_CACHE_READ_ADAPTIVE;
1409 ld->properties.current_cache_policy = MR_LD_CACHE_READ_AHEAD |
1410 MR_LD_CACHE_READ_ADAPTIVE;
1411 ld->params.state = MFI_LD_STATE_OPTIMAL;
1412 ld->params.stripe_size = 3;
1413 ld->params.num_drives = 1;
1414 ld->params.span_depth = 1;
1415 ld->params.is_consistent = 1;
1416 ld->span[0].start_block = 0;
1417 ld->span[0].num_blocks = cpu_to_le64(pd_size);
1418 ld->span[0].array_ref = cpu_to_le16(sdev_id);
1419 ld_offset += sizeof(struct mfi_ld_config);
1420 }
1421
1422 dma_buf_read(data, info->size, &residual, &cmd->qsg,
1423 MEMTXATTRS_UNSPECIFIED);
1424 cmd->iov_size -= residual;
1425 return MFI_STAT_OK;
1426 }
1427
1428 static int megasas_dcmd_get_properties(MegasasState *s, MegasasCmd *cmd)
1429 {
1430 struct mfi_ctrl_props info = {};
1431 size_t dcmd_size = sizeof(info);
1432 dma_addr_t residual;
1433
1434 if (cmd->iov_size < dcmd_size) {
1435 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1436 dcmd_size);
1437 return MFI_STAT_INVALID_PARAMETER;
1438 }
1439 info.pred_fail_poll_interval = cpu_to_le16(300);
1440 info.intr_throttle_cnt = cpu_to_le16(16);
1441 info.intr_throttle_timeout = cpu_to_le16(50);
1442 info.rebuild_rate = 30;
1443 info.patrol_read_rate = 30;
1444 info.bgi_rate = 30;
1445 info.cc_rate = 30;
1446 info.recon_rate = 30;
1447 info.cache_flush_interval = 4;
1448 info.spinup_drv_cnt = 2;
1449 info.spinup_delay = 6;
1450 info.ecc_bucket_size = 15;
1451 info.ecc_bucket_leak_rate = cpu_to_le16(1440);
1452 info.expose_encl_devices = 1;
1453
1454 dma_buf_read(&info, dcmd_size, &residual, &cmd->qsg,
1455 MEMTXATTRS_UNSPECIFIED);
1456 cmd->iov_size -= residual;
1457 return MFI_STAT_OK;
1458 }
1459
1460 static int megasas_cache_flush(MegasasState *s, MegasasCmd *cmd)
1461 {
1462 blk_drain_all();
1463 return MFI_STAT_OK;
1464 }
1465
1466 static int megasas_ctrl_shutdown(MegasasState *s, MegasasCmd *cmd)
1467 {
1468 s->fw_state = MFI_FWSTATE_READY;
1469 return MFI_STAT_OK;
1470 }
1471
1472 /* Some implementations use CLUSTER RESET LD to simulate a device reset */
1473 static int megasas_cluster_reset_ld(MegasasState *s, MegasasCmd *cmd)
1474 {
1475 uint16_t target_id;
1476 int i;
1477
1478 /* mbox0 contains the device index */
1479 target_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1480 trace_megasas_dcmd_reset_ld(cmd->index, target_id);
1481 for (i = 0; i < s->fw_cmds; i++) {
1482 MegasasCmd *tmp_cmd = &s->frames[i];
1483 if (tmp_cmd->req && tmp_cmd->req->dev->id == target_id) {
1484 SCSIDevice *d = tmp_cmd->req->dev;
1485 device_cold_reset(&d->qdev);
1486 }
1487 }
1488 return MFI_STAT_OK;
1489 }
1490
1491 static int megasas_dcmd_set_properties(MegasasState *s, MegasasCmd *cmd)
1492 {
1493 struct mfi_ctrl_props info;
1494 size_t dcmd_size = sizeof(info);
1495
1496 if (cmd->iov_size < dcmd_size) {
1497 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1498 dcmd_size);
1499 return MFI_STAT_INVALID_PARAMETER;
1500 }
1501 dma_buf_write(&info, dcmd_size, NULL, &cmd->qsg, MEMTXATTRS_UNSPECIFIED);
1502 trace_megasas_dcmd_unsupported(cmd->index, cmd->iov_size);
1503 return MFI_STAT_OK;
1504 }
1505
1506 static int megasas_dcmd_dummy(MegasasState *s, MegasasCmd *cmd)
1507 {
1508 trace_megasas_dcmd_dummy(cmd->index, cmd->iov_size);
1509 return MFI_STAT_OK;
1510 }
1511
1512 static const struct dcmd_cmd_tbl_t {
1513 int opcode;
1514 const char *desc;
1515 int (*func)(MegasasState *s, MegasasCmd *cmd);
1516 } dcmd_cmd_tbl[] = {
1517 { MFI_DCMD_CTRL_MFI_HOST_MEM_ALLOC, "CTRL_HOST_MEM_ALLOC",
1518 megasas_dcmd_dummy },
1519 { MFI_DCMD_CTRL_GET_INFO, "CTRL_GET_INFO",
1520 megasas_ctrl_get_info },
1521 { MFI_DCMD_CTRL_GET_PROPERTIES, "CTRL_GET_PROPERTIES",
1522 megasas_dcmd_get_properties },
1523 { MFI_DCMD_CTRL_SET_PROPERTIES, "CTRL_SET_PROPERTIES",
1524 megasas_dcmd_set_properties },
1525 { MFI_DCMD_CTRL_ALARM_GET, "CTRL_ALARM_GET",
1526 megasas_dcmd_dummy },
1527 { MFI_DCMD_CTRL_ALARM_ENABLE, "CTRL_ALARM_ENABLE",
1528 megasas_dcmd_dummy },
1529 { MFI_DCMD_CTRL_ALARM_DISABLE, "CTRL_ALARM_DISABLE",
1530 megasas_dcmd_dummy },
1531 { MFI_DCMD_CTRL_ALARM_SILENCE, "CTRL_ALARM_SILENCE",
1532 megasas_dcmd_dummy },
1533 { MFI_DCMD_CTRL_ALARM_TEST, "CTRL_ALARM_TEST",
1534 megasas_dcmd_dummy },
1535 { MFI_DCMD_CTRL_EVENT_GETINFO, "CTRL_EVENT_GETINFO",
1536 megasas_event_info },
1537 { MFI_DCMD_CTRL_EVENT_GET, "CTRL_EVENT_GET",
1538 megasas_dcmd_dummy },
1539 { MFI_DCMD_CTRL_EVENT_WAIT, "CTRL_EVENT_WAIT",
1540 megasas_event_wait },
1541 { MFI_DCMD_CTRL_SHUTDOWN, "CTRL_SHUTDOWN",
1542 megasas_ctrl_shutdown },
1543 { MFI_DCMD_HIBERNATE_STANDBY, "CTRL_STANDBY",
1544 megasas_dcmd_dummy },
1545 { MFI_DCMD_CTRL_GET_TIME, "CTRL_GET_TIME",
1546 megasas_dcmd_get_fw_time },
1547 { MFI_DCMD_CTRL_SET_TIME, "CTRL_SET_TIME",
1548 megasas_dcmd_set_fw_time },
1549 { MFI_DCMD_CTRL_BIOS_DATA_GET, "CTRL_BIOS_DATA_GET",
1550 megasas_dcmd_get_bios_info },
1551 { MFI_DCMD_CTRL_FACTORY_DEFAULTS, "CTRL_FACTORY_DEFAULTS",
1552 megasas_dcmd_dummy },
1553 { MFI_DCMD_CTRL_MFC_DEFAULTS_GET, "CTRL_MFC_DEFAULTS_GET",
1554 megasas_mfc_get_defaults },
1555 { MFI_DCMD_CTRL_MFC_DEFAULTS_SET, "CTRL_MFC_DEFAULTS_SET",
1556 megasas_dcmd_dummy },
1557 { MFI_DCMD_CTRL_CACHE_FLUSH, "CTRL_CACHE_FLUSH",
1558 megasas_cache_flush },
1559 { MFI_DCMD_PD_GET_LIST, "PD_GET_LIST",
1560 megasas_dcmd_pd_get_list },
1561 { MFI_DCMD_PD_LIST_QUERY, "PD_LIST_QUERY",
1562 megasas_dcmd_pd_list_query },
1563 { MFI_DCMD_PD_GET_INFO, "PD_GET_INFO",
1564 megasas_dcmd_pd_get_info },
1565 { MFI_DCMD_PD_STATE_SET, "PD_STATE_SET",
1566 megasas_dcmd_dummy },
1567 { MFI_DCMD_PD_REBUILD, "PD_REBUILD",
1568 megasas_dcmd_dummy },
1569 { MFI_DCMD_PD_BLINK, "PD_BLINK",
1570 megasas_dcmd_dummy },
1571 { MFI_DCMD_PD_UNBLINK, "PD_UNBLINK",
1572 megasas_dcmd_dummy },
1573 { MFI_DCMD_LD_GET_LIST, "LD_GET_LIST",
1574 megasas_dcmd_ld_get_list},
1575 { MFI_DCMD_LD_LIST_QUERY, "LD_LIST_QUERY",
1576 megasas_dcmd_ld_list_query },
1577 { MFI_DCMD_LD_GET_INFO, "LD_GET_INFO",
1578 megasas_dcmd_ld_get_info },
1579 { MFI_DCMD_LD_GET_PROP, "LD_GET_PROP",
1580 megasas_dcmd_dummy },
1581 { MFI_DCMD_LD_SET_PROP, "LD_SET_PROP",
1582 megasas_dcmd_dummy },
1583 { MFI_DCMD_LD_DELETE, "LD_DELETE",
1584 megasas_dcmd_dummy },
1585 { MFI_DCMD_CFG_READ, "CFG_READ",
1586 megasas_dcmd_cfg_read },
1587 { MFI_DCMD_CFG_ADD, "CFG_ADD",
1588 megasas_dcmd_dummy },
1589 { MFI_DCMD_CFG_CLEAR, "CFG_CLEAR",
1590 megasas_dcmd_dummy },
1591 { MFI_DCMD_CFG_FOREIGN_READ, "CFG_FOREIGN_READ",
1592 megasas_dcmd_dummy },
1593 { MFI_DCMD_CFG_FOREIGN_IMPORT, "CFG_FOREIGN_IMPORT",
1594 megasas_dcmd_dummy },
1595 { MFI_DCMD_BBU_STATUS, "BBU_STATUS",
1596 megasas_dcmd_dummy },
1597 { MFI_DCMD_BBU_CAPACITY_INFO, "BBU_CAPACITY_INFO",
1598 megasas_dcmd_dummy },
1599 { MFI_DCMD_BBU_DESIGN_INFO, "BBU_DESIGN_INFO",
1600 megasas_dcmd_dummy },
1601 { MFI_DCMD_BBU_PROP_GET, "BBU_PROP_GET",
1602 megasas_dcmd_dummy },
1603 { MFI_DCMD_CLUSTER, "CLUSTER",
1604 megasas_dcmd_dummy },
1605 { MFI_DCMD_CLUSTER_RESET_ALL, "CLUSTER_RESET_ALL",
1606 megasas_dcmd_dummy },
1607 { MFI_DCMD_CLUSTER_RESET_LD, "CLUSTER_RESET_LD",
1608 megasas_cluster_reset_ld },
1609 { -1, NULL, NULL }
1610 };
1611
1612 static int megasas_handle_dcmd(MegasasState *s, MegasasCmd *cmd)
1613 {
1614 int retval = 0;
1615 size_t len;
1616 const struct dcmd_cmd_tbl_t *cmdptr = dcmd_cmd_tbl;
1617
1618 cmd->dcmd_opcode = le32_to_cpu(cmd->frame->dcmd.opcode);
1619 trace_megasas_handle_dcmd(cmd->index, cmd->dcmd_opcode);
1620 if (megasas_map_dcmd(s, cmd) < 0) {
1621 return MFI_STAT_MEMORY_NOT_AVAILABLE;
1622 }
1623 while (cmdptr->opcode != -1 && cmdptr->opcode != cmd->dcmd_opcode) {
1624 cmdptr++;
1625 }
1626 len = cmd->iov_size;
1627 if (cmdptr->opcode == -1) {
1628 trace_megasas_dcmd_unhandled(cmd->index, cmd->dcmd_opcode, len);
1629 retval = megasas_dcmd_dummy(s, cmd);
1630 } else {
1631 trace_megasas_dcmd_enter(cmd->index, cmdptr->desc, len);
1632 retval = cmdptr->func(s, cmd);
1633 }
1634 if (retval != MFI_STAT_INVALID_STATUS) {
1635 megasas_finish_dcmd(cmd, len);
1636 }
1637 return retval;
1638 }
1639
1640 static int megasas_finish_internal_dcmd(MegasasCmd *cmd,
1641 SCSIRequest *req, dma_addr_t residual)
1642 {
1643 int retval = MFI_STAT_OK;
1644 int lun = req->lun;
1645
1646 trace_megasas_dcmd_internal_finish(cmd->index, cmd->dcmd_opcode, lun);
1647 cmd->iov_size -= residual;
1648 switch (cmd->dcmd_opcode) {
1649 case MFI_DCMD_PD_GET_INFO:
1650 retval = megasas_pd_get_info_submit(req->dev, lun, cmd);
1651 break;
1652 case MFI_DCMD_LD_GET_INFO:
1653 retval = megasas_ld_get_info_submit(req->dev, lun, cmd);
1654 break;
1655 default:
1656 trace_megasas_dcmd_internal_invalid(cmd->index, cmd->dcmd_opcode);
1657 retval = MFI_STAT_INVALID_DCMD;
1658 break;
1659 }
1660 if (retval != MFI_STAT_INVALID_STATUS) {
1661 megasas_finish_dcmd(cmd, cmd->iov_size);
1662 }
1663 return retval;
1664 }
1665
1666 static int megasas_enqueue_req(MegasasCmd *cmd, bool is_write)
1667 {
1668 int len;
1669
1670 len = scsi_req_enqueue(cmd->req);
1671 if (len < 0) {
1672 len = -len;
1673 }
1674 if (len > 0) {
1675 if (len > cmd->iov_size) {
1676 if (is_write) {
1677 trace_megasas_iov_write_overflow(cmd->index, len,
1678 cmd->iov_size);
1679 } else {
1680 trace_megasas_iov_read_overflow(cmd->index, len,
1681 cmd->iov_size);
1682 }
1683 }
1684 if (len < cmd->iov_size) {
1685 if (is_write) {
1686 trace_megasas_iov_write_underflow(cmd->index, len,
1687 cmd->iov_size);
1688 } else {
1689 trace_megasas_iov_read_underflow(cmd->index, len,
1690 cmd->iov_size);
1691 }
1692 cmd->iov_size = len;
1693 }
1694 scsi_req_continue(cmd->req);
1695 }
1696 return len;
1697 }
1698
1699 static int megasas_handle_scsi(MegasasState *s, MegasasCmd *cmd,
1700 int frame_cmd)
1701 {
1702 uint8_t *cdb;
1703 int target_id, lun_id, cdb_len;
1704 bool is_write;
1705 struct SCSIDevice *sdev = NULL;
1706 bool is_logical = (frame_cmd == MFI_CMD_LD_SCSI_IO);
1707
1708 cdb = cmd->frame->pass.cdb;
1709 target_id = cmd->frame->header.target_id;
1710 lun_id = cmd->frame->header.lun_id;
1711 cdb_len = cmd->frame->header.cdb_len;
1712
1713 if (is_logical) {
1714 if (target_id >= MFI_MAX_LD || lun_id != 0) {
1715 trace_megasas_scsi_target_not_present(
1716 mfi_frame_desc(frame_cmd), is_logical, target_id, lun_id);
1717 return MFI_STAT_DEVICE_NOT_FOUND;
1718 }
1719 }
1720 sdev = scsi_device_find(&s->bus, 0, target_id, lun_id);
1721
1722 cmd->iov_size = le32_to_cpu(cmd->frame->header.data_len);
1723 trace_megasas_handle_scsi(mfi_frame_desc(frame_cmd), is_logical,
1724 target_id, lun_id, sdev, cmd->iov_size);
1725
1726 if (!sdev || (megasas_is_jbod(s) && is_logical)) {
1727 trace_megasas_scsi_target_not_present(
1728 mfi_frame_desc(frame_cmd), is_logical, target_id, lun_id);
1729 return MFI_STAT_DEVICE_NOT_FOUND;
1730 }
1731
1732 if (cdb_len > 16) {
1733 trace_megasas_scsi_invalid_cdb_len(
1734 mfi_frame_desc(frame_cmd), is_logical,
1735 target_id, lun_id, cdb_len);
1736 megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE));
1737 cmd->frame->header.scsi_status = CHECK_CONDITION;
1738 s->event_count++;
1739 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1740 }
1741
1742 if (megasas_map_sgl(s, cmd, &cmd->frame->pass.sgl)) {
1743 megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE));
1744 cmd->frame->header.scsi_status = CHECK_CONDITION;
1745 s->event_count++;
1746 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1747 }
1748
1749 cmd->req = scsi_req_new(sdev, cmd->index, lun_id, cdb, cdb_len, cmd);
1750 if (!cmd->req) {
1751 trace_megasas_scsi_req_alloc_failed(
1752 mfi_frame_desc(frame_cmd), target_id, lun_id);
1753 megasas_write_sense(cmd, SENSE_CODE(NO_SENSE));
1754 cmd->frame->header.scsi_status = BUSY;
1755 s->event_count++;
1756 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1757 }
1758
1759 is_write = (cmd->req->cmd.mode == SCSI_XFER_TO_DEV);
1760 if (cmd->iov_size) {
1761 if (is_write) {
1762 trace_megasas_scsi_write_start(cmd->index, cmd->iov_size);
1763 } else {
1764 trace_megasas_scsi_read_start(cmd->index, cmd->iov_size);
1765 }
1766 } else {
1767 trace_megasas_scsi_nodata(cmd->index);
1768 }
1769 megasas_enqueue_req(cmd, is_write);
1770 return MFI_STAT_INVALID_STATUS;
1771 }
1772
1773 static int megasas_handle_io(MegasasState *s, MegasasCmd *cmd, int frame_cmd)
1774 {
1775 uint32_t lba_count, lba_start_hi, lba_start_lo;
1776 uint64_t lba_start;
1777 bool is_write = (frame_cmd == MFI_CMD_LD_WRITE);
1778 uint8_t cdb[16];
1779 int len;
1780 struct SCSIDevice *sdev = NULL;
1781 int target_id, lun_id;
1782
1783 lba_count = le32_to_cpu(cmd->frame->io.header.data_len);
1784 lba_start_lo = le32_to_cpu(cmd->frame->io.lba_lo);
1785 lba_start_hi = le32_to_cpu(cmd->frame->io.lba_hi);
1786 lba_start = ((uint64_t)lba_start_hi << 32) | lba_start_lo;
1787
1788 target_id = cmd->frame->header.target_id;
1789 lun_id = cmd->frame->header.lun_id;
1790
1791 if (target_id < MFI_MAX_LD && lun_id == 0) {
1792 sdev = scsi_device_find(&s->bus, 0, target_id, lun_id);
1793 }
1794
1795 trace_megasas_handle_io(cmd->index,
1796 mfi_frame_desc(frame_cmd), target_id, lun_id,
1797 (unsigned long)lba_start, (unsigned long)lba_count);
1798 if (!sdev) {
1799 trace_megasas_io_target_not_present(cmd->index,
1800 mfi_frame_desc(frame_cmd), target_id, lun_id);
1801 return MFI_STAT_DEVICE_NOT_FOUND;
1802 }
1803
1804 cmd->iov_size = lba_count * sdev->blocksize;
1805 if (megasas_map_sgl(s, cmd, &cmd->frame->io.sgl)) {
1806 megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE));
1807 cmd->frame->header.scsi_status = CHECK_CONDITION;
1808 s->event_count++;
1809 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1810 }
1811
1812 megasas_encode_lba(cdb, lba_start, lba_count, is_write);
1813 cmd->req = scsi_req_new(sdev, cmd->index,
1814 lun_id, cdb, sizeof(cdb), cmd);
1815 if (!cmd->req) {
1816 trace_megasas_scsi_req_alloc_failed(
1817 mfi_frame_desc(frame_cmd), target_id, lun_id);
1818 megasas_write_sense(cmd, SENSE_CODE(NO_SENSE));
1819 cmd->frame->header.scsi_status = BUSY;
1820 s->event_count++;
1821 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1822 }
1823 len = megasas_enqueue_req(cmd, is_write);
1824 if (len > 0) {
1825 if (is_write) {
1826 trace_megasas_io_write_start(cmd->index, lba_start, lba_count, len);
1827 } else {
1828 trace_megasas_io_read_start(cmd->index, lba_start, lba_count, len);
1829 }
1830 }
1831 return MFI_STAT_INVALID_STATUS;
1832 }
1833
1834 static QEMUSGList *megasas_get_sg_list(SCSIRequest *req)
1835 {
1836 MegasasCmd *cmd = req->hba_private;
1837
1838 if (cmd->dcmd_opcode != -1) {
1839 return NULL;
1840 } else {
1841 return &cmd->qsg;
1842 }
1843 }
1844
1845 static void megasas_xfer_complete(SCSIRequest *req, uint32_t len)
1846 {
1847 MegasasCmd *cmd = req->hba_private;
1848 uint8_t *buf;
1849
1850 trace_megasas_io_complete(cmd->index, len);
1851
1852 if (cmd->dcmd_opcode != -1) {
1853 scsi_req_continue(req);
1854 return;
1855 }
1856
1857 buf = scsi_req_get_buf(req);
1858 if (cmd->dcmd_opcode == MFI_DCMD_PD_GET_INFO && cmd->iov_buf) {
1859 struct mfi_pd_info *info = cmd->iov_buf;
1860
1861 if (info->inquiry_data[0] == 0x7f) {
1862 memset(info->inquiry_data, 0, sizeof(info->inquiry_data));
1863 memcpy(info->inquiry_data, buf, len);
1864 } else if (info->vpd_page83[0] == 0x7f) {
1865 memset(info->vpd_page83, 0, sizeof(info->vpd_page83));
1866 memcpy(info->vpd_page83, buf, len);
1867 }
1868 scsi_req_continue(req);
1869 } else if (cmd->dcmd_opcode == MFI_DCMD_LD_GET_INFO) {
1870 struct mfi_ld_info *info = cmd->iov_buf;
1871
1872 if (cmd->iov_buf) {
1873 memcpy(info->vpd_page83, buf, sizeof(info->vpd_page83));
1874 scsi_req_continue(req);
1875 }
1876 }
1877 }
1878
1879 static void megasas_command_complete(SCSIRequest *req, size_t residual)
1880 {
1881 MegasasCmd *cmd = req->hba_private;
1882 uint8_t cmd_status = MFI_STAT_OK;
1883
1884 trace_megasas_command_complete(cmd->index, req->status, residual);
1885
1886 if (req->io_canceled) {
1887 return;
1888 }
1889
1890 if (cmd->dcmd_opcode != -1) {
1891 /*
1892 * Internal command complete
1893 */
1894 cmd_status = megasas_finish_internal_dcmd(cmd, req, residual);
1895 if (cmd_status == MFI_STAT_INVALID_STATUS) {
1896 return;
1897 }
1898 } else {
1899 trace_megasas_scsi_complete(cmd->index, req->status,
1900 cmd->iov_size, req->cmd.xfer);
1901 if (req->status != GOOD) {
1902 cmd_status = MFI_STAT_SCSI_DONE_WITH_ERROR;
1903 }
1904 if (req->status == CHECK_CONDITION) {
1905 megasas_copy_sense(cmd);
1906 }
1907
1908 cmd->frame->header.scsi_status = req->status;
1909 }
1910 cmd->frame->header.cmd_status = cmd_status;
1911 megasas_complete_command(cmd);
1912 }
1913
1914 static void megasas_command_cancelled(SCSIRequest *req)
1915 {
1916 MegasasCmd *cmd = req->hba_private;
1917
1918 if (!cmd) {
1919 return;
1920 }
1921 cmd->frame->header.cmd_status = MFI_STAT_SCSI_IO_FAILED;
1922 megasas_complete_command(cmd);
1923 }
1924
1925 static int megasas_handle_abort(MegasasState *s, MegasasCmd *cmd)
1926 {
1927 uint64_t abort_ctx = le64_to_cpu(cmd->frame->abort.abort_context);
1928 hwaddr abort_addr, addr_hi, addr_lo;
1929 MegasasCmd *abort_cmd;
1930
1931 addr_hi = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_hi);
1932 addr_lo = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_lo);
1933 abort_addr = ((uint64_t)addr_hi << 32) | addr_lo;
1934
1935 abort_cmd = megasas_lookup_frame(s, abort_addr);
1936 if (!abort_cmd) {
1937 trace_megasas_abort_no_cmd(cmd->index, abort_ctx);
1938 s->event_count++;
1939 return MFI_STAT_OK;
1940 }
1941 if (!megasas_use_queue64(s)) {
1942 abort_ctx &= (uint64_t)0xFFFFFFFF;
1943 }
1944 if (abort_cmd->context != abort_ctx) {
1945 trace_megasas_abort_invalid_context(cmd->index, abort_cmd->context,
1946 abort_cmd->index);
1947 s->event_count++;
1948 return MFI_STAT_ABORT_NOT_POSSIBLE;
1949 }
1950 trace_megasas_abort_frame(cmd->index, abort_cmd->index);
1951 megasas_abort_command(abort_cmd);
1952 if (!s->event_cmd || abort_cmd != s->event_cmd) {
1953 s->event_cmd = NULL;
1954 }
1955 s->event_count++;
1956 return MFI_STAT_OK;
1957 }
1958
1959 static void megasas_handle_frame(MegasasState *s, uint64_t frame_addr,
1960 uint32_t frame_count)
1961 {
1962 uint8_t frame_status = MFI_STAT_INVALID_CMD;
1963 uint64_t frame_context;
1964 int frame_cmd;
1965 MegasasCmd *cmd;
1966
1967 /*
1968 * Always read 64bit context, top bits will be
1969 * masked out if required in megasas_enqueue_frame()
1970 */
1971 frame_context = megasas_frame_get_context(s, frame_addr);
1972
1973 cmd = megasas_enqueue_frame(s, frame_addr, frame_context, frame_count);
1974 if (!cmd) {
1975 /* reply queue full */
1976 trace_megasas_frame_busy(frame_addr);
1977 megasas_frame_set_scsi_status(s, frame_addr, BUSY);
1978 megasas_frame_set_cmd_status(s, frame_addr, MFI_STAT_SCSI_DONE_WITH_ERROR);
1979 megasas_complete_frame(s, frame_context);
1980 s->event_count++;
1981 return;
1982 }
1983 frame_cmd = cmd->frame->header.frame_cmd;
1984 switch (frame_cmd) {
1985 case MFI_CMD_INIT:
1986 frame_status = megasas_init_firmware(s, cmd);
1987 break;
1988 case MFI_CMD_DCMD:
1989 frame_status = megasas_handle_dcmd(s, cmd);
1990 break;
1991 case MFI_CMD_ABORT:
1992 frame_status = megasas_handle_abort(s, cmd);
1993 break;
1994 case MFI_CMD_PD_SCSI_IO:
1995 case MFI_CMD_LD_SCSI_IO:
1996 frame_status = megasas_handle_scsi(s, cmd, frame_cmd);
1997 break;
1998 case MFI_CMD_LD_READ:
1999 case MFI_CMD_LD_WRITE:
2000 frame_status = megasas_handle_io(s, cmd, frame_cmd);
2001 break;
2002 default:
2003 trace_megasas_unhandled_frame_cmd(cmd->index, frame_cmd);
2004 s->event_count++;
2005 break;
2006 }
2007 if (frame_status != MFI_STAT_INVALID_STATUS) {
2008 if (cmd->frame) {
2009 cmd->frame->header.cmd_status = frame_status;
2010 } else {
2011 megasas_frame_set_cmd_status(s, frame_addr, frame_status);
2012 }
2013 megasas_unmap_frame(s, cmd);
2014 megasas_complete_frame(s, cmd->context);
2015 }
2016 }
2017
2018 static uint64_t megasas_mmio_read(void *opaque, hwaddr addr,
2019 unsigned size)
2020 {
2021 MegasasState *s = opaque;
2022 PCIDevice *pci_dev = PCI_DEVICE(s);
2023 MegasasBaseClass *base_class = MEGASAS_GET_CLASS(s);
2024 uint32_t retval = 0;
2025
2026 switch (addr) {
2027 case MFI_IDB:
2028 retval = 0;
2029 trace_megasas_mmio_readl("MFI_IDB", retval);
2030 break;
2031 case MFI_OMSG0:
2032 case MFI_OSP0:
2033 retval = (msix_present(pci_dev) ? MFI_FWSTATE_MSIX_SUPPORTED : 0) |
2034 (s->fw_state & MFI_FWSTATE_MASK) |
2035 ((s->fw_sge & 0xff) << 16) |
2036 (s->fw_cmds & 0xFFFF);
2037 trace_megasas_mmio_readl(addr == MFI_OMSG0 ? "MFI_OMSG0" : "MFI_OSP0",
2038 retval);
2039 break;
2040 case MFI_OSTS:
2041 if (megasas_intr_enabled(s) && s->doorbell) {
2042 retval = base_class->osts;
2043 }
2044 trace_megasas_mmio_readl("MFI_OSTS", retval);
2045 break;
2046 case MFI_OMSK:
2047 retval = s->intr_mask;
2048 trace_megasas_mmio_readl("MFI_OMSK", retval);
2049 break;
2050 case MFI_ODCR0:
2051 retval = s->doorbell ? 1 : 0;
2052 trace_megasas_mmio_readl("MFI_ODCR0", retval);
2053 break;
2054 case MFI_DIAG:
2055 retval = s->diag;
2056 trace_megasas_mmio_readl("MFI_DIAG", retval);
2057 break;
2058 case MFI_OSP1:
2059 retval = 15;
2060 trace_megasas_mmio_readl("MFI_OSP1", retval);
2061 break;
2062 default:
2063 trace_megasas_mmio_invalid_readl(addr);
2064 break;
2065 }
2066 return retval;
2067 }
2068
2069 static int adp_reset_seq[] = {0x00, 0x04, 0x0b, 0x02, 0x07, 0x0d};
2070
2071 static void megasas_mmio_write(void *opaque, hwaddr addr,
2072 uint64_t val, unsigned size)
2073 {
2074 MegasasState *s = opaque;
2075 PCIDevice *pci_dev = PCI_DEVICE(s);
2076 uint64_t frame_addr;
2077 uint32_t frame_count;
2078 int i;
2079
2080 switch (addr) {
2081 case MFI_IDB:
2082 trace_megasas_mmio_writel("MFI_IDB", val);
2083 if (val & MFI_FWINIT_ABORT) {
2084 /* Abort all pending cmds */
2085 for (i = 0; i < s->fw_cmds; i++) {
2086 megasas_abort_command(&s->frames[i]);
2087 }
2088 }
2089 if (val & MFI_FWINIT_READY) {
2090 /* move to FW READY */
2091 megasas_soft_reset(s);
2092 }
2093 if (val & MFI_FWINIT_MFIMODE) {
2094 /* discard MFIs */
2095 }
2096 if (val & MFI_FWINIT_STOP_ADP) {
2097 /* Terminal error, stop processing */
2098 s->fw_state = MFI_FWSTATE_FAULT;
2099 }
2100 break;
2101 case MFI_OMSK:
2102 trace_megasas_mmio_writel("MFI_OMSK", val);
2103 s->intr_mask = val;
2104 if (!megasas_intr_enabled(s) &&
2105 !msi_enabled(pci_dev) &&
2106 !msix_enabled(pci_dev)) {
2107 trace_megasas_irq_lower();
2108 pci_irq_deassert(pci_dev);
2109 }
2110 if (megasas_intr_enabled(s)) {
2111 if (msix_enabled(pci_dev)) {
2112 trace_megasas_msix_enabled(0);
2113 } else if (msi_enabled(pci_dev)) {
2114 trace_megasas_msi_enabled(0);
2115 } else {
2116 trace_megasas_intr_enabled();
2117 }
2118 } else {
2119 trace_megasas_intr_disabled();
2120 megasas_soft_reset(s);
2121 }
2122 break;
2123 case MFI_ODCR0:
2124 trace_megasas_mmio_writel("MFI_ODCR0", val);
2125 s->doorbell = 0;
2126 if (megasas_intr_enabled(s)) {
2127 if (!msix_enabled(pci_dev) && !msi_enabled(pci_dev)) {
2128 trace_megasas_irq_lower();
2129 pci_irq_deassert(pci_dev);
2130 }
2131 }
2132 break;
2133 case MFI_IQPH:
2134 trace_megasas_mmio_writel("MFI_IQPH", val);
2135 /* Received high 32 bits of a 64 bit MFI frame address */
2136 s->frame_hi = val;
2137 break;
2138 case MFI_IQPL:
2139 trace_megasas_mmio_writel("MFI_IQPL", val);
2140 /* Received low 32 bits of a 64 bit MFI frame address */
2141 /* Fallthrough */
2142 case MFI_IQP:
2143 if (addr == MFI_IQP) {
2144 trace_megasas_mmio_writel("MFI_IQP", val);
2145 /* Received 64 bit MFI frame address */
2146 s->frame_hi = 0;
2147 }
2148 frame_addr = (val & ~0x1F);
2149 /* Add possible 64 bit offset */
2150 frame_addr |= ((uint64_t)s->frame_hi << 32);
2151 s->frame_hi = 0;
2152 frame_count = (val >> 1) & 0xF;
2153 megasas_handle_frame(s, frame_addr, frame_count);
2154 break;
2155 case MFI_SEQ:
2156 trace_megasas_mmio_writel("MFI_SEQ", val);
2157 /* Magic sequence to start ADP reset */
2158 if (adp_reset_seq[s->adp_reset++] == val) {
2159 if (s->adp_reset == 6) {
2160 s->adp_reset = 0;
2161 s->diag = MFI_DIAG_WRITE_ENABLE;
2162 }
2163 } else {
2164 s->adp_reset = 0;
2165 s->diag = 0;
2166 }
2167 break;
2168 case MFI_DIAG:
2169 trace_megasas_mmio_writel("MFI_DIAG", val);
2170 /* ADP reset */
2171 if ((s->diag & MFI_DIAG_WRITE_ENABLE) &&
2172 (val & MFI_DIAG_RESET_ADP)) {
2173 s->diag |= MFI_DIAG_RESET_ADP;
2174 megasas_soft_reset(s);
2175 s->adp_reset = 0;
2176 s->diag = 0;
2177 }
2178 break;
2179 default:
2180 trace_megasas_mmio_invalid_writel(addr, val);
2181 break;
2182 }
2183 }
2184
2185 static const MemoryRegionOps megasas_mmio_ops = {
2186 .read = megasas_mmio_read,
2187 .write = megasas_mmio_write,
2188 .endianness = DEVICE_LITTLE_ENDIAN,
2189 .impl = {
2190 .min_access_size = 8,
2191 .max_access_size = 8,
2192 }
2193 };
2194
2195 static uint64_t megasas_port_read(void *opaque, hwaddr addr,
2196 unsigned size)
2197 {
2198 return megasas_mmio_read(opaque, addr & 0xff, size);
2199 }
2200
2201 static void megasas_port_write(void *opaque, hwaddr addr,
2202 uint64_t val, unsigned size)
2203 {
2204 megasas_mmio_write(opaque, addr & 0xff, val, size);
2205 }
2206
2207 static const MemoryRegionOps megasas_port_ops = {
2208 .read = megasas_port_read,
2209 .write = megasas_port_write,
2210 .endianness = DEVICE_LITTLE_ENDIAN,
2211 .impl = {
2212 .min_access_size = 4,
2213 .max_access_size = 4,
2214 }
2215 };
2216
2217 static uint64_t megasas_queue_read(void *opaque, hwaddr addr,
2218 unsigned size)
2219 {
2220 return 0;
2221 }
2222
2223 static void megasas_queue_write(void *opaque, hwaddr addr,
2224 uint64_t val, unsigned size)
2225 {
2226 }
2227
2228 static const MemoryRegionOps megasas_queue_ops = {
2229 .read = megasas_queue_read,
2230 .write = megasas_queue_write,
2231 .endianness = DEVICE_LITTLE_ENDIAN,
2232 .impl = {
2233 .min_access_size = 8,
2234 .max_access_size = 8,
2235 }
2236 };
2237
2238 static void megasas_soft_reset(MegasasState *s)
2239 {
2240 int i;
2241 MegasasCmd *cmd;
2242
2243 trace_megasas_reset(s->fw_state);
2244 for (i = 0; i < s->fw_cmds; i++) {
2245 cmd = &s->frames[i];
2246 megasas_abort_command(cmd);
2247 }
2248 if (s->fw_state == MFI_FWSTATE_READY) {
2249 BusChild *kid;
2250
2251 /*
2252 * The EFI firmware doesn't handle UA,
2253 * so we need to clear the Power On/Reset UA
2254 * after the initial reset.
2255 */
2256 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
2257 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
2258
2259 sdev->unit_attention = SENSE_CODE(NO_SENSE);
2260 scsi_device_unit_attention_reported(sdev);
2261 }
2262 }
2263 megasas_reset_frames(s);
2264 s->reply_queue_len = s->fw_cmds;
2265 s->reply_queue_pa = 0;
2266 s->consumer_pa = 0;
2267 s->producer_pa = 0;
2268 s->fw_state = MFI_FWSTATE_READY;
2269 s->doorbell = 0;
2270 s->intr_mask = MEGASAS_INTR_DISABLED_MASK;
2271 s->frame_hi = 0;
2272 s->flags &= ~MEGASAS_MASK_USE_QUEUE64;
2273 s->event_count++;
2274 s->boot_event = s->event_count;
2275 }
2276
2277 static void megasas_scsi_reset(DeviceState *dev)
2278 {
2279 MegasasState *s = MEGASAS(dev);
2280
2281 megasas_soft_reset(s);
2282 }
2283
2284 static const VMStateDescription vmstate_megasas_gen1 = {
2285 .name = "megasas",
2286 .version_id = 0,
2287 .minimum_version_id = 0,
2288 .fields = (const VMStateField[]) {
2289 VMSTATE_PCI_DEVICE(parent_obj, MegasasState),
2290 VMSTATE_MSIX(parent_obj, MegasasState),
2291
2292 VMSTATE_UINT32(fw_state, MegasasState),
2293 VMSTATE_UINT32(intr_mask, MegasasState),
2294 VMSTATE_UINT32(doorbell, MegasasState),
2295 VMSTATE_UINT64(reply_queue_pa, MegasasState),
2296 VMSTATE_UINT64(consumer_pa, MegasasState),
2297 VMSTATE_UINT64(producer_pa, MegasasState),
2298 VMSTATE_END_OF_LIST()
2299 }
2300 };
2301
2302 static const VMStateDescription vmstate_megasas_gen2 = {
2303 .name = "megasas-gen2",
2304 .version_id = 0,
2305 .minimum_version_id = 0,
2306 .fields = (const VMStateField[]) {
2307 VMSTATE_PCI_DEVICE(parent_obj, MegasasState),
2308 VMSTATE_MSIX(parent_obj, MegasasState),
2309
2310 VMSTATE_UINT32(fw_state, MegasasState),
2311 VMSTATE_UINT32(intr_mask, MegasasState),
2312 VMSTATE_UINT32(doorbell, MegasasState),
2313 VMSTATE_UINT64(reply_queue_pa, MegasasState),
2314 VMSTATE_UINT64(consumer_pa, MegasasState),
2315 VMSTATE_UINT64(producer_pa, MegasasState),
2316 VMSTATE_END_OF_LIST()
2317 }
2318 };
2319
2320 static void megasas_scsi_uninit(PCIDevice *d)
2321 {
2322 MegasasState *s = MEGASAS(d);
2323
2324 if (megasas_use_msix(s)) {
2325 msix_uninit(d, &s->mmio_io, &s->mmio_io);
2326 }
2327 msi_uninit(d);
2328 }
2329
2330 static const struct SCSIBusInfo megasas_scsi_info = {
2331 .tcq = true,
2332 .max_target = MFI_MAX_LD,
2333 .max_lun = 255,
2334
2335 .transfer_data = megasas_xfer_complete,
2336 .get_sg_list = megasas_get_sg_list,
2337 .complete = megasas_command_complete,
2338 .cancel = megasas_command_cancelled,
2339 };
2340
2341 static void megasas_scsi_realize(PCIDevice *dev, Error **errp)
2342 {
2343 MegasasState *s = MEGASAS(dev);
2344 MegasasBaseClass *b = MEGASAS_GET_CLASS(s);
2345 uint8_t *pci_conf;
2346 uint32_t sge;
2347 int i, bar_type;
2348 Error *err = NULL;
2349 int ret;
2350
2351 pci_conf = dev->config;
2352
2353 /* PCI latency timer = 0 */
2354 pci_conf[PCI_LATENCY_TIMER] = 0;
2355 /* Interrupt pin 1 */
2356 pci_conf[PCI_INTERRUPT_PIN] = 0x01;
2357
2358 if (s->msi != ON_OFF_AUTO_OFF) {
2359 ret = msi_init(dev, 0x50, 1, true, false, &err);
2360 /* Any error other than -ENOTSUP(board's MSI support is broken)
2361 * is a programming error */
2362 assert(!ret || ret == -ENOTSUP);
2363 if (ret && s->msi == ON_OFF_AUTO_ON) {
2364 /* Can't satisfy user's explicit msi=on request, fail */
2365 error_append_hint(&err, "You have to use msi=auto (default) or "
2366 "msi=off with this machine type.\n");
2367 error_propagate(errp, err);
2368 return;
2369 } else if (ret) {
2370 /* With msi=auto, we fall back to MSI off silently */
2371 s->msi = ON_OFF_AUTO_OFF;
2372 error_free(err);
2373 }
2374 }
2375
2376 memory_region_init_io(&s->mmio_io, OBJECT(s), &megasas_mmio_ops, s,
2377 "megasas-mmio", 0x4000);
2378 memory_region_init_io(&s->port_io, OBJECT(s), &megasas_port_ops, s,
2379 "megasas-io", 256);
2380 memory_region_init_io(&s->queue_io, OBJECT(s), &megasas_queue_ops, s,
2381 "megasas-queue", 0x40000);
2382
2383 if (megasas_use_msix(s)) {
2384 ret = msix_init(dev, 15, &s->mmio_io, b->mmio_bar, 0x2000,
2385 &s->mmio_io, b->mmio_bar, 0x3800, 0x68,
2386 s->msix == ON_OFF_AUTO_ON ? errp : NULL);
2387
2388 if (ret < 0) {
2389 if (s->msix == ON_OFF_AUTO_ON) {
2390 return;
2391 }
2392 s->msix = ON_OFF_AUTO_OFF;
2393 }
2394 }
2395
2396 if (pci_is_express(dev)) {
2397 pcie_endpoint_cap_init(dev, 0xa0);
2398 }
2399
2400 bar_type = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64;
2401 pci_register_bar(dev, b->ioport_bar,
2402 PCI_BASE_ADDRESS_SPACE_IO, &s->port_io);
2403 pci_register_bar(dev, b->mmio_bar, bar_type, &s->mmio_io);
2404 pci_register_bar(dev, 3, bar_type, &s->queue_io);
2405
2406 if (megasas_use_msix(s)) {
2407 msix_vector_use(dev, 0);
2408 }
2409
2410 s->fw_state = MFI_FWSTATE_READY;
2411 if (!s->sas_addr) {
2412 s->sas_addr = ((NAA_LOCALLY_ASSIGNED_ID << 24) |
2413 IEEE_COMPANY_LOCALLY_ASSIGNED) << 36;
2414 s->sas_addr |= pci_dev_bus_num(dev) << 16;
2415 s->sas_addr |= PCI_SLOT(dev->devfn) << 8;
2416 s->sas_addr |= PCI_FUNC(dev->devfn);
2417 }
2418 if (!s->hba_serial) {
2419 s->hba_serial = g_strdup(MEGASAS_HBA_SERIAL);
2420 }
2421
2422 sge = s->fw_sge + MFI_PASS_FRAME_SIZE;
2423 if (sge < MEGASAS_MIN_SGE) {
2424 sge = MEGASAS_MIN_SGE;
2425 } else if (sge >= MEGASAS_MAX_SGE) {
2426 sge = MEGASAS_MAX_SGE;
2427 }
2428 s->fw_sge = sge - MFI_PASS_FRAME_SIZE;
2429
2430 if (s->fw_cmds > MEGASAS_MAX_FRAMES) {
2431 s->fw_cmds = MEGASAS_MAX_FRAMES;
2432 }
2433 trace_megasas_init(s->fw_sge, s->fw_cmds,
2434 megasas_is_jbod(s) ? "jbod" : "raid");
2435
2436 if (megasas_is_jbod(s)) {
2437 s->fw_luns = MFI_MAX_SYS_PDS;
2438 } else {
2439 s->fw_luns = MFI_MAX_LD;
2440 }
2441 s->producer_pa = 0;
2442 s->consumer_pa = 0;
2443 for (i = 0; i < s->fw_cmds; i++) {
2444 s->frames[i].index = i;
2445 s->frames[i].context = -1;
2446 s->frames[i].pa = 0;
2447 s->frames[i].state = s;
2448 }
2449
2450 scsi_bus_init(&s->bus, sizeof(s->bus), DEVICE(dev), &megasas_scsi_info);
2451 }
2452
2453 static const Property megasas_properties_gen1[] = {
2454 DEFINE_PROP_UINT32("max_sge", MegasasState, fw_sge,
2455 MEGASAS_DEFAULT_SGE),
2456 DEFINE_PROP_UINT32("max_cmds", MegasasState, fw_cmds,
2457 MEGASAS_DEFAULT_FRAMES),
2458 DEFINE_PROP_STRING("hba_serial", MegasasState, hba_serial),
2459 DEFINE_PROP_UINT64("sas_address", MegasasState, sas_addr, 0),
2460 DEFINE_PROP_ON_OFF_AUTO("msi", MegasasState, msi, ON_OFF_AUTO_AUTO),
2461 DEFINE_PROP_ON_OFF_AUTO("msix", MegasasState, msix, ON_OFF_AUTO_AUTO),
2462 DEFINE_PROP_BIT("use_jbod", MegasasState, flags,
2463 MEGASAS_FLAG_USE_JBOD, false),
2464 };
2465
2466 static const Property megasas_properties_gen2[] = {
2467 DEFINE_PROP_UINT32("max_sge", MegasasState, fw_sge,
2468 MEGASAS_DEFAULT_SGE),
2469 DEFINE_PROP_UINT32("max_cmds", MegasasState, fw_cmds,
2470 MEGASAS_GEN2_DEFAULT_FRAMES),
2471 DEFINE_PROP_STRING("hba_serial", MegasasState, hba_serial),
2472 DEFINE_PROP_UINT64("sas_address", MegasasState, sas_addr, 0),
2473 DEFINE_PROP_ON_OFF_AUTO("msi", MegasasState, msi, ON_OFF_AUTO_AUTO),
2474 DEFINE_PROP_ON_OFF_AUTO("msix", MegasasState, msix, ON_OFF_AUTO_AUTO),
2475 DEFINE_PROP_BIT("use_jbod", MegasasState, flags,
2476 MEGASAS_FLAG_USE_JBOD, false),
2477 };
2478
2479 typedef struct MegasasInfo {
2480 const char *name;
2481 const char *desc;
2482 const char *product_name;
2483 const char *product_version;
2484 uint16_t device_id;
2485 uint16_t subsystem_id;
2486 int ioport_bar;
2487 int mmio_bar;
2488 int osts;
2489 const VMStateDescription *vmsd;
2490 const Property *props;
2491 size_t props_count;
2492 const InterfaceInfo *interfaces;
2493 } MegasasInfo;
2494
2495 static struct MegasasInfo megasas_devices[] = {
2496 {
2497 .name = TYPE_MEGASAS_GEN1,
2498 .desc = "LSI MegaRAID SAS 1078",
2499 .product_name = "LSI MegaRAID SAS 8708EM2",
2500 .product_version = MEGASAS_VERSION_GEN1,
2501 .device_id = PCI_DEVICE_ID_LSI_SAS1078,
2502 .subsystem_id = 0x1013,
2503 .ioport_bar = 2,
2504 .mmio_bar = 0,
2505 .osts = MFI_1078_RM | 1,
2506 .vmsd = &vmstate_megasas_gen1,
2507 .props = megasas_properties_gen1,
2508 .props_count = ARRAY_SIZE(megasas_properties_gen1),
2509 .interfaces = (const InterfaceInfo[]) {
2510 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
2511 { },
2512 },
2513 },{
2514 .name = TYPE_MEGASAS_GEN2,
2515 .desc = "LSI MegaRAID SAS 2108",
2516 .product_name = "LSI MegaRAID SAS 9260-8i",
2517 .product_version = MEGASAS_VERSION_GEN2,
2518 .device_id = PCI_DEVICE_ID_LSI_SAS0079,
2519 .subsystem_id = 0x9261,
2520 .ioport_bar = 0,
2521 .mmio_bar = 1,
2522 .osts = MFI_GEN2_RM,
2523 .vmsd = &vmstate_megasas_gen2,
2524 .props = megasas_properties_gen2,
2525 .props_count = ARRAY_SIZE(megasas_properties_gen2),
2526 .interfaces = (const InterfaceInfo[]) {
2527 { INTERFACE_PCIE_DEVICE },
2528 { }
2529 },
2530 }
2531 };
2532
2533 static void megasas_class_init(ObjectClass *oc, const void *data)
2534 {
2535 DeviceClass *dc = DEVICE_CLASS(oc);
2536 PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc);
2537 MegasasBaseClass *e = MEGASAS_CLASS(oc);
2538 const MegasasInfo *info = data;
2539
2540 pc->realize = megasas_scsi_realize;
2541 pc->exit = megasas_scsi_uninit;
2542 pc->vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
2543 pc->device_id = info->device_id;
2544 pc->subsystem_vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
2545 pc->subsystem_id = info->subsystem_id;
2546 pc->class_id = PCI_CLASS_STORAGE_RAID;
2547 e->mmio_bar = info->mmio_bar;
2548 e->ioport_bar = info->ioport_bar;
2549 e->osts = info->osts;
2550 e->product_name = info->product_name;
2551 e->product_version = info->product_version;
2552 device_class_set_props_n(dc, info->props, info->props_count);
2553 device_class_set_legacy_reset(dc, megasas_scsi_reset);
2554 dc->vmsd = info->vmsd;
2555 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
2556 dc->desc = info->desc;
2557 }
2558
2559 static const TypeInfo megasas_info = {
2560 .name = TYPE_MEGASAS_BASE,
2561 .parent = TYPE_PCI_DEVICE,
2562 .instance_size = sizeof(MegasasState),
2563 .class_size = sizeof(MegasasBaseClass),
2564 .abstract = true,
2565 };
2566
2567 static void megasas_register_types(void)
2568 {
2569 int i;
2570
2571 type_register_static(&megasas_info);
2572 for (i = 0; i < ARRAY_SIZE(megasas_devices); i++) {
2573 const MegasasInfo *info = &megasas_devices[i];
2574 TypeInfo type_info = {};
2575
2576 type_info.name = info->name;
2577 type_info.parent = TYPE_MEGASAS_BASE;
2578 type_info.class_data = info;
2579 type_info.class_init = megasas_class_init;
2580 type_info.interfaces = info->interfaces;
2581
2582 type_register_static(&type_info);
2583 }
2584 }
2585
2586 type_init(megasas_register_types)