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1 /*
2 * QEMU LSI SAS1068 Host Bus Adapter emulation
3 * Based on the QEMU Megaraid emulator
4 *
5 * Copyright (c) 2009-2012 Hannes Reinecke, SUSE Labs
6 * Copyright (c) 2012 Verizon, Inc.
7 * Copyright (c) 2016 Red Hat, Inc.
8 *
9 * Authors: Don Slutz, Paolo Bonzini
10 *
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License as published by the Free Software Foundation; either
14 * version 2.1 of the License, or (at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * Lesser General Public License for more details.
20 *
21 * You should have received a copy of the GNU Lesser General Public
22 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 */
24
25 #include "qemu/osdep.h"
26 #include "hw/pci/pci.h"
27 #include "hw/core/qdev-properties.h"
28 #include "system/dma.h"
29 #include "hw/pci/msi.h"
30 #include "qemu/iov.h"
31 #include "qemu/main-loop.h"
32 #include "qemu/module.h"
33 #include "hw/scsi/scsi.h"
34 #include "scsi/constants.h"
35 #include "trace.h"
36 #include "qapi/error.h"
37 #include "mptsas.h"
38 #include "migration/qemu-file-types.h"
39 #include "migration/vmstate.h"
40 #include "mpi.h"
41
42 #define NAA_LOCALLY_ASSIGNED_ID 0x3ULL
43 #define IEEE_COMPANY_LOCALLY_ASSIGNED 0x525400
44
45 #define MPTSAS1068_PRODUCT_ID \
46 (MPI_FW_HEADER_PID_FAMILY_1068_SAS | \
47 MPI_FW_HEADER_PID_PROD_INITIATOR_SCSI | \
48 MPI_FW_HEADER_PID_TYPE_SAS)
49
50 struct MPTSASRequest {
51 MPIMsgSCSIIORequest scsi_io;
52 SCSIRequest *sreq;
53 QEMUSGList qsg;
54 MPTSASState *dev;
55
56 QTAILQ_ENTRY(MPTSASRequest) next;
57 };
58
59 static void mptsas_update_interrupt(MPTSASState *s)
60 {
61 PCIDevice *pci = (PCIDevice *) s;
62 uint32_t state = s->intr_status & ~(s->intr_mask | MPI_HIS_IOP_DOORBELL_STATUS);
63
64 if (msi_enabled(pci)) {
65 if (state) {
66 trace_mptsas_irq_msi(s);
67 msi_notify(pci, 0);
68 }
69 }
70
71 trace_mptsas_irq_intx(s, !!state);
72 pci_set_irq(pci, !!state);
73 }
74
75 static void mptsas_set_fault(MPTSASState *s, uint32_t code)
76 {
77 if ((s->state & MPI_IOC_STATE_FAULT) == 0) {
78 s->state = MPI_IOC_STATE_FAULT | code;
79 }
80 }
81
82 #define MPTSAS_FIFO_INVALID(s, name) \
83 ((s)->name##_head > ARRAY_SIZE((s)->name) || \
84 (s)->name##_tail > ARRAY_SIZE((s)->name))
85
86 #define MPTSAS_FIFO_EMPTY(s, name) \
87 ((s)->name##_head == (s)->name##_tail)
88
89 #define MPTSAS_FIFO_FULL(s, name) \
90 ((s)->name##_head == ((s)->name##_tail + 1) % ARRAY_SIZE((s)->name))
91
92 #define MPTSAS_FIFO_GET(s, name) ({ \
93 uint32_t _val = (s)->name[(s)->name##_head++]; \
94 (s)->name##_head %= ARRAY_SIZE((s)->name); \
95 _val; \
96 })
97
98 #define MPTSAS_FIFO_PUT(s, name, val) do { \
99 (s)->name[(s)->name##_tail++] = (val); \
100 (s)->name##_tail %= ARRAY_SIZE((s)->name); \
101 } while(0)
102
103 static void mptsas_post_reply(MPTSASState *s, MPIDefaultReply *reply)
104 {
105 PCIDevice *pci = (PCIDevice *) s;
106 uint32_t addr_lo;
107
108 if (MPTSAS_FIFO_EMPTY(s, reply_free) || MPTSAS_FIFO_FULL(s, reply_post)) {
109 mptsas_set_fault(s, MPI_IOCSTATUS_INSUFFICIENT_RESOURCES);
110 return;
111 }
112
113 addr_lo = MPTSAS_FIFO_GET(s, reply_free);
114
115 pci_dma_write(pci, addr_lo | s->host_mfa_high_addr, reply,
116 MIN(s->reply_frame_size, 4 * reply->MsgLength));
117
118 MPTSAS_FIFO_PUT(s, reply_post, MPI_ADDRESS_REPLY_A_BIT | (addr_lo >> 1));
119
120 s->intr_status |= MPI_HIS_REPLY_MESSAGE_INTERRUPT;
121 if (s->doorbell_state == DOORBELL_WRITE) {
122 s->doorbell_state = DOORBELL_NONE;
123 s->intr_status |= MPI_HIS_DOORBELL_INTERRUPT;
124 }
125 mptsas_update_interrupt(s);
126 }
127
128 void mptsas_reply(MPTSASState *s, MPIDefaultReply *reply)
129 {
130 if (s->doorbell_state == DOORBELL_WRITE) {
131 /* The reply is sent out in 16 bit chunks, while the size
132 * in the reply is in 32 bit units.
133 */
134 s->doorbell_state = DOORBELL_READ;
135 s->doorbell_reply_idx = 0;
136 s->doorbell_reply_size = reply->MsgLength * 2;
137 memcpy(s->doorbell_reply, reply, s->doorbell_reply_size * 2);
138 s->intr_status |= MPI_HIS_DOORBELL_INTERRUPT;
139 mptsas_update_interrupt(s);
140 } else {
141 mptsas_post_reply(s, reply);
142 }
143 }
144
145 static void mptsas_turbo_reply(MPTSASState *s, uint32_t msgctx)
146 {
147 if (MPTSAS_FIFO_FULL(s, reply_post)) {
148 mptsas_set_fault(s, MPI_IOCSTATUS_INSUFFICIENT_RESOURCES);
149 return;
150 }
151
152 /* The reply is just the message context ID (bit 31 = clear). */
153 MPTSAS_FIFO_PUT(s, reply_post, msgctx);
154
155 s->intr_status |= MPI_HIS_REPLY_MESSAGE_INTERRUPT;
156 mptsas_update_interrupt(s);
157 }
158
159 #define MPTSAS_MAX_REQUEST_SIZE 52
160
161 static const int mpi_request_sizes[] = {
162 [MPI_FUNCTION_SCSI_IO_REQUEST] = sizeof(MPIMsgSCSIIORequest),
163 [MPI_FUNCTION_SCSI_TASK_MGMT] = sizeof(MPIMsgSCSITaskMgmt),
164 [MPI_FUNCTION_IOC_INIT] = sizeof(MPIMsgIOCInit),
165 [MPI_FUNCTION_IOC_FACTS] = sizeof(MPIMsgIOCFacts),
166 [MPI_FUNCTION_CONFIG] = sizeof(MPIMsgConfig),
167 [MPI_FUNCTION_PORT_FACTS] = sizeof(MPIMsgPortFacts),
168 [MPI_FUNCTION_PORT_ENABLE] = sizeof(MPIMsgPortEnable),
169 [MPI_FUNCTION_EVENT_NOTIFICATION] = sizeof(MPIMsgEventNotify),
170 };
171
172 static dma_addr_t mptsas_ld_sg_base(MPTSASState *s, uint32_t flags_and_length,
173 dma_addr_t *sgaddr)
174 {
175 const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
176 PCIDevice *pci = (PCIDevice *) s;
177 dma_addr_t addr;
178
179 if (flags_and_length & MPI_SGE_FLAGS_64_BIT_ADDRESSING) {
180 uint64_t addr64;
181
182 ldq_le_pci_dma(pci, *sgaddr + 4, &addr64, attrs);
183 addr = addr64;
184 *sgaddr += 12;
185 } else {
186 uint32_t addr32;
187
188 ldl_le_pci_dma(pci, *sgaddr + 4, &addr32, attrs);
189 addr = addr32;
190 *sgaddr += 8;
191 }
192 return addr;
193 }
194
195 static int mptsas_build_sgl(MPTSASState *s, MPTSASRequest *req, hwaddr req_addr)
196 {
197 PCIDevice *pci = (PCIDevice *) s;
198 hwaddr next_chain_addr;
199 uint32_t left;
200 hwaddr sgaddr;
201 uint32_t chain_offset;
202
203 chain_offset = req->scsi_io.ChainOffset;
204 next_chain_addr = req_addr + chain_offset * sizeof(uint32_t);
205 sgaddr = req_addr + sizeof(MPIMsgSCSIIORequest);
206 pci_dma_sglist_init(&req->qsg, pci, 4);
207 left = req->scsi_io.DataLength;
208
209 for(;;) {
210 dma_addr_t addr, len;
211 uint32_t flags_and_length;
212
213 ldl_le_pci_dma(pci, sgaddr, &flags_and_length, MEMTXATTRS_UNSPECIFIED);
214 len = flags_and_length & MPI_SGE_LENGTH_MASK;
215 if ((flags_and_length & MPI_SGE_FLAGS_ELEMENT_TYPE_MASK)
216 != MPI_SGE_FLAGS_SIMPLE_ELEMENT ||
217 (!len &&
218 !(flags_and_length & MPI_SGE_FLAGS_END_OF_LIST) &&
219 !(flags_and_length & MPI_SGE_FLAGS_END_OF_BUFFER))) {
220 return MPI_IOCSTATUS_INVALID_SGL;
221 }
222
223 len = MIN(len, left);
224 if (!len) {
225 /* We reached the desired transfer length, ignore extra
226 * elements of the s/g list.
227 */
228 break;
229 }
230
231 addr = mptsas_ld_sg_base(s, flags_and_length, &sgaddr);
232 qemu_sglist_add(&req->qsg, addr, len);
233 left -= len;
234
235 if (flags_and_length & MPI_SGE_FLAGS_END_OF_LIST) {
236 break;
237 }
238
239 if (flags_and_length & MPI_SGE_FLAGS_LAST_ELEMENT) {
240 if (!chain_offset) {
241 break;
242 }
243
244 ldl_le_pci_dma(pci, next_chain_addr, &flags_and_length,
245 MEMTXATTRS_UNSPECIFIED);
246 if ((flags_and_length & MPI_SGE_FLAGS_ELEMENT_TYPE_MASK)
247 != MPI_SGE_FLAGS_CHAIN_ELEMENT) {
248 return MPI_IOCSTATUS_INVALID_SGL;
249 }
250
251 sgaddr = mptsas_ld_sg_base(s, flags_and_length, &next_chain_addr);
252 chain_offset =
253 (flags_and_length & MPI_SGE_CHAIN_OFFSET_MASK) >> MPI_SGE_CHAIN_OFFSET_SHIFT;
254 next_chain_addr = sgaddr + chain_offset * sizeof(uint32_t);
255 }
256 }
257 return 0;
258 }
259
260 static void mptsas_free_request(MPTSASRequest *req)
261 {
262 if (req->sreq != NULL) {
263 req->sreq->hba_private = NULL;
264 scsi_req_unref(req->sreq);
265 req->sreq = NULL;
266 }
267 qemu_sglist_destroy(&req->qsg);
268 g_free(req);
269 }
270
271 static int mptsas_scsi_device_find(MPTSASState *s, int bus, int target,
272 uint8_t *lun, SCSIDevice **sdev)
273 {
274 if (bus != 0) {
275 return MPI_IOCSTATUS_SCSI_INVALID_BUS;
276 }
277
278 if (target >= s->max_devices) {
279 return MPI_IOCSTATUS_SCSI_INVALID_TARGETID;
280 }
281
282 *sdev = scsi_device_find(&s->bus, bus, target, lun[1]);
283 if (!*sdev) {
284 return MPI_IOCSTATUS_SCSI_DEVICE_NOT_THERE;
285 }
286
287 return 0;
288 }
289
290 static int mptsas_process_scsi_io_request(MPTSASState *s,
291 MPIMsgSCSIIORequest *scsi_io,
292 hwaddr addr)
293 {
294 MPTSASRequest *req;
295 MPIMsgSCSIIOReply reply;
296 SCSIDevice *sdev;
297 int status;
298
299 mptsas_fix_scsi_io_endianness(scsi_io);
300
301 trace_mptsas_process_scsi_io_request(s, scsi_io->Bus, scsi_io->TargetID,
302 scsi_io->LUN[1], scsi_io->DataLength);
303
304 status = mptsas_scsi_device_find(s, scsi_io->Bus, scsi_io->TargetID,
305 scsi_io->LUN, &sdev);
306 if (status) {
307 goto bad;
308 }
309
310 req = g_new0(MPTSASRequest, 1);
311 req->scsi_io = *scsi_io;
312 req->dev = s;
313
314 status = mptsas_build_sgl(s, req, addr);
315 if (status) {
316 goto free_bad;
317 }
318
319 if (req->qsg.size < scsi_io->DataLength) {
320 trace_mptsas_sgl_overflow(s, scsi_io->MsgContext, scsi_io->DataLength,
321 req->qsg.size);
322 status = MPI_IOCSTATUS_INVALID_SGL;
323 goto free_bad;
324 }
325
326 req->sreq = scsi_req_new(sdev, scsi_io->MsgContext,
327 scsi_io->LUN[1], scsi_io->CDB,
328 scsi_io->CDBLength, req);
329
330 if (req->sreq->cmd.xfer > scsi_io->DataLength) {
331 goto overrun;
332 }
333 switch (scsi_io->Control & MPI_SCSIIO_CONTROL_DATADIRECTION_MASK) {
334 case MPI_SCSIIO_CONTROL_NODATATRANSFER:
335 if (req->sreq->cmd.mode != SCSI_XFER_NONE) {
336 goto overrun;
337 }
338 break;
339
340 case MPI_SCSIIO_CONTROL_WRITE:
341 if (req->sreq->cmd.mode != SCSI_XFER_TO_DEV) {
342 goto overrun;
343 }
344 break;
345
346 case MPI_SCSIIO_CONTROL_READ:
347 if (req->sreq->cmd.mode != SCSI_XFER_FROM_DEV) {
348 goto overrun;
349 }
350 break;
351 }
352
353 if (scsi_req_enqueue(req->sreq)) {
354 scsi_req_continue(req->sreq);
355 }
356 return 0;
357
358 overrun:
359 trace_mptsas_scsi_overflow(s, scsi_io->MsgContext, req->sreq->cmd.xfer,
360 scsi_io->DataLength);
361 status = MPI_IOCSTATUS_SCSI_DATA_OVERRUN;
362 free_bad:
363 mptsas_free_request(req);
364 bad:
365 memset(&reply, 0, sizeof(reply));
366 reply.TargetID = scsi_io->TargetID;
367 reply.Bus = scsi_io->Bus;
368 reply.MsgLength = sizeof(reply) / 4;
369 reply.Function = scsi_io->Function;
370 reply.CDBLength = scsi_io->CDBLength;
371 reply.SenseBufferLength = scsi_io->SenseBufferLength;
372 reply.MsgContext = scsi_io->MsgContext;
373 reply.SCSIState = MPI_SCSI_STATE_NO_SCSI_STATUS;
374 reply.IOCStatus = status;
375
376 mptsas_fix_scsi_io_reply_endianness(&reply);
377 mptsas_reply(s, (MPIDefaultReply *)&reply);
378
379 return 0;
380 }
381
382 typedef struct {
383 Notifier notifier;
384 MPTSASState *s;
385 MPIMsgSCSITaskMgmtReply *reply;
386 } MPTSASCancelNotifier;
387
388 static void mptsas_cancel_notify(Notifier *notifier, void *data)
389 {
390 MPTSASCancelNotifier *n = container_of(notifier,
391 MPTSASCancelNotifier,
392 notifier);
393
394 /* Abusing IOCLogInfo to store the expected number of requests... */
395 if (++n->reply->TerminationCount == n->reply->IOCLogInfo) {
396 n->reply->IOCLogInfo = 0;
397 mptsas_fix_scsi_task_mgmt_reply_endianness(n->reply);
398 mptsas_post_reply(n->s, (MPIDefaultReply *)n->reply);
399 g_free(n->reply);
400 }
401 g_free(n);
402 }
403
404 static void mptsas_process_scsi_task_mgmt(MPTSASState *s, MPIMsgSCSITaskMgmt *req)
405 {
406 MPIMsgSCSITaskMgmtReply reply;
407 MPIMsgSCSITaskMgmtReply *reply_async;
408 int status, count;
409 SCSIDevice *sdev;
410 SCSIRequest *r, *next;
411 BusChild *kid;
412
413 mptsas_fix_scsi_task_mgmt_endianness(req);
414
415 QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req));
416 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req));
417 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply));
418
419 memset(&reply, 0, sizeof(reply));
420 reply.TargetID = req->TargetID;
421 reply.Bus = req->Bus;
422 reply.MsgLength = sizeof(reply) / 4;
423 reply.Function = req->Function;
424 reply.TaskType = req->TaskType;
425 reply.MsgContext = req->MsgContext;
426
427 switch (req->TaskType) {
428 case MPI_SCSITASKMGMT_TASKTYPE_ABORT_TASK:
429 case MPI_SCSITASKMGMT_TASKTYPE_QUERY_TASK:
430 status = mptsas_scsi_device_find(s, req->Bus, req->TargetID,
431 req->LUN, &sdev);
432 if (status) {
433 reply.IOCStatus = status;
434 goto out;
435 }
436 if (sdev->lun != req->LUN[1]) {
437 reply.ResponseCode = MPI_SCSITASKMGMT_RSP_TM_INVALID_LUN;
438 goto out;
439 }
440
441 QTAILQ_FOREACH_SAFE(r, &sdev->requests, next, next) {
442 MPTSASRequest *cmd_req = r->hba_private;
443 if (cmd_req && cmd_req->scsi_io.MsgContext == req->TaskMsgContext) {
444 break;
445 }
446 }
447 if (r) {
448 /*
449 * Assert that the request has not been completed yet, we
450 * check for it in the loop above.
451 */
452 assert(r->hba_private);
453 if (req->TaskType == MPI_SCSITASKMGMT_TASKTYPE_QUERY_TASK) {
454 /* "If the specified command is present in the task set, then
455 * return a service response set to FUNCTION SUCCEEDED".
456 */
457 reply.ResponseCode = MPI_SCSITASKMGMT_RSP_TM_SUCCEEDED;
458 } else {
459 MPTSASCancelNotifier *notifier;
460
461 reply_async = g_memdup(&reply, sizeof(MPIMsgSCSITaskMgmtReply));
462 reply_async->IOCLogInfo = INT_MAX;
463
464 count = 1;
465 notifier = g_new(MPTSASCancelNotifier, 1);
466 notifier->s = s;
467 notifier->reply = reply_async;
468 notifier->notifier.notify = mptsas_cancel_notify;
469 scsi_req_cancel_async(r, &notifier->notifier);
470 goto reply_maybe_async;
471 }
472 }
473 break;
474
475 case MPI_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET:
476 case MPI_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET:
477 status = mptsas_scsi_device_find(s, req->Bus, req->TargetID,
478 req->LUN, &sdev);
479 if (status) {
480 reply.IOCStatus = status;
481 goto out;
482 }
483 if (sdev->lun != req->LUN[1]) {
484 reply.ResponseCode = MPI_SCSITASKMGMT_RSP_TM_INVALID_LUN;
485 goto out;
486 }
487
488 reply_async = g_memdup(&reply, sizeof(MPIMsgSCSITaskMgmtReply));
489 reply_async->IOCLogInfo = INT_MAX;
490
491 count = 0;
492 QTAILQ_FOREACH_SAFE(r, &sdev->requests, next, next) {
493 if (r->hba_private) {
494 MPTSASCancelNotifier *notifier;
495
496 count++;
497 notifier = g_new(MPTSASCancelNotifier, 1);
498 notifier->s = s;
499 notifier->reply = reply_async;
500 notifier->notifier.notify = mptsas_cancel_notify;
501 scsi_req_cancel_async(r, &notifier->notifier);
502 }
503 }
504
505 reply_maybe_async:
506 if (reply_async->TerminationCount < count) {
507 reply_async->IOCLogInfo = count;
508 return;
509 }
510 g_free(reply_async);
511 reply.TerminationCount = count;
512 break;
513
514 case MPI_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET:
515 status = mptsas_scsi_device_find(s, req->Bus, req->TargetID,
516 req->LUN, &sdev);
517 if (status) {
518 reply.IOCStatus = status;
519 goto out;
520 }
521 if (sdev->lun != req->LUN[1]) {
522 reply.ResponseCode = MPI_SCSITASKMGMT_RSP_TM_INVALID_LUN;
523 goto out;
524 }
525 device_cold_reset(&sdev->qdev);
526 break;
527
528 case MPI_SCSITASKMGMT_TASKTYPE_TARGET_RESET:
529 if (req->Bus != 0) {
530 reply.IOCStatus = MPI_IOCSTATUS_SCSI_INVALID_BUS;
531 goto out;
532 }
533 if (req->TargetID > s->max_devices) {
534 reply.IOCStatus = MPI_IOCSTATUS_SCSI_INVALID_TARGETID;
535 goto out;
536 }
537
538 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
539 sdev = SCSI_DEVICE(kid->child);
540 if (sdev->channel == 0 && sdev->id == req->TargetID) {
541 device_cold_reset(kid->child);
542 }
543 }
544 break;
545
546 case MPI_SCSITASKMGMT_TASKTYPE_RESET_BUS:
547 bus_cold_reset(BUS(&s->bus));
548 break;
549
550 default:
551 reply.ResponseCode = MPI_SCSITASKMGMT_RSP_TM_NOT_SUPPORTED;
552 break;
553 }
554
555 out:
556 mptsas_fix_scsi_task_mgmt_reply_endianness(&reply);
557 mptsas_post_reply(s, (MPIDefaultReply *)&reply);
558 }
559
560 static void mptsas_process_ioc_init(MPTSASState *s, MPIMsgIOCInit *req)
561 {
562 MPIMsgIOCInitReply reply;
563
564 mptsas_fix_ioc_init_endianness(req);
565
566 QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req));
567 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req));
568 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply));
569
570 s->who_init = req->WhoInit;
571 s->reply_frame_size = req->ReplyFrameSize;
572 s->max_buses = req->MaxBuses;
573 s->max_devices = req->MaxDevices ? req->MaxDevices : 256;
574 s->host_mfa_high_addr = (hwaddr)req->HostMfaHighAddr << 32;
575 s->sense_buffer_high_addr = (hwaddr)req->SenseBufferHighAddr << 32;
576
577 if (s->state == MPI_IOC_STATE_READY) {
578 s->state = MPI_IOC_STATE_OPERATIONAL;
579 }
580
581 memset(&reply, 0, sizeof(reply));
582 reply.WhoInit = req->WhoInit;
583 reply.MsgLength = sizeof(reply) / 4;
584 reply.Function = req->Function;
585 reply.MaxDevices = req->MaxDevices;
586 reply.MaxBuses = req->MaxBuses;
587 reply.MsgContext = req->MsgContext;
588
589 mptsas_fix_ioc_init_reply_endianness(&reply);
590 mptsas_reply(s, (MPIDefaultReply *)&reply);
591 }
592
593 static void mptsas_process_ioc_facts(MPTSASState *s,
594 MPIMsgIOCFacts *req)
595 {
596 MPIMsgIOCFactsReply reply;
597
598 mptsas_fix_ioc_facts_endianness(req);
599
600 QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req));
601 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req));
602 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply));
603
604 memset(&reply, 0, sizeof(reply));
605 reply.MsgVersion = 0x0105;
606 reply.MsgLength = sizeof(reply) / 4;
607 reply.Function = req->Function;
608 reply.MsgContext = req->MsgContext;
609 reply.MaxChainDepth = MPTSAS_MAXIMUM_CHAIN_DEPTH;
610 reply.WhoInit = s->who_init;
611 reply.BlockSize = MPTSAS_MAX_REQUEST_SIZE / sizeof(uint32_t);
612 reply.ReplyQueueDepth = ARRAY_SIZE(s->reply_post) - 1;
613 QEMU_BUILD_BUG_ON(ARRAY_SIZE(s->reply_post) != ARRAY_SIZE(s->reply_free));
614
615 reply.RequestFrameSize = 128;
616 reply.ProductID = MPTSAS1068_PRODUCT_ID;
617 reply.CurrentHostMfaHighAddr = s->host_mfa_high_addr >> 32;
618 reply.GlobalCredits = ARRAY_SIZE(s->request_post) - 1;
619 reply.NumberOfPorts = MPTSAS_NUM_PORTS;
620 reply.CurrentSenseBufferHighAddr = s->sense_buffer_high_addr >> 32;
621 reply.CurReplyFrameSize = s->reply_frame_size;
622 reply.MaxDevices = s->max_devices;
623 reply.MaxBuses = s->max_buses;
624 reply.FWVersionDev = 0;
625 reply.FWVersionUnit = 0x92;
626 reply.FWVersionMinor = 0x32;
627 reply.FWVersionMajor = 0x1;
628
629 mptsas_fix_ioc_facts_reply_endianness(&reply);
630 mptsas_reply(s, (MPIDefaultReply *)&reply);
631 }
632
633 static void mptsas_process_port_facts(MPTSASState *s,
634 MPIMsgPortFacts *req)
635 {
636 MPIMsgPortFactsReply reply;
637
638 mptsas_fix_port_facts_endianness(req);
639
640 QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req));
641 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req));
642 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply));
643
644 memset(&reply, 0, sizeof(reply));
645 reply.MsgLength = sizeof(reply) / 4;
646 reply.Function = req->Function;
647 reply.PortNumber = req->PortNumber;
648 reply.MsgContext = req->MsgContext;
649
650 if (req->PortNumber < MPTSAS_NUM_PORTS) {
651 reply.PortType = MPI_PORTFACTS_PORTTYPE_SAS;
652 reply.MaxDevices = MPTSAS_NUM_PORTS;
653 reply.PortSCSIID = MPTSAS_NUM_PORTS;
654 reply.ProtocolFlags = MPI_PORTFACTS_PROTOCOL_LOGBUSADDR | MPI_PORTFACTS_PROTOCOL_INITIATOR;
655 }
656
657 mptsas_fix_port_facts_reply_endianness(&reply);
658 mptsas_reply(s, (MPIDefaultReply *)&reply);
659 }
660
661 static void mptsas_process_port_enable(MPTSASState *s,
662 MPIMsgPortEnable *req)
663 {
664 MPIMsgPortEnableReply reply;
665
666 mptsas_fix_port_enable_endianness(req);
667
668 QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req));
669 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req));
670 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply));
671
672 memset(&reply, 0, sizeof(reply));
673 reply.MsgLength = sizeof(reply) / 4;
674 reply.PortNumber = req->PortNumber;
675 reply.Function = req->Function;
676 reply.MsgContext = req->MsgContext;
677
678 mptsas_fix_port_enable_reply_endianness(&reply);
679 mptsas_reply(s, (MPIDefaultReply *)&reply);
680 }
681
682 static void mptsas_process_event_notification(MPTSASState *s,
683 MPIMsgEventNotify *req)
684 {
685 MPIMsgEventNotifyReply reply;
686
687 mptsas_fix_event_notification_endianness(req);
688
689 QEMU_BUILD_BUG_ON(MPTSAS_MAX_REQUEST_SIZE < sizeof(*req));
690 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_msg) < sizeof(*req));
691 QEMU_BUILD_BUG_ON(sizeof(s->doorbell_reply) < sizeof(reply));
692
693 /* Don't even bother storing whether event notification is enabled,
694 * since it is not accessible.
695 */
696
697 memset(&reply, 0, sizeof(reply));
698 reply.EventDataLength = sizeof(reply.Data) / 4;
699 reply.MsgLength = sizeof(reply) / 4;
700 reply.Function = req->Function;
701
702 /* This is set because events are sent through the reply FIFOs. */
703 reply.MsgFlags = MPI_MSGFLAGS_CONTINUATION_REPLY;
704
705 reply.MsgContext = req->MsgContext;
706 reply.Event = MPI_EVENT_EVENT_CHANGE;
707 reply.Data[0] = !!req->Switch;
708
709 mptsas_fix_event_notification_reply_endianness(&reply);
710 mptsas_reply(s, (MPIDefaultReply *)&reply);
711 }
712
713 static void mptsas_process_message(MPTSASState *s, MPIRequestHeader *req)
714 {
715 trace_mptsas_process_message(s, req->Function, req->MsgContext);
716 switch (req->Function) {
717 case MPI_FUNCTION_SCSI_TASK_MGMT:
718 mptsas_process_scsi_task_mgmt(s, (MPIMsgSCSITaskMgmt *)req);
719 break;
720
721 case MPI_FUNCTION_IOC_INIT:
722 mptsas_process_ioc_init(s, (MPIMsgIOCInit *)req);
723 break;
724
725 case MPI_FUNCTION_IOC_FACTS:
726 mptsas_process_ioc_facts(s, (MPIMsgIOCFacts *)req);
727 break;
728
729 case MPI_FUNCTION_PORT_FACTS:
730 mptsas_process_port_facts(s, (MPIMsgPortFacts *)req);
731 break;
732
733 case MPI_FUNCTION_PORT_ENABLE:
734 mptsas_process_port_enable(s, (MPIMsgPortEnable *)req);
735 break;
736
737 case MPI_FUNCTION_EVENT_NOTIFICATION:
738 mptsas_process_event_notification(s, (MPIMsgEventNotify *)req);
739 break;
740
741 case MPI_FUNCTION_CONFIG:
742 mptsas_process_config(s, (MPIMsgConfig *)req);
743 break;
744
745 default:
746 trace_mptsas_unhandled_cmd(s, req->Function, 0);
747 mptsas_set_fault(s, MPI_IOCSTATUS_INVALID_FUNCTION);
748 break;
749 }
750 }
751
752 static void mptsas_fetch_request(MPTSASState *s)
753 {
754 PCIDevice *pci = (PCIDevice *) s;
755 char req[MPTSAS_MAX_REQUEST_SIZE];
756 MPIRequestHeader *hdr = (MPIRequestHeader *)req;
757 hwaddr addr;
758 int size;
759
760 /* Read the message header from the guest first. */
761 addr = s->host_mfa_high_addr | MPTSAS_FIFO_GET(s, request_post);
762 pci_dma_read(pci, addr, req, sizeof(*hdr));
763
764 if (hdr->Function < ARRAY_SIZE(mpi_request_sizes) &&
765 mpi_request_sizes[hdr->Function]) {
766 /* Read the rest of the request based on the type. Do not
767 * reread everything, as that could cause a TOC/TOU mismatch
768 * and leak data from the QEMU stack.
769 */
770 size = mpi_request_sizes[hdr->Function];
771 assert(size <= MPTSAS_MAX_REQUEST_SIZE);
772 pci_dma_read(pci, addr + sizeof(*hdr), &req[sizeof(*hdr)],
773 size - sizeof(*hdr));
774 }
775
776 if (hdr->Function == MPI_FUNCTION_SCSI_IO_REQUEST) {
777 /* SCSI I/O requests are separate from mptsas_process_message
778 * because they cannot be sent through the doorbell yet.
779 */
780 mptsas_process_scsi_io_request(s, (MPIMsgSCSIIORequest *)req, addr);
781 } else {
782 mptsas_process_message(s, (MPIRequestHeader *)req);
783 }
784 }
785
786 static void mptsas_fetch_requests(void *opaque)
787 {
788 MPTSASState *s = opaque;
789
790 if (s->state != MPI_IOC_STATE_OPERATIONAL) {
791 mptsas_set_fault(s, MPI_IOCSTATUS_INVALID_STATE);
792 return;
793 }
794 while (!MPTSAS_FIFO_EMPTY(s, request_post)) {
795 mptsas_fetch_request(s);
796 }
797 }
798
799 static void mptsas_soft_reset(MPTSASState *s)
800 {
801 uint32_t save_mask;
802
803 trace_mptsas_reset(s);
804
805 /* Temporarily disable interrupts */
806 save_mask = s->intr_mask;
807 s->intr_mask = MPI_HIM_DIM | MPI_HIM_RIM;
808 mptsas_update_interrupt(s);
809
810 bus_cold_reset(BUS(&s->bus));
811 s->intr_status = 0;
812 s->intr_mask = save_mask;
813
814 s->doorbell_state = DOORBELL_NONE;
815 s->doorbell_reply_idx = 0;
816 s->doorbell_reply_size = 0;
817
818 s->reply_free_tail = 0;
819 s->reply_free_head = 0;
820 s->reply_post_tail = 0;
821 s->reply_post_head = 0;
822 s->request_post_tail = 0;
823 s->request_post_head = 0;
824 qemu_bh_cancel(s->request_bh);
825
826 s->state = MPI_IOC_STATE_READY;
827 }
828
829 static uint32_t mptsas_doorbell_read(MPTSASState *s)
830 {
831 uint32_t ret;
832
833 ret = (s->who_init << MPI_DOORBELL_WHO_INIT_SHIFT) & MPI_DOORBELL_WHO_INIT_MASK;
834 ret |= s->state;
835 switch (s->doorbell_state) {
836 case DOORBELL_NONE:
837 break;
838
839 case DOORBELL_WRITE:
840 ret |= MPI_DOORBELL_ACTIVE;
841 break;
842
843 case DOORBELL_READ:
844 /* Get rid of the IOC fault code. */
845 ret &= ~MPI_DOORBELL_DATA_MASK;
846
847 assert(s->intr_status & MPI_HIS_DOORBELL_INTERRUPT);
848 assert(s->doorbell_reply_idx <= s->doorbell_reply_size);
849
850 ret |= MPI_DOORBELL_ACTIVE;
851 if (s->doorbell_reply_idx < s->doorbell_reply_size) {
852 /* For more information about this endian switch, see the
853 * commit message for commit 36b62ae ("fw_cfg: fix endianness in
854 * fw_cfg_data_mem_read() / _write()", 2015-01-16).
855 */
856 ret |= le16_to_cpu(s->doorbell_reply[s->doorbell_reply_idx++]);
857 }
858 break;
859
860 default:
861 abort();
862 }
863
864 return ret;
865 }
866
867 static void mptsas_doorbell_write(MPTSASState *s, uint32_t val)
868 {
869 if (s->doorbell_state == DOORBELL_WRITE) {
870 if (s->doorbell_idx < s->doorbell_cnt) {
871 /* For more information about this endian switch, see the
872 * commit message for commit 36b62ae ("fw_cfg: fix endianness in
873 * fw_cfg_data_mem_read() / _write()", 2015-01-16).
874 */
875 s->doorbell_msg[s->doorbell_idx++] = cpu_to_le32(val);
876 if (s->doorbell_idx == s->doorbell_cnt) {
877 mptsas_process_message(s, (MPIRequestHeader *)s->doorbell_msg);
878 }
879 }
880 return;
881 }
882
883 switch ((val & MPI_DOORBELL_FUNCTION_MASK) >> MPI_DOORBELL_FUNCTION_SHIFT) {
884 case MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET:
885 mptsas_soft_reset(s);
886 break;
887 case MPI_FUNCTION_IO_UNIT_RESET:
888 break;
889 case MPI_FUNCTION_HANDSHAKE:
890 s->doorbell_state = DOORBELL_WRITE;
891 s->doorbell_idx = 0;
892 s->doorbell_cnt = (val & MPI_DOORBELL_ADD_DWORDS_MASK)
893 >> MPI_DOORBELL_ADD_DWORDS_SHIFT;
894 s->intr_status |= MPI_HIS_DOORBELL_INTERRUPT;
895 mptsas_update_interrupt(s);
896 break;
897 default:
898 trace_mptsas_unhandled_doorbell_cmd(s, val);
899 break;
900 }
901 }
902
903 static void mptsas_write_sequence_write(MPTSASState *s, uint32_t val)
904 {
905 /* If the diagnostic register is enabled, any write to this register
906 * will disable it. Otherwise, the guest has to do a magic five-write
907 * sequence.
908 */
909 if (s->diagnostic & MPI_DIAG_DRWE) {
910 goto disable;
911 }
912
913 switch (s->diagnostic_idx) {
914 case 0:
915 if ((val & MPI_WRSEQ_KEY_VALUE_MASK) != MPI_WRSEQ_1ST_KEY_VALUE) {
916 goto disable;
917 }
918 break;
919 case 1:
920 if ((val & MPI_WRSEQ_KEY_VALUE_MASK) != MPI_WRSEQ_2ND_KEY_VALUE) {
921 goto disable;
922 }
923 break;
924 case 2:
925 if ((val & MPI_WRSEQ_KEY_VALUE_MASK) != MPI_WRSEQ_3RD_KEY_VALUE) {
926 goto disable;
927 }
928 break;
929 case 3:
930 if ((val & MPI_WRSEQ_KEY_VALUE_MASK) != MPI_WRSEQ_4TH_KEY_VALUE) {
931 goto disable;
932 }
933 break;
934 case 4:
935 if ((val & MPI_WRSEQ_KEY_VALUE_MASK) != MPI_WRSEQ_5TH_KEY_VALUE) {
936 goto disable;
937 }
938 /* Prepare Spaceball One for departure, and change the
939 * combination on my luggage!
940 */
941 s->diagnostic |= MPI_DIAG_DRWE;
942 break;
943 }
944 s->diagnostic_idx++;
945 return;
946
947 disable:
948 s->diagnostic &= ~MPI_DIAG_DRWE;
949 s->diagnostic_idx = 0;
950 }
951
952 static int mptsas_hard_reset(MPTSASState *s)
953 {
954 mptsas_soft_reset(s);
955
956 s->intr_mask = MPI_HIM_DIM | MPI_HIM_RIM;
957
958 s->host_mfa_high_addr = 0;
959 s->sense_buffer_high_addr = 0;
960 s->reply_frame_size = 0;
961 s->max_devices = MPTSAS_NUM_PORTS;
962 s->max_buses = 1;
963
964 return 0;
965 }
966
967 static void mptsas_interrupt_status_write(MPTSASState *s)
968 {
969 switch (s->doorbell_state) {
970 case DOORBELL_NONE:
971 case DOORBELL_WRITE:
972 s->intr_status &= ~MPI_HIS_DOORBELL_INTERRUPT;
973 break;
974
975 case DOORBELL_READ:
976 /* The reply can be read continuously, so leave the interrupt up. */
977 assert(s->intr_status & MPI_HIS_DOORBELL_INTERRUPT);
978 if (s->doorbell_reply_idx == s->doorbell_reply_size) {
979 s->doorbell_state = DOORBELL_NONE;
980 }
981 break;
982
983 default:
984 abort();
985 }
986 mptsas_update_interrupt(s);
987 }
988
989 static uint32_t mptsas_reply_post_read(MPTSASState *s)
990 {
991 uint32_t ret;
992
993 if (!MPTSAS_FIFO_EMPTY(s, reply_post)) {
994 ret = MPTSAS_FIFO_GET(s, reply_post);
995 } else {
996 ret = -1;
997 s->intr_status &= ~MPI_HIS_REPLY_MESSAGE_INTERRUPT;
998 mptsas_update_interrupt(s);
999 }
1000
1001 return ret;
1002 }
1003
1004 static uint64_t mptsas_mmio_read(void *opaque, hwaddr addr,
1005 unsigned size)
1006 {
1007 MPTSASState *s = opaque;
1008 uint32_t ret = 0;
1009
1010 switch (addr & ~3) {
1011 case MPI_DOORBELL_OFFSET:
1012 ret = mptsas_doorbell_read(s);
1013 break;
1014
1015 case MPI_DIAGNOSTIC_OFFSET:
1016 ret = s->diagnostic;
1017 break;
1018
1019 case MPI_HOST_INTERRUPT_STATUS_OFFSET:
1020 ret = s->intr_status;
1021 break;
1022
1023 case MPI_HOST_INTERRUPT_MASK_OFFSET:
1024 ret = s->intr_mask;
1025 break;
1026
1027 case MPI_REPLY_POST_FIFO_OFFSET:
1028 ret = mptsas_reply_post_read(s);
1029 break;
1030
1031 default:
1032 trace_mptsas_mmio_unhandled_read(s, addr);
1033 break;
1034 }
1035 trace_mptsas_mmio_read(s, addr, ret);
1036 return ret;
1037 }
1038
1039 static void mptsas_mmio_write(void *opaque, hwaddr addr,
1040 uint64_t val, unsigned size)
1041 {
1042 MPTSASState *s = opaque;
1043
1044 trace_mptsas_mmio_write(s, addr, val);
1045 switch (addr) {
1046 case MPI_DOORBELL_OFFSET:
1047 mptsas_doorbell_write(s, val);
1048 break;
1049
1050 case MPI_WRITE_SEQUENCE_OFFSET:
1051 mptsas_write_sequence_write(s, val);
1052 break;
1053
1054 case MPI_DIAGNOSTIC_OFFSET:
1055 if (val & MPI_DIAG_RESET_ADAPTER) {
1056 mptsas_hard_reset(s);
1057 }
1058 break;
1059
1060 case MPI_HOST_INTERRUPT_STATUS_OFFSET:
1061 mptsas_interrupt_status_write(s);
1062 break;
1063
1064 case MPI_HOST_INTERRUPT_MASK_OFFSET:
1065 s->intr_mask = val & (MPI_HIM_RIM | MPI_HIM_DIM);
1066 mptsas_update_interrupt(s);
1067 break;
1068
1069 case MPI_REQUEST_POST_FIFO_OFFSET:
1070 if (MPTSAS_FIFO_FULL(s, request_post)) {
1071 mptsas_set_fault(s, MPI_IOCSTATUS_INSUFFICIENT_RESOURCES);
1072 } else {
1073 MPTSAS_FIFO_PUT(s, request_post, val & ~0x03);
1074 qemu_bh_schedule(s->request_bh);
1075 }
1076 break;
1077
1078 case MPI_REPLY_FREE_FIFO_OFFSET:
1079 if (MPTSAS_FIFO_FULL(s, reply_free)) {
1080 mptsas_set_fault(s, MPI_IOCSTATUS_INSUFFICIENT_RESOURCES);
1081 } else {
1082 MPTSAS_FIFO_PUT(s, reply_free, val);
1083 }
1084 break;
1085
1086 default:
1087 trace_mptsas_mmio_unhandled_write(s, addr, val);
1088 break;
1089 }
1090 }
1091
1092 static const MemoryRegionOps mptsas_mmio_ops = {
1093 .read = mptsas_mmio_read,
1094 .write = mptsas_mmio_write,
1095 .endianness = DEVICE_LITTLE_ENDIAN,
1096 .impl = {
1097 .min_access_size = 4,
1098 .max_access_size = 4,
1099 }
1100 };
1101
1102 static const MemoryRegionOps mptsas_port_ops = {
1103 .read = mptsas_mmio_read,
1104 .write = mptsas_mmio_write,
1105 .endianness = DEVICE_LITTLE_ENDIAN,
1106 .impl = {
1107 .min_access_size = 4,
1108 .max_access_size = 4,
1109 }
1110 };
1111
1112 static uint64_t mptsas_diag_read(void *opaque, hwaddr addr,
1113 unsigned size)
1114 {
1115 MPTSASState *s = opaque;
1116 trace_mptsas_diag_read(s, addr, 0);
1117 return 0;
1118 }
1119
1120 static void mptsas_diag_write(void *opaque, hwaddr addr,
1121 uint64_t val, unsigned size)
1122 {
1123 MPTSASState *s = opaque;
1124 trace_mptsas_diag_write(s, addr, val);
1125 }
1126
1127 static const MemoryRegionOps mptsas_diag_ops = {
1128 .read = mptsas_diag_read,
1129 .write = mptsas_diag_write,
1130 .endianness = DEVICE_LITTLE_ENDIAN,
1131 .impl = {
1132 .min_access_size = 4,
1133 .max_access_size = 4,
1134 }
1135 };
1136
1137 static QEMUSGList *mptsas_get_sg_list(SCSIRequest *sreq)
1138 {
1139 MPTSASRequest *req = sreq->hba_private;
1140
1141 return &req->qsg;
1142 }
1143
1144 static void mptsas_command_complete(SCSIRequest *sreq,
1145 size_t resid)
1146 {
1147 MPTSASRequest *req = sreq->hba_private;
1148 MPTSASState *s = req->dev;
1149 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE];
1150 uint8_t sense_len;
1151
1152 hwaddr sense_buffer_addr = req->dev->sense_buffer_high_addr |
1153 req->scsi_io.SenseBufferLowAddr;
1154
1155 trace_mptsas_command_complete(s, req->scsi_io.MsgContext,
1156 sreq->status, resid);
1157
1158 sense_len = scsi_req_get_sense(sreq, sense_buf, SCSI_SENSE_BUF_SIZE);
1159 if (sense_len > 0) {
1160 pci_dma_write(PCI_DEVICE(s), sense_buffer_addr, sense_buf,
1161 MIN(req->scsi_io.SenseBufferLength, sense_len));
1162 }
1163
1164 if (sreq->status != GOOD || resid ||
1165 req->dev->doorbell_state == DOORBELL_WRITE) {
1166 MPIMsgSCSIIOReply reply;
1167
1168 memset(&reply, 0, sizeof(reply));
1169 reply.TargetID = req->scsi_io.TargetID;
1170 reply.Bus = req->scsi_io.Bus;
1171 reply.MsgLength = sizeof(reply) / 4;
1172 reply.Function = req->scsi_io.Function;
1173 reply.CDBLength = req->scsi_io.CDBLength;
1174 reply.SenseBufferLength = req->scsi_io.SenseBufferLength;
1175 reply.MsgFlags = req->scsi_io.MsgFlags;
1176 reply.MsgContext = req->scsi_io.MsgContext;
1177 reply.SCSIStatus = sreq->status;
1178 if (sreq->status == GOOD) {
1179 reply.TransferCount = req->scsi_io.DataLength - resid;
1180 if (resid) {
1181 reply.IOCStatus = MPI_IOCSTATUS_SCSI_DATA_UNDERRUN;
1182 }
1183 } else {
1184 reply.SCSIState = MPI_SCSI_STATE_AUTOSENSE_VALID;
1185 reply.SenseCount = sense_len;
1186 reply.IOCStatus = MPI_IOCSTATUS_SCSI_DATA_UNDERRUN;
1187 }
1188
1189 mptsas_fix_scsi_io_reply_endianness(&reply);
1190 mptsas_post_reply(req->dev, (MPIDefaultReply *)&reply);
1191 } else {
1192 mptsas_turbo_reply(req->dev, req->scsi_io.MsgContext);
1193 }
1194
1195 mptsas_free_request(req);
1196 }
1197
1198 static void mptsas_request_cancelled(SCSIRequest *sreq)
1199 {
1200 MPTSASRequest *req = sreq->hba_private;
1201 MPIMsgSCSIIOReply reply;
1202
1203 memset(&reply, 0, sizeof(reply));
1204 reply.TargetID = req->scsi_io.TargetID;
1205 reply.Bus = req->scsi_io.Bus;
1206 reply.MsgLength = sizeof(reply) / 4;
1207 reply.Function = req->scsi_io.Function;
1208 reply.CDBLength = req->scsi_io.CDBLength;
1209 reply.SenseBufferLength = req->scsi_io.SenseBufferLength;
1210 reply.MsgFlags = req->scsi_io.MsgFlags;
1211 reply.MsgContext = req->scsi_io.MsgContext;
1212 reply.SCSIState = MPI_SCSI_STATE_NO_SCSI_STATUS;
1213 reply.IOCStatus = MPI_IOCSTATUS_SCSI_TASK_TERMINATED;
1214
1215 mptsas_fix_scsi_io_reply_endianness(&reply);
1216 mptsas_post_reply(req->dev, (MPIDefaultReply *)&reply);
1217 mptsas_free_request(req);
1218 }
1219
1220 static void mptsas_save_request(QEMUFile *f, SCSIRequest *sreq)
1221 {
1222 MPTSASRequest *req = sreq->hba_private;
1223 int i;
1224
1225 qemu_put_buffer(f, (unsigned char *)&req->scsi_io, sizeof(req->scsi_io));
1226 qemu_put_be32(f, req->qsg.nsg);
1227 for (i = 0; i < req->qsg.nsg; i++) {
1228 qemu_put_be64(f, req->qsg.sg[i].base);
1229 qemu_put_be64(f, req->qsg.sg[i].len);
1230 }
1231 }
1232
1233 static void *mptsas_load_request(QEMUFile *f, SCSIRequest *sreq)
1234 {
1235 SCSIBus *bus = sreq->bus;
1236 MPTSASState *s = container_of(bus, MPTSASState, bus);
1237 PCIDevice *pci = PCI_DEVICE(s);
1238 MPTSASRequest *req;
1239 int i, n;
1240
1241 req = g_new(MPTSASRequest, 1);
1242 qemu_get_buffer(f, (unsigned char *)&req->scsi_io, sizeof(req->scsi_io));
1243
1244 n = qemu_get_be32(f);
1245 /* TODO: add a way for SCSIBusInfo's load_request to fail,
1246 * and fail migration instead of asserting here.
1247 * This is just one thing (there are probably more) that must be
1248 * fixed before we can allow NDEBUG compilation.
1249 */
1250 assert(n >= 0);
1251
1252 pci_dma_sglist_init(&req->qsg, pci, n);
1253 for (i = 0; i < n; i++) {
1254 uint64_t base = qemu_get_be64(f);
1255 uint64_t len = qemu_get_be64(f);
1256 qemu_sglist_add(&req->qsg, base, len);
1257 }
1258
1259 scsi_req_ref(sreq);
1260 req->sreq = sreq;
1261 req->dev = s;
1262
1263 return req;
1264 }
1265
1266 static const struct SCSIBusInfo mptsas_scsi_info = {
1267 .tcq = true,
1268 .max_target = MPTSAS_NUM_PORTS,
1269 .max_lun = 1,
1270
1271 .get_sg_list = mptsas_get_sg_list,
1272 .complete = mptsas_command_complete,
1273 .cancel = mptsas_request_cancelled,
1274 .save_request = mptsas_save_request,
1275 .load_request = mptsas_load_request,
1276 };
1277
1278 static void mptsas_scsi_realize(PCIDevice *dev, Error **errp)
1279 {
1280 MPTSASState *s = MPT_SAS(dev);
1281 Error *err = NULL;
1282 int ret;
1283
1284 dev->config[PCI_LATENCY_TIMER] = 0;
1285 dev->config[PCI_INTERRUPT_PIN] = 0x01;
1286
1287 if (s->msi != ON_OFF_AUTO_OFF) {
1288 ret = msi_init(dev, 0, 1, true, false, &err);
1289 /* Any error other than -ENOTSUP(board's MSI support is broken)
1290 * is a programming error */
1291 assert(!ret || ret == -ENOTSUP);
1292 if (ret && s->msi == ON_OFF_AUTO_ON) {
1293 /* Can't satisfy user's explicit msi=on request, fail */
1294 error_append_hint(&err, "You have to use msi=auto (default) or "
1295 "msi=off with this machine type.\n");
1296 error_propagate(errp, err);
1297 return;
1298 }
1299 assert(!err || s->msi == ON_OFF_AUTO_AUTO);
1300 /* With msi=auto, we fall back to MSI off silently */
1301 error_free(err);
1302
1303 /* Only used for migration. */
1304 s->msi_in_use = (ret == 0);
1305 }
1306
1307 memory_region_init_io(&s->mmio_io, OBJECT(s), &mptsas_mmio_ops, s,
1308 "mptsas-mmio", 0x4000);
1309 memory_region_init_io(&s->port_io, OBJECT(s), &mptsas_port_ops, s,
1310 "mptsas-io", 256);
1311 memory_region_init_io(&s->diag_io, OBJECT(s), &mptsas_diag_ops, s,
1312 "mptsas-diag", 0x10000);
1313
1314 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->port_io);
1315 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY |
1316 PCI_BASE_ADDRESS_MEM_TYPE_32, &s->mmio_io);
1317 pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY |
1318 PCI_BASE_ADDRESS_MEM_TYPE_32, &s->diag_io);
1319
1320 if (!s->sas_addr) {
1321 s->sas_addr = ((NAA_LOCALLY_ASSIGNED_ID << 24) |
1322 IEEE_COMPANY_LOCALLY_ASSIGNED) << 36;
1323 s->sas_addr |= (pci_dev_bus_num(dev) << 16);
1324 s->sas_addr |= (PCI_SLOT(dev->devfn) << 8);
1325 s->sas_addr |= PCI_FUNC(dev->devfn);
1326 }
1327 s->max_devices = MPTSAS_NUM_PORTS;
1328
1329 s->request_bh = qemu_bh_new_guarded(mptsas_fetch_requests, s,
1330 &DEVICE(dev)->mem_reentrancy_guard);
1331
1332 scsi_bus_init(&s->bus, sizeof(s->bus), &dev->qdev, &mptsas_scsi_info);
1333 }
1334
1335 static void mptsas_scsi_uninit(PCIDevice *dev)
1336 {
1337 MPTSASState *s = MPT_SAS(dev);
1338
1339 qemu_bh_delete(s->request_bh);
1340 msi_uninit(dev);
1341 }
1342
1343 static void mptsas_reset(DeviceState *dev)
1344 {
1345 MPTSASState *s = MPT_SAS(dev);
1346
1347 mptsas_hard_reset(s);
1348 }
1349
1350 static int mptsas_post_load(void *opaque, int version_id)
1351 {
1352 MPTSASState *s = opaque;
1353
1354 if (s->doorbell_idx > s->doorbell_cnt ||
1355 s->doorbell_cnt > ARRAY_SIZE(s->doorbell_msg) ||
1356 s->doorbell_reply_idx > s->doorbell_reply_size ||
1357 s->doorbell_reply_size > ARRAY_SIZE(s->doorbell_reply) ||
1358 MPTSAS_FIFO_INVALID(s, request_post) ||
1359 MPTSAS_FIFO_INVALID(s, reply_post) ||
1360 MPTSAS_FIFO_INVALID(s, reply_free) ||
1361 s->diagnostic_idx > 4) {
1362 return -EINVAL;
1363 }
1364
1365 return 0;
1366 }
1367
1368 static const VMStateDescription vmstate_mptsas = {
1369 .name = "mptsas",
1370 .version_id = 0,
1371 .minimum_version_id = 0,
1372 .post_load = mptsas_post_load,
1373 .fields = (const VMStateField[]) {
1374 VMSTATE_PCI_DEVICE(dev, MPTSASState),
1375 VMSTATE_BOOL(msi_in_use, MPTSASState),
1376 VMSTATE_UINT32(state, MPTSASState),
1377 VMSTATE_UINT8(who_init, MPTSASState),
1378 VMSTATE_UINT8(doorbell_state, MPTSASState),
1379 VMSTATE_UINT32_ARRAY(doorbell_msg, MPTSASState, 256),
1380 VMSTATE_INT32(doorbell_idx, MPTSASState),
1381 VMSTATE_INT32(doorbell_cnt, MPTSASState),
1382
1383 VMSTATE_UINT16_ARRAY(doorbell_reply, MPTSASState, 256),
1384 VMSTATE_INT32(doorbell_reply_idx, MPTSASState),
1385 VMSTATE_INT32(doorbell_reply_size, MPTSASState),
1386
1387 VMSTATE_UINT32(diagnostic, MPTSASState),
1388 VMSTATE_UINT8(diagnostic_idx, MPTSASState),
1389
1390 VMSTATE_UINT32(intr_status, MPTSASState),
1391 VMSTATE_UINT32(intr_mask, MPTSASState),
1392
1393 VMSTATE_UINT32_ARRAY(request_post, MPTSASState,
1394 MPTSAS_REQUEST_QUEUE_DEPTH + 1),
1395 VMSTATE_UINT16(request_post_head, MPTSASState),
1396 VMSTATE_UINT16(request_post_tail, MPTSASState),
1397
1398 VMSTATE_UINT32_ARRAY(reply_post, MPTSASState,
1399 MPTSAS_REPLY_QUEUE_DEPTH + 1),
1400 VMSTATE_UINT16(reply_post_head, MPTSASState),
1401 VMSTATE_UINT16(reply_post_tail, MPTSASState),
1402
1403 VMSTATE_UINT32_ARRAY(reply_free, MPTSASState,
1404 MPTSAS_REPLY_QUEUE_DEPTH + 1),
1405 VMSTATE_UINT16(reply_free_head, MPTSASState),
1406 VMSTATE_UINT16(reply_free_tail, MPTSASState),
1407
1408 VMSTATE_UINT16(max_buses, MPTSASState),
1409 VMSTATE_UINT16(max_devices, MPTSASState),
1410 VMSTATE_UINT16(reply_frame_size, MPTSASState),
1411 VMSTATE_UINT64(host_mfa_high_addr, MPTSASState),
1412 VMSTATE_UINT64(sense_buffer_high_addr, MPTSASState),
1413 VMSTATE_END_OF_LIST()
1414 }
1415 };
1416
1417 static const Property mptsas_properties[] = {
1418 DEFINE_PROP_UINT64("sas_address", MPTSASState, sas_addr, 0),
1419 /* TODO: test MSI support under Windows */
1420 DEFINE_PROP_ON_OFF_AUTO("msi", MPTSASState, msi, ON_OFF_AUTO_AUTO),
1421 };
1422
1423 static void mptsas1068_class_init(ObjectClass *oc, const void *data)
1424 {
1425 DeviceClass *dc = DEVICE_CLASS(oc);
1426 PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc);
1427
1428 pc->realize = mptsas_scsi_realize;
1429 pc->exit = mptsas_scsi_uninit;
1430 pc->romfile = 0;
1431 pc->vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
1432 pc->device_id = PCI_DEVICE_ID_LSI_SAS1068;
1433 pc->subsystem_vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
1434 pc->subsystem_id = 0x8000;
1435 pc->class_id = PCI_CLASS_STORAGE_SCSI;
1436 device_class_set_props(dc, mptsas_properties);
1437 device_class_set_legacy_reset(dc, mptsas_reset);
1438 dc->vmsd = &vmstate_mptsas;
1439 dc->desc = "LSI SAS 1068";
1440 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
1441 }
1442
1443 static const TypeInfo mptsas_info = {
1444 .name = TYPE_MPTSAS1068,
1445 .parent = TYPE_PCI_DEVICE,
1446 .instance_size = sizeof(MPTSASState),
1447 .class_init = mptsas1068_class_init,
1448 .interfaces = (const InterfaceInfo[]) {
1449 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
1450 { },
1451 },
1452 };
1453
1454 static void mptsas_register_types(void)
1455 {
1456 type_register_static(&mptsas_info);
1457 }
1458
1459 type_init(mptsas_register_types)