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1 /*
2 * QEMU VMWARE PVSCSI paravirtual SCSI bus
3 *
4 * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
5 *
6 * Developed by Daynix Computing LTD (http://www.daynix.com)
7 *
8 * Based on implementation by Paolo Bonzini
9 * http://lists.gnu.org/archive/html/qemu-devel/2011-08/msg00729.html
10 *
11 * Authors:
12 * Paolo Bonzini <pbonzini@redhat.com>
13 * Dmitry Fleytman <dmitry@daynix.com>
14 * Yan Vugenfirer <yan@daynix.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2.
17 * See the COPYING file in the top-level directory.
18 *
19 * NOTE about MSI-X:
20 * MSI-X support has been removed for the moment because it leads Windows OS
21 * to crash on startup. The crash happens because Windows driver requires
22 * MSI-X shared memory to be part of the same BAR used for rings state
23 * registers, etc. This is not supported by QEMU infrastructure so separate
24 * BAR created from MSI-X purposes. Windows driver fails to deal with 2 BARs.
25 *
26 */
27
28 #include "qemu/osdep.h"
29 #include "qapi/error.h"
30 #include "qemu/main-loop.h"
31 #include "qemu/module.h"
32 #include "hw/scsi/scsi.h"
33 #include "migration/vmstate.h"
34 #include "scsi/constants.h"
35 #include "hw/pci/msi.h"
36 #include "hw/core/qdev-properties.h"
37 #include "system/physmem.h"
38 #include "vmw_pvscsi.h"
39 #include "trace.h"
40 #include "qom/object.h"
41
42
43 #define PVSCSI_USE_64BIT (true)
44 #define PVSCSI_PER_VECTOR_MASK (false)
45
46 #define PVSCSI_MAX_DEVS (64)
47 #define PVSCSI_MSIX_NUM_VECTORS (1)
48
49 #define PVSCSI_MAX_SG_ELEM 2048
50
51 #define PVSCSI_MAX_CMD_DATA_WORDS \
52 (sizeof(PVSCSICmdDescSetupRings)/sizeof(uint32_t))
53
54 #define RS_GET_FIELD(pval, m, field) \
55 ldl_le_pci_dma(&container_of(m, PVSCSIState, rings)->parent_obj, \
56 (m)->rs_pa + offsetof(struct PVSCSIRingsState, field), \
57 pval, MEMTXATTRS_UNSPECIFIED)
58 #define RS_SET_FIELD(m, field, val) \
59 (stl_le_pci_dma(&container_of(m, PVSCSIState, rings)->parent_obj, \
60 (m)->rs_pa + offsetof(struct PVSCSIRingsState, field), val, \
61 MEMTXATTRS_UNSPECIFIED))
62
63 struct PVSCSIClass {
64 PCIDeviceClass parent_class;
65 DeviceRealize parent_dc_realize;
66 };
67
68 #define TYPE_PVSCSI "pvscsi"
69 OBJECT_DECLARE_TYPE(PVSCSIState, PVSCSIClass, PVSCSI)
70
71
72 #define PVSCSI_MSI_OFFSET (0x7c)
73 #define PVSCSI_EXP_EP_OFFSET (0x40)
74
75 typedef struct PVSCSIRingInfo {
76 uint64_t rs_pa;
77 uint32_t txr_len_mask;
78 uint32_t rxr_len_mask;
79 uint32_t msg_len_mask;
80 uint64_t req_ring_pages_pa[PVSCSI_SETUP_RINGS_MAX_NUM_PAGES];
81 uint64_t cmp_ring_pages_pa[PVSCSI_SETUP_RINGS_MAX_NUM_PAGES];
82 uint64_t msg_ring_pages_pa[PVSCSI_SETUP_MSG_RING_MAX_NUM_PAGES];
83 uint64_t consumed_ptr;
84 uint64_t filled_cmp_ptr;
85 uint64_t filled_msg_ptr;
86 } PVSCSIRingInfo;
87
88 typedef struct PVSCSISGState {
89 hwaddr elemAddr;
90 hwaddr dataAddr;
91 uint32_t resid;
92 } PVSCSISGState;
93
94 typedef QTAILQ_HEAD(, PVSCSIRequest) PVSCSIRequestList;
95
96 struct PVSCSIState {
97 PCIDevice parent_obj;
98 MemoryRegion io_space;
99 SCSIBus bus;
100 QEMUBH *completion_worker;
101 PVSCSIRequestList pending_queue;
102 PVSCSIRequestList completion_queue;
103
104 uint64_t reg_interrupt_status; /* Interrupt status register value */
105 uint64_t reg_interrupt_enabled; /* Interrupt mask register value */
106 uint64_t reg_command_status; /* Command status register value */
107
108 /* Command data adoption mechanism */
109 uint64_t curr_cmd; /* Last command arrived */
110 uint32_t curr_cmd_data_cntr; /* Amount of data for last command */
111
112 /* Collector for current command data */
113 uint32_t curr_cmd_data[PVSCSI_MAX_CMD_DATA_WORDS];
114
115 uint8_t rings_info_valid; /* Whether data rings initialized */
116 uint8_t msg_ring_info_valid; /* Whether message ring initialized */
117 uint8_t use_msg; /* Whether to use message ring */
118
119 uint8_t msi_used; /* For migration compatibility */
120 PVSCSIRingInfo rings; /* Data transfer rings manager */
121 uint32_t resetting; /* Reset in progress */
122 };
123
124 typedef struct PVSCSIRequest {
125 SCSIRequest *sreq;
126 PVSCSIState *dev;
127 uint8_t sense_key;
128 uint8_t completed;
129 int lun;
130 QEMUSGList sgl;
131 PVSCSISGState sg;
132 struct PVSCSIRingReqDesc req;
133 struct PVSCSIRingCmpDesc cmp;
134 QTAILQ_ENTRY(PVSCSIRequest) next;
135 } PVSCSIRequest;
136
137 /* Integer binary logarithm */
138 static int
139 pvscsi_log2(uint32_t input)
140 {
141 int log = 0;
142 assert(input > 0);
143 while (input >> ++log) {
144 }
145 return log;
146 }
147
148 static void
149 pvscsi_ring_init_data(PVSCSIRingInfo *m, PVSCSICmdDescSetupRings *ri)
150 {
151 int i;
152 uint32_t txr_len_log2, rxr_len_log2;
153 uint32_t req_ring_size, cmp_ring_size;
154 m->rs_pa = ri->ringsStatePPN << VMW_PAGE_SHIFT;
155
156 req_ring_size = ri->reqRingNumPages * PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE;
157 cmp_ring_size = ri->cmpRingNumPages * PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE;
158 txr_len_log2 = pvscsi_log2(req_ring_size - 1);
159 rxr_len_log2 = pvscsi_log2(cmp_ring_size - 1);
160
161 m->txr_len_mask = MASK(txr_len_log2);
162 m->rxr_len_mask = MASK(rxr_len_log2);
163
164 m->consumed_ptr = 0;
165 m->filled_cmp_ptr = 0;
166
167 for (i = 0; i < ri->reqRingNumPages; i++) {
168 m->req_ring_pages_pa[i] = ri->reqRingPPNs[i] << VMW_PAGE_SHIFT;
169 }
170
171 for (i = 0; i < ri->cmpRingNumPages; i++) {
172 m->cmp_ring_pages_pa[i] = ri->cmpRingPPNs[i] << VMW_PAGE_SHIFT;
173 }
174
175 RS_SET_FIELD(m, reqProdIdx, 0);
176 RS_SET_FIELD(m, reqConsIdx, 0);
177 RS_SET_FIELD(m, reqNumEntriesLog2, txr_len_log2);
178
179 RS_SET_FIELD(m, cmpProdIdx, 0);
180 RS_SET_FIELD(m, cmpConsIdx, 0);
181 RS_SET_FIELD(m, cmpNumEntriesLog2, rxr_len_log2);
182
183 trace_pvscsi_ring_init_data(txr_len_log2, rxr_len_log2);
184
185 /* Flush ring state page changes */
186 smp_wmb();
187 }
188
189 static int
190 pvscsi_ring_init_msg(PVSCSIRingInfo *m, PVSCSICmdDescSetupMsgRing *ri)
191 {
192 int i;
193 uint32_t len_log2;
194 uint32_t ring_size;
195
196 if (!ri->numPages || ri->numPages > PVSCSI_SETUP_MSG_RING_MAX_NUM_PAGES) {
197 return -1;
198 }
199 ring_size = ri->numPages * PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE;
200 len_log2 = pvscsi_log2(ring_size - 1);
201
202 m->msg_len_mask = MASK(len_log2);
203
204 m->filled_msg_ptr = 0;
205
206 for (i = 0; i < ri->numPages; i++) {
207 m->msg_ring_pages_pa[i] = ri->ringPPNs[i] << VMW_PAGE_SHIFT;
208 }
209
210 RS_SET_FIELD(m, msgProdIdx, 0);
211 RS_SET_FIELD(m, msgConsIdx, 0);
212 RS_SET_FIELD(m, msgNumEntriesLog2, len_log2);
213
214 trace_pvscsi_ring_init_msg(len_log2);
215
216 /* Flush ring state page changes */
217 smp_wmb();
218
219 return 0;
220 }
221
222 static void
223 pvscsi_ring_cleanup(PVSCSIRingInfo *mgr)
224 {
225 mgr->rs_pa = 0;
226 mgr->txr_len_mask = 0;
227 mgr->rxr_len_mask = 0;
228 mgr->msg_len_mask = 0;
229 mgr->consumed_ptr = 0;
230 mgr->filled_cmp_ptr = 0;
231 mgr->filled_msg_ptr = 0;
232 memset(mgr->req_ring_pages_pa, 0, sizeof(mgr->req_ring_pages_pa));
233 memset(mgr->cmp_ring_pages_pa, 0, sizeof(mgr->cmp_ring_pages_pa));
234 memset(mgr->msg_ring_pages_pa, 0, sizeof(mgr->msg_ring_pages_pa));
235 }
236
237 static hwaddr
238 pvscsi_ring_pop_req_descr(PVSCSIRingInfo *mgr)
239 {
240 uint32_t ready_ptr;
241 uint32_t ring_size = PVSCSI_MAX_NUM_PAGES_REQ_RING
242 * PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE;
243
244 RS_GET_FIELD(&ready_ptr, mgr, reqProdIdx);
245 if (ready_ptr != mgr->consumed_ptr
246 && ready_ptr - mgr->consumed_ptr < ring_size) {
247 uint32_t next_ready_ptr =
248 mgr->consumed_ptr++ & mgr->txr_len_mask;
249 uint32_t next_ready_page =
250 next_ready_ptr / PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE;
251 uint32_t inpage_idx =
252 next_ready_ptr % PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE;
253
254 return mgr->req_ring_pages_pa[next_ready_page] +
255 inpage_idx * sizeof(PVSCSIRingReqDesc);
256 } else {
257 return 0;
258 }
259 }
260
261 static void
262 pvscsi_ring_flush_req(PVSCSIRingInfo *mgr)
263 {
264 RS_SET_FIELD(mgr, reqConsIdx, mgr->consumed_ptr);
265 }
266
267 static hwaddr
268 pvscsi_ring_pop_cmp_descr(PVSCSIRingInfo *mgr)
269 {
270 /*
271 * According to Linux driver code it explicitly verifies that number
272 * of requests being processed by device is less then the size of
273 * completion queue, so device may omit completion queue overflow
274 * conditions check. We assume that this is true for other (Windows)
275 * drivers as well.
276 */
277
278 uint32_t free_cmp_ptr =
279 mgr->filled_cmp_ptr++ & mgr->rxr_len_mask;
280 uint32_t free_cmp_page =
281 free_cmp_ptr / PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE;
282 uint32_t inpage_idx =
283 free_cmp_ptr % PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE;
284 return mgr->cmp_ring_pages_pa[free_cmp_page] +
285 inpage_idx * sizeof(PVSCSIRingCmpDesc);
286 }
287
288 static hwaddr
289 pvscsi_ring_pop_msg_descr(PVSCSIRingInfo *mgr)
290 {
291 uint32_t free_msg_ptr =
292 mgr->filled_msg_ptr++ & mgr->msg_len_mask;
293 uint32_t free_msg_page =
294 free_msg_ptr / PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE;
295 uint32_t inpage_idx =
296 free_msg_ptr % PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE;
297 return mgr->msg_ring_pages_pa[free_msg_page] +
298 inpage_idx * sizeof(PVSCSIRingMsgDesc);
299 }
300
301 static void
302 pvscsi_ring_flush_cmp(PVSCSIRingInfo *mgr)
303 {
304 /* Flush descriptor changes */
305 smp_wmb();
306
307 trace_pvscsi_ring_flush_cmp(mgr->filled_cmp_ptr);
308
309 RS_SET_FIELD(mgr, cmpProdIdx, mgr->filled_cmp_ptr);
310 }
311
312 static bool
313 pvscsi_ring_msg_has_room(PVSCSIRingInfo *mgr)
314 {
315 uint32_t prodIdx;
316 uint32_t consIdx;
317
318 RS_GET_FIELD(&prodIdx, mgr, msgProdIdx);
319 RS_GET_FIELD(&consIdx, mgr, msgConsIdx);
320
321 return (prodIdx - consIdx) < (mgr->msg_len_mask + 1);
322 }
323
324 static void
325 pvscsi_ring_flush_msg(PVSCSIRingInfo *mgr)
326 {
327 /* Flush descriptor changes */
328 smp_wmb();
329
330 trace_pvscsi_ring_flush_msg(mgr->filled_msg_ptr);
331
332 RS_SET_FIELD(mgr, msgProdIdx, mgr->filled_msg_ptr);
333 }
334
335 static void
336 pvscsi_reset_state(PVSCSIState *s)
337 {
338 s->curr_cmd = PVSCSI_CMD_FIRST;
339 s->curr_cmd_data_cntr = 0;
340 s->reg_command_status = PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
341 s->reg_interrupt_status = 0;
342 pvscsi_ring_cleanup(&s->rings);
343 s->rings_info_valid = FALSE;
344 s->msg_ring_info_valid = FALSE;
345 QTAILQ_INIT(&s->pending_queue);
346 QTAILQ_INIT(&s->completion_queue);
347 }
348
349 static void
350 pvscsi_update_irq_status(PVSCSIState *s)
351 {
352 PCIDevice *d = PCI_DEVICE(s);
353 bool should_raise = s->reg_interrupt_enabled & s->reg_interrupt_status;
354
355 trace_pvscsi_update_irq_level(should_raise, s->reg_interrupt_enabled,
356 s->reg_interrupt_status);
357
358 if (msi_enabled(d)) {
359 if (should_raise) {
360 trace_pvscsi_update_irq_msi();
361 msi_notify(d, PVSCSI_VECTOR_COMPLETION);
362 }
363 return;
364 }
365
366 pci_set_irq(d, !!should_raise);
367 }
368
369 static void
370 pvscsi_raise_completion_interrupt(PVSCSIState *s)
371 {
372 s->reg_interrupt_status |= PVSCSI_INTR_CMPL_0;
373
374 /* Memory barrier to flush interrupt status register changes*/
375 smp_wmb();
376
377 pvscsi_update_irq_status(s);
378 }
379
380 static void
381 pvscsi_raise_message_interrupt(PVSCSIState *s)
382 {
383 s->reg_interrupt_status |= PVSCSI_INTR_MSG_0;
384
385 /* Memory barrier to flush interrupt status register changes*/
386 smp_wmb();
387
388 pvscsi_update_irq_status(s);
389 }
390
391 static void
392 pvscsi_cmp_ring_put(PVSCSIState *s, struct PVSCSIRingCmpDesc *cmp_desc)
393 {
394 hwaddr cmp_descr_pa;
395 PVSCSIRingCmpDesc cmp_desc_conv;
396
397 cmp_descr_pa = pvscsi_ring_pop_cmp_descr(&s->rings);
398 trace_pvscsi_cmp_ring_put(cmp_descr_pa);
399 cmp_desc_conv = (struct PVSCSIRingCmpDesc) {
400 .context = cpu_to_le64(cmp_desc->context),
401 .dataLen = cpu_to_le64(cmp_desc->dataLen),
402 .senseLen = cpu_to_le32(cmp_desc->senseLen),
403 .hostStatus = cpu_to_le16(cmp_desc->hostStatus),
404 .scsiStatus = cpu_to_le16(cmp_desc->scsiStatus),
405 };
406 cmp_desc = &cmp_desc_conv;
407 physical_memory_write(cmp_descr_pa, cmp_desc, sizeof(*cmp_desc));
408 }
409
410 static void
411 pvscsi_msg_ring_put(PVSCSIState *s, struct PVSCSIRingMsgDesc *msg_desc)
412 {
413 hwaddr msg_descr_pa;
414 PVSCSIRingMsgDesc msg_desc_conv;
415 int i;
416
417 msg_descr_pa = pvscsi_ring_pop_msg_descr(&s->rings);
418 trace_pvscsi_msg_ring_put(msg_descr_pa);
419 msg_desc_conv = (PVSCSIRingMsgDesc) {
420 .type = cpu_to_le32(msg_desc->type),
421 };
422 for (i = 0; i < ARRAY_SIZE(msg_desc->args); i++) {
423 msg_desc_conv.args[i] = cpu_to_le32(msg_desc->args[i]);
424 }
425 msg_desc = &msg_desc_conv;
426 physical_memory_write(msg_descr_pa, msg_desc, sizeof(*msg_desc));
427 }
428
429 static void
430 pvscsi_process_completion_queue(void *opaque)
431 {
432 PVSCSIState *s = opaque;
433 PVSCSIRequest *pvscsi_req;
434 bool has_completed = false;
435
436 while (!QTAILQ_EMPTY(&s->completion_queue)) {
437 pvscsi_req = QTAILQ_FIRST(&s->completion_queue);
438 QTAILQ_REMOVE(&s->completion_queue, pvscsi_req, next);
439 pvscsi_cmp_ring_put(s, &pvscsi_req->cmp);
440 g_free(pvscsi_req);
441 has_completed = true;
442 }
443
444 if (has_completed) {
445 pvscsi_ring_flush_cmp(&s->rings);
446 pvscsi_raise_completion_interrupt(s);
447 }
448 }
449
450 static void
451 pvscsi_reset_adapter(PVSCSIState *s)
452 {
453 s->resetting++;
454 bus_cold_reset(BUS(&s->bus));
455 s->resetting--;
456 pvscsi_process_completion_queue(s);
457 assert(QTAILQ_EMPTY(&s->pending_queue));
458 pvscsi_reset_state(s);
459 }
460
461 static void
462 pvscsi_schedule_completion_processing(PVSCSIState *s)
463 {
464 /* Try putting more complete requests on the ring. */
465 if (!QTAILQ_EMPTY(&s->completion_queue)) {
466 qemu_bh_schedule(s->completion_worker);
467 }
468 }
469
470 static void
471 pvscsi_complete_request(PVSCSIState *s, PVSCSIRequest *r)
472 {
473 assert(!r->completed);
474
475 trace_pvscsi_complete_request(r->cmp.context, r->cmp.dataLen,
476 r->sense_key);
477 if (r->sreq != NULL) {
478 scsi_req_unref(r->sreq);
479 r->sreq = NULL;
480 }
481 r->completed = 1;
482 QTAILQ_REMOVE(&s->pending_queue, r, next);
483 QTAILQ_INSERT_TAIL(&s->completion_queue, r, next);
484 pvscsi_schedule_completion_processing(s);
485 }
486
487 static QEMUSGList *pvscsi_get_sg_list(SCSIRequest *r)
488 {
489 PVSCSIRequest *req = r->hba_private;
490
491 trace_pvscsi_get_sg_list(req->sgl.nsg, req->sgl.size);
492
493 return &req->sgl;
494 }
495
496 static void
497 pvscsi_get_next_sg_elem(PVSCSISGState *sg)
498 {
499 struct PVSCSISGElement elem;
500
501 physical_memory_read(sg->elemAddr, &elem, sizeof(elem));
502 elem.addr = le64_to_cpu(elem.addr);
503 elem.length = le32_to_cpu(elem.length);
504 elem.flags = le32_to_cpu(elem.flags);
505 if ((elem.flags & ~PVSCSI_KNOWN_FLAGS) != 0) {
506 /*
507 * There is PVSCSI_SGE_FLAG_CHAIN_ELEMENT flag described in
508 * header file but its value is unknown. This flag requires
509 * additional processing, so we put warning here to catch it
510 * some day and make proper implementation
511 */
512 trace_pvscsi_get_next_sg_elem(elem.flags);
513 }
514
515 sg->elemAddr += sizeof(elem);
516 sg->dataAddr = elem.addr;
517 sg->resid = elem.length;
518 }
519
520 static void
521 pvscsi_write_sense(PVSCSIRequest *r, uint8_t *sense, int len)
522 {
523 r->cmp.senseLen = MIN(r->req.senseLen, len);
524 r->sense_key = sense[(sense[0] & 2) ? 1 : 2];
525 physical_memory_write(r->req.senseAddr, sense, r->cmp.senseLen);
526 }
527
528 static void
529 pvscsi_command_failed(SCSIRequest *req)
530 {
531 PVSCSIRequest *pvscsi_req = req->hba_private;
532 PVSCSIState *s;
533
534 if (!pvscsi_req) {
535 trace_pvscsi_command_complete_not_found(req->tag);
536 return;
537 }
538 s = pvscsi_req->dev;
539
540 switch (req->host_status) {
541 case SCSI_HOST_NO_LUN:
542 pvscsi_req->cmp.hostStatus = BTSTAT_LUNMISMATCH;
543 break;
544 case SCSI_HOST_BUSY:
545 pvscsi_req->cmp.hostStatus = BTSTAT_ABORTQUEUE;
546 break;
547 case SCSI_HOST_TIME_OUT:
548 case SCSI_HOST_ABORTED:
549 pvscsi_req->cmp.hostStatus = BTSTAT_SENTRST;
550 break;
551 case SCSI_HOST_BAD_RESPONSE:
552 pvscsi_req->cmp.hostStatus = BTSTAT_SELTIMEO;
553 break;
554 case SCSI_HOST_RESET:
555 pvscsi_req->cmp.hostStatus = BTSTAT_BUSRESET;
556 break;
557 default:
558 pvscsi_req->cmp.hostStatus = BTSTAT_HASOFTWARE;
559 break;
560 }
561 pvscsi_req->cmp.scsiStatus = GOOD;
562 qemu_sglist_destroy(&pvscsi_req->sgl);
563 pvscsi_complete_request(s, pvscsi_req);
564 }
565
566 static void
567 pvscsi_command_complete(SCSIRequest *req, size_t resid)
568 {
569 PVSCSIRequest *pvscsi_req = req->hba_private;
570 PVSCSIState *s;
571
572 if (!pvscsi_req) {
573 trace_pvscsi_command_complete_not_found(req->tag);
574 return;
575 }
576 s = pvscsi_req->dev;
577
578 if (resid) {
579 /* Short transfer. */
580 trace_pvscsi_command_complete_data_run();
581 pvscsi_req->cmp.hostStatus = BTSTAT_DATARUN;
582 }
583
584 pvscsi_req->cmp.scsiStatus = req->status;
585 if (pvscsi_req->cmp.scsiStatus == CHECK_CONDITION) {
586 uint8_t sense[SCSI_SENSE_BUF_SIZE];
587 int sense_len =
588 scsi_req_get_sense(pvscsi_req->sreq, sense, sizeof(sense));
589
590 trace_pvscsi_command_complete_sense_len(sense_len);
591 pvscsi_write_sense(pvscsi_req, sense, sense_len);
592 }
593 qemu_sglist_destroy(&pvscsi_req->sgl);
594 pvscsi_complete_request(s, pvscsi_req);
595 }
596
597 static void
598 pvscsi_send_msg(PVSCSIState *s, SCSIDevice *dev, uint32_t msg_type)
599 {
600 if (s->msg_ring_info_valid && pvscsi_ring_msg_has_room(&s->rings)) {
601 PVSCSIMsgDescDevStatusChanged msg = {0};
602
603 msg.type = msg_type;
604 msg.bus = dev->channel;
605 msg.target = dev->id;
606 msg.lun[1] = dev->lun;
607
608 pvscsi_msg_ring_put(s, (PVSCSIRingMsgDesc *)&msg);
609 pvscsi_ring_flush_msg(&s->rings);
610 pvscsi_raise_message_interrupt(s);
611 }
612 }
613
614 static void
615 pvscsi_hotplug(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp)
616 {
617 PVSCSIState *s = PVSCSI(hotplug_dev);
618
619 pvscsi_send_msg(s, SCSI_DEVICE(dev), PVSCSI_MSG_DEV_ADDED);
620 }
621
622 static void
623 pvscsi_hot_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp)
624 {
625 PVSCSIState *s = PVSCSI(hotplug_dev);
626
627 pvscsi_send_msg(s, SCSI_DEVICE(dev), PVSCSI_MSG_DEV_REMOVED);
628 qdev_simple_device_unplug_cb(hotplug_dev, dev, errp);
629 }
630
631 static void
632 pvscsi_request_cancelled(SCSIRequest *req)
633 {
634 PVSCSIRequest *pvscsi_req = req->hba_private;
635 PVSCSIState *s = pvscsi_req->dev;
636
637 if (pvscsi_req->completed) {
638 return;
639 }
640
641 if (pvscsi_req->dev->resetting) {
642 pvscsi_req->cmp.hostStatus = BTSTAT_BUSRESET;
643 } else {
644 pvscsi_req->cmp.hostStatus = BTSTAT_ABORTQUEUE;
645 }
646
647 pvscsi_complete_request(s, pvscsi_req);
648 }
649
650 static SCSIDevice*
651 pvscsi_device_find(PVSCSIState *s, int channel, int target,
652 uint8_t *requested_lun, uint8_t *target_lun)
653 {
654 if (requested_lun[0] || requested_lun[2] || requested_lun[3] ||
655 requested_lun[4] || requested_lun[5] || requested_lun[6] ||
656 requested_lun[7] || (target > PVSCSI_MAX_DEVS)) {
657 return NULL;
658 } else {
659 *target_lun = requested_lun[1];
660 return scsi_device_find(&s->bus, channel, target, *target_lun);
661 }
662 }
663
664 static PVSCSIRequest *
665 pvscsi_queue_pending_descriptor(PVSCSIState *s, SCSIDevice **d,
666 struct PVSCSIRingReqDesc *descr)
667 {
668 PVSCSIRequest *pvscsi_req;
669 uint8_t lun;
670
671 pvscsi_req = g_malloc0(sizeof(*pvscsi_req));
672 pvscsi_req->dev = s;
673 pvscsi_req->req = *descr;
674 pvscsi_req->cmp.context = pvscsi_req->req.context;
675 QTAILQ_INSERT_TAIL(&s->pending_queue, pvscsi_req, next);
676
677 *d = pvscsi_device_find(s, descr->bus, descr->target, descr->lun, &lun);
678 if (*d) {
679 pvscsi_req->lun = lun;
680 }
681
682 return pvscsi_req;
683 }
684
685 static void
686 pvscsi_convert_sglist(PVSCSIRequest *r)
687 {
688 uint32_t chunk_size, elmcnt = 0;
689 uint64_t data_length = r->req.dataLen;
690 PVSCSISGState sg = r->sg;
691 while (data_length && elmcnt < PVSCSI_MAX_SG_ELEM) {
692 while (!sg.resid && elmcnt++ < PVSCSI_MAX_SG_ELEM) {
693 pvscsi_get_next_sg_elem(&sg);
694 trace_pvscsi_convert_sglist(r->req.context, r->sg.dataAddr,
695 r->sg.resid);
696 }
697 chunk_size = MIN(data_length, sg.resid);
698 if (chunk_size) {
699 qemu_sglist_add(&r->sgl, sg.dataAddr, chunk_size);
700 }
701
702 sg.dataAddr += chunk_size;
703 data_length -= chunk_size;
704 sg.resid -= chunk_size;
705 }
706 }
707
708 static void
709 pvscsi_build_sglist(PVSCSIState *s, PVSCSIRequest *r)
710 {
711 PCIDevice *d = PCI_DEVICE(s);
712
713 pci_dma_sglist_init(&r->sgl, d, 1);
714 if (r->req.flags & PVSCSI_FLAG_CMD_WITH_SG_LIST) {
715 pvscsi_convert_sglist(r);
716 } else {
717 qemu_sglist_add(&r->sgl, r->req.dataAddr, r->req.dataLen);
718 }
719 }
720
721 static void
722 pvscsi_process_request_descriptor(PVSCSIState *s,
723 struct PVSCSIRingReqDesc *descr)
724 {
725 SCSIDevice *d;
726 PVSCSIRequest *r = pvscsi_queue_pending_descriptor(s, &d, descr);
727 int64_t n;
728
729 trace_pvscsi_process_req_descr(descr->cdb[0], descr->context);
730
731 if (!d) {
732 r->cmp.hostStatus = BTSTAT_SELTIMEO;
733 trace_pvscsi_process_req_descr_unknown_device();
734 pvscsi_complete_request(s, r);
735 return;
736 }
737
738 if (descr->flags & PVSCSI_FLAG_CMD_WITH_SG_LIST) {
739 r->sg.elemAddr = descr->dataAddr;
740 }
741
742 r->sreq = scsi_req_new(d, descr->context, r->lun, descr->cdb, descr->cdbLen, r);
743 if (r->sreq->cmd.mode == SCSI_XFER_FROM_DEV &&
744 (descr->flags & PVSCSI_FLAG_CMD_DIR_TODEVICE)) {
745 r->cmp.hostStatus = BTSTAT_BADMSG;
746 trace_pvscsi_process_req_descr_invalid_dir();
747 scsi_req_cancel(r->sreq);
748 return;
749 }
750 if (r->sreq->cmd.mode == SCSI_XFER_TO_DEV &&
751 (descr->flags & PVSCSI_FLAG_CMD_DIR_TOHOST)) {
752 r->cmp.hostStatus = BTSTAT_BADMSG;
753 trace_pvscsi_process_req_descr_invalid_dir();
754 scsi_req_cancel(r->sreq);
755 return;
756 }
757
758 pvscsi_build_sglist(s, r);
759 n = scsi_req_enqueue(r->sreq);
760
761 if (n) {
762 scsi_req_continue(r->sreq);
763 }
764 }
765
766 static void
767 pvscsi_process_io(PVSCSIState *s)
768 {
769 PVSCSIRingReqDesc descr;
770 hwaddr next_descr_pa;
771
772 if (!s->rings_info_valid) {
773 return;
774 }
775
776 while ((next_descr_pa = pvscsi_ring_pop_req_descr(&s->rings)) != 0) {
777
778 /* Only read after production index verification */
779 smp_rmb();
780
781 trace_pvscsi_process_io(next_descr_pa);
782 physical_memory_read(next_descr_pa, &descr, sizeof(descr));
783 descr.context = le64_to_cpu(descr.context);
784 descr.dataAddr = le64_to_cpu(descr.dataAddr);
785 descr.dataLen = le64_to_cpu(descr.dataLen);
786 descr.senseAddr = le64_to_cpu(descr.senseAddr);
787 descr.senseLen = le32_to_cpu(descr.senseLen);
788 descr.flags = le32_to_cpu(descr.flags);
789 pvscsi_process_request_descriptor(s, &descr);
790 }
791
792 pvscsi_ring_flush_req(&s->rings);
793 }
794
795 static void
796 pvscsi_dbg_dump_tx_rings_config(PVSCSICmdDescSetupRings *rc)
797 {
798 int i;
799 trace_pvscsi_tx_rings_ppn("Rings State", rc->ringsStatePPN);
800
801 trace_pvscsi_tx_rings_num_pages("Request Ring", rc->reqRingNumPages);
802 for (i = 0; i < rc->reqRingNumPages; i++) {
803 trace_pvscsi_tx_rings_ppn("Request Ring", rc->reqRingPPNs[i]);
804 }
805
806 trace_pvscsi_tx_rings_num_pages("Confirm Ring", rc->cmpRingNumPages);
807 for (i = 0; i < rc->cmpRingNumPages; i++) {
808 trace_pvscsi_tx_rings_ppn("Confirm Ring", rc->cmpRingPPNs[i]);
809 }
810 }
811
812 static uint64_t
813 pvscsi_on_cmd_config(PVSCSIState *s)
814 {
815 trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_CONFIG");
816 return PVSCSI_COMMAND_PROCESSING_FAILED;
817 }
818
819 static uint64_t
820 pvscsi_on_cmd_unplug(PVSCSIState *s)
821 {
822 trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_DEVICE_UNPLUG");
823 return PVSCSI_COMMAND_PROCESSING_FAILED;
824 }
825
826 static uint64_t
827 pvscsi_on_issue_scsi(PVSCSIState *s)
828 {
829 trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_ISSUE_SCSI");
830 return PVSCSI_COMMAND_PROCESSING_FAILED;
831 }
832
833 static uint64_t
834 pvscsi_on_cmd_setup_rings(PVSCSIState *s)
835 {
836 PVSCSICmdDescSetupRings *rc =
837 (PVSCSICmdDescSetupRings *) s->curr_cmd_data;
838 PVSCSICmdDescSetupRings translated;
839 int i;
840
841 translated.reqRingNumPages = le32_to_cpu(rc->reqRingNumPages);
842 translated.cmpRingNumPages = le32_to_cpu(rc->cmpRingNumPages);
843 translated.ringsStatePPN = le64_to_cpu(rc->ringsStatePPN);
844 for (i = 0; i < PVSCSI_SETUP_RINGS_MAX_NUM_PAGES; i++) {
845 translated.reqRingPPNs[i] = le64_to_cpu(rc->reqRingPPNs[i]);
846 translated.cmpRingPPNs[i] = le64_to_cpu(rc->cmpRingPPNs[i]);
847 }
848 rc = &translated;
849
850 trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_SETUP_RINGS");
851
852 if (!rc->reqRingNumPages
853 || rc->reqRingNumPages > PVSCSI_SETUP_RINGS_MAX_NUM_PAGES
854 || !rc->cmpRingNumPages
855 || rc->cmpRingNumPages > PVSCSI_SETUP_RINGS_MAX_NUM_PAGES) {
856 return PVSCSI_COMMAND_PROCESSING_FAILED;
857 }
858
859 pvscsi_dbg_dump_tx_rings_config(rc);
860 pvscsi_ring_init_data(&s->rings, rc);
861
862 s->rings_info_valid = TRUE;
863 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
864 }
865
866 static uint64_t
867 pvscsi_on_cmd_abort(PVSCSIState *s)
868 {
869 PVSCSICmdDescAbortCmd *cmd = (PVSCSICmdDescAbortCmd *) s->curr_cmd_data;
870 PVSCSIRequest *r, *next;
871
872 PVSCSICmdDescAbortCmd translated = *cmd;
873 translated.context = le32_to_cpu(cmd->context);
874 translated.target = le32_to_cpu(cmd->target);
875 cmd = &translated;
876
877 trace_pvscsi_on_cmd_abort(cmd->context, cmd->target);
878
879 QTAILQ_FOREACH_SAFE(r, &s->pending_queue, next, next) {
880 if (r->req.context == cmd->context) {
881 break;
882 }
883 }
884 if (r) {
885 assert(!r->completed);
886 r->cmp.hostStatus = BTSTAT_ABORTQUEUE;
887 scsi_req_cancel(r->sreq);
888 }
889
890 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
891 }
892
893 static uint64_t
894 pvscsi_on_cmd_unknown(PVSCSIState *s)
895 {
896 trace_pvscsi_on_cmd_unknown_data(s->curr_cmd_data[0]);
897 return PVSCSI_COMMAND_PROCESSING_FAILED;
898 }
899
900 static uint64_t
901 pvscsi_on_cmd_reset_device(PVSCSIState *s)
902 {
903 uint8_t target_lun = 0;
904 struct PVSCSICmdDescResetDevice *cmd =
905 (struct PVSCSICmdDescResetDevice *) s->curr_cmd_data;
906 SCSIDevice *sdev;
907
908 PVSCSICmdDescResetDevice translated = *cmd;
909 translated.target = le32_to_cpu(cmd->target);
910 cmd = &translated;
911
912 sdev = pvscsi_device_find(s, 0, cmd->target, cmd->lun, &target_lun);
913
914 trace_pvscsi_on_cmd_reset_dev(cmd->target, (int) target_lun, sdev);
915
916 if (sdev != NULL) {
917 s->resetting++;
918 device_cold_reset(&sdev->qdev);
919 s->resetting--;
920 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
921 }
922
923 return PVSCSI_COMMAND_PROCESSING_FAILED;
924 }
925
926 static uint64_t
927 pvscsi_on_cmd_reset_bus(PVSCSIState *s)
928 {
929 trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_RESET_BUS");
930
931 s->resetting++;
932 bus_cold_reset(BUS(&s->bus));
933 s->resetting--;
934 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
935 }
936
937 static uint64_t
938 pvscsi_on_cmd_setup_msg_ring(PVSCSIState *s)
939 {
940 PVSCSICmdDescSetupMsgRing *rc =
941 (PVSCSICmdDescSetupMsgRing *) s->curr_cmd_data;
942 PVSCSICmdDescSetupMsgRing translated = *rc;
943 int i;
944
945 translated.numPages = le32_to_cpu(rc->numPages);
946 for (i = 0; i < PVSCSI_SETUP_MSG_RING_MAX_NUM_PAGES; i++) {
947 translated.ringPPNs[i] = le64_to_cpu(rc->ringPPNs[i]);
948 }
949 rc = &translated;
950
951 trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_SETUP_MSG_RING");
952
953 if (!s->use_msg) {
954 return PVSCSI_COMMAND_PROCESSING_FAILED;
955 }
956
957 if (s->rings_info_valid) {
958 if (pvscsi_ring_init_msg(&s->rings, rc) < 0) {
959 return PVSCSI_COMMAND_PROCESSING_FAILED;
960 }
961 s->msg_ring_info_valid = TRUE;
962 }
963 return sizeof(PVSCSICmdDescSetupMsgRing) / sizeof(uint32_t);
964 }
965
966 static uint64_t
967 pvscsi_on_cmd_adapter_reset(PVSCSIState *s)
968 {
969 trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_ADAPTER_RESET");
970
971 pvscsi_reset_adapter(s);
972 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
973 }
974
975 static const struct {
976 int data_size;
977 uint64_t (*handler_fn)(PVSCSIState *s);
978 } pvscsi_commands[] = {
979 [PVSCSI_CMD_FIRST] = {
980 .data_size = 0,
981 .handler_fn = pvscsi_on_cmd_unknown,
982 },
983
984 /* Not implemented, data size defined based on what arrives on windows */
985 [PVSCSI_CMD_CONFIG] = {
986 .data_size = 6 * sizeof(uint32_t),
987 .handler_fn = pvscsi_on_cmd_config,
988 },
989
990 /* Command not implemented, data size is unknown */
991 [PVSCSI_CMD_ISSUE_SCSI] = {
992 .data_size = 0,
993 .handler_fn = pvscsi_on_issue_scsi,
994 },
995
996 /* Command not implemented, data size is unknown */
997 [PVSCSI_CMD_DEVICE_UNPLUG] = {
998 .data_size = 0,
999 .handler_fn = pvscsi_on_cmd_unplug,
1000 },
1001
1002 [PVSCSI_CMD_SETUP_RINGS] = {
1003 .data_size = sizeof(PVSCSICmdDescSetupRings),
1004 .handler_fn = pvscsi_on_cmd_setup_rings,
1005 },
1006
1007 [PVSCSI_CMD_RESET_DEVICE] = {
1008 .data_size = sizeof(struct PVSCSICmdDescResetDevice),
1009 .handler_fn = pvscsi_on_cmd_reset_device,
1010 },
1011
1012 [PVSCSI_CMD_RESET_BUS] = {
1013 .data_size = 0,
1014 .handler_fn = pvscsi_on_cmd_reset_bus,
1015 },
1016
1017 [PVSCSI_CMD_SETUP_MSG_RING] = {
1018 .data_size = sizeof(PVSCSICmdDescSetupMsgRing),
1019 .handler_fn = pvscsi_on_cmd_setup_msg_ring,
1020 },
1021
1022 [PVSCSI_CMD_ADAPTER_RESET] = {
1023 .data_size = 0,
1024 .handler_fn = pvscsi_on_cmd_adapter_reset,
1025 },
1026
1027 [PVSCSI_CMD_ABORT_CMD] = {
1028 .data_size = sizeof(struct PVSCSICmdDescAbortCmd),
1029 .handler_fn = pvscsi_on_cmd_abort,
1030 },
1031 };
1032
1033 static void
1034 pvscsi_do_command_processing(PVSCSIState *s)
1035 {
1036 size_t bytes_arrived = s->curr_cmd_data_cntr * sizeof(uint32_t);
1037
1038 assert(s->curr_cmd < PVSCSI_CMD_LAST);
1039 if (bytes_arrived >= pvscsi_commands[s->curr_cmd].data_size) {
1040 s->reg_command_status = pvscsi_commands[s->curr_cmd].handler_fn(s);
1041 s->curr_cmd = PVSCSI_CMD_FIRST;
1042 s->curr_cmd_data_cntr = 0;
1043 }
1044 }
1045
1046 static void
1047 pvscsi_on_command_data(PVSCSIState *s, uint32_t value)
1048 {
1049 size_t bytes_arrived = s->curr_cmd_data_cntr * sizeof(uint32_t);
1050
1051 assert(bytes_arrived < sizeof(s->curr_cmd_data));
1052 s->curr_cmd_data[s->curr_cmd_data_cntr++] = cpu_to_le32(value);
1053
1054 pvscsi_do_command_processing(s);
1055 }
1056
1057 static void
1058 pvscsi_on_command(PVSCSIState *s, uint64_t cmd_id)
1059 {
1060 if ((cmd_id > PVSCSI_CMD_FIRST) && (cmd_id < PVSCSI_CMD_LAST)) {
1061 s->curr_cmd = cmd_id;
1062 } else {
1063 s->curr_cmd = PVSCSI_CMD_FIRST;
1064 trace_pvscsi_on_cmd_unknown(cmd_id);
1065 }
1066
1067 s->curr_cmd_data_cntr = 0;
1068 s->reg_command_status = PVSCSI_COMMAND_NOT_ENOUGH_DATA;
1069
1070 pvscsi_do_command_processing(s);
1071 }
1072
1073 static void
1074 pvscsi_io_write(void *opaque, hwaddr addr,
1075 uint64_t val, unsigned size)
1076 {
1077 PVSCSIState *s = opaque;
1078
1079 switch (addr) {
1080 case PVSCSI_REG_OFFSET_COMMAND:
1081 pvscsi_on_command(s, val);
1082 break;
1083
1084 case PVSCSI_REG_OFFSET_COMMAND_DATA:
1085 pvscsi_on_command_data(s, (uint32_t) val);
1086 break;
1087
1088 case PVSCSI_REG_OFFSET_INTR_STATUS:
1089 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_INTR_STATUS", val);
1090 s->reg_interrupt_status &= ~val;
1091 pvscsi_update_irq_status(s);
1092 pvscsi_schedule_completion_processing(s);
1093 break;
1094
1095 case PVSCSI_REG_OFFSET_INTR_MASK:
1096 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_INTR_MASK", val);
1097 s->reg_interrupt_enabled = val;
1098 pvscsi_update_irq_status(s);
1099 break;
1100
1101 case PVSCSI_REG_OFFSET_KICK_NON_RW_IO:
1102 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_KICK_NON_RW_IO", val);
1103 pvscsi_process_io(s);
1104 break;
1105
1106 case PVSCSI_REG_OFFSET_KICK_RW_IO:
1107 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_KICK_RW_IO", val);
1108 pvscsi_process_io(s);
1109 break;
1110
1111 case PVSCSI_REG_OFFSET_DEBUG:
1112 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_DEBUG", val);
1113 break;
1114
1115 default:
1116 trace_pvscsi_io_write_unknown(addr, size, val);
1117 break;
1118 }
1119
1120 }
1121
1122 static uint64_t
1123 pvscsi_io_read(void *opaque, hwaddr addr, unsigned size)
1124 {
1125 PVSCSIState *s = opaque;
1126
1127 switch (addr) {
1128 case PVSCSI_REG_OFFSET_INTR_STATUS:
1129 trace_pvscsi_io_read("PVSCSI_REG_OFFSET_INTR_STATUS",
1130 s->reg_interrupt_status);
1131 return s->reg_interrupt_status;
1132
1133 case PVSCSI_REG_OFFSET_INTR_MASK:
1134 trace_pvscsi_io_read("PVSCSI_REG_OFFSET_INTR_MASK",
1135 s->reg_interrupt_status);
1136 return s->reg_interrupt_enabled;
1137
1138 case PVSCSI_REG_OFFSET_COMMAND_STATUS:
1139 trace_pvscsi_io_read("PVSCSI_REG_OFFSET_COMMAND_STATUS",
1140 s->reg_interrupt_status);
1141 return s->reg_command_status;
1142
1143 default:
1144 trace_pvscsi_io_read_unknown(addr, size);
1145 return 0;
1146 }
1147 }
1148
1149
1150 static void
1151 pvscsi_init_msi(PVSCSIState *s)
1152 {
1153 int res;
1154 PCIDevice *d = PCI_DEVICE(s);
1155
1156 res = msi_init(d, PVSCSI_MSI_OFFSET, PVSCSI_MSIX_NUM_VECTORS,
1157 PVSCSI_USE_64BIT, PVSCSI_PER_VECTOR_MASK, NULL);
1158 if (res < 0) {
1159 trace_pvscsi_init_msi_fail(res);
1160 s->msi_used = false;
1161 } else {
1162 s->msi_used = true;
1163 }
1164 }
1165
1166 static void
1167 pvscsi_cleanup_msi(PVSCSIState *s)
1168 {
1169 PCIDevice *d = PCI_DEVICE(s);
1170
1171 msi_uninit(d);
1172 }
1173
1174 static const MemoryRegionOps pvscsi_ops = {
1175 .read = pvscsi_io_read,
1176 .write = pvscsi_io_write,
1177 .endianness = DEVICE_LITTLE_ENDIAN,
1178 .impl = {
1179 .min_access_size = 4,
1180 .max_access_size = 4,
1181 },
1182 };
1183
1184 static const struct SCSIBusInfo pvscsi_scsi_info = {
1185 .tcq = true,
1186 .max_target = PVSCSI_MAX_DEVS,
1187 .max_channel = 0,
1188 .max_lun = 0,
1189
1190 .get_sg_list = pvscsi_get_sg_list,
1191 .complete = pvscsi_command_complete,
1192 .cancel = pvscsi_request_cancelled,
1193 .fail = pvscsi_command_failed,
1194 };
1195
1196 static void
1197 pvscsi_realizefn(PCIDevice *pci_dev, Error **errp)
1198 {
1199 PVSCSIState *s = PVSCSI(pci_dev);
1200
1201 trace_pvscsi_state("init");
1202
1203 /* PCI subsystem ID, subsystem vendor ID, revision */
1204 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
1205 PCI_VENDOR_ID_VMWARE);
1206 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
1207 PCI_DEVICE_ID_VMWARE_PVSCSI);
1208 pci_config_set_revision(pci_dev->config, 0x2);
1209
1210 /* PCI latency timer = 255 */
1211 pci_dev->config[PCI_LATENCY_TIMER] = 0xff;
1212
1213 /* Interrupt pin A */
1214 pci_config_set_interrupt_pin(pci_dev->config, 1);
1215
1216 memory_region_init_io(&s->io_space, OBJECT(s), &pvscsi_ops, s,
1217 "pvscsi-io", PVSCSI_MEM_SPACE_SIZE);
1218 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->io_space);
1219
1220 pvscsi_init_msi(s);
1221
1222 if (pci_is_express(pci_dev) && pci_bus_is_express(pci_get_bus(pci_dev))) {
1223 pcie_endpoint_cap_init(pci_dev, PVSCSI_EXP_EP_OFFSET);
1224 }
1225
1226 s->completion_worker = qemu_bh_new_guarded(pvscsi_process_completion_queue, s,
1227 &DEVICE(pci_dev)->mem_reentrancy_guard);
1228
1229 scsi_bus_init(&s->bus, sizeof(s->bus), DEVICE(pci_dev), &pvscsi_scsi_info);
1230 /* override default SCSI bus hotplug-handler, with pvscsi's one */
1231 qbus_set_hotplug_handler(BUS(&s->bus), OBJECT(s));
1232 pvscsi_reset_state(s);
1233 }
1234
1235 static void
1236 pvscsi_uninit(PCIDevice *pci_dev)
1237 {
1238 PVSCSIState *s = PVSCSI(pci_dev);
1239
1240 trace_pvscsi_state("uninit");
1241 qemu_bh_delete(s->completion_worker);
1242
1243 pvscsi_cleanup_msi(s);
1244 }
1245
1246 static void
1247 pvscsi_reset(DeviceState *dev)
1248 {
1249 PCIDevice *d = PCI_DEVICE(dev);
1250 PVSCSIState *s = PVSCSI(d);
1251
1252 trace_pvscsi_state("reset");
1253 pvscsi_reset_adapter(s);
1254 }
1255
1256 static int
1257 pvscsi_pre_save(void *opaque)
1258 {
1259 PVSCSIState *s = (PVSCSIState *) opaque;
1260
1261 trace_pvscsi_state("presave");
1262
1263 assert(QTAILQ_EMPTY(&s->pending_queue));
1264 assert(QTAILQ_EMPTY(&s->completion_queue));
1265
1266 return 0;
1267 }
1268
1269 static int
1270 pvscsi_post_load(void *opaque, int version_id)
1271 {
1272 trace_pvscsi_state("postload");
1273 return 0;
1274 }
1275
1276 static const VMStateDescription vmstate_pvscsi_pcie_device = {
1277 .name = "pvscsi/pcie",
1278 .fields = (const VMStateField[]) {
1279 VMSTATE_PCI_DEVICE(parent_obj, PVSCSIState),
1280 VMSTATE_END_OF_LIST()
1281 }
1282 };
1283
1284 static const VMStateDescription vmstate_pvscsi = {
1285 .name = "pvscsi",
1286 .version_id = 0,
1287 .minimum_version_id = 0,
1288 .pre_save = pvscsi_pre_save,
1289 .post_load = pvscsi_post_load,
1290 .fields = (const VMStateField[]) {
1291 VMSTATE_UINT8(msi_used, PVSCSIState),
1292 VMSTATE_UINT32(resetting, PVSCSIState),
1293 VMSTATE_UINT64(reg_interrupt_status, PVSCSIState),
1294 VMSTATE_UINT64(reg_interrupt_enabled, PVSCSIState),
1295 VMSTATE_UINT64(reg_command_status, PVSCSIState),
1296 VMSTATE_UINT64(curr_cmd, PVSCSIState),
1297 VMSTATE_UINT32(curr_cmd_data_cntr, PVSCSIState),
1298 VMSTATE_UINT32_ARRAY(curr_cmd_data, PVSCSIState,
1299 ARRAY_SIZE(((PVSCSIState *)NULL)->curr_cmd_data)),
1300 VMSTATE_UINT8(rings_info_valid, PVSCSIState),
1301 VMSTATE_UINT8(msg_ring_info_valid, PVSCSIState),
1302 VMSTATE_UINT8(use_msg, PVSCSIState),
1303
1304 VMSTATE_UINT64(rings.rs_pa, PVSCSIState),
1305 VMSTATE_UINT32(rings.txr_len_mask, PVSCSIState),
1306 VMSTATE_UINT32(rings.rxr_len_mask, PVSCSIState),
1307 VMSTATE_UINT64_ARRAY(rings.req_ring_pages_pa, PVSCSIState,
1308 PVSCSI_SETUP_RINGS_MAX_NUM_PAGES),
1309 VMSTATE_UINT64_ARRAY(rings.cmp_ring_pages_pa, PVSCSIState,
1310 PVSCSI_SETUP_RINGS_MAX_NUM_PAGES),
1311 VMSTATE_UINT64(rings.consumed_ptr, PVSCSIState),
1312 VMSTATE_UINT64(rings.filled_cmp_ptr, PVSCSIState),
1313
1314 VMSTATE_END_OF_LIST()
1315 },
1316 .subsections = (const VMStateDescription * const []) {
1317 &vmstate_pvscsi_pcie_device,
1318 NULL
1319 }
1320 };
1321
1322 static const Property pvscsi_properties[] = {
1323 DEFINE_PROP_UINT8("use_msg", PVSCSIState, use_msg, 1),
1324 };
1325
1326 static void pvscsi_instance_init(Object *obj)
1327 {
1328 PCI_DEVICE(obj)->cap_present |= QEMU_PCI_CAP_EXPRESS;
1329 }
1330
1331 static void pvscsi_class_init(ObjectClass *klass, const void *data)
1332 {
1333 DeviceClass *dc = DEVICE_CLASS(klass);
1334 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1335 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
1336
1337 k->realize = pvscsi_realizefn;
1338 k->exit = pvscsi_uninit;
1339 k->vendor_id = PCI_VENDOR_ID_VMWARE;
1340 k->device_id = PCI_DEVICE_ID_VMWARE_PVSCSI;
1341 k->class_id = PCI_CLASS_STORAGE_SCSI;
1342 k->subsystem_id = 0x1000;
1343 device_class_set_legacy_reset(dc, pvscsi_reset);
1344 dc->vmsd = &vmstate_pvscsi;
1345 device_class_set_props(dc, pvscsi_properties);
1346 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
1347 hc->unplug = pvscsi_hot_unplug;
1348 hc->plug = pvscsi_hotplug;
1349 }
1350
1351 static const TypeInfo pvscsi_info = {
1352 .name = TYPE_PVSCSI,
1353 .parent = TYPE_PCI_DEVICE,
1354 .class_size = sizeof(PVSCSIClass),
1355 .instance_size = sizeof(PVSCSIState),
1356 .class_init = pvscsi_class_init,
1357 .instance_init = pvscsi_instance_init,
1358 .interfaces = (const InterfaceInfo[]) {
1359 { TYPE_HOTPLUG_HANDLER },
1360 { INTERFACE_PCIE_DEVICE },
1361 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
1362 { }
1363 }
1364 };
1365
1366 static void
1367 pvscsi_register_types(void)
1368 {
1369 type_register_static(&pvscsi_info);
1370 }
1371
1372 type_init(pvscsi_register_types);