| 1 | /* |
| 2 | * Axiado SD Host Controller with embedded PHY |
| 3 | * |
| 4 | * Author: Kuan-Jui Chiu <kchiu@axiado.com> |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 7 | */ |
| 8 | |
| 9 | #include "qemu/osdep.h" |
| 10 | #include "hw/sd/axiado_sdhci.h" |
| 11 | #include "sdhci-internal.h" |
| 12 | #include "qapi/error.h" |
| 13 | #include "hw/core/qdev-properties.h" |
| 14 | #include "qemu/log.h" |
| 15 | |
| 16 | #define EMMC_PHY_ID 0x00 |
| 17 | #define EMMC_PHY_STATUS 0x50 |
| 18 | |
| 19 | #define DLL_RDY (1u << 0) |
| 20 | #define CAL_DONE (1u << 6) |
| 21 | |
| 22 | static uint64_t emmc_phy_read(void *opaque, hwaddr offset, unsigned size) |
| 23 | { |
| 24 | uint32_t val = 0x00; |
| 25 | |
| 26 | switch (offset) { |
| 27 | case EMMC_PHY_ID: |
| 28 | val = 0x3dff6870; |
| 29 | break; |
| 30 | case EMMC_PHY_STATUS: |
| 31 | val = DLL_RDY | CAL_DONE; |
| 32 | break; |
| 33 | default: |
| 34 | qemu_log_mask(LOG_UNIMP, |
| 35 | "Register 0x%" HWADDR_PRIx " not implemented\n", offset); |
| 36 | break; |
| 37 | } |
| 38 | |
| 39 | return val; |
| 40 | } |
| 41 | |
| 42 | static void emmc_phy_write(void *opaque, hwaddr offset, uint64_t value, |
| 43 | unsigned size) |
| 44 | { |
| 45 | qemu_log_mask(LOG_UNIMP, |
| 46 | "Register 0x%" HWADDR_PRIx " not implemented\n", offset); |
| 47 | } |
| 48 | |
| 49 | static const MemoryRegionOps emmc_phy_ops = { |
| 50 | .read = emmc_phy_read, |
| 51 | .write = emmc_phy_write, |
| 52 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 53 | .impl = { |
| 54 | .min_access_size = 4, |
| 55 | .max_access_size = 4, |
| 56 | }, |
| 57 | .valid = { |
| 58 | .min_access_size = 4, |
| 59 | .max_access_size = 4, |
| 60 | } |
| 61 | }; |
| 62 | |
| 63 | static void axiado_sdhci_realize(DeviceState *dev, Error **errp) |
| 64 | { |
| 65 | AxiadoSDHCIState *s = AXIADO_SDHCI(dev); |
| 66 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
| 67 | SysBusDevice *sdhci_sbd; |
| 68 | |
| 69 | qdev_prop_set_uint64(DEVICE(&s->sdhci), "capareg", 0x216737eed0b0); |
| 70 | qdev_prop_set_uint64(DEVICE(&s->sdhci), "sd-spec-version", 3); |
| 71 | |
| 72 | sdhci_sbd = SYS_BUS_DEVICE(&s->sdhci); |
| 73 | if (!sysbus_realize(sdhci_sbd, errp)) { |
| 74 | return; |
| 75 | } |
| 76 | |
| 77 | sysbus_init_mmio(sbd, sysbus_mmio_get_region(sdhci_sbd, 0)); |
| 78 | |
| 79 | /* Propagate IRQ from SDHCI and SD bus */ |
| 80 | sysbus_pass_irq(sbd, sdhci_sbd); |
| 81 | s->sd_bus = qdev_get_child_bus(DEVICE(sdhci_sbd), "sd-bus"); |
| 82 | |
| 83 | /* Initialize eMMC PHY MMIO */ |
| 84 | memory_region_init_io(&s->emmc_phy, OBJECT(s), &emmc_phy_ops, s, |
| 85 | "axiado.emmc-phy", 0x1000); |
| 86 | |
| 87 | sysbus_init_mmio(sbd, &s->emmc_phy); |
| 88 | } |
| 89 | |
| 90 | static void axiado_sdhci_instance_init(Object *obj) |
| 91 | { |
| 92 | AxiadoSDHCIState *s = AXIADO_SDHCI(obj); |
| 93 | |
| 94 | object_initialize_child(OBJECT(s), "sdhci", &s->sdhci, |
| 95 | TYPE_SYSBUS_SDHCI); |
| 96 | } |
| 97 | |
| 98 | static void axiado_sdhci_class_init(ObjectClass *klass, const void *data) |
| 99 | { |
| 100 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 101 | |
| 102 | dc->realize = axiado_sdhci_realize; |
| 103 | dc->desc = "Axiado SD Host Controller with eMMC PHY"; |
| 104 | } |
| 105 | |
| 106 | static const TypeInfo axiado_sdhci_info = { |
| 107 | .name = TYPE_AXIADO_SDHCI, |
| 108 | .parent = TYPE_SYS_BUS_DEVICE, |
| 109 | .instance_size = sizeof(AxiadoSDHCIState), |
| 110 | .instance_init = axiado_sdhci_instance_init, |
| 111 | .class_init = axiado_sdhci_class_init, |
| 112 | }; |
| 113 | |
| 114 | static void axiado_sdhci_register_types(void) |
| 115 | { |
| 116 | type_register_static(&axiado_sdhci_info); |
| 117 | } |
| 118 | |
| 119 | type_init(axiado_sdhci_register_types); |