| 1 | /* |
| 2 | * OMAP on-chip MMC/SD host emulation. |
| 3 | * |
| 4 | * Datasheet: TI Multimedia Card (MMC/SD/SDIO) Interface (SPRU765A) |
| 5 | * |
| 6 | * Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 or |
| 11 | * (at your option) version 3 of the License. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License along |
| 19 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
| 20 | */ |
| 21 | |
| 22 | #include "qemu/osdep.h" |
| 23 | #include "qemu/log.h" |
| 24 | #include "qapi/error.h" |
| 25 | #include "hw/core/irq.h" |
| 26 | #include "hw/core/sysbus.h" |
| 27 | #include "hw/arm/omap.h" |
| 28 | #include "hw/sd/sd.h" |
| 29 | |
| 30 | typedef struct OMAPMMCState { |
| 31 | SysBusDevice parent_obj; |
| 32 | |
| 33 | SDBus sdbus; |
| 34 | |
| 35 | qemu_irq irq; |
| 36 | qemu_irq dma_tx_gpio; |
| 37 | qemu_irq dma_rx_gpio; |
| 38 | MemoryRegion iomem; |
| 39 | omap_clk clk; |
| 40 | uint16_t last_cmd; |
| 41 | uint16_t sdio; |
| 42 | uint16_t rsp[8]; |
| 43 | uint32_t arg; |
| 44 | int lines; |
| 45 | int dw; |
| 46 | int mode; |
| 47 | int enable; |
| 48 | int be; |
| 49 | int rev; |
| 50 | uint16_t status; |
| 51 | uint16_t mask; |
| 52 | uint8_t cto; |
| 53 | uint16_t dto; |
| 54 | int clkdiv; |
| 55 | uint16_t fifo[32]; |
| 56 | int fifo_start; |
| 57 | int fifo_len; |
| 58 | uint16_t blen; |
| 59 | uint16_t blen_counter; |
| 60 | uint16_t nblk; |
| 61 | uint16_t nblk_counter; |
| 62 | int tx_dma; |
| 63 | int rx_dma; |
| 64 | int af_level; |
| 65 | int ae_level; |
| 66 | |
| 67 | int ddir; |
| 68 | int transfer; |
| 69 | |
| 70 | int cdet_wakeup; |
| 71 | int cdet_enable; |
| 72 | qemu_irq cdet; |
| 73 | } OMAPMMCState; |
| 74 | |
| 75 | static void omap_mmc_interrupts_update(OMAPMMCState *s) |
| 76 | { |
| 77 | qemu_set_irq(s->irq, !!(s->status & s->mask)); |
| 78 | } |
| 79 | |
| 80 | static void omap_mmc_fifolevel_update(OMAPMMCState *host) |
| 81 | { |
| 82 | if (!host->transfer && !host->fifo_len) { |
| 83 | host->status &= 0xf3ff; |
| 84 | return; |
| 85 | } |
| 86 | |
| 87 | if (host->fifo_len > host->af_level && host->ddir) { |
| 88 | if (host->rx_dma) { |
| 89 | host->status &= 0xfbff; |
| 90 | qemu_irq_raise(host->dma_rx_gpio); |
| 91 | } else |
| 92 | host->status |= 0x0400; |
| 93 | } else { |
| 94 | host->status &= 0xfbff; |
| 95 | qemu_irq_lower(host->dma_rx_gpio); |
| 96 | } |
| 97 | |
| 98 | if (host->fifo_len < host->ae_level && !host->ddir) { |
| 99 | if (host->tx_dma) { |
| 100 | host->status &= 0xf7ff; |
| 101 | qemu_irq_raise(host->dma_tx_gpio); |
| 102 | } else |
| 103 | host->status |= 0x0800; |
| 104 | } else { |
| 105 | qemu_irq_lower(host->dma_tx_gpio); |
| 106 | host->status &= 0xf7ff; |
| 107 | } |
| 108 | } |
| 109 | |
| 110 | /* These must match the encoding of the MMC_CMD Response field */ |
| 111 | typedef enum { |
| 112 | sd_nore = 0, /* no response */ |
| 113 | sd_r1, /* normal response command */ |
| 114 | sd_r2, /* CID, CSD registers */ |
| 115 | sd_r3, /* OCR register */ |
| 116 | sd_r6 = 6, /* Published RCA response */ |
| 117 | sd_r1b = -1, |
| 118 | } sd_rsp_type_t; |
| 119 | |
| 120 | /* These must match the encoding of the MMC_CMD Type field */ |
| 121 | typedef enum { |
| 122 | SD_TYPE_BC = 0, /* broadcast -- no response */ |
| 123 | SD_TYPE_BCR = 1, /* broadcast with response */ |
| 124 | SD_TYPE_AC = 2, /* addressed -- no data transfer */ |
| 125 | SD_TYPE_ADTC = 3, /* addressed with data transfer */ |
| 126 | } MMCCmdType; |
| 127 | |
| 128 | static void omap_mmc_command(OMAPMMCState *host, int cmd, int dir, |
| 129 | MMCCmdType type, int busy, |
| 130 | sd_rsp_type_t resptype, int init) |
| 131 | { |
| 132 | uint32_t rspstatus, mask; |
| 133 | size_t rsplen; |
| 134 | int timeout; |
| 135 | SDRequest request; |
| 136 | uint8_t response[16]; |
| 137 | |
| 138 | if (init && cmd == 0) { |
| 139 | host->status |= 0x0001; |
| 140 | return; |
| 141 | } |
| 142 | |
| 143 | if (resptype == sd_r1 && busy) |
| 144 | resptype = sd_r1b; |
| 145 | |
| 146 | if (type == SD_TYPE_ADTC) { |
| 147 | host->fifo_start = 0; |
| 148 | host->fifo_len = 0; |
| 149 | host->transfer = 1; |
| 150 | host->ddir = dir; |
| 151 | } else |
| 152 | host->transfer = 0; |
| 153 | timeout = 0; |
| 154 | mask = 0; |
| 155 | rspstatus = 0; |
| 156 | |
| 157 | request.cmd = cmd; |
| 158 | request.arg = host->arg; |
| 159 | request.crc = 0; /* FIXME */ |
| 160 | |
| 161 | rsplen = sdbus_do_command(&host->sdbus, &request, response, sizeof(response)); |
| 162 | |
| 163 | /* TODO: validate CRCs */ |
| 164 | switch (resptype) { |
| 165 | case sd_nore: |
| 166 | rsplen = 0; |
| 167 | break; |
| 168 | |
| 169 | case sd_r1: |
| 170 | case sd_r1b: |
| 171 | if (rsplen < 4) { |
| 172 | timeout = 1; |
| 173 | break; |
| 174 | } |
| 175 | rsplen = 4; |
| 176 | |
| 177 | mask = OUT_OF_RANGE | ADDRESS_ERROR | BLOCK_LEN_ERROR | |
| 178 | ERASE_SEQ_ERROR | ERASE_PARAM | WP_VIOLATION | |
| 179 | LOCK_UNLOCK_FAILED | COM_CRC_ERROR | ILLEGAL_COMMAND | |
| 180 | CARD_ECC_FAILED | CC_ERROR | SD_ERROR | |
| 181 | CID_CSD_OVERWRITE; |
| 182 | if (host->sdio & (1 << 13)) |
| 183 | mask |= AKE_SEQ_ERROR; |
| 184 | rspstatus = ldl_be_p(response); |
| 185 | break; |
| 186 | |
| 187 | case sd_r2: |
| 188 | if (rsplen < 16) { |
| 189 | timeout = 1; |
| 190 | break; |
| 191 | } |
| 192 | rsplen = 16; |
| 193 | break; |
| 194 | |
| 195 | case sd_r3: |
| 196 | if (rsplen < 4) { |
| 197 | timeout = 1; |
| 198 | break; |
| 199 | } |
| 200 | rsplen = 4; |
| 201 | |
| 202 | rspstatus = ldl_be_p(response); |
| 203 | if (rspstatus & 0x80000000) |
| 204 | host->status &= 0xe000; |
| 205 | else |
| 206 | host->status |= 0x1000; |
| 207 | break; |
| 208 | |
| 209 | case sd_r6: |
| 210 | if (rsplen < 4) { |
| 211 | timeout = 1; |
| 212 | break; |
| 213 | } |
| 214 | rsplen = 4; |
| 215 | |
| 216 | mask = 0xe000 | AKE_SEQ_ERROR; |
| 217 | rspstatus = (response[2] << 8) | (response[3] << 0); |
| 218 | } |
| 219 | |
| 220 | if (rspstatus & mask) |
| 221 | host->status |= 0x4000; |
| 222 | else |
| 223 | host->status &= 0xb000; |
| 224 | |
| 225 | if (rsplen) |
| 226 | for (rsplen = 0; rsplen < 8; rsplen ++) |
| 227 | host->rsp[~rsplen & 7] = response[(rsplen << 1) | 1] | |
| 228 | (response[(rsplen << 1) | 0] << 8); |
| 229 | |
| 230 | if (timeout) |
| 231 | host->status |= 0x0080; |
| 232 | else if (cmd == 12) |
| 233 | host->status |= 0x0005; /* Makes it more real */ |
| 234 | else |
| 235 | host->status |= 0x0001; |
| 236 | } |
| 237 | |
| 238 | static void omap_mmc_transfer(OMAPMMCState *host) |
| 239 | { |
| 240 | uint8_t value; |
| 241 | |
| 242 | if (!host->transfer) |
| 243 | return; |
| 244 | |
| 245 | while (1) { |
| 246 | if (host->ddir) { |
| 247 | if (host->fifo_len > host->af_level) |
| 248 | break; |
| 249 | |
| 250 | value = sdbus_read_byte(&host->sdbus); |
| 251 | host->fifo[(host->fifo_start + host->fifo_len) & 31] = value; |
| 252 | if (-- host->blen_counter) { |
| 253 | value = sdbus_read_byte(&host->sdbus); |
| 254 | host->fifo[(host->fifo_start + host->fifo_len) & 31] |= |
| 255 | value << 8; |
| 256 | host->blen_counter --; |
| 257 | } |
| 258 | |
| 259 | host->fifo_len ++; |
| 260 | } else { |
| 261 | if (!host->fifo_len) |
| 262 | break; |
| 263 | |
| 264 | value = host->fifo[host->fifo_start] & 0xff; |
| 265 | sdbus_write_byte(&host->sdbus, value); |
| 266 | if (-- host->blen_counter) { |
| 267 | value = host->fifo[host->fifo_start] >> 8; |
| 268 | sdbus_write_byte(&host->sdbus, value); |
| 269 | host->blen_counter --; |
| 270 | } |
| 271 | |
| 272 | host->fifo_start ++; |
| 273 | host->fifo_len --; |
| 274 | host->fifo_start &= 31; |
| 275 | } |
| 276 | |
| 277 | if (host->blen_counter == 0) { |
| 278 | host->nblk_counter --; |
| 279 | host->blen_counter = host->blen; |
| 280 | |
| 281 | if (host->nblk_counter == 0) { |
| 282 | host->nblk_counter = host->nblk; |
| 283 | host->transfer = 0; |
| 284 | host->status |= 0x0008; |
| 285 | break; |
| 286 | } |
| 287 | } |
| 288 | } |
| 289 | } |
| 290 | |
| 291 | static void omap_mmc_update(void *opaque) |
| 292 | { |
| 293 | OMAPMMCState *s = opaque; |
| 294 | omap_mmc_transfer(s); |
| 295 | omap_mmc_fifolevel_update(s); |
| 296 | omap_mmc_interrupts_update(s); |
| 297 | } |
| 298 | |
| 299 | static void omap_mmc_pseudo_reset(OMAPMMCState *host) |
| 300 | { |
| 301 | host->status = 0; |
| 302 | host->fifo_len = 0; |
| 303 | } |
| 304 | |
| 305 | static void omap_mmc_reset(OMAPMMCState *host) |
| 306 | { |
| 307 | host->last_cmd = 0; |
| 308 | memset(host->rsp, 0, sizeof(host->rsp)); |
| 309 | host->arg = 0; |
| 310 | host->dw = 0; |
| 311 | host->mode = 0; |
| 312 | host->enable = 0; |
| 313 | host->mask = 0; |
| 314 | host->cto = 0; |
| 315 | host->dto = 0; |
| 316 | host->blen = 0; |
| 317 | host->blen_counter = 0; |
| 318 | host->nblk = 0; |
| 319 | host->nblk_counter = 0; |
| 320 | host->tx_dma = 0; |
| 321 | host->rx_dma = 0; |
| 322 | host->ae_level = 0x00; |
| 323 | host->af_level = 0x1f; |
| 324 | host->transfer = 0; |
| 325 | host->cdet_wakeup = 0; |
| 326 | host->cdet_enable = 0; |
| 327 | host->clkdiv = 0; |
| 328 | |
| 329 | omap_mmc_pseudo_reset(host); |
| 330 | } |
| 331 | |
| 332 | static uint64_t omap_mmc_read(void *opaque, hwaddr offset, unsigned size) |
| 333 | { |
| 334 | uint16_t i; |
| 335 | OMAPMMCState *s = opaque; |
| 336 | |
| 337 | if (size != 2) { |
| 338 | qemu_log_mask(LOG_GUEST_ERROR, "%s: read at offset 0x%" HWADDR_PRIx |
| 339 | " with bad width %d\n", __func__, offset, size); |
| 340 | return 0; |
| 341 | } |
| 342 | |
| 343 | switch (offset) { |
| 344 | case 0x00: /* MMC_CMD */ |
| 345 | return s->last_cmd; |
| 346 | |
| 347 | case 0x04: /* MMC_ARGL */ |
| 348 | return s->arg & 0x0000ffff; |
| 349 | |
| 350 | case 0x08: /* MMC_ARGH */ |
| 351 | return s->arg >> 16; |
| 352 | |
| 353 | case 0x0c: /* MMC_CON */ |
| 354 | return (s->dw << 15) | (s->mode << 12) | (s->enable << 11) | |
| 355 | (s->be << 10) | s->clkdiv; |
| 356 | |
| 357 | case 0x10: /* MMC_STAT */ |
| 358 | return s->status; |
| 359 | |
| 360 | case 0x14: /* MMC_IE */ |
| 361 | return s->mask; |
| 362 | |
| 363 | case 0x18: /* MMC_CTO */ |
| 364 | return s->cto; |
| 365 | |
| 366 | case 0x1c: /* MMC_DTO */ |
| 367 | return s->dto; |
| 368 | |
| 369 | case 0x20: /* MMC_DATA */ |
| 370 | /* TODO: support 8-bit access */ |
| 371 | i = s->fifo[s->fifo_start]; |
| 372 | if (s->fifo_len == 0) { |
| 373 | printf("MMC: FIFO underrun\n"); |
| 374 | return i; |
| 375 | } |
| 376 | s->fifo_start ++; |
| 377 | s->fifo_len --; |
| 378 | s->fifo_start &= 31; |
| 379 | omap_mmc_transfer(s); |
| 380 | omap_mmc_fifolevel_update(s); |
| 381 | omap_mmc_interrupts_update(s); |
| 382 | return i; |
| 383 | |
| 384 | case 0x24: /* MMC_BLEN */ |
| 385 | return s->blen_counter; |
| 386 | |
| 387 | case 0x28: /* MMC_NBLK */ |
| 388 | return s->nblk_counter; |
| 389 | |
| 390 | case 0x2c: /* MMC_BUF */ |
| 391 | return (s->rx_dma << 15) | (s->af_level << 8) | |
| 392 | (s->tx_dma << 7) | s->ae_level; |
| 393 | |
| 394 | case 0x30: /* MMC_SPI */ |
| 395 | return 0x0000; |
| 396 | case 0x34: /* MMC_SDIO */ |
| 397 | return (s->cdet_wakeup << 2) | (s->cdet_enable) | s->sdio; |
| 398 | case 0x38: /* MMC_SYST */ |
| 399 | return 0x0000; |
| 400 | |
| 401 | case 0x3c: /* MMC_REV */ |
| 402 | return s->rev; |
| 403 | |
| 404 | case 0x40: /* MMC_RSP0 */ |
| 405 | case 0x44: /* MMC_RSP1 */ |
| 406 | case 0x48: /* MMC_RSP2 */ |
| 407 | case 0x4c: /* MMC_RSP3 */ |
| 408 | case 0x50: /* MMC_RSP4 */ |
| 409 | case 0x54: /* MMC_RSP5 */ |
| 410 | case 0x58: /* MMC_RSP6 */ |
| 411 | case 0x5c: /* MMC_RSP7 */ |
| 412 | return s->rsp[(offset - 0x40) >> 2]; |
| 413 | |
| 414 | /* OMAP2-specific */ |
| 415 | case 0x60: /* MMC_IOSR */ |
| 416 | case 0x64: /* MMC_SYSC */ |
| 417 | return 0; |
| 418 | case 0x68: /* MMC_SYSS */ |
| 419 | return 1; /* RSTD */ |
| 420 | } |
| 421 | |
| 422 | OMAP_BAD_REG(offset); |
| 423 | return 0; |
| 424 | } |
| 425 | |
| 426 | static void omap_mmc_write(void *opaque, hwaddr offset, |
| 427 | uint64_t value, unsigned size) |
| 428 | { |
| 429 | int i; |
| 430 | OMAPMMCState *s = opaque; |
| 431 | |
| 432 | if (size != 2) { |
| 433 | qemu_log_mask(LOG_GUEST_ERROR, "%s: write at offset 0x%" HWADDR_PRIx |
| 434 | " with bad width %d\n", __func__, offset, size); |
| 435 | return; |
| 436 | } |
| 437 | |
| 438 | switch (offset) { |
| 439 | case 0x00: /* MMC_CMD */ |
| 440 | if (!s->enable) |
| 441 | break; |
| 442 | |
| 443 | s->last_cmd = value; |
| 444 | for (i = 0; i < 8; i ++) |
| 445 | s->rsp[i] = 0x0000; |
| 446 | omap_mmc_command(s, value & 63, (value >> 15) & 1, |
| 447 | (MMCCmdType)((value >> 12) & 3), |
| 448 | (value >> 11) & 1, |
| 449 | (sd_rsp_type_t) ((value >> 8) & 7), |
| 450 | (value >> 7) & 1); |
| 451 | omap_mmc_update(s); |
| 452 | break; |
| 453 | |
| 454 | case 0x04: /* MMC_ARGL */ |
| 455 | s->arg &= 0xffff0000; |
| 456 | s->arg |= 0x0000ffff & value; |
| 457 | break; |
| 458 | |
| 459 | case 0x08: /* MMC_ARGH */ |
| 460 | s->arg &= 0x0000ffff; |
| 461 | s->arg |= value << 16; |
| 462 | break; |
| 463 | |
| 464 | case 0x0c: /* MMC_CON */ |
| 465 | s->dw = (value >> 15) & 1; |
| 466 | s->mode = (value >> 12) & 3; |
| 467 | s->enable = (value >> 11) & 1; |
| 468 | s->be = (value >> 10) & 1; |
| 469 | s->clkdiv = (value >> 0) & (s->rev >= 2 ? 0x3ff : 0xff); |
| 470 | if (s->mode != 0) { |
| 471 | qemu_log_mask(LOG_UNIMP, |
| 472 | "omap_mmc_wr: mode #%i unimplemented\n", s->mode); |
| 473 | } |
| 474 | if (s->be != 0) { |
| 475 | qemu_log_mask(LOG_UNIMP, |
| 476 | "omap_mmc_wr: Big Endian not implemented\n"); |
| 477 | } |
| 478 | if (s->dw != 0 && s->lines < 4) |
| 479 | printf("4-bit SD bus enabled\n"); |
| 480 | if (!s->enable) |
| 481 | omap_mmc_pseudo_reset(s); |
| 482 | break; |
| 483 | |
| 484 | case 0x10: /* MMC_STAT */ |
| 485 | s->status &= ~value; |
| 486 | omap_mmc_interrupts_update(s); |
| 487 | break; |
| 488 | |
| 489 | case 0x14: /* MMC_IE */ |
| 490 | s->mask = value & 0x7fff; |
| 491 | omap_mmc_interrupts_update(s); |
| 492 | break; |
| 493 | |
| 494 | case 0x18: /* MMC_CTO */ |
| 495 | s->cto = value & 0xff; |
| 496 | if (s->cto > 0xfd && s->rev <= 1) |
| 497 | printf("MMC: CTO of 0xff and 0xfe cannot be used!\n"); |
| 498 | break; |
| 499 | |
| 500 | case 0x1c: /* MMC_DTO */ |
| 501 | s->dto = value & 0xffff; |
| 502 | break; |
| 503 | |
| 504 | case 0x20: /* MMC_DATA */ |
| 505 | /* TODO: support 8-bit access */ |
| 506 | if (s->fifo_len == 32) |
| 507 | break; |
| 508 | s->fifo[(s->fifo_start + s->fifo_len) & 31] = value; |
| 509 | s->fifo_len ++; |
| 510 | omap_mmc_transfer(s); |
| 511 | omap_mmc_fifolevel_update(s); |
| 512 | omap_mmc_interrupts_update(s); |
| 513 | break; |
| 514 | |
| 515 | case 0x24: /* MMC_BLEN */ |
| 516 | s->blen = (value & 0x07ff) + 1; |
| 517 | s->blen_counter = s->blen; |
| 518 | break; |
| 519 | |
| 520 | case 0x28: /* MMC_NBLK */ |
| 521 | s->nblk = (value & 0x07ff) + 1; |
| 522 | s->nblk_counter = s->nblk; |
| 523 | s->blen_counter = s->blen; |
| 524 | break; |
| 525 | |
| 526 | case 0x2c: /* MMC_BUF */ |
| 527 | s->rx_dma = (value >> 15) & 1; |
| 528 | s->af_level = (value >> 8) & 0x1f; |
| 529 | s->tx_dma = (value >> 7) & 1; |
| 530 | s->ae_level = value & 0x1f; |
| 531 | |
| 532 | if (s->rx_dma) |
| 533 | s->status &= 0xfbff; |
| 534 | if (s->tx_dma) |
| 535 | s->status &= 0xf7ff; |
| 536 | omap_mmc_fifolevel_update(s); |
| 537 | omap_mmc_interrupts_update(s); |
| 538 | break; |
| 539 | |
| 540 | /* SPI, SDIO and TEST modes unimplemented */ |
| 541 | case 0x30: /* MMC_SPI (OMAP1 only) */ |
| 542 | break; |
| 543 | case 0x34: /* MMC_SDIO */ |
| 544 | s->sdio = value & (s->rev >= 2 ? 0xfbf3 : 0x2020); |
| 545 | s->cdet_wakeup = (value >> 9) & 1; |
| 546 | s->cdet_enable = (value >> 2) & 1; |
| 547 | break; |
| 548 | case 0x38: /* MMC_SYST */ |
| 549 | break; |
| 550 | |
| 551 | case 0x3c: /* MMC_REV */ |
| 552 | case 0x40: /* MMC_RSP0 */ |
| 553 | case 0x44: /* MMC_RSP1 */ |
| 554 | case 0x48: /* MMC_RSP2 */ |
| 555 | case 0x4c: /* MMC_RSP3 */ |
| 556 | case 0x50: /* MMC_RSP4 */ |
| 557 | case 0x54: /* MMC_RSP5 */ |
| 558 | case 0x58: /* MMC_RSP6 */ |
| 559 | case 0x5c: /* MMC_RSP7 */ |
| 560 | OMAP_RO_REG(offset); |
| 561 | break; |
| 562 | |
| 563 | /* OMAP2-specific */ |
| 564 | case 0x60: /* MMC_IOSR */ |
| 565 | if (value & 0xf) |
| 566 | printf("MMC: SDIO bits used!\n"); |
| 567 | break; |
| 568 | case 0x64: /* MMC_SYSC */ |
| 569 | if (value & (1 << 2)) /* SRTS */ |
| 570 | omap_mmc_reset(s); |
| 571 | break; |
| 572 | case 0x68: /* MMC_SYSS */ |
| 573 | OMAP_RO_REG(offset); |
| 574 | break; |
| 575 | |
| 576 | default: |
| 577 | OMAP_BAD_REG(offset); |
| 578 | } |
| 579 | } |
| 580 | |
| 581 | static const MemoryRegionOps omap_mmc_ops = { |
| 582 | .read = omap_mmc_read, |
| 583 | .write = omap_mmc_write, |
| 584 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 585 | }; |
| 586 | |
| 587 | void omap_mmc_set_clk(DeviceState *dev, omap_clk clk) |
| 588 | { |
| 589 | OMAPMMCState *s = OMAP_MMC(dev); |
| 590 | |
| 591 | s->clk = clk; |
| 592 | } |
| 593 | |
| 594 | static void omap_mmc_reset_hold(Object *obj, ResetType type) |
| 595 | { |
| 596 | OMAPMMCState *s = OMAP_MMC(obj); |
| 597 | |
| 598 | omap_mmc_reset(s); |
| 599 | } |
| 600 | |
| 601 | static void omap_mmc_initfn(Object *obj) |
| 602 | { |
| 603 | OMAPMMCState *s = OMAP_MMC(obj); |
| 604 | |
| 605 | /* In theory these could be settable per-board */ |
| 606 | s->lines = 1; |
| 607 | s->rev = 1; |
| 608 | |
| 609 | memory_region_init_io(&s->iomem, obj, &omap_mmc_ops, s, "omap.mmc", 0x800); |
| 610 | sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); |
| 611 | |
| 612 | sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); |
| 613 | qdev_init_gpio_out_named(DEVICE(obj), &s->dma_tx_gpio, "dma-tx", 1); |
| 614 | qdev_init_gpio_out_named(DEVICE(obj), &s->dma_rx_gpio, "dma-rx", 1); |
| 615 | |
| 616 | qbus_init(&s->sdbus, sizeof(s->sdbus), TYPE_SD_BUS, DEVICE(obj), "sd-bus"); |
| 617 | } |
| 618 | |
| 619 | static void omap_mmc_class_init(ObjectClass *oc, const void *data) |
| 620 | { |
| 621 | ResettableClass *rc = RESETTABLE_CLASS(oc); |
| 622 | |
| 623 | rc->phases.hold = omap_mmc_reset_hold; |
| 624 | } |
| 625 | |
| 626 | static const TypeInfo omap_mmc_info = { |
| 627 | .name = TYPE_OMAP_MMC, |
| 628 | .parent = TYPE_SYS_BUS_DEVICE, |
| 629 | .instance_size = sizeof(OMAPMMCState), |
| 630 | .instance_init = omap_mmc_initfn, |
| 631 | .class_init = omap_mmc_class_init, |
| 632 | }; |
| 633 | |
| 634 | static void omap_mmc_register_types(void) |
| 635 | { |
| 636 | type_register_static(&omap_mmc_info); |
| 637 | } |
| 638 | |
| 639 | type_init(omap_mmc_register_types) |