sdhci.c · samitouri/QOSamiQemu · siGit Code & Deploy

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1	/*
2	* SD Association Host Standard Specification v2.0 controller emulation
3	*
4	* Datasheet: PartA2_SD_Host_Controller_Simplified_Specification_Ver2.00.pdf
5	*
6	* Copyright (c) 2011 Samsung Electronics Co., Ltd.
7	* Mitsyanko Igor <i.mitsyanko@samsung.com>
8	* Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com>
9	*
10	* Based on MMC controller for Samsung S5PC1xx-based board emulation
11	* by Alexey Merkulov and Vladimir Monakhov.
12	*
13	* This program is free software; you can redistribute it and/or modify it
14	* under the terms of the GNU General Public License as published by the
15	* Free Software Foundation; either version 2 of the License, or (at your
16	* option) any later version.
17	*
18	* This program is distributed in the hope that it will be useful,
19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
21	* See the GNU General Public License for more details.
22	*
23	* You should have received a copy of the GNU General Public License along
24	* with this program; if not, see <http://www.gnu.org/licenses/>.
25	*/
26
27	#include "qemu/osdep.h"
28	#include "qemu/units.h"
29	#include "qemu/error-report.h"
30	#include "qapi/error.h"
31	#include "hw/core/irq.h"
32	#include "hw/core/qdev-properties.h"
33	#include "system/dma.h"
34	#include "qemu/timer.h"
35	#include "qemu/bitops.h"
36	#include "hw/sd/sdhci.h"
37	#include "migration/vmstate.h"
38	#include "sdhci-internal.h"
39	#include "qemu/log.h"
40	#include "trace.h"
41	#include "qom/object.h"
42
43	#define TYPE_SDHCI_BUS "sdhci-bus"
44	/* This is reusing the SDBus typedef from SD_BUS */
45	DECLARE_INSTANCE_CHECKER(SDBus, SDHCI_BUS,
46	TYPE_SDHCI_BUS)
47
48	#define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) \| (val))
49
50	static inline unsigned int sdhci_get_fifolen(SDHCIState *s)
51	{
52	return 1 << (9 + FIELD_EX32(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH));
53	}
54
55	/* return true on error */
56	static bool sdhci_check_capab_freq_range(SDHCIState s, const char desc,
57	uint8_t freq, Error **errp)
58	{
59	if (s->sd_spec_version >= 3) {
60	return false;
61	}
62	switch (freq) {
63	case 0:
64	case 10 ... 63:
65	break;
66	default:
67	error_setg(errp, "SD %s clock frequency can have value"
68	"in range 0-63 only", desc);
69	return true;
70	}
71	return false;
72	}
73
74	static void sdhci_check_capareg(SDHCIState s, Error *errp)
75	{
76	uint64_t msk = s->capareg;
77	uint32_t val;
78	bool y;
79
80	switch (s->sd_spec_version) {
81	case 4:
82	val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT_V4);
83	trace_sdhci_capareg("64-bit system bus (v4)", val);
84	msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT_V4, 0);
85
86	val = FIELD_EX64(s->capareg, SDHC_CAPAB, UHS_II);
87	trace_sdhci_capareg("UHS-II", val);
88	msk = FIELD_DP64(msk, SDHC_CAPAB, UHS_II, 0);
89
90	val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA3);
91	trace_sdhci_capareg("ADMA3", val);
92	msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA3, 0);
93
94	/* fallthrough */
95	case 3:
96	val = FIELD_EX64(s->capareg, SDHC_CAPAB, ASYNC_INT);
97	trace_sdhci_capareg("async interrupt", val);
98	msk = FIELD_DP64(msk, SDHC_CAPAB, ASYNC_INT, 0);
99
100	val = FIELD_EX64(s->capareg, SDHC_CAPAB, SLOT_TYPE);
101	if (val) {
102	error_setg(errp, "slot-type not supported");
103	return;
104	}
105	trace_sdhci_capareg("slot type", val);
106	msk = FIELD_DP64(msk, SDHC_CAPAB, SLOT_TYPE, 0);
107
108	if (val != 2) {
109	val = FIELD_EX64(s->capareg, SDHC_CAPAB, EMBEDDED_8BIT);
110	trace_sdhci_capareg("8-bit bus", val);
111	}
112	msk = FIELD_DP64(msk, SDHC_CAPAB, EMBEDDED_8BIT, 0);
113
114	val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS_SPEED);
115	trace_sdhci_capareg("bus speed mask", val);
116	msk = FIELD_DP64(msk, SDHC_CAPAB, BUS_SPEED, 0);
117
118	val = FIELD_EX64(s->capareg, SDHC_CAPAB, DRIVER_STRENGTH);
119	trace_sdhci_capareg("driver strength mask", val);
120	msk = FIELD_DP64(msk, SDHC_CAPAB, DRIVER_STRENGTH, 0);
121
122	val = FIELD_EX64(s->capareg, SDHC_CAPAB, TIMER_RETUNING);
123	trace_sdhci_capareg("timer re-tuning", val);
124	msk = FIELD_DP64(msk, SDHC_CAPAB, TIMER_RETUNING, 0);
125
126	val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDR50_TUNING);
127	trace_sdhci_capareg("use SDR50 tuning", val);
128	msk = FIELD_DP64(msk, SDHC_CAPAB, SDR50_TUNING, 0);
129
130	val = FIELD_EX64(s->capareg, SDHC_CAPAB, RETUNING_MODE);
131	trace_sdhci_capareg("re-tuning mode", val);
132	msk = FIELD_DP64(msk, SDHC_CAPAB, RETUNING_MODE, 0);
133
134	val = FIELD_EX64(s->capareg, SDHC_CAPAB, CLOCK_MULT);
135	trace_sdhci_capareg("clock multiplier", val);
136	msk = FIELD_DP64(msk, SDHC_CAPAB, CLOCK_MULT, 0);
137
138	/* fallthrough */
139	case 2: /* default version */
140	val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA2);
141	trace_sdhci_capareg("ADMA2", val);
142	msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA2, 0);
143
144	val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA1);
145	trace_sdhci_capareg("ADMA1", val);
146	msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA1, 0);
147
148	val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT);
149	trace_sdhci_capareg("64-bit system bus (v3)", val);
150	msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT, 0);
151
152	/* fallthrough */
153	case 1:
154	y = FIELD_EX64(s->capareg, SDHC_CAPAB, TOUNIT);
155	msk = FIELD_DP64(msk, SDHC_CAPAB, TOUNIT, 0);
156
157	val = FIELD_EX64(s->capareg, SDHC_CAPAB, TOCLKFREQ);
158	trace_sdhci_capareg(y ? "timeout (MHz)" : "Timeout (KHz)", val);
159	if (sdhci_check_capab_freq_range(s, "timeout", val, errp)) {
160	return;
161	}
162	msk = FIELD_DP64(msk, SDHC_CAPAB, TOCLKFREQ, 0);
163
164	val = FIELD_EX64(s->capareg, SDHC_CAPAB, BASECLKFREQ);
165	trace_sdhci_capareg(y ? "base (MHz)" : "Base (KHz)", val);
166	if (sdhci_check_capab_freq_range(s, "base", val, errp)) {
167	return;
168	}
169	msk = FIELD_DP64(msk, SDHC_CAPAB, BASECLKFREQ, 0);
170
171	val = FIELD_EX64(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH);
172	if (val >= 3) {
173	error_setg(errp, "block size can be 512, 1024 or 2048 only");
174	return;
175	}
176	trace_sdhci_capareg("max block length", sdhci_get_fifolen(s));
177	msk = FIELD_DP64(msk, SDHC_CAPAB, MAXBLOCKLENGTH, 0);
178
179	val = FIELD_EX64(s->capareg, SDHC_CAPAB, HIGHSPEED);
180	trace_sdhci_capareg("high speed", val);
181	msk = FIELD_DP64(msk, SDHC_CAPAB, HIGHSPEED, 0);
182
183	val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDMA);
184	trace_sdhci_capareg("SDMA", val);
185	msk = FIELD_DP64(msk, SDHC_CAPAB, SDMA, 0);
186
187	val = FIELD_EX64(s->capareg, SDHC_CAPAB, SUSPRESUME);
188	trace_sdhci_capareg("suspend/resume", val);
189	msk = FIELD_DP64(msk, SDHC_CAPAB, SUSPRESUME, 0);
190
191	val = FIELD_EX64(s->capareg, SDHC_CAPAB, V33);
192	trace_sdhci_capareg("3.3v", val);
193	msk = FIELD_DP64(msk, SDHC_CAPAB, V33, 0);
194
195	val = FIELD_EX64(s->capareg, SDHC_CAPAB, V30);
196	trace_sdhci_capareg("3.0v", val);
197	msk = FIELD_DP64(msk, SDHC_CAPAB, V30, 0);
198
199	val = FIELD_EX64(s->capareg, SDHC_CAPAB, V18);
200	trace_sdhci_capareg("1.8v", val);
201	msk = FIELD_DP64(msk, SDHC_CAPAB, V18, 0);
202	break;
203
204	default:
205	error_setg(errp, "Unsupported spec version: %u", s->sd_spec_version);
206	}
207	if (msk) {
208	qemu_log_mask(LOG_UNIMP,
209	"SDHCI: unknown CAPAB mask: 0x%016" PRIx64 "\n", msk);
210	}
211	}
212
213	static uint8_t sdhci_slotint(SDHCIState *s)
214	{
215	return (s->norintsts & s->norintsigen) \|\| (s->errintsts & s->errintsigen) \|\|
216	((s->norintsts & SDHC_NIS_INSERT) && (s->wakcon & SDHC_WKUP_ON_INS)) \|\|
217	((s->norintsts & SDHC_NIS_REMOVE) && (s->wakcon & SDHC_WKUP_ON_RMV));
218	}
219
220	/* Return true if IRQ was pending and delivered */
221	static bool sdhci_update_irq(SDHCIState *s)
222	{
223	bool pending = sdhci_slotint(s);
224
225	qemu_set_irq(s->irq, pending);
226
227	return pending;
228	}
229
230	static void sdhci_raise_insertion_irq(void *opaque)
231	{
232	SDHCIState s = (SDHCIState )opaque;
233
234	if (s->norintsts & SDHC_NIS_REMOVE) {
235	timer_mod(s->insert_timer,
236	qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY);
237	} else {
238	s->prnsts = 0x1ff0000;
239	if (s->norintstsen & SDHC_NISEN_INSERT) {
240	s->norintsts \|= SDHC_NIS_INSERT;
241	}
242	sdhci_update_irq(s);
243	}
244	}
245
246	static void sdhci_set_inserted(DeviceState *dev, bool level)
247	{
248	SDHCIState s = (SDHCIState )dev;
249
250	trace_sdhci_set_inserted(level ? "insert" : "eject");
251	if ((s->norintsts & SDHC_NIS_REMOVE) && level) {
252	/* Give target some time to notice card ejection */
253	timer_mod(s->insert_timer,
254	qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY);
255	} else {
256	if (level) {
257	s->prnsts = 0x1ff0000;
258	if (s->norintstsen & SDHC_NISEN_INSERT) {
259	s->norintsts \|= SDHC_NIS_INSERT;
260	}
261	} else {
262	s->prnsts = 0x1fa0000;
263	s->pwrcon &= ~SDHC_POWER_ON;
264	s->clkcon &= ~SDHC_CLOCK_SDCLK_EN;
265	if (s->norintstsen & SDHC_NISEN_REMOVE) {
266	s->norintsts \|= SDHC_NIS_REMOVE;
267	}
268	}
269	sdhci_update_irq(s);
270	}
271	}
272
273	static void sdhci_set_readonly(DeviceState *dev, bool level)
274	{
275	SDHCIState s = (SDHCIState )dev;
276
277	if (s->wp_inverted) {
278	level = !level;
279	}
280
281	if (level) {
282	s->prnsts &= ~SDHC_WRITE_PROTECT;
283	} else {
284	/* Write enabled */
285	s->prnsts \|= SDHC_WRITE_PROTECT;
286	}
287	}
288
289	static void sdhci_reset(SDHCIState *s)
290	{
291	DeviceState *dev = DEVICE(s);
292
293	timer_del(s->insert_timer);
294	timer_del(s->transfer_timer);
295
296	/*
297	* Set all registers to 0. Capabilities/Version registers are not cleared
298	* and assumed to always preserve their value, given to them during
299	* initialization
300	*/
301	memset(&s->sdmasysad, 0, (uintptr_t)&s->capareg - (uintptr_t)&s->sdmasysad);
302
303	/* Reset other state based on current card insertion/readonly status */
304	sdhci_set_inserted(dev, sdbus_get_inserted(&s->sdbus));
305	sdhci_set_readonly(dev, sdbus_get_readonly(&s->sdbus));
306
307	s->data_count = 0;
308	s->stopped_state = sdhc_not_stopped;
309	s->pending_insert_state = false;
310	if (object_dynamic_cast(OBJECT(s), TYPE_FSL_ESDHC_BE) \|\|
311	object_dynamic_cast(OBJECT(s), TYPE_FSL_ESDHC_LE)) {
312	s->norintstsen = 0x013f;
313	s->errintstsen = 0x117f;
314	}
315	}
316
317	static void sdhci_poweron_reset(DeviceState *dev)
318	{
319	/*
320	* QOM (ie power-on) reset. This is identical to reset
321	* commanded via device register apart from handling of the
322	* 'pending insert on powerup' quirk.
323	*/
324	SDHCIState s = (SDHCIState )dev;
325
326	sdhci_reset(s);
327
328	if (s->pending_insert_quirk) {
329	s->pending_insert_state = true;
330	}
331	}
332
333	static void sdhci_data_transfer(void *opaque);
334
335	#define BLOCK_SIZE_MASK (4 * KiB - 1)
336
337	static void sdhci_send_command(SDHCIState *s)
338	{
339	SDRequest request;
340	uint8_t response[16];
341	size_t rlen;
342	bool timeout = false;
343
344	s->errintsts = 0;
345	s->acmd12errsts = 0;
346	request.cmd = s->cmdreg >> 8;
347	request.arg = s->argument;
348
349	trace_sdhci_send_command(request.cmd, request.arg);
350	rlen = sdbus_do_command(&s->sdbus, &request, response, sizeof(response));
351
352	if (s->cmdreg & SDHC_CMD_RESPONSE) {
353	if (rlen == 4) {
354	s->rspreg[0] = ldl_be_p(response);
355	s->rspreg[1] = s->rspreg[2] = s->rspreg[3] = 0;
356	trace_sdhci_response4(s->rspreg[0]);
357	} else if (rlen == 16) {
358	s->rspreg[0] = ldl_be_p(&response[11]);
359	s->rspreg[1] = ldl_be_p(&response[7]);
360	s->rspreg[2] = ldl_be_p(&response[3]);
361	s->rspreg[3] = (response[0] << 16) \| (response[1] << 8) \|
362	response[2];
363	trace_sdhci_response16(s->rspreg[3], s->rspreg[2],
364	s->rspreg[1], s->rspreg[0]);
365	} else {
366	timeout = true;
367	trace_sdhci_error("timeout waiting for command response");
368	if (s->errintstsen & SDHC_EISEN_CMDTIMEOUT) {
369	s->errintsts \|= SDHC_EIS_CMDTIMEOUT;
370	s->norintsts \|= SDHC_NIS_ERR;
371	}
372	}
373
374	if (!(s->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
375	(s->norintstsen & SDHC_NISEN_TRSCMP) &&
376	(s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY) {
377	s->norintsts \|= SDHC_NIS_TRSCMP;
378	}
379	}
380
381	if (s->norintstsen & SDHC_NISEN_CMDCMP) {
382	s->norintsts \|= SDHC_NIS_CMDCMP;
383	}
384
385	sdhci_update_irq(s);
386
387	if (!timeout && (s->blksize & BLOCK_SIZE_MASK) &&
388	(s->cmdreg & SDHC_CMD_DATA_PRESENT)) {
389	s->data_count = 0;
390	sdhci_data_transfer(s);
391	}
392	}
393
394	static void sdhci_end_transfer(SDHCIState *s)
395	{
396	/* Automatically send CMD12 to stop transfer if AutoCMD12 enabled */
397	if ((s->trnmod & SDHC_TRNS_ACMD12) != 0) {
398	SDRequest request;
399	uint8_t response[16];
400
401	request.cmd = 0x0C;
402	request.arg = 0;
403	trace_sdhci_end_transfer(request.cmd, request.arg);
404	sdbus_do_command(&s->sdbus, &request, response, sizeof(response));
405	/* Auto CMD12 response goes to the upper Response register */
406	s->rspreg[3] = ldl_be_p(response);
407	}
408
409	s->prnsts &= ~(SDHC_DOING_READ \| SDHC_DOING_WRITE \|
410	SDHC_DAT_LINE_ACTIVE \| SDHC_DATA_INHIBIT \|
411	SDHC_SPACE_AVAILABLE \| SDHC_DATA_AVAILABLE);
412
413	if (s->norintstsen & SDHC_NISEN_TRSCMP) {
414	s->norintsts \|= SDHC_NIS_TRSCMP;
415	}
416
417	sdhci_update_irq(s);
418	}
419
420	/*
421	* Programmed i/o data transfer
422	*/
423
424	/* Fill host controller's read buffer with BLKSIZE bytes of data from card */
425	static void sdhci_read_block_from_card(SDHCIState *s)
426	{
427	const uint16_t blk_size = s->blksize & BLOCK_SIZE_MASK;
428
429	if ((s->trnmod & SDHC_TRNS_MULTI) &&
430	(s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) {
431	return;
432	}
433
434	if (!FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) {
435	/* Device is not in tuning */
436	sdbus_read_data(&s->sdbus, s->fifo_buffer, blk_size);
437	}
438
439	if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) {
440	/* Device is in tuning */
441	s->hostctl2 &= ~R_SDHC_HOSTCTL2_EXECUTE_TUNING_MASK;
442	s->hostctl2 \|= R_SDHC_HOSTCTL2_SAMPLING_CLKSEL_MASK;
443	s->prnsts &= ~(SDHC_DAT_LINE_ACTIVE \| SDHC_DOING_READ \|
444	SDHC_DATA_INHIBIT);
445	goto read_done;
446	}
447
448	/* New data now available for READ through Buffer Port Register */
449	s->prnsts \|= SDHC_DATA_AVAILABLE;
450	if (s->norintstsen & SDHC_NISEN_RBUFRDY) {
451	s->norintsts \|= SDHC_NIS_RBUFRDY;
452	}
453
454	/* Clear DAT line active status if that was the last block */
455	if ((s->trnmod & SDHC_TRNS_MULTI) == 0 \|\|
456	((s->trnmod & SDHC_TRNS_MULTI) && s->blkcnt == 1)) {
457	s->prnsts &= ~SDHC_DAT_LINE_ACTIVE;
458	}
459
460	/*
461	* If stop at block gap request was set and it's not the last block of
462	* data - generate Block Event interrupt
463	*/
464	if (s->stopped_state == sdhc_gap_read && (s->trnmod & SDHC_TRNS_MULTI) &&
465	s->blkcnt != 1) {
466	s->prnsts &= ~SDHC_DAT_LINE_ACTIVE;
467	if (s->norintstsen & SDHC_EISEN_BLKGAP) {
468	s->norintsts \|= SDHC_EIS_BLKGAP;
469	}
470	}
471
472	read_done:
473	sdhci_update_irq(s);
474	}
475
476	/* Read @size byte of data from host controller @s BUFFER DATA PORT register */
477	static uint32_t sdhci_read_dataport(SDHCIState *s, unsigned size)
478	{
479	uint32_t value = 0;
480	int i;
481
482	/* first check that a valid data exists in host controller input buffer */
483	if ((s->prnsts & SDHC_DATA_AVAILABLE) == 0) {
484	trace_sdhci_error("read from empty buffer");
485	return 0;
486	}
487
488	for (i = 0; i < size; i++) {
489	assert(s->data_count < s->buf_maxsz);
490	value \|= s->fifo_buffer[s->data_count] << i * 8;
491	s->data_count++;
492	/* check if we've read all valid data (blksize bytes) from buffer */
493	if ((s->data_count) >= (s->blksize & BLOCK_SIZE_MASK)) {
494	trace_sdhci_read_dataport(s->data_count);
495	s->prnsts &= ~SDHC_DATA_AVAILABLE; /* no more data in a buffer */
496	s->data_count = 0; /* next buff read must start at position [0] */
497
498	if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
499	s->blkcnt--;
500	}
501
502	/* if that was the last block of data */
503	if ((s->trnmod & SDHC_TRNS_MULTI) == 0 \|\|
504	((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) \|\|
505	/* stop at gap request */
506	(s->stopped_state == sdhc_gap_read &&
507	!(s->prnsts & SDHC_DAT_LINE_ACTIVE))) {
508	sdhci_end_transfer(s);
509	} else { /* if there are more data, read next block from card */
510	sdhci_read_block_from_card(s);
511	}
512	break;
513	}
514	}
515
516	return value;
517	}
518
519	/* Write data from host controller FIFO to card */
520	static void sdhci_write_block_to_card(SDHCIState *s)
521	{
522	if (s->prnsts & SDHC_SPACE_AVAILABLE) {
523	if (s->norintstsen & SDHC_NISEN_WBUFRDY) {
524	s->norintsts \|= SDHC_NIS_WBUFRDY;
525	}
526	sdhci_update_irq(s);
527	return;
528	}
529
530	if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
531	if (s->blkcnt == 0) {
532	return;
533	} else {
534	s->blkcnt--;
535	}
536	}
537
538	sdbus_write_data(&s->sdbus, s->fifo_buffer, s->blksize & BLOCK_SIZE_MASK);
539
540	/* Next data can be written through BUFFER DATORT register */
541	s->prnsts \|= SDHC_SPACE_AVAILABLE;
542
543	/* Finish transfer if that was the last block of data */
544	if ((s->trnmod & SDHC_TRNS_MULTI) == 0 \|\|
545	((s->trnmod & SDHC_TRNS_MULTI) &&
546	(s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0))) {
547	sdhci_end_transfer(s);
548	} else if (s->norintstsen & SDHC_NISEN_WBUFRDY) {
549	s->norintsts \|= SDHC_NIS_WBUFRDY;
550	}
551
552	/* Generate Block Gap Event if requested and if not the last block */
553	if (s->stopped_state == sdhc_gap_write && (s->trnmod & SDHC_TRNS_MULTI) &&
554	s->blkcnt > 0) {
555	s->prnsts &= ~SDHC_DOING_WRITE;
556	if (s->norintstsen & SDHC_EISEN_BLKGAP) {
557	s->norintsts \|= SDHC_EIS_BLKGAP;
558	}
559	sdhci_end_transfer(s);
560	}
561
562	sdhci_update_irq(s);
563	}
564
565	/*
566	* Write @size bytes of @value data to host controller @s Buffer Data Port
567	* register
568	*/
569	static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned size)
570	{
571	unsigned i;
572
573	/* Check that there is free space left in a buffer */
574	if (!(s->prnsts & SDHC_SPACE_AVAILABLE)) {
575	trace_sdhci_error("Can't write to data buffer: buffer full");
576	return;
577	}
578
579	for (i = 0; i < size; i++) {
580	assert(s->data_count < s->buf_maxsz);
581	s->fifo_buffer[s->data_count] = value & 0xFF;
582	s->data_count++;
583	value >>= 8;
584	if (s->data_count >= (s->blksize & BLOCK_SIZE_MASK)) {
585	trace_sdhci_write_dataport(s->data_count);
586	s->data_count = 0;
587	s->prnsts &= ~SDHC_SPACE_AVAILABLE;
588	if (s->prnsts & SDHC_DOING_WRITE) {
589	sdhci_write_block_to_card(s);
590	}
591	}
592	}
593	}
594
595	/*
596	* Single DMA data transfer
597	*/
598
599	/* Multi block SDMA transfer */
600	static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s)
601	{
602	bool page_aligned = false;
603	unsigned int begin;
604	const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK;
605	uint32_t boundary_chk = 1 << (((s->blksize & ~BLOCK_SIZE_MASK) >> 12) + 12);
606	uint32_t boundary_count = boundary_chk - (s->sdmasysad % boundary_chk);
607
608	if (!(s->trnmod & SDHC_TRNS_BLK_CNT_EN) \|\| !s->blkcnt) {
609	qemu_log_mask(LOG_UNIMP, "infinite transfer is not supported\n");
610	return;
611	}
612
613	/*
614	* XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for
615	* possible stop at page boundary if initial address is not page aligned,
616	* allow them to work properly
617	*/
618	if ((s->sdmasysad % boundary_chk) == 0) {
619	page_aligned = true;
620	}
621
622	s->prnsts \|= SDHC_DATA_INHIBIT \| SDHC_DAT_LINE_ACTIVE;
623	if (s->trnmod & SDHC_TRNS_READ) {
624	s->prnsts \|= SDHC_DOING_READ;
625	while (s->blkcnt) {
626	if (s->data_count == 0) {
627	sdbus_read_data(&s->sdbus, s->fifo_buffer, block_size);
628	}
629	begin = s->data_count;
630	if (((boundary_count + begin) < block_size) && page_aligned) {
631	s->data_count = boundary_count + begin;
632	boundary_count = 0;
633	} else {
634	s->data_count = block_size;
635	boundary_count -= block_size - begin;
636	if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
637	s->blkcnt--;
638	}
639	}
640	dma_memory_write(s->dma_as, s->sdmasysad, &s->fifo_buffer[begin],
641	s->data_count - begin, MEMTXATTRS_UNSPECIFIED);
642	s->sdmasysad += s->data_count - begin;
643	if (s->data_count == block_size) {
644	s->data_count = 0;
645	}
646	if (page_aligned && boundary_count == 0) {
647	break;
648	}
649	}
650	} else {
651	s->prnsts \|= SDHC_DOING_WRITE;
652	while (s->blkcnt) {
653	begin = s->data_count;
654	if (((boundary_count + begin) < block_size) && page_aligned) {
655	s->data_count = boundary_count + begin;
656	boundary_count = 0;
657	} else {
658	s->data_count = block_size;
659	boundary_count -= block_size - begin;
660	}
661	dma_memory_read(s->dma_as, s->sdmasysad, &s->fifo_buffer[begin],
662	s->data_count - begin, MEMTXATTRS_UNSPECIFIED);
663	s->sdmasysad += s->data_count - begin;
664	if (s->data_count == block_size) {
665	sdbus_write_data(&s->sdbus, s->fifo_buffer, block_size);
666	s->data_count = 0;
667	if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
668	s->blkcnt--;
669	}
670	}
671	if (page_aligned && boundary_count == 0) {
672	break;
673	}
674	}
675	}
676
677	if (s->norintstsen & SDHC_NISEN_DMA) {
678	s->norintsts \|= SDHC_NIS_DMA;
679	}
680
681	if (s->blkcnt == 0) {
682	sdhci_end_transfer(s);
683	} else {
684	sdhci_update_irq(s);
685	}
686	}
687
688	/* single block SDMA transfer */
689	static void sdhci_sdma_transfer_single_block(SDHCIState *s)
690	{
691	uint32_t datacnt = s->blksize & BLOCK_SIZE_MASK;
692
693	if (s->trnmod & SDHC_TRNS_READ) {
694	sdbus_read_data(&s->sdbus, s->fifo_buffer, datacnt);
695	dma_memory_write(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt,
696	MEMTXATTRS_UNSPECIFIED);
697	} else {
698	dma_memory_read(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt,
699	MEMTXATTRS_UNSPECIFIED);
700	sdbus_write_data(&s->sdbus, s->fifo_buffer, datacnt);
701	}
702	s->blkcnt--;
703
704	if (s->norintstsen & SDHC_NISEN_DMA) {
705	s->norintsts \|= SDHC_NIS_DMA;
706	}
707
708	sdhci_end_transfer(s);
709	}
710
711	static void sdhci_sdma_transfer(SDHCIState *s)
712	{
713	if ((s->blkcnt == 1) \|\| !(s->trnmod & SDHC_TRNS_MULTI)) {
714	sdhci_sdma_transfer_single_block(s);
715	} else {
716	sdhci_sdma_transfer_multi_blocks(s);
717	}
718	}
719
720	typedef struct ADMADescr {
721	hwaddr addr;
722	uint16_t length;
723	uint8_t attr;
724	uint8_t incr;
725	} ADMADescr;
726
727	static void get_adma_description(SDHCIState s, ADMADescr dscr)
728	{
729	uint32_t adma1 = 0;
730	uint64_t adma2 = 0;
731	hwaddr entry_addr = (hwaddr)s->admasysaddr;
732	switch (SDHC_DMA_TYPE(s->hostctl1)) {
733	case SDHC_CTRL_ADMA2_32:
734	dma_memory_read(s->dma_as, entry_addr, &adma2, sizeof(adma2),
735	MEMTXATTRS_UNSPECIFIED);
736	adma2 = le64_to_cpu(adma2);
737	/*
738	* The spec does not specify endianness of descriptor table.
739	* We currently assume that it is LE.
740	*/
741	dscr->addr = (hwaddr)extract64(adma2, 32, 32) & ~0x3ull;
742	dscr->length = (uint16_t)extract64(adma2, 16, 16);
743	dscr->attr = (uint8_t)extract64(adma2, 0, 7);
744	dscr->incr = 8;
745	break;
746	case SDHC_CTRL_ADMA1_32:
747	dma_memory_read(s->dma_as, entry_addr, &adma1, sizeof(adma1),
748	MEMTXATTRS_UNSPECIFIED);
749	adma1 = le32_to_cpu(adma1);
750	dscr->addr = (hwaddr)(adma1 & 0xFFFFF000);
751	dscr->attr = (uint8_t)extract32(adma1, 0, 7);
752	dscr->incr = 4;
753	if ((dscr->attr & SDHC_ADMA_ATTR_ACT_MASK) == SDHC_ADMA_ATTR_SET_LEN) {
754	dscr->length = (uint16_t)extract32(adma1, 12, 16);
755	} else {
756	dscr->length = 4 * KiB;
757	}
758	break;
759	case SDHC_CTRL_ADMA2_64:
760	dma_memory_read(s->dma_as, entry_addr, &dscr->attr, 1,
761	MEMTXATTRS_UNSPECIFIED);
762	dma_memory_read(s->dma_as, entry_addr + 2, &dscr->length, 2,
763	MEMTXATTRS_UNSPECIFIED);
764	dscr->length = le16_to_cpu(dscr->length);
765	dma_memory_read(s->dma_as, entry_addr + 4, &dscr->addr, 8,
766	MEMTXATTRS_UNSPECIFIED);
767	dscr->addr = le64_to_cpu(dscr->addr);
768	dscr->attr &= (uint8_t) ~0xC0;
769	dscr->incr = 12;
770	break;
771	}
772	}
773
774	/* Advanced DMA data transfer */
775
776	static void sdhci_do_adma(SDHCIState *s)
777	{
778	unsigned int begin, length;
779	const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK;
780	const MemTxAttrs attrs = { .memory = true };
781	ADMADescr dscr = {};
782	MemTxResult res = MEMTX_ERROR;
783	int i;
784
785	if (s->trnmod & SDHC_TRNS_BLK_CNT_EN && !s->blkcnt) {
786	/* Stop Multiple Transfer */
787	sdhci_end_transfer(s);
788	return;
789	}
790
791	for (i = 0; i < SDHC_ADMA_DESCS_PER_DELAY; ++i) {
792	s->admaerr &= ~SDHC_ADMAERR_LENGTH_MISMATCH;
793
794	get_adma_description(s, &dscr);
795	trace_sdhci_adma_loop(dscr.addr, dscr.length, dscr.attr);
796
797	if ((dscr.attr & SDHC_ADMA_ATTR_VALID) == 0) {
798	/* Indicate that error occurred in ST_FDS state */
799	s->admaerr &= ~SDHC_ADMAERR_STATE_MASK;
800	s->admaerr \|= SDHC_ADMAERR_STATE_ST_FDS;
801
802	/* Generate ADMA error interrupt */
803	if (s->errintstsen & SDHC_EISEN_ADMAERR) {
804	s->errintsts \|= SDHC_EIS_ADMAERR;
805	s->norintsts \|= SDHC_NIS_ERR;
806	}
807
808	sdhci_update_irq(s);
809	return;
810	}
811
812	length = dscr.length ? dscr.length : 64 * KiB;
813
814	switch (dscr.attr & SDHC_ADMA_ATTR_ACT_MASK) {
815	case SDHC_ADMA_ATTR_ACT_TRAN: /* data transfer */
816	s->prnsts \|= SDHC_DATA_INHIBIT \| SDHC_DAT_LINE_ACTIVE;
817	if (s->trnmod & SDHC_TRNS_READ) {
818	s->prnsts \|= SDHC_DOING_READ;
819	while (length) {
820	if (s->data_count == 0) {
821	sdbus_read_data(&s->sdbus, s->fifo_buffer, block_size);
822	}
823	begin = s->data_count;
824	if ((length + begin) < block_size) {
825	s->data_count = length + begin;
826	length = 0;
827	} else {
828	s->data_count = block_size;
829	length -= block_size - begin;
830	}
831	res = dma_memory_write(s->dma_as, dscr.addr,
832	&s->fifo_buffer[begin],
833	s->data_count - begin,
834	attrs);
835	if (res != MEMTX_OK) {
836	break;
837	}
838	dscr.addr += s->data_count - begin;
839	if (s->data_count == block_size) {
840	s->data_count = 0;
841	if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
842	s->blkcnt--;
843	if (s->blkcnt == 0) {
844	break;
845	}
846	}
847	}
848	}
849	} else {
850	s->prnsts \|= SDHC_DOING_WRITE;
851	while (length) {
852	begin = s->data_count;
853	if ((length + begin) < block_size) {
854	s->data_count = length + begin;
855	length = 0;
856	} else {
857	s->data_count = block_size;
858	length -= block_size - begin;
859	}
860	res = dma_memory_read(s->dma_as, dscr.addr,
861	&s->fifo_buffer[begin],
862	s->data_count - begin,
863	attrs);
864	if (res != MEMTX_OK) {
865	break;
866	}
867	dscr.addr += s->data_count - begin;
868	if (s->data_count == block_size) {
869	sdbus_write_data(&s->sdbus, s->fifo_buffer, block_size);
870	s->data_count = 0;
871	if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) {
872	s->blkcnt--;
873	if (s->blkcnt == 0) {
874	break;
875	}
876	}
877	}
878	}
879	}
880	if (res != MEMTX_OK) {
881	s->data_count = 0;
882	if (s->errintstsen & SDHC_EISEN_ADMAERR) {
883	trace_sdhci_error("Set ADMA error flag");
884	s->errintsts \|= SDHC_EIS_ADMAERR;
885	s->norintsts \|= SDHC_NIS_ERR;
886	}
887	sdhci_update_irq(s);
888	} else {
889	s->admasysaddr += dscr.incr;
890	}
891	break;
892	case SDHC_ADMA_ATTR_ACT_LINK: /* link to next descriptor table */
893	s->admasysaddr = dscr.addr;
894	trace_sdhci_adma("link", s->admasysaddr);
895	break;
896	default:
897	s->admasysaddr += dscr.incr;
898	break;
899	}
900
901	if (dscr.attr & SDHC_ADMA_ATTR_INT) {
902	trace_sdhci_adma("interrupt", s->admasysaddr);
903	if (s->norintstsen & SDHC_NISEN_DMA) {
904	s->norintsts \|= SDHC_NIS_DMA;
905	}
906
907	if (sdhci_update_irq(s) && !(dscr.attr & SDHC_ADMA_ATTR_END)) {
908	/* IRQ delivered, reschedule current transfer */
909	break;
910	}
911	}
912
913	/* ADMA transfer terminates if blkcnt == 0 or by END attribute */
914	if (((s->trnmod & SDHC_TRNS_BLK_CNT_EN) &&
915	(s->blkcnt == 0)) \|\| (dscr.attr & SDHC_ADMA_ATTR_END)) {
916	trace_sdhci_adma_transfer_completed();
917	if (length \|\| ((dscr.attr & SDHC_ADMA_ATTR_END) &&
918	(s->trnmod & SDHC_TRNS_BLK_CNT_EN) &&
919	s->blkcnt != 0)) {
920	trace_sdhci_error("SD/MMC host ADMA length mismatch");
921	s->admaerr \|= SDHC_ADMAERR_LENGTH_MISMATCH \|
922	SDHC_ADMAERR_STATE_ST_TFR;
923	if (s->errintstsen & SDHC_EISEN_ADMAERR) {
924	trace_sdhci_error("Set ADMA error flag");
925	s->errintsts \|= SDHC_EIS_ADMAERR;
926	s->norintsts \|= SDHC_NIS_ERR;
927	}
928
929	sdhci_update_irq(s);
930	}
931	sdhci_end_transfer(s);
932	return;
933	}
934
935	}
936
937	/* we have unfinished business - reschedule to continue ADMA */
938	timer_mod(s->transfer_timer,
939	qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_TRANSFER_DELAY);
940	}
941
942	/* Perform data transfer according to controller configuration */
943
944	static void sdhci_data_transfer(void *opaque)
945	{
946	SDHCIState s = (SDHCIState )opaque;
947
948	if (s->trnmod & SDHC_TRNS_DMA) {
949	switch (SDHC_DMA_TYPE(s->hostctl1)) {
950	case SDHC_CTRL_SDMA:
951	sdhci_sdma_transfer(s);
952	break;
953	case SDHC_CTRL_ADMA1_32:
954	if (!(s->capareg & R_SDHC_CAPAB_ADMA1_MASK)) {
955	trace_sdhci_error("ADMA1 not supported");
956	break;
957	}
958
959	sdhci_do_adma(s);
960	break;
961	case SDHC_CTRL_ADMA2_32:
962	if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK)) {
963	trace_sdhci_error("ADMA2 not supported");
964	break;
965	}
966
967	sdhci_do_adma(s);
968	break;
969	case SDHC_CTRL_ADMA2_64:
970	if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK) \|\|
971	!(s->capareg & R_SDHC_CAPAB_BUS64BIT_MASK)) {
972	trace_sdhci_error("64 bit ADMA not supported");
973	break;
974	}
975
976	sdhci_do_adma(s);
977	break;
978	default:
979	trace_sdhci_error("Unsupported DMA type");
980	break;
981	}
982	} else {
983	if ((s->trnmod & SDHC_TRNS_READ) && sdbus_data_ready(&s->sdbus)) {
984	s->prnsts \|= SDHC_DOING_READ \| SDHC_DATA_INHIBIT \|
985	SDHC_DAT_LINE_ACTIVE;
986	sdhci_read_block_from_card(s);
987	} else {
988	s->prnsts \|= SDHC_DOING_WRITE \| SDHC_DAT_LINE_ACTIVE \|
989	SDHC_SPACE_AVAILABLE \| SDHC_DATA_INHIBIT;
990	sdhci_write_block_to_card(s);
991	}
992	}
993	}
994
995	static bool sdhci_can_issue_command(SDHCIState *s)
996	{
997	if (!SDHC_CLOCK_IS_ON(s->clkcon) \|\|
998	(((s->prnsts & SDHC_DATA_INHIBIT) \|\| s->stopped_state) &&
999	((s->cmdreg & SDHC_CMD_DATA_PRESENT) \|\|
1000	((s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY &&
1001	!(SDHC_COMMAND_TYPE(s->cmdreg) == SDHC_CMD_ABORT))))) {
1002	return false;
1003	}
1004
1005	return true;
1006	}
1007
1008	/*
1009	* The Buffer Data Port register must be accessed in sequential and
1010	* continuous manner
1011	*/
1012	static inline bool
1013	sdhci_buff_access_is_sequential(SDHCIState *s, unsigned byte_num)
1014	{
1015	if ((s->data_count & 0x3) != byte_num) {
1016	qemu_log_mask(LOG_GUEST_ERROR,
1017	"SDHCI: Non-sequential access to Buffer Data Port"
1018	" register is prohibited\n");
1019	return false;
1020	}
1021	return true;
1022	}
1023
1024	static void sdhci_resume_pending_transfer(SDHCIState *s)
1025	{
1026	timer_del(s->transfer_timer);
1027	sdhci_data_transfer(s);
1028	}
1029
1030	static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size)
1031	{
1032	SDHCIState s = (SDHCIState )opaque;
1033	uint32_t ret = 0;
1034
1035	if (timer_pending(s->transfer_timer)) {
1036	sdhci_resume_pending_transfer(s);
1037	}
1038
1039	switch (offset & ~0x3) {
1040	case SDHC_SYSAD:
1041	ret = s->sdmasysad;
1042	break;
1043	case SDHC_BLKSIZE:
1044	ret = s->blksize \| (s->blkcnt << 16);
1045	break;
1046	case SDHC_ARGUMENT:
1047	ret = s->argument;
1048	break;
1049	case SDHC_TRNMOD:
1050	ret = s->trnmod \| (s->cmdreg << 16);
1051	break;
1052	case SDHC_RSPREG0 ... SDHC_RSPREG3:
1053	ret = s->rspreg[((offset & ~0x3) - SDHC_RSPREG0) >> 2];
1054	break;
1055	case SDHC_BDATA:
1056	if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) {
1057	ret = sdhci_read_dataport(s, size);
1058	trace_sdhci_access("rd", size << 3, offset, "->", ret, ret);
1059	return ret;
1060	}
1061	break;
1062	case SDHC_PRNSTS:
1063	ret = s->prnsts;
1064	ret = FIELD_DP32(ret, SDHC_PRNSTS, DAT_LVL,
1065	sdbus_get_dat_lines(&s->sdbus));
1066	ret = FIELD_DP32(ret, SDHC_PRNSTS, CMD_LVL,
1067	sdbus_get_cmd_line(&s->sdbus));
1068	break;
1069	case SDHC_HOSTCTL:
1070	ret = s->hostctl1 \| (s->pwrcon << 8) \| (s->blkgap << 16) \|
1071	(s->wakcon << 24);
1072	break;
1073	case SDHC_CLKCON:
1074	ret = s->clkcon \| (s->timeoutcon << 16);
1075	break;
1076	case SDHC_NORINTSTS:
1077	ret = s->norintsts \| (s->errintsts << 16);
1078	break;
1079	case SDHC_NORINTSTSEN:
1080	ret = s->norintstsen \| (s->errintstsen << 16);
1081	break;
1082	case SDHC_NORINTSIGEN:
1083	ret = s->norintsigen \| (s->errintsigen << 16);
1084	break;
1085	case SDHC_ACMD12ERRSTS:
1086	ret = s->acmd12errsts \| (s->hostctl2 << 16);
1087	break;
1088	case SDHC_CAPAB:
1089	ret = (uint32_t)s->capareg;
1090	break;
1091	case SDHC_CAPAB + 4:
1092	ret = (uint32_t)(s->capareg >> 32);
1093	break;
1094	case SDHC_MAXCURR:
1095	ret = (uint32_t)s->maxcurr;
1096	break;
1097	case SDHC_MAXCURR + 4:
1098	ret = (uint32_t)(s->maxcurr >> 32);
1099	break;
1100	case SDHC_ADMAERR:
1101	ret = s->admaerr;
1102	break;
1103	case SDHC_ADMASYSADDR:
1104	ret = (uint32_t)s->admasysaddr;
1105	break;
1106	case SDHC_ADMASYSADDR + 4:
1107	ret = (uint32_t)(s->admasysaddr >> 32);
1108	break;
1109	case SDHC_SLOT_INT_STATUS:
1110	ret = (s->version << 16) \| sdhci_slotint(s);
1111	break;
1112	default:
1113	qemu_log_mask(LOG_UNIMP, "SDHC rd_%ub @0x%02" HWADDR_PRIx " "
1114	"not implemented\n", size, offset);
1115	break;
1116	}
1117
1118	ret >>= (offset & 0x3) * 8;
1119	ret &= (1ULL << (size * 8)) - 1;
1120	trace_sdhci_access("rd", size << 3, offset, "->", ret, ret);
1121	return ret;
1122	}
1123
1124	static inline void sdhci_blkgap_write(SDHCIState *s, uint8_t value)
1125	{
1126	if ((value & SDHC_STOP_AT_GAP_REQ) && (s->blkgap & SDHC_STOP_AT_GAP_REQ)) {
1127	return;
1128	}
1129	s->blkgap = value & SDHC_STOP_AT_GAP_REQ;
1130
1131	if ((value & SDHC_CONTINUE_REQ) && s->stopped_state &&
1132	(s->blkgap & SDHC_STOP_AT_GAP_REQ) == 0) {
1133	if (s->stopped_state == sdhc_gap_read) {
1134	s->prnsts \|= SDHC_DAT_LINE_ACTIVE \| SDHC_DOING_READ;
1135	sdhci_read_block_from_card(s);
1136	} else {
1137	s->prnsts \|= SDHC_DAT_LINE_ACTIVE \| SDHC_DOING_WRITE;
1138	sdhci_write_block_to_card(s);
1139	}
1140	s->stopped_state = sdhc_not_stopped;
1141	} else if (!s->stopped_state && (value & SDHC_STOP_AT_GAP_REQ)) {
1142	if (s->prnsts & SDHC_DOING_READ) {
1143	s->stopped_state = sdhc_gap_read;
1144	} else if (s->prnsts & SDHC_DOING_WRITE) {
1145	s->stopped_state = sdhc_gap_write;
1146	}
1147	}
1148	}
1149
1150	static inline void sdhci_reset_write(SDHCIState *s, uint8_t value)
1151	{
1152	switch (value) {
1153	case SDHC_RESET_ALL:
1154	sdhci_reset(s);
1155	break;
1156	case SDHC_RESET_CMD:
1157	s->prnsts &= ~SDHC_CMD_INHIBIT;
1158	s->norintsts &= ~SDHC_NIS_CMDCMP;
1159	break;
1160	case SDHC_RESET_DATA:
1161	s->data_count = 0;
1162	s->prnsts &= ~(SDHC_SPACE_AVAILABLE \| SDHC_DATA_AVAILABLE \|
1163	SDHC_DOING_READ \| SDHC_DOING_WRITE \|
1164	SDHC_DATA_INHIBIT \| SDHC_DAT_LINE_ACTIVE);
1165	s->blkgap &= ~(SDHC_STOP_AT_GAP_REQ \| SDHC_CONTINUE_REQ);
1166	s->stopped_state = sdhc_not_stopped;
1167	s->norintsts &= ~(SDHC_NIS_WBUFRDY \| SDHC_NIS_RBUFRDY \|
1168	SDHC_NIS_DMA \| SDHC_NIS_TRSCMP \| SDHC_NIS_BLKGAP);
1169	break;
1170	}
1171	}
1172
1173	static void
1174	sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
1175	{
1176	SDHCIState s = (SDHCIState )opaque;
1177	unsigned shift = 8 * (offset & 0x3);
1178	uint32_t mask = ~(((1ULL << (size * 8)) - 1) << shift);
1179	uint32_t value = val;
1180	value <<= shift;
1181
1182	if (timer_pending(s->transfer_timer)) {
1183	sdhci_resume_pending_transfer(s);
1184	}
1185
1186	switch (offset & ~0x3) {
1187	case SDHC_SYSAD:
1188	if (!TRANSFERRING_DATA(s->prnsts)) {
1189	s->sdmasysad = (s->sdmasysad & mask) \| value;
1190	MASKED_WRITE(s->sdmasysad, mask, value);
1191	/* Writing to last byte of sdmasysad might trigger transfer */
1192	if (!(mask & 0xFF000000) && s->blkcnt &&
1193	(s->blksize & BLOCK_SIZE_MASK) &&
1194	SDHC_DMA_TYPE(s->hostctl1) == SDHC_CTRL_SDMA) {
1195	sdhci_sdma_transfer(s);
1196	}
1197	}
1198	break;
1199	case SDHC_BLKSIZE:
1200	if (!TRANSFERRING_DATA(s->prnsts)) {
1201	uint16_t blksize = s->blksize;
1202
1203	/*
1204	* [14:12] SDMA Buffer Boundary
1205	* [11:00] Transfer Block Size
1206	*/
1207	MASKED_WRITE(s->blksize, mask, extract32(value, 0, 15));
1208	MASKED_WRITE(s->blkcnt, mask >> 16, value >> 16);
1209
1210	/* Limit block size to the maximum buffer size */
1211	if (extract32(s->blksize, 0, 12) > s->buf_maxsz) {
1212	qemu_log_mask(LOG_GUEST_ERROR, "%s: Size 0x%x is larger than "
1213	"the maximum buffer 0x%x\n", __func__, s->blksize,
1214	s->buf_maxsz);
1215
1216	s->blksize = deposit32(s->blksize, 0, 12, s->buf_maxsz);
1217	}
1218
1219	/*
1220	* If the block size is programmed to a different value from
1221	* the previous one, reset the data pointer of s->fifo_buffer[]
1222	* so that s->fifo_buffer[] can be filled in using the new block
1223	* size in the next transfer.
1224	*/
1225	if (blksize != s->blksize) {
1226	s->data_count = 0;
1227	}
1228	}
1229
1230	break;
1231	case SDHC_ARGUMENT:
1232	MASKED_WRITE(s->argument, mask, value);
1233	break;
1234	case SDHC_TRNMOD:
1235	/*
1236	* DMA can be enabled only if it is supported as indicated by
1237	* capabilities register
1238	*/
1239	if (!(s->capareg & R_SDHC_CAPAB_SDMA_MASK)) {
1240	value &= ~SDHC_TRNS_DMA;
1241	}
1242
1243	/* TRNMOD writes are inhibited while Command Inhibit (DAT) is true */
1244	if (s->prnsts & SDHC_DATA_INHIBIT) {
1245	mask \|= 0xffff;
1246	}
1247
1248	MASKED_WRITE(s->trnmod, mask, value & SDHC_TRNMOD_MASK);
1249	MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16);
1250
1251	/* Writing to the upper byte of CMDREG triggers SD command generation */
1252	if ((mask & 0xFF000000) \|\| !sdhci_can_issue_command(s)) {
1253	break;
1254	}
1255
1256	sdhci_send_command(s);
1257	break;
1258	case SDHC_BDATA:
1259	if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) {
1260	sdhci_write_dataport(s, value >> shift, size);
1261	}
1262	break;
1263	case SDHC_HOSTCTL:
1264	if (!(mask & 0xFF0000)) {
1265	sdhci_blkgap_write(s, value >> 16);
1266	}
1267	MASKED_WRITE(s->hostctl1, mask, value);
1268	MASKED_WRITE(s->pwrcon, mask >> 8, value >> 8);
1269	MASKED_WRITE(s->wakcon, mask >> 24, value >> 24);
1270	if (!(s->prnsts & SDHC_CARD_PRESENT) \|\| ((s->pwrcon >> 1) & 0x7) < 5 \|\|
1271	!(s->capareg & (1 << (31 - ((s->pwrcon >> 1) & 0x7))))) {
1272	s->pwrcon &= ~SDHC_POWER_ON;
1273	}
1274	break;
1275	case SDHC_CLKCON:
1276	if (!(mask & 0xFF000000)) {
1277	sdhci_reset_write(s, value >> 24);
1278	}
1279	MASKED_WRITE(s->clkcon, mask, value);
1280	MASKED_WRITE(s->timeoutcon, mask >> 16, value >> 16);
1281	if (s->clkcon & SDHC_CLOCK_INT_EN) {
1282	s->clkcon \|= SDHC_CLOCK_INT_STABLE;
1283	} else {
1284	s->clkcon &= ~SDHC_CLOCK_INT_STABLE;
1285	}
1286	break;
1287	case SDHC_NORINTSTS:
1288	if (s->norintstsen & SDHC_NISEN_CARDINT) {
1289	value &= ~SDHC_NIS_CARDINT;
1290	}
1291	s->norintsts &= mask \| ~value;
1292	s->errintsts &= (mask >> 16) \| ~(value >> 16);
1293	if (s->errintsts) {
1294	s->norintsts \|= SDHC_NIS_ERR;
1295	} else {
1296	s->norintsts &= ~SDHC_NIS_ERR;
1297	}
1298	sdhci_update_irq(s);
1299	break;
1300	case SDHC_NORINTSTSEN:
1301	MASKED_WRITE(s->norintstsen, mask, value);
1302	MASKED_WRITE(s->errintstsen, mask >> 16, value >> 16);
1303	s->norintsts &= s->norintstsen;
1304	s->errintsts &= s->errintstsen;
1305	if (s->errintsts) {
1306	s->norintsts \|= SDHC_NIS_ERR;
1307	} else {
1308	s->norintsts &= ~SDHC_NIS_ERR;
1309	}
1310	/*
1311	* Quirk for Raspberry Pi: pending card insert interrupt
1312	* appears when first enabled after power on
1313	*/
1314	if ((s->norintstsen & SDHC_NISEN_INSERT) && s->pending_insert_state) {
1315	assert(s->pending_insert_quirk);
1316	s->norintsts \|= SDHC_NIS_INSERT;
1317	s->pending_insert_state = false;
1318	}
1319	sdhci_update_irq(s);
1320	break;
1321	case SDHC_NORINTSIGEN:
1322	MASKED_WRITE(s->norintsigen, mask, value);
1323	MASKED_WRITE(s->errintsigen, mask >> 16, value >> 16);
1324	sdhci_update_irq(s);
1325	break;
1326	case SDHC_ADMAERR:
1327	MASKED_WRITE(s->admaerr, mask, value);
1328	break;
1329	case SDHC_ADMASYSADDR:
1330	s->admasysaddr = (s->admasysaddr & (0xFFFFFFFF00000000ULL \|
1331	(uint64_t)mask)) \| (uint64_t)value;
1332	break;
1333	case SDHC_ADMASYSADDR + 4:
1334	s->admasysaddr = (s->admasysaddr & (0x00000000FFFFFFFFULL \|
1335	((uint64_t)mask << 32))) \| ((uint64_t)value << 32);
1336	break;
1337	case SDHC_FEAER:
1338	s->acmd12errsts \|= value;
1339	s->errintsts \|= (value >> 16) & s->errintstsen;
1340	if (s->acmd12errsts) {
1341	s->errintsts \|= SDHC_EIS_CMD12ERR;
1342	}
1343	if (s->errintsts) {
1344	s->norintsts \|= SDHC_NIS_ERR;
1345	}
1346	sdhci_update_irq(s);
1347	break;
1348	case SDHC_ACMD12ERRSTS:
1349	MASKED_WRITE(s->acmd12errsts, mask, value & UINT16_MAX);
1350	if (s->uhs_mode >= UHS_I) {
1351	MASKED_WRITE(s->hostctl2, mask >> 16, value >> 16);
1352
1353	if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, V18_ENA)) {
1354	sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_1_8V);
1355	} else {
1356	sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_3_3V);
1357	}
1358	}
1359	break;
1360
1361	case SDHC_CAPAB:
1362	case SDHC_CAPAB + 4:
1363	case SDHC_MAXCURR:
1364	case SDHC_MAXCURR + 4:
1365	qemu_log_mask(LOG_GUEST_ERROR, "SDHC wr_%ub @0x%02" HWADDR_PRIx
1366	" <- 0x%08x read-only\n", size, offset, value >> shift);
1367	break;
1368
1369	default:
1370	qemu_log_mask(LOG_UNIMP, "SDHC wr_%ub @0x%02" HWADDR_PRIx " <- 0x%08x "
1371	"not implemented\n", size, offset, value >> shift);
1372	break;
1373	}
1374	trace_sdhci_access("wr", size << 3, offset, "<-",
1375	value >> shift, value >> shift);
1376	}
1377
1378	static const MemoryRegionOps sdhci_mmio_ops = {
1379	.read = sdhci_read,
1380	.write = sdhci_write,
1381	.valid = {
1382	.min_access_size = 1,
1383	.max_access_size = 4,
1384	.unaligned = false
1385	},
1386	.endianness = DEVICE_LITTLE_ENDIAN,
1387	};
1388
1389	static void sdhci_init_readonly_registers(SDHCIState s, Error *errp)
1390	{
1391	ERRP_GUARD();
1392
1393	switch (s->sd_spec_version) {
1394	case 2 ... 3:
1395	break;
1396	default:
1397	error_setg(errp, "Only Spec v2/v3 are supported");
1398	return;
1399	}
1400	s->version = (SDHC_HCVER_VENDOR << 8) \| (s->sd_spec_version - 1);
1401
1402	sdhci_check_capareg(s, errp);
1403	if (*errp) {
1404	return;
1405	}
1406	}
1407
1408	/* --- qdev common --- */
1409
1410	void sdhci_initfn(SDHCIState *s)
1411	{
1412	qbus_init(&s->sdbus, sizeof(s->sdbus), TYPE_SDHCI_BUS, DEVICE(s), "sd-bus");
1413
1414	s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
1415	sdhci_raise_insertion_irq, s);
1416	s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
1417	sdhci_data_transfer, s);
1418
1419	s->io_ops = &sdhci_mmio_ops;
1420	}
1421
1422	void sdhci_uninitfn(SDHCIState *s)
1423	{
1424	timer_free(s->insert_timer);
1425	timer_free(s->transfer_timer);
1426
1427	g_free(s->fifo_buffer);
1428	s->fifo_buffer = NULL;
1429	}
1430
1431	void sdhci_common_realize(SDHCIState s, Error *errp)
1432	{
1433	ERRP_GUARD();
1434
1435	sdhci_init_readonly_registers(s, errp);
1436	if (*errp) {
1437	return;
1438	}
1439
1440	s->buf_maxsz = sdhci_get_fifolen(s);
1441	s->fifo_buffer = g_malloc0(s->buf_maxsz);
1442
1443	memory_region_init_io(&s->iomem, OBJECT(s), s->io_ops, s, "sdhci",
1444	SDHC_REGISTERS_MAP_SIZE);
1445	}
1446
1447	void sdhci_common_unrealize(SDHCIState *s)
1448	{
1449	/*
1450	* This function is expected to be called only once for each class:
1451	* - SysBus: via DeviceClass->unrealize(),
1452	* - PCI: via PCIDeviceClass->exit().
1453	* However to avoid double-free and/or use-after-free we still nullify
1454	* this variable (better safe than sorry!).
1455	*/
1456	g_free(s->fifo_buffer);
1457	s->fifo_buffer = NULL;
1458	}
1459
1460	static bool sdhci_pending_insert_vmstate_needed(void *opaque)
1461	{
1462	SDHCIState *s = opaque;
1463
1464	return s->pending_insert_state;
1465	}
1466
1467	static const VMStateDescription sdhci_pending_insert_vmstate = {
1468	.name = "sdhci/pending-insert",
1469	.version_id = 1,
1470	.minimum_version_id = 1,
1471	.needed = sdhci_pending_insert_vmstate_needed,
1472	.fields = (const VMStateField[]) {
1473	VMSTATE_BOOL(pending_insert_state, SDHCIState),
1474	VMSTATE_END_OF_LIST()
1475	},
1476	};
1477
1478	const VMStateDescription sdhci_vmstate = {
1479	.name = "sdhci",
1480	.version_id = 1,
1481	.minimum_version_id = 1,
1482	.fields = (const VMStateField[]) {
1483	VMSTATE_UINT32(sdmasysad, SDHCIState),
1484	VMSTATE_UINT16(blksize, SDHCIState),
1485	VMSTATE_UINT16(blkcnt, SDHCIState),
1486	VMSTATE_UINT32(argument, SDHCIState),
1487	VMSTATE_UINT16(trnmod, SDHCIState),
1488	VMSTATE_UINT16(cmdreg, SDHCIState),
1489	VMSTATE_UINT32_ARRAY(rspreg, SDHCIState, 4),
1490	VMSTATE_UINT32(prnsts, SDHCIState),
1491	VMSTATE_UINT8(hostctl1, SDHCIState),
1492	VMSTATE_UINT8(pwrcon, SDHCIState),
1493	VMSTATE_UINT8(blkgap, SDHCIState),
1494	VMSTATE_UINT8(wakcon, SDHCIState),
1495	VMSTATE_UINT16(clkcon, SDHCIState),
1496	VMSTATE_UINT8(timeoutcon, SDHCIState),
1497	VMSTATE_UINT8(admaerr, SDHCIState),
1498	VMSTATE_UINT16(norintsts, SDHCIState),
1499	VMSTATE_UINT16(errintsts, SDHCIState),
1500	VMSTATE_UINT16(norintstsen, SDHCIState),
1501	VMSTATE_UINT16(errintstsen, SDHCIState),
1502	VMSTATE_UINT16(norintsigen, SDHCIState),
1503	VMSTATE_UINT16(errintsigen, SDHCIState),
1504	VMSTATE_UINT16(acmd12errsts, SDHCIState),
1505	VMSTATE_UINT16(data_count, SDHCIState),
1506	VMSTATE_UINT64(admasysaddr, SDHCIState),
1507	VMSTATE_UINT8(stopped_state, SDHCIState),
1508	VMSTATE_VBUFFER_UINT32(fifo_buffer, SDHCIState, 1, NULL, buf_maxsz),
1509	VMSTATE_TIMER_PTR(insert_timer, SDHCIState),
1510	VMSTATE_TIMER_PTR(transfer_timer, SDHCIState),
1511	VMSTATE_END_OF_LIST()
1512	},
1513	.subsections = (const VMStateDescription * const []) {
1514	&sdhci_pending_insert_vmstate,
1515	NULL
1516	},
1517	};
1518
1519	void sdhci_common_class_init(ObjectClass klass, const void data)
1520	{
1521	DeviceClass *dc = DEVICE_CLASS(klass);
1522
1523	set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
1524	dc->vmsd = &sdhci_vmstate;
1525	device_class_set_legacy_reset(dc, sdhci_poweron_reset);
1526	}
1527
1528	/* --- qdev SysBus --- */
1529
1530	static const Property sdhci_sysbus_properties[] = {
1531	DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState),
1532	DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk,
1533	false),
1534	DEFINE_PROP_LINK("dma", SDHCIState,
1535	dma_mr, TYPE_MEMORY_REGION, MemoryRegion *),
1536	DEFINE_PROP_BOOL("wp-inverted", SDHCIState,
1537	wp_inverted, false),
1538	};
1539
1540	static void sdhci_sysbus_init(Object *obj)
1541	{
1542	SDHCIState *s = SYSBUS_SDHCI(obj);
1543
1544	sdhci_initfn(s);
1545	}
1546
1547	static void sdhci_sysbus_finalize(Object *obj)
1548	{
1549	SDHCIState *s = SYSBUS_SDHCI(obj);
1550
1551	sdhci_uninitfn(s);
1552	}
1553
1554	static void sdhci_sysbus_realize(DeviceState dev, Error *errp)
1555	{
1556	ERRP_GUARD();
1557	SDHCIState *s = SYSBUS_SDHCI(dev);
1558	SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1559
1560	sdhci_common_realize(s, errp);
1561	if (*errp) {
1562	return;
1563	}
1564
1565	if (s->dma_mr) {
1566	s->dma_as = &s->sysbus_dma_as;
1567	address_space_init(s->dma_as, s->dma_mr, "sdhci-dma");
1568	} else {
1569	/* use system_memory() if property "dma" not set */
1570	s->dma_as = &address_space_memory;
1571	}
1572
1573	sysbus_init_irq(sbd, &s->irq);
1574
1575	sysbus_init_mmio(sbd, &s->iomem);
1576	}
1577
1578	static void sdhci_sysbus_unrealize(DeviceState *dev)
1579	{
1580	SDHCIState *s = SYSBUS_SDHCI(dev);
1581
1582	sdhci_common_unrealize(s);
1583
1584	if (s->dma_mr) {
1585	address_space_destroy(s->dma_as);
1586	}
1587	}
1588
1589	static void sdhci_sysbus_class_init(ObjectClass klass, const void data)
1590	{
1591	DeviceClass *dc = DEVICE_CLASS(klass);
1592
1593	device_class_set_props(dc, sdhci_sysbus_properties);
1594	dc->realize = sdhci_sysbus_realize;
1595	dc->unrealize = sdhci_sysbus_unrealize;
1596
1597	sdhci_common_class_init(klass, data);
1598	}
1599
1600	/* --- qdev bus master --- */
1601
1602	static void sdhci_bus_class_init(ObjectClass klass, const void data)
1603	{
1604	SDBusClass *sbc = SD_BUS_CLASS(klass);
1605
1606	sbc->set_inserted = sdhci_set_inserted;
1607	sbc->set_readonly = sdhci_set_readonly;
1608	}
1609
1610	/* --- qdev i.MX eSDHC --- */
1611
1612	#define ESDHC_MIX_CTRL 0x48
1613
1614	#define ESDHC_VENDOR_SPEC 0xc0
1615	#define ESDHC_FRC_SDCLK_ON (1 << 8)
1616
1617	#define ESDHC_DLL_CTRL 0x60
1618
1619	#define ESDHC_TUNING_CTRL 0xcc
1620	#define ESDHC_TUNE_CTRL_STATUS 0x68
1621	#define ESDHC_WTMK_LVL 0x44
1622
1623	/* Undocumented register used by guests working around erratum ERR004536 */
1624	#define ESDHC_UNDOCUMENTED_REG27 0x6c
1625
1626	#define ESDHC_CTRL_4BITBUS (0x1 << 1)
1627	#define ESDHC_CTRL_8BITBUS (0x2 << 1)
1628
1629	#define ESDHC_PRNSTS_SDSTB (1 << 3)
1630	#define ESDHC_PRNSTS_CLOCK_GATE_OFF BIT(7)
1631
1632	static uint64_t esdhc_read(void *opaque, hwaddr offset, unsigned size)
1633	{
1634	SDHCIState *s = SYSBUS_SDHCI(opaque);
1635	uint32_t ret;
1636	uint16_t hostctl1;
1637
1638	switch (offset) {
1639	default:
1640	return sdhci_read(opaque, offset, size);
1641
1642	case SDHC_HOSTCTL:
1643	/*
1644	* For a detailed explanation on the following bit
1645	* manipulation code see comments in a similar part of
1646	* esdhc_write()
1647	*/
1648	hostctl1 = SDHC_DMA_TYPE(s->hostctl1) << (8 - 3);
1649
1650	if (s->hostctl1 & SDHC_CTRL_8BITBUS) {
1651	hostctl1 \|= ESDHC_CTRL_8BITBUS;
1652	}
1653
1654	if (s->hostctl1 & SDHC_CTRL_4BITBUS) {
1655	hostctl1 \|= ESDHC_CTRL_4BITBUS;
1656	}
1657
1658	ret = hostctl1;
1659	ret \|= (uint32_t)s->blkgap << 16;
1660	ret \|= (uint32_t)s->wakcon << 24;
1661
1662	break;
1663
1664	case SDHC_PRNSTS:
1665	/* Add SDSTB (SD Clock Stable) bit to PRNSTS */
1666	ret = sdhci_read(opaque, offset, size) & ~ESDHC_PRNSTS_SDSTB;
1667	if (s->clkcon & SDHC_CLOCK_INT_STABLE) {
1668	ret \|= ESDHC_PRNSTS_SDSTB;
1669	}
1670	break;
1671
1672	case ESDHC_VENDOR_SPEC:
1673	ret = s->vendor_spec;
1674	break;
1675	case ESDHC_DLL_CTRL:
1676	case ESDHC_TUNE_CTRL_STATUS:
1677	case ESDHC_UNDOCUMENTED_REG27:
1678	case ESDHC_TUNING_CTRL:
1679	case ESDHC_MIX_CTRL:
1680	case ESDHC_WTMK_LVL:
1681	ret = 0;
1682	break;
1683	}
1684
1685	return ret;
1686	}
1687
1688	static void
1689	esdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
1690	{
1691	SDHCIState *s = SYSBUS_SDHCI(opaque);
1692	uint8_t hostctl1;
1693	uint32_t value = (uint32_t)val;
1694
1695	switch (offset) {
1696	case ESDHC_DLL_CTRL:
1697	case ESDHC_TUNE_CTRL_STATUS:
1698	case ESDHC_UNDOCUMENTED_REG27:
1699	case ESDHC_TUNING_CTRL:
1700	case ESDHC_WTMK_LVL:
1701	break;
1702
1703	case ESDHC_VENDOR_SPEC:
1704	s->vendor_spec = value;
1705	if (value & ESDHC_FRC_SDCLK_ON) {
1706	s->prnsts &= ~ESDHC_PRNSTS_CLOCK_GATE_OFF;
1707	} else {
1708	s->prnsts \|= ESDHC_PRNSTS_CLOCK_GATE_OFF;
1709	}
1710	break;
1711
1712	case SDHC_HOSTCTL:
1713	/*
1714	* Here's What ESDHCI has at offset 0x28 (SDHC_HOSTCTL)
1715	*
1716	* 7 6 5 4 3 2 1 0
1717	* \|-----------+--------+--------+-----------+----------+---------\|
1718	* \| Card \| Card \| Endian \| DATA3 \| Data \| Led \|
1719	* \| Detect \| Detect \| Mode \| as Card \| Transfer \| Control \|
1720	* \| Signal \| Test \| \| Detection \| Width \| \|
1721	* \| Selection \| Level \| \| Pin \| \| \|
1722	* \|-----------+--------+--------+-----------+----------+---------\|
1723	*
1724	* and 0x29
1725	*
1726	* 15 10 9 8
1727	* \|----------+------\|
1728	* \| Reserved \| DMA \|
1729	* \| \| Sel. \|
1730	* \| \| \|
1731	* \|----------+------\|
1732	*
1733	* and here's what SDCHI spec expects those offsets to be:
1734	*
1735	* 0x28 (Host Control Register)
1736	*
1737	* 7 6 5 4 3 2 1 0
1738	* \|--------+--------+----------+------+--------+----------+---------\|
1739	* \| Card \| Card \| Extended \| DMA \| High \| Data \| LED \|
1740	* \| Detect \| Detect \| Data \| Sel. \| Speed \| Transfer \| Control \|
1741	* \| Signal \| Test \| Transfer \| \| Enable \| Width \| \|
1742	* \| Sel. \| Level \| Width \| \| \| \| \|
1743	* \|--------+--------+----------+------+--------+----------+---------\|
1744	*
1745	* and 0x29 (Power Control Register)
1746	*
1747	* \|----------------------------------\|
1748	* \| Power Control Register \|
1749	* \| \|
1750	* \| Description omitted, \|
1751	* \| since it has no analog in ESDHCI \|
1752	* \| \|
1753	* \|----------------------------------\|
1754	*
1755	* Since offsets 0x2A and 0x2B should be compatible between
1756	* both IP specs we only need to reconcile least 16-bit of the
1757	* word we've been given.
1758	*/
1759
1760	/*
1761	* First, save bits 7 6 and 0 since they are identical
1762	*/
1763	hostctl1 = value & (SDHC_CTRL_LED \|
1764	SDHC_CTRL_CDTEST_INS \|
1765	SDHC_CTRL_CDTEST_EN);
1766	/*
1767	* Second, split "Data Transfer Width" from bits 2 and 1 in to
1768	* bits 5 and 1
1769	*/
1770	if (value & ESDHC_CTRL_8BITBUS) {
1771	hostctl1 \|= SDHC_CTRL_8BITBUS;
1772	}
1773
1774	if (value & ESDHC_CTRL_4BITBUS) {
1775	hostctl1 \|= ESDHC_CTRL_4BITBUS;
1776	}
1777
1778	/*
1779	* Third, move DMA select from bits 9 and 8 to bits 4 and 3
1780	*/
1781	hostctl1 \|= SDHC_DMA_TYPE(value >> (8 - 3));
1782
1783	/*
1784	* Now place the corrected value into low 16-bit of the value
1785	* we are going to give standard SDHCI write function
1786	*
1787	* NOTE: This transformation should be the inverse of what can
1788	* be found in drivers/mmc/host/sdhci-esdhc-imx.c in Linux
1789	* kernel
1790	*/
1791	value &= ~UINT16_MAX;
1792	value \|= hostctl1;
1793	value \|= (uint16_t)s->pwrcon << 8;
1794
1795	sdhci_write(opaque, offset, value, size);
1796	break;
1797
1798	case SDHC_BLKSIZE:
1799	/*
1800	* ESDHCI does not implement "Host SDMA Buffer Boundary", and
1801	* Linux driver will try to zero this field out which will
1802	* break the rest of SDHCI emulation.
1803	*
1804	* Linux defaults to maximum possible setting (512K boundary)
1805	* and it seems to be the only option that i.MX IP implements,
1806	* so we artificially set it to that value.
1807	*/
1808	val \|= 0x7 << 12;
1809	/* FALLTHROUGH */
1810	default:
1811	sdhci_write(opaque, offset, val, size);
1812	break;
1813	}
1814	}
1815
1816	static const MemoryRegionOps esdhc_mmio_be_ops = {
1817	.read = esdhc_read,
1818	.write = esdhc_write,
1819	.impl = {
1820	.min_access_size = 4,
1821	.max_access_size = 4,
1822	},
1823	.valid = {
1824	.min_access_size = 1,
1825	.max_access_size = 4,
1826	.unaligned = false
1827	},
1828	.endianness = DEVICE_BIG_ENDIAN,
1829	};
1830
1831	static void fsl_esdhc_be_init(Object *obj)
1832	{
1833	SDHCIState *s = SYSBUS_SDHCI(obj);
1834	DeviceState *dev = DEVICE(obj);
1835
1836	s->io_ops = &esdhc_mmio_be_ops;
1837	s->quirks = SDHCI_QUIRK_NO_BUSY_IRQ;
1838	qdev_prop_set_uint8(dev, "sd-spec-version", 2);
1839	}
1840
1841	static const MemoryRegionOps esdhc_mmio_le_ops = {
1842	.read = esdhc_read,
1843	.write = esdhc_write,
1844	.impl = {
1845	.min_access_size = 4,
1846	.max_access_size = 4,
1847	},
1848	.valid = {
1849	.min_access_size = 1,
1850	.max_access_size = 4,
1851	.unaligned = false
1852	},
1853	.endianness = DEVICE_LITTLE_ENDIAN,
1854	};
1855
1856	static void fsl_esdhc_le_init(Object *obj)
1857	{
1858	SDHCIState *s = SYSBUS_SDHCI(obj);
1859	DeviceState *dev = DEVICE(obj);
1860
1861	s->io_ops = &esdhc_mmio_le_ops;
1862	s->quirks = SDHCI_QUIRK_NO_BUSY_IRQ;
1863	qdev_prop_set_uint8(dev, "sd-spec-version", 2);
1864	}
1865
1866	static void
1867	usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
1868	{
1869	SDHCIState *s = SYSBUS_SDHCI(opaque);
1870	uint32_t value = (uint32_t)val;
1871
1872	switch (offset) {
1873	case ESDHC_MIX_CTRL:
1874	/*
1875	* So, when SD/MMC stack in Linux tries to write to "Transfer
1876	* Mode Register", uSDHC i.MX quirk code will translate it
1877	* into a write to ESDHC_MIX_CTRL, so we do the opposite in
1878	* order to get where we started.
1879	*
1880	* Note that Auto CMD23 Enable bit is located in a wrong place
1881	* on i.MX, but since it is not used by QEMU we do not care.
1882	*
1883	* We don't want to call sdhci_write(.., SDHC_TRNMOD, ...)
1884	* here because it will result in a call to
1885	* sdhci_send_command(s) which we don't want.
1886	*
1887	*/
1888	s->trnmod = value & UINT16_MAX;
1889	break;
1890
1891	case SDHC_TRNMOD:
1892	/*
1893	* Similar to above, but this time a write to "Command
1894	* Register" will be translated into a 4-byte write to
1895	* "Transfer Mode register" where lower 16-bit of value would
1896	* be set to zero. So what we do is fill those bits with
1897	* cached value from s->trnmod and let the SDHCI
1898	* infrastructure handle the rest
1899	*/
1900	sdhci_write(opaque, offset, val \| s->trnmod, size);
1901	break;
1902
1903	default:
1904	esdhc_write(opaque, offset, val, size);
1905	break;
1906	}
1907	}
1908
1909	static const MemoryRegionOps usdhc_mmio_ops = {
1910	.read = esdhc_read,
1911	.write = usdhc_write,
1912	.valid = {
1913	.min_access_size = 1,
1914	.max_access_size = 4,
1915	.unaligned = false
1916	},
1917	.endianness = DEVICE_LITTLE_ENDIAN,
1918	};
1919
1920	static void imx_usdhc_init(Object *obj)
1921	{
1922	SDHCIState *s = SYSBUS_SDHCI(obj);
1923	DeviceState *dev = DEVICE(obj);
1924
1925	s->io_ops = &usdhc_mmio_ops;
1926	s->quirks = SDHCI_QUIRK_NO_BUSY_IRQ;
1927	qdev_prop_set_uint8(dev, "sd-spec-version", 3);
1928	}
1929
1930	/* --- qdev Samsung s3c --- */
1931
1932	#define S3C_SDHCI_CONTROL2 0x80
1933	#define S3C_SDHCI_CONTROL3 0x84
1934	#define S3C_SDHCI_CONTROL4 0x8c
1935
1936	static uint64_t sdhci_s3c_read(void *opaque, hwaddr offset, unsigned size)
1937	{
1938	uint64_t ret;
1939
1940	switch (offset) {
1941	case S3C_SDHCI_CONTROL2:
1942	case S3C_SDHCI_CONTROL3:
1943	case S3C_SDHCI_CONTROL4:
1944	/* ignore */
1945	ret = 0;
1946	break;
1947	default:
1948	ret = sdhci_read(opaque, offset, size);
1949	break;
1950	}
1951
1952	return ret;
1953	}
1954
1955	static void sdhci_s3c_write(void *opaque, hwaddr offset, uint64_t val,
1956	unsigned size)
1957	{
1958	switch (offset) {
1959	case S3C_SDHCI_CONTROL2:
1960	case S3C_SDHCI_CONTROL3:
1961	case S3C_SDHCI_CONTROL4:
1962	/* ignore */
1963	break;
1964	default:
1965	sdhci_write(opaque, offset, val, size);
1966	break;
1967	}
1968	}
1969
1970	static const MemoryRegionOps sdhci_s3c_mmio_ops = {
1971	.read = sdhci_s3c_read,
1972	.write = sdhci_s3c_write,
1973	.valid = {
1974	.min_access_size = 1,
1975	.max_access_size = 4,
1976	.unaligned = false
1977	},
1978	.endianness = DEVICE_LITTLE_ENDIAN,
1979	};
1980
1981	static void sdhci_s3c_init(Object *obj)
1982	{
1983	SDHCIState *s = SYSBUS_SDHCI(obj);
1984
1985	s->io_ops = &sdhci_s3c_mmio_ops;
1986	}
1987
1988	static const TypeInfo sdhci_types[] = {
1989	{
1990	.name = TYPE_SDHCI_BUS,
1991	.parent = TYPE_SD_BUS,
1992	.instance_size = sizeof(SDBus),
1993	.class_init = sdhci_bus_class_init,
1994	},
1995	{
1996	.name = TYPE_SYSBUS_SDHCI,
1997	.parent = TYPE_SYS_BUS_DEVICE,
1998	.instance_size = sizeof(SDHCIState),
1999	.instance_init = sdhci_sysbus_init,
2000	.instance_finalize = sdhci_sysbus_finalize,
2001	.class_init = sdhci_sysbus_class_init,
2002	},
2003	{
2004	.name = TYPE_FSL_ESDHC_BE,
2005	.parent = TYPE_SYSBUS_SDHCI,
2006	.instance_init = fsl_esdhc_be_init,
2007	},
2008	{
2009	.name = TYPE_FSL_ESDHC_LE,
2010	.parent = TYPE_SYSBUS_SDHCI,
2011	.instance_init = fsl_esdhc_le_init,
2012	},
2013	{
2014	.name = TYPE_IMX_USDHC,
2015	.parent = TYPE_SYSBUS_SDHCI,
2016	.instance_init = imx_usdhc_init,
2017	},
2018	{
2019	.name = TYPE_S3C_SDHCI,
2020	.parent = TYPE_SYSBUS_SDHCI,
2021	.instance_init = sdhci_s3c_init,
2022	},
2023	};
2024
2025	DEFINE_TYPES(sdhci_types)