| 1 | /* |
| 2 | * SSI to SD card adapter. |
| 3 | * |
| 4 | * Copyright (c) 2007-2009 CodeSourcery. |
| 5 | * Written by Paul Brook |
| 6 | * |
| 7 | * Copyright (c) 2021 Wind River Systems, Inc. |
| 8 | * Improved by Bin Meng <bin.meng@windriver.com> |
| 9 | * |
| 10 | * Validated with U-Boot v2021.01 and Linux v5.10 mmc_spi driver |
| 11 | * |
| 12 | * This code is licensed under the GNU GPL v2. |
| 13 | * |
| 14 | * Contributions after 2012-01-13 are licensed under the terms of the |
| 15 | * GNU GPL, version 2 or (at your option) any later version. |
| 16 | */ |
| 17 | |
| 18 | #include "qemu/osdep.h" |
| 19 | #include "hw/ssi/ssi.h" |
| 20 | #include "migration/vmstate.h" |
| 21 | #include "hw/sd/sd.h" |
| 22 | #include "qemu/bswap.h" |
| 23 | #include "qemu/crc-ccitt.h" |
| 24 | #include "qom/object.h" |
| 25 | |
| 26 | //#define DEBUG_SSI_SD 1 |
| 27 | |
| 28 | #ifdef DEBUG_SSI_SD |
| 29 | #define DPRINTF(fmt, ...) \ |
| 30 | do { printf("ssi_sd: " fmt , ## __VA_ARGS__); } while (0) |
| 31 | #define BADF(fmt, ...) \ |
| 32 | do { fprintf(stderr, "ssi_sd: error: " fmt , ## __VA_ARGS__); exit(1);} while (0) |
| 33 | #else |
| 34 | #define DPRINTF(fmt, ...) do {} while(0) |
| 35 | #define BADF(fmt, ...) \ |
| 36 | do { fprintf(stderr, "ssi_sd: error: " fmt , ## __VA_ARGS__);} while (0) |
| 37 | #endif |
| 38 | |
| 39 | typedef enum { |
| 40 | SSI_SD_CMD = 0, |
| 41 | SSI_SD_CMDARG, |
| 42 | SSI_SD_PREP_RESP, |
| 43 | SSI_SD_RESPONSE, |
| 44 | SSI_SD_PREP_DATA, |
| 45 | SSI_SD_DATA_START, |
| 46 | SSI_SD_DATA_READ, |
| 47 | SSI_SD_DATA_CRC16, |
| 48 | SSI_SD_DATA_WRITE, |
| 49 | SSI_SD_SKIP_CRC16, |
| 50 | } ssi_sd_mode; |
| 51 | |
| 52 | struct ssi_sd_state { |
| 53 | SSIPeripheral ssidev; |
| 54 | uint32_t mode; |
| 55 | int cmd; |
| 56 | uint8_t cmdarg[4]; |
| 57 | uint8_t response[5]; |
| 58 | uint16_t crc16; |
| 59 | int32_t read_bytes; |
| 60 | int32_t write_bytes; |
| 61 | int32_t arglen; |
| 62 | int32_t response_pos; |
| 63 | int32_t stopping; |
| 64 | SDBus sdbus; |
| 65 | }; |
| 66 | |
| 67 | #define TYPE_SSI_SD "ssi-sd" |
| 68 | OBJECT_DECLARE_SIMPLE_TYPE(ssi_sd_state, SSI_SD) |
| 69 | |
| 70 | /* multiple block write */ |
| 71 | #define SSI_TOKEN_MULTI_WRITE 0xfc |
| 72 | /* terminate multiple block write */ |
| 73 | #define SSI_TOKEN_STOP_TRAN 0xfd |
| 74 | /* single block read/write, multiple block read */ |
| 75 | #define SSI_TOKEN_SINGLE 0xfe |
| 76 | |
| 77 | /* dummy value - don't care */ |
| 78 | #define SSI_DUMMY 0xff |
| 79 | |
| 80 | /* data accepted */ |
| 81 | #define DATA_RESPONSE_ACCEPTED 0x05 |
| 82 | |
| 83 | static uint32_t ssi_sd_transfer(SSIPeripheral *dev, uint32_t val) |
| 84 | { |
| 85 | ssi_sd_state *s = SSI_SD(dev); |
| 86 | SDRequest request; |
| 87 | uint8_t longresp[5]; |
| 88 | |
| 89 | if (!sdbus_get_inserted(&s->sdbus)) { |
| 90 | return SSI_DUMMY; |
| 91 | } |
| 92 | |
| 93 | /* |
| 94 | * Special case: allow CMD12 (STOP TRANSMISSION) while reading data. |
| 95 | * |
| 96 | * See "Physical Layer Specification Version 8.00" chapter 7.5.2.2, |
| 97 | * to avoid conflict between CMD12 response and next data block, |
| 98 | * timing of CMD12 should be controlled as follows: |
| 99 | * |
| 100 | * - CMD12 issued at the timing that end bit of CMD12 and end bit of |
| 101 | * data block is overlapped |
| 102 | * - CMD12 issued after one clock cycle after host receives a token |
| 103 | * (either Start Block token or Data Error token) |
| 104 | * |
| 105 | * We need to catch CMD12 in all of the data read states. |
| 106 | */ |
| 107 | if (s->mode >= SSI_SD_PREP_DATA && s->mode <= SSI_SD_DATA_CRC16) { |
| 108 | if (val == 0x4c) { |
| 109 | s->mode = SSI_SD_CMD; |
| 110 | /* There must be at least one byte delay before the card responds */ |
| 111 | s->stopping = 1; |
| 112 | } |
| 113 | } |
| 114 | |
| 115 | switch (s->mode) { |
| 116 | case SSI_SD_CMD: |
| 117 | switch (val) { |
| 118 | case SSI_DUMMY: |
| 119 | DPRINTF("NULL command\n"); |
| 120 | return SSI_DUMMY; |
| 121 | break; |
| 122 | case SSI_TOKEN_SINGLE: |
| 123 | case SSI_TOKEN_MULTI_WRITE: |
| 124 | DPRINTF("Start write block\n"); |
| 125 | s->mode = SSI_SD_DATA_WRITE; |
| 126 | return SSI_DUMMY; |
| 127 | case SSI_TOKEN_STOP_TRAN: |
| 128 | DPRINTF("Stop multiple write\n"); |
| 129 | |
| 130 | /* manually issue cmd12 to stop the transfer */ |
| 131 | request.cmd = 12; |
| 132 | request.arg = 0; |
| 133 | s->arglen = sdbus_do_command(&s->sdbus, &request, |
| 134 | longresp, sizeof(longresp)); |
| 135 | if (s->arglen == 0) { |
| 136 | s->arglen = 1; |
| 137 | /* a zero value indicates the card is busy */ |
| 138 | s->response[0] = 0; |
| 139 | DPRINTF("SD card busy\n"); |
| 140 | } else { |
| 141 | s->arglen = 1; |
| 142 | /* a non-zero value indicates the card is ready */ |
| 143 | s->response[0] = SSI_DUMMY; |
| 144 | } |
| 145 | |
| 146 | return SSI_DUMMY; |
| 147 | } |
| 148 | |
| 149 | s->cmd = val & 0x3f; |
| 150 | s->mode = SSI_SD_CMDARG; |
| 151 | s->arglen = 0; |
| 152 | return SSI_DUMMY; |
| 153 | case SSI_SD_CMDARG: |
| 154 | if (s->arglen == 4) { |
| 155 | /* FIXME: Check CRC. */ |
| 156 | request.cmd = s->cmd; |
| 157 | request.arg = ldl_be_p(s->cmdarg); |
| 158 | s->arglen = sdbus_do_command(&s->sdbus, &request, |
| 159 | longresp, sizeof(longresp)); |
| 160 | DPRINTF("CMD%d arg 0x%08x = %d\n", s->cmd, request.arg, s->arglen); |
| 161 | assert(s->arglen > 0); |
| 162 | memcpy(s->response, longresp, s->arglen); |
| 163 | |
| 164 | /* handle R1b (busy signal) */ |
| 165 | if (s->cmd == 28 || s->cmd == 29 || s->cmd == 38) { |
| 166 | s->stopping = 1; |
| 167 | } |
| 168 | s->mode = SSI_SD_PREP_RESP; |
| 169 | s->response_pos = 0; |
| 170 | } else { |
| 171 | s->cmdarg[s->arglen++] = val; |
| 172 | } |
| 173 | return SSI_DUMMY; |
| 174 | case SSI_SD_PREP_RESP: |
| 175 | DPRINTF("Prepare card response (Ncr)\n"); |
| 176 | s->mode = SSI_SD_RESPONSE; |
| 177 | return SSI_DUMMY; |
| 178 | case SSI_SD_RESPONSE: |
| 179 | if (s->response_pos < s->arglen) { |
| 180 | DPRINTF("Response 0x%02x\n", s->response[s->response_pos]); |
| 181 | return s->response[s->response_pos++]; |
| 182 | } |
| 183 | if (s->stopping) { |
| 184 | s->stopping = 0; |
| 185 | s->mode = SSI_SD_CMD; |
| 186 | return SSI_DUMMY; |
| 187 | } |
| 188 | if (sdbus_data_ready(&s->sdbus)) { |
| 189 | DPRINTF("Data read\n"); |
| 190 | s->mode = SSI_SD_DATA_START; |
| 191 | } else { |
| 192 | DPRINTF("End of command\n"); |
| 193 | s->mode = SSI_SD_CMD; |
| 194 | } |
| 195 | return SSI_DUMMY; |
| 196 | case SSI_SD_PREP_DATA: |
| 197 | DPRINTF("Prepare data block (Nac)\n"); |
| 198 | s->mode = SSI_SD_DATA_START; |
| 199 | return SSI_DUMMY; |
| 200 | case SSI_SD_DATA_START: |
| 201 | DPRINTF("Start read block\n"); |
| 202 | s->mode = SSI_SD_DATA_READ; |
| 203 | s->response_pos = 0; |
| 204 | return SSI_TOKEN_SINGLE; |
| 205 | case SSI_SD_DATA_READ: |
| 206 | val = sdbus_read_byte(&s->sdbus); |
| 207 | s->read_bytes++; |
| 208 | s->crc16 = crc_ccitt_false(s->crc16, (uint8_t *)&val, 1); |
| 209 | if (!sdbus_data_ready(&s->sdbus) || s->read_bytes == 512) { |
| 210 | DPRINTF("Data read end\n"); |
| 211 | s->mode = SSI_SD_DATA_CRC16; |
| 212 | } |
| 213 | return val; |
| 214 | case SSI_SD_DATA_CRC16: |
| 215 | val = (s->crc16 & 0xff00) >> 8; |
| 216 | s->crc16 <<= 8; |
| 217 | s->response_pos++; |
| 218 | if (s->response_pos == 2) { |
| 219 | DPRINTF("CRC16 read end\n"); |
| 220 | if (s->read_bytes == 512 && s->cmd != 17) { |
| 221 | s->mode = SSI_SD_PREP_DATA; |
| 222 | } else { |
| 223 | s->mode = SSI_SD_CMD; |
| 224 | } |
| 225 | s->read_bytes = 0; |
| 226 | s->response_pos = 0; |
| 227 | } |
| 228 | return val; |
| 229 | case SSI_SD_DATA_WRITE: |
| 230 | sdbus_write_byte(&s->sdbus, val); |
| 231 | s->write_bytes++; |
| 232 | if (!sdbus_receive_ready(&s->sdbus) || s->write_bytes == 512) { |
| 233 | DPRINTF("Data write end\n"); |
| 234 | s->mode = SSI_SD_SKIP_CRC16; |
| 235 | s->response_pos = 0; |
| 236 | } |
| 237 | return val; |
| 238 | case SSI_SD_SKIP_CRC16: |
| 239 | /* we don't verify the crc16 */ |
| 240 | s->response_pos++; |
| 241 | if (s->response_pos == 2) { |
| 242 | DPRINTF("CRC16 receive end\n"); |
| 243 | s->mode = SSI_SD_RESPONSE; |
| 244 | s->write_bytes = 0; |
| 245 | s->arglen = 1; |
| 246 | s->response[0] = DATA_RESPONSE_ACCEPTED; |
| 247 | s->response_pos = 0; |
| 248 | } |
| 249 | return SSI_DUMMY; |
| 250 | } |
| 251 | /* Should never happen. */ |
| 252 | return SSI_DUMMY; |
| 253 | } |
| 254 | |
| 255 | static int ssi_sd_post_load(void *opaque, int version_id) |
| 256 | { |
| 257 | ssi_sd_state *s = (ssi_sd_state *)opaque; |
| 258 | |
| 259 | if (s->mode > SSI_SD_SKIP_CRC16) { |
| 260 | return -EINVAL; |
| 261 | } |
| 262 | if (s->mode == SSI_SD_CMDARG && |
| 263 | (s->arglen >= ARRAY_SIZE(s->cmdarg))) { |
| 264 | return -EINVAL; |
| 265 | } |
| 266 | if (s->mode == SSI_SD_RESPONSE && |
| 267 | (s->response_pos < 0 || s->response_pos >= ARRAY_SIZE(s->response) || |
| 268 | (!s->stopping && s->arglen > ARRAY_SIZE(s->response)))) { |
| 269 | return -EINVAL; |
| 270 | } |
| 271 | |
| 272 | return 0; |
| 273 | } |
| 274 | |
| 275 | static const VMStateDescription vmstate_ssi_sd = { |
| 276 | .name = "ssi_sd", |
| 277 | .version_id = 7, |
| 278 | .minimum_version_id = 7, |
| 279 | .post_load = ssi_sd_post_load, |
| 280 | .fields = (const VMStateField []) { |
| 281 | VMSTATE_UINT32(mode, ssi_sd_state), |
| 282 | VMSTATE_INT32(cmd, ssi_sd_state), |
| 283 | VMSTATE_UINT8_ARRAY(cmdarg, ssi_sd_state, 4), |
| 284 | VMSTATE_UINT8_ARRAY(response, ssi_sd_state, 5), |
| 285 | VMSTATE_UINT16(crc16, ssi_sd_state), |
| 286 | VMSTATE_INT32(read_bytes, ssi_sd_state), |
| 287 | VMSTATE_INT32(write_bytes, ssi_sd_state), |
| 288 | VMSTATE_INT32(arglen, ssi_sd_state), |
| 289 | VMSTATE_INT32(response_pos, ssi_sd_state), |
| 290 | VMSTATE_INT32(stopping, ssi_sd_state), |
| 291 | VMSTATE_SSI_PERIPHERAL(ssidev, ssi_sd_state), |
| 292 | VMSTATE_END_OF_LIST() |
| 293 | } |
| 294 | }; |
| 295 | |
| 296 | static void ssi_sd_realize(SSIPeripheral *d, Error **errp) |
| 297 | { |
| 298 | ssi_sd_state *s = SSI_SD(d); |
| 299 | |
| 300 | qbus_init(&s->sdbus, sizeof(s->sdbus), TYPE_SD_BUS, DEVICE(d), "sd-bus"); |
| 301 | } |
| 302 | |
| 303 | static void ssi_sd_reset(DeviceState *dev) |
| 304 | { |
| 305 | ssi_sd_state *s = SSI_SD(dev); |
| 306 | |
| 307 | s->mode = SSI_SD_CMD; |
| 308 | s->cmd = 0; |
| 309 | memset(s->cmdarg, 0, sizeof(s->cmdarg)); |
| 310 | memset(s->response, 0, sizeof(s->response)); |
| 311 | s->crc16 = 0; |
| 312 | s->read_bytes = 0; |
| 313 | s->write_bytes = 0; |
| 314 | s->arglen = 0; |
| 315 | s->response_pos = 0; |
| 316 | s->stopping = 0; |
| 317 | } |
| 318 | |
| 319 | static void ssi_sd_class_init(ObjectClass *klass, const void *data) |
| 320 | { |
| 321 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 322 | SSIPeripheralClass *k = SSI_PERIPHERAL_CLASS(klass); |
| 323 | |
| 324 | k->realize = ssi_sd_realize; |
| 325 | k->transfer = ssi_sd_transfer; |
| 326 | k->cs_polarity = SSI_CS_LOW; |
| 327 | dc->vmsd = &vmstate_ssi_sd; |
| 328 | device_class_set_legacy_reset(dc, ssi_sd_reset); |
| 329 | /* Reason: GPIO chip-select line should be wired up */ |
| 330 | dc->user_creatable = false; |
| 331 | } |
| 332 | |
| 333 | static const TypeInfo ssi_sd_types[] = { |
| 334 | { |
| 335 | .name = TYPE_SSI_SD, |
| 336 | .parent = TYPE_SSI_PERIPHERAL, |
| 337 | .instance_size = sizeof(ssi_sd_state), |
| 338 | .class_init = ssi_sd_class_init, |
| 339 | }, |
| 340 | }; |
| 341 | |
| 342 | DEFINE_TYPES(ssi_sd_types) |