| 1 | /* |
| 2 | * QEMU Leon3 System Emulator |
| 3 | * |
| 4 | * SPDX-License-Identifier: MIT |
| 5 | * |
| 6 | * Copyright (c) 2010-2024 AdaCore |
| 7 | * |
| 8 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 9 | * of this software and associated documentation files (the "Software"), to deal |
| 10 | * in the Software without restriction, including without limitation the rights |
| 11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 12 | * copies of the Software, and to permit persons to whom the Software is |
| 13 | * furnished to do so, subject to the following conditions: |
| 14 | * |
| 15 | * The above copyright notice and this permission notice shall be included in |
| 16 | * all copies or substantial portions of the Software. |
| 17 | * |
| 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 24 | * THE SOFTWARE. |
| 25 | */ |
| 26 | |
| 27 | #include "qemu/osdep.h" |
| 28 | #include "qemu/units.h" |
| 29 | #include "qemu/error-report.h" |
| 30 | #include "qapi/error.h" |
| 31 | #include "qemu/datadir.h" |
| 32 | #include "exec/cpu-common.h" |
| 33 | #include "target/sparc/cpu.h" |
| 34 | #include "hw/core/irq.h" |
| 35 | #include "qemu/timer.h" |
| 36 | #include "hw/core/ptimer.h" |
| 37 | #include "hw/core/qdev-properties.h" |
| 38 | #include "system/system.h" |
| 39 | #include "system/qtest.h" |
| 40 | #include "system/reset.h" |
| 41 | #include "hw/core/boards.h" |
| 42 | #include "hw/core/loader.h" |
| 43 | #include "elf.h" |
| 44 | #include "trace.h" |
| 45 | |
| 46 | #include "hw/timer/grlib_gptimer.h" |
| 47 | #include "hw/char/grlib_uart.h" |
| 48 | #include "hw/intc/grlib_irqmp.h" |
| 49 | #include "hw/misc/grlib_ahb_apb_pnp.h" |
| 50 | |
| 51 | /* Default system clock. */ |
| 52 | #define CPU_CLK (40 * 1000 * 1000) |
| 53 | |
| 54 | #define LEON3_PROM_FILENAME "u-boot.bin" |
| 55 | #define LEON3_PROM_OFFSET (0x00000000) |
| 56 | #define LEON3_RAM_OFFSET (0x40000000) |
| 57 | |
| 58 | #define MAX_CPUS 4 |
| 59 | |
| 60 | #define LEON3_UART_OFFSET (0x80000100) |
| 61 | #define LEON3_UART_IRQ (3) |
| 62 | |
| 63 | #define LEON3_IRQMP_OFFSET (0x80000200) |
| 64 | |
| 65 | #define LEON3_TIMER_OFFSET (0x80000300) |
| 66 | #define LEON3_TIMER_IRQ (6) |
| 67 | #define LEON3_TIMER_COUNT (2) |
| 68 | |
| 69 | #define LEON3_APB_PNP_OFFSET (0x800FF000) |
| 70 | #define LEON3_AHB_PNP_OFFSET (0xFFFFF000) |
| 71 | |
| 72 | typedef struct ResetData { |
| 73 | struct CPUResetData { |
| 74 | int id; |
| 75 | SPARCCPU *cpu; |
| 76 | } info[MAX_CPUS]; |
| 77 | uint32_t entry; /* save kernel entry in case of reset */ |
| 78 | } ResetData; |
| 79 | |
| 80 | static uint32_t *gen_store_u32(uint32_t *code, hwaddr addr, uint32_t val) |
| 81 | { |
| 82 | stl_be_p(code++, 0x82100000); /* mov %g0, %g1 */ |
| 83 | stl_be_p(code++, 0x84100000); /* mov %g0, %g2 */ |
| 84 | stl_be_p(code++, 0x03000000 + |
| 85 | extract32(addr, 10, 22)); |
| 86 | /* sethi %hi(addr), %g1 */ |
| 87 | stl_be_p(code++, 0x82106000 + |
| 88 | extract32(addr, 0, 10)); |
| 89 | /* or %g1, addr, %g1 */ |
| 90 | stl_be_p(code++, 0x05000000 + |
| 91 | extract32(val, 10, 22)); |
| 92 | /* sethi %hi(val), %g2 */ |
| 93 | stl_be_p(code++, 0x8410a000 + |
| 94 | extract32(val, 0, 10)); |
| 95 | /* or %g2, val, %g2 */ |
| 96 | stl_be_p(code++, 0xc4204000); /* st %g2, [ %g1 ] */ |
| 97 | |
| 98 | return code; |
| 99 | } |
| 100 | |
| 101 | /* |
| 102 | * When loading a kernel in RAM the machine is expected to be in a different |
| 103 | * state (eg: initialized by the bootloader). This little code reproduces |
| 104 | * this behavior. Also this code can be executed by the secondary cpus as |
| 105 | * well since it looks at the %asr17 register before doing any |
| 106 | * initialization, it allows to use the same reset address for all the |
| 107 | * cpus. |
| 108 | */ |
| 109 | static void write_bootloader(void *ptr, hwaddr kernel_addr) |
| 110 | { |
| 111 | uint32_t *p = ptr; |
| 112 | uint32_t *sec_cpu_branch_p = NULL; |
| 113 | |
| 114 | /* If we are running on a secondary CPU, jump directly to the kernel. */ |
| 115 | |
| 116 | stl_be_p(p++, 0x85444000); /* rd %asr17, %g2 */ |
| 117 | stl_be_p(p++, 0x8530a01c); /* srl %g2, 0x1c, %g2 */ |
| 118 | stl_be_p(p++, 0x80908000); /* tst %g2 */ |
| 119 | /* Filled below. */ |
| 120 | sec_cpu_branch_p = p; |
| 121 | stl_be_p(p++, 0x0BADC0DE); /* bne xxx */ |
| 122 | stl_be_p(p++, 0x01000000); /* nop */ |
| 123 | |
| 124 | /* Initialize the UARTs */ |
| 125 | /* *UART_CONTROL = UART_RECEIVE_ENABLE | UART_TRANSMIT_ENABLE; */ |
| 126 | p = gen_store_u32(p, 0x80000108, 3); |
| 127 | |
| 128 | /* Initialize the TIMER 0 */ |
| 129 | /* *GPTIMER_SCALER_RELOAD = 40 - 1; */ |
| 130 | p = gen_store_u32(p, 0x80000304, 39); |
| 131 | /* *GPTIMER0_COUNTER_RELOAD = 0xFFFE; */ |
| 132 | p = gen_store_u32(p, 0x80000314, 0xFFFFFFFE); |
| 133 | /* *GPTIMER0_CONFIG = GPTIMER_ENABLE | GPTIMER_RESTART; */ |
| 134 | p = gen_store_u32(p, 0x80000318, 3); |
| 135 | |
| 136 | /* Now, the relative branch above can be computed. */ |
| 137 | stl_be_p(sec_cpu_branch_p, 0x12800000 |
| 138 | + (p - sec_cpu_branch_p)); |
| 139 | |
| 140 | /* JUMP to the entry point */ |
| 141 | stl_be_p(p++, 0x82100000); /* mov %g0, %g1 */ |
| 142 | stl_be_p(p++, 0x03000000 + extract32(kernel_addr, 10, 22)); |
| 143 | /* sethi %hi(kernel_addr), %g1 */ |
| 144 | stl_be_p(p++, 0x82106000 + extract32(kernel_addr, 0, 10)); |
| 145 | /* or kernel_addr, %g1 */ |
| 146 | stl_be_p(p++, 0x81c04000); /* jmp %g1 */ |
| 147 | stl_be_p(p++, 0x01000000); /* nop */ |
| 148 | } |
| 149 | |
| 150 | static void leon3_cpu_reset(void *opaque) |
| 151 | { |
| 152 | struct CPUResetData *info = (struct CPUResetData *) opaque; |
| 153 | int id = info->id; |
| 154 | ResetData *s = container_of(info, ResetData, info[id]); |
| 155 | CPUState *cpu = CPU(s->info[id].cpu); |
| 156 | CPUSPARCState *env = cpu_env(cpu); |
| 157 | |
| 158 | cpu_reset(cpu); |
| 159 | |
| 160 | cpu->halted = cpu->cpu_index != 0; |
| 161 | env->pc = s->entry; |
| 162 | env->npc = s->entry + 4; |
| 163 | } |
| 164 | |
| 165 | static void leon3_cache_control_int(CPUSPARCState *env) |
| 166 | { |
| 167 | uint32_t state = 0; |
| 168 | |
| 169 | if (env->cache_control & CACHE_CTRL_IF) { |
| 170 | /* Instruction cache state */ |
| 171 | state = env->cache_control & CACHE_STATE_MASK; |
| 172 | if (state == CACHE_ENABLED) { |
| 173 | state = CACHE_FROZEN; |
| 174 | trace_int_helper_icache_freeze(); |
| 175 | } |
| 176 | |
| 177 | env->cache_control &= ~CACHE_STATE_MASK; |
| 178 | env->cache_control |= state; |
| 179 | } |
| 180 | |
| 181 | if (env->cache_control & CACHE_CTRL_DF) { |
| 182 | /* Data cache state */ |
| 183 | state = (env->cache_control >> 2) & CACHE_STATE_MASK; |
| 184 | if (state == CACHE_ENABLED) { |
| 185 | state = CACHE_FROZEN; |
| 186 | trace_int_helper_dcache_freeze(); |
| 187 | } |
| 188 | |
| 189 | env->cache_control &= ~(CACHE_STATE_MASK << 2); |
| 190 | env->cache_control |= (state << 2); |
| 191 | } |
| 192 | } |
| 193 | |
| 194 | static void leon3_irq_ack(CPUSPARCState *env, int intno) |
| 195 | { |
| 196 | CPUState *cpu = env_cpu(env); |
| 197 | grlib_irqmp_ack(env->irq_manager, cpu->cpu_index, intno); |
| 198 | } |
| 199 | |
| 200 | /* |
| 201 | * This device assumes that the incoming 'level' value on the |
| 202 | * qemu_irq is the interrupt number, not just a simple 0/1 level. |
| 203 | */ |
| 204 | static void leon3_set_pil_in(void *opaque, int n, int level) |
| 205 | { |
| 206 | DeviceState *cpu = opaque; |
| 207 | CPUState *cs = CPU(cpu); |
| 208 | CPUSPARCState *env = cpu_env(cs); |
| 209 | uint32_t pil_in = level; |
| 210 | |
| 211 | assert(env != NULL); |
| 212 | |
| 213 | env->pil_in = pil_in; |
| 214 | |
| 215 | if (env->pil_in && (env->interrupt_index == 0 || |
| 216 | (env->interrupt_index & ~15) == TT_EXTINT)) { |
| 217 | unsigned int i; |
| 218 | |
| 219 | for (i = 15; i > 0; i--) { |
| 220 | if (env->pil_in & (1 << i)) { |
| 221 | int old_interrupt = env->interrupt_index; |
| 222 | |
| 223 | env->interrupt_index = TT_EXTINT | i; |
| 224 | if (old_interrupt != env->interrupt_index) { |
| 225 | trace_leon3_set_irq(i); |
| 226 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); |
| 227 | } |
| 228 | break; |
| 229 | } |
| 230 | } |
| 231 | } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { |
| 232 | trace_leon3_reset_irq(env->interrupt_index & 15); |
| 233 | env->interrupt_index = 0; |
| 234 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); |
| 235 | } |
| 236 | } |
| 237 | |
| 238 | static void leon3_start_cpu_async_work(CPUState *cpu, run_on_cpu_data data) |
| 239 | { |
| 240 | cpu->halted = 0; |
| 241 | } |
| 242 | |
| 243 | static void leon3_start_cpu(void *opaque, int n, int level) |
| 244 | { |
| 245 | DeviceState *cpu = opaque; |
| 246 | CPUState *cs = CPU(cpu); |
| 247 | |
| 248 | assert(level == 1); |
| 249 | async_run_on_cpu(cs, leon3_start_cpu_async_work, RUN_ON_CPU_NULL); |
| 250 | } |
| 251 | |
| 252 | static void leon3_irq_manager(CPUSPARCState *env, int intno) |
| 253 | { |
| 254 | leon3_irq_ack(env, intno); |
| 255 | leon3_cache_control_int(env); |
| 256 | } |
| 257 | |
| 258 | static void leon3_generic_hw_init(MachineState *machine) |
| 259 | { |
| 260 | ram_addr_t ram_size = machine->ram_size; |
| 261 | const char *bios_name = machine->firmware ?: LEON3_PROM_FILENAME; |
| 262 | const char *kernel_filename = machine->kernel_filename; |
| 263 | SPARCCPU *cpu; |
| 264 | CPUSPARCState *env; |
| 265 | MemoryRegion *address_space_mem = get_system_memory(); |
| 266 | MemoryRegion *prom = g_new(MemoryRegion, 1); |
| 267 | int ret; |
| 268 | char *filename; |
| 269 | int bios_size; |
| 270 | int prom_size; |
| 271 | ResetData *reset_info; |
| 272 | DeviceState *dev, *irqmpdev; |
| 273 | int i; |
| 274 | AHBPnp *ahb_pnp; |
| 275 | APBPnp *apb_pnp; |
| 276 | |
| 277 | reset_info = g_malloc0(sizeof(ResetData)); |
| 278 | |
| 279 | for (i = 0; i < machine->smp.cpus; i++) { |
| 280 | /* Init CPU */ |
| 281 | cpu = SPARC_CPU(object_new(machine->cpu_type)); |
| 282 | qdev_init_gpio_in_named(DEVICE(cpu), leon3_start_cpu, "start_cpu", 1); |
| 283 | qdev_init_gpio_in_named(DEVICE(cpu), leon3_set_pil_in, "pil", 1); |
| 284 | qdev_realize(DEVICE(cpu), NULL, &error_fatal); |
| 285 | env = &cpu->env; |
| 286 | |
| 287 | cpu_sparc_set_id(env, i); |
| 288 | |
| 289 | /* Reset data */ |
| 290 | reset_info->info[i].id = i; |
| 291 | reset_info->info[i].cpu = cpu; |
| 292 | qemu_register_reset(leon3_cpu_reset, &reset_info->info[i]); |
| 293 | } |
| 294 | |
| 295 | ahb_pnp = GRLIB_AHB_PNP(qdev_new(TYPE_GRLIB_AHB_PNP)); |
| 296 | sysbus_realize_and_unref(SYS_BUS_DEVICE(ahb_pnp), &error_fatal); |
| 297 | sysbus_mmio_map(SYS_BUS_DEVICE(ahb_pnp), 0, LEON3_AHB_PNP_OFFSET); |
| 298 | grlib_ahb_pnp_add_entry(ahb_pnp, 0, 0, GRLIB_VENDOR_GAISLER, |
| 299 | GRLIB_LEON3_DEV, GRLIB_AHB_MASTER, |
| 300 | GRLIB_CPU_AREA); |
| 301 | |
| 302 | apb_pnp = GRLIB_APB_PNP(qdev_new(TYPE_GRLIB_APB_PNP)); |
| 303 | sysbus_realize_and_unref(SYS_BUS_DEVICE(apb_pnp), &error_fatal); |
| 304 | sysbus_mmio_map(SYS_BUS_DEVICE(apb_pnp), 0, LEON3_APB_PNP_OFFSET); |
| 305 | grlib_ahb_pnp_add_entry(ahb_pnp, LEON3_APB_PNP_OFFSET, 0xFFF, |
| 306 | GRLIB_VENDOR_GAISLER, GRLIB_APBMST_DEV, |
| 307 | GRLIB_AHB_SLAVE, GRLIB_AHBMEM_AREA); |
| 308 | |
| 309 | /* Allocate IRQ manager */ |
| 310 | irqmpdev = qdev_new(TYPE_GRLIB_IRQMP); |
| 311 | object_property_set_int(OBJECT(irqmpdev), "ncpus", machine->smp.cpus, |
| 312 | &error_fatal); |
| 313 | sysbus_realize_and_unref(SYS_BUS_DEVICE(irqmpdev), &error_fatal); |
| 314 | |
| 315 | for (i = 0; i < machine->smp.cpus; i++) { |
| 316 | cpu = reset_info->info[i].cpu; |
| 317 | env = &cpu->env; |
| 318 | qdev_connect_gpio_out_named(irqmpdev, "grlib-start-cpu", i, |
| 319 | qdev_get_gpio_in_named(DEVICE(cpu), |
| 320 | "start_cpu", 0)); |
| 321 | qdev_connect_gpio_out_named(irqmpdev, "grlib-irq", i, |
| 322 | qdev_get_gpio_in_named(DEVICE(cpu), |
| 323 | "pil", 0)); |
| 324 | env->irq_manager = irqmpdev; |
| 325 | env->qemu_irq_ack = leon3_irq_manager; |
| 326 | } |
| 327 | |
| 328 | sysbus_mmio_map(SYS_BUS_DEVICE(irqmpdev), 0, LEON3_IRQMP_OFFSET); |
| 329 | grlib_apb_pnp_add_entry(apb_pnp, LEON3_IRQMP_OFFSET, 0xFFF, |
| 330 | GRLIB_VENDOR_GAISLER, GRLIB_IRQMP_DEV, |
| 331 | 2, 0, GRLIB_APBIO_AREA); |
| 332 | |
| 333 | /* Allocate RAM */ |
| 334 | if (ram_size > 1 * GiB) { |
| 335 | error_report("Too much memory for this machine: %" PRId64 "MB," |
| 336 | " maximum 1G", |
| 337 | ram_size / MiB); |
| 338 | exit(1); |
| 339 | } |
| 340 | |
| 341 | memory_region_add_subregion(address_space_mem, LEON3_RAM_OFFSET, |
| 342 | machine->ram); |
| 343 | |
| 344 | /* Allocate BIOS */ |
| 345 | prom_size = 8 * MiB; |
| 346 | memory_region_init_rom(prom, NULL, "Leon3.bios", prom_size, &error_fatal); |
| 347 | memory_region_add_subregion(address_space_mem, LEON3_PROM_OFFSET, prom); |
| 348 | |
| 349 | /* Load boot prom */ |
| 350 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
| 351 | |
| 352 | if (filename) { |
| 353 | bios_size = get_image_size(filename, NULL); |
| 354 | } else { |
| 355 | bios_size = -1; |
| 356 | } |
| 357 | |
| 358 | if (bios_size > prom_size) { |
| 359 | error_report("could not load prom '%s': file too big", filename); |
| 360 | exit(1); |
| 361 | } |
| 362 | |
| 363 | if (bios_size > 0) { |
| 364 | ret = load_image_targphys(filename, LEON3_PROM_OFFSET, bios_size, NULL); |
| 365 | if (ret < 0 || ret > prom_size) { |
| 366 | error_report("could not load prom '%s'", filename); |
| 367 | exit(1); |
| 368 | } |
| 369 | } else if (kernel_filename == NULL && !qtest_enabled()) { |
| 370 | error_report("Can't read bios image '%s'", filename |
| 371 | ? filename |
| 372 | : LEON3_PROM_FILENAME); |
| 373 | exit(1); |
| 374 | } |
| 375 | g_free(filename); |
| 376 | |
| 377 | /* Can directly load an application. */ |
| 378 | if (kernel_filename != NULL) { |
| 379 | long kernel_size; |
| 380 | uint64_t entry; |
| 381 | |
| 382 | kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, |
| 383 | &entry, NULL, NULL, NULL, |
| 384 | ELFDATA2MSB, EM_SPARC, 0, 0); |
| 385 | if (kernel_size < 0) { |
| 386 | kernel_size = load_uimage(kernel_filename, NULL, &entry, |
| 387 | NULL, NULL, NULL); |
| 388 | } |
| 389 | if (kernel_size < 0) { |
| 390 | error_report("could not load kernel '%s'", kernel_filename); |
| 391 | exit(1); |
| 392 | } |
| 393 | if (bios_size <= 0) { |
| 394 | /* |
| 395 | * If there is no bios/monitor just start the application but put |
| 396 | * the machine in an initialized state through a little |
| 397 | * bootloader. |
| 398 | */ |
| 399 | write_bootloader(memory_region_get_ram_ptr(prom), entry); |
| 400 | reset_info->entry = LEON3_PROM_OFFSET; |
| 401 | for (i = 0; i < machine->smp.cpus; i++) { |
| 402 | reset_info->info[i].cpu->env.pc = LEON3_PROM_OFFSET; |
| 403 | reset_info->info[i].cpu->env.npc = LEON3_PROM_OFFSET + 4; |
| 404 | } |
| 405 | } |
| 406 | } |
| 407 | |
| 408 | /* Allocate timers */ |
| 409 | dev = qdev_new(TYPE_GRLIB_GPTIMER); |
| 410 | qdev_prop_set_uint32(dev, "nr-timers", LEON3_TIMER_COUNT); |
| 411 | qdev_prop_set_uint32(dev, "frequency", CPU_CLK); |
| 412 | qdev_prop_set_uint32(dev, "irq-line", LEON3_TIMER_IRQ); |
| 413 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
| 414 | |
| 415 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_TIMER_OFFSET); |
| 416 | for (i = 0; i < LEON3_TIMER_COUNT; i++) { |
| 417 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, |
| 418 | qdev_get_gpio_in(irqmpdev, LEON3_TIMER_IRQ + i)); |
| 419 | } |
| 420 | |
| 421 | grlib_apb_pnp_add_entry(apb_pnp, LEON3_TIMER_OFFSET, 0xFFF, |
| 422 | GRLIB_VENDOR_GAISLER, GRLIB_GPTIMER_DEV, |
| 423 | 0, LEON3_TIMER_IRQ, GRLIB_APBIO_AREA); |
| 424 | |
| 425 | /* Allocate uart */ |
| 426 | dev = qdev_new(TYPE_GRLIB_APB_UART); |
| 427 | qdev_prop_set_chr(dev, "chrdev", serial_hd(0)); |
| 428 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
| 429 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_UART_OFFSET); |
| 430 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, |
| 431 | qdev_get_gpio_in(irqmpdev, LEON3_UART_IRQ)); |
| 432 | grlib_apb_pnp_add_entry(apb_pnp, LEON3_UART_OFFSET, 0xFFF, |
| 433 | GRLIB_VENDOR_GAISLER, GRLIB_APBUART_DEV, 1, |
| 434 | LEON3_UART_IRQ, GRLIB_APBIO_AREA); |
| 435 | } |
| 436 | |
| 437 | static void leon3_generic_machine_init(MachineClass *mc) |
| 438 | { |
| 439 | mc->desc = "Leon-3 generic"; |
| 440 | mc->init = leon3_generic_hw_init; |
| 441 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("LEON3"); |
| 442 | mc->default_ram_id = "leon3.ram"; |
| 443 | mc->max_cpus = MAX_CPUS; |
| 444 | } |
| 445 | |
| 446 | DEFINE_MACHINE("leon3_generic", leon3_generic_machine_init) |