| 1 | /* |
| 2 | * QEMU Sun4m & Sun4d & Sun4c System Emulator |
| 3 | * |
| 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
| 24 | |
| 25 | #include "qemu/osdep.h" |
| 26 | #include "qemu/units.h" |
| 27 | #include "qapi/error.h" |
| 28 | #include "qemu/datadir.h" |
| 29 | #include "target/sparc/cpu.h" |
| 30 | #include "exec/target_page.h" |
| 31 | #include "hw/core/sysbus.h" |
| 32 | #include "qemu/error-report.h" |
| 33 | #include "qemu/timer.h" |
| 34 | #include "hw/sparc/sun4m_iommu.h" |
| 35 | #include "hw/rtc/m48t59.h" |
| 36 | #include "migration/vmstate.h" |
| 37 | #include "hw/sparc/sparc32_dma.h" |
| 38 | #include "hw/block/fdc.h" |
| 39 | #include "system/reset.h" |
| 40 | #include "system/runstate.h" |
| 41 | #include "system/system.h" |
| 42 | #include "net/net.h" |
| 43 | #include "hw/core/boards.h" |
| 44 | #include "hw/scsi/esp.h" |
| 45 | #include "hw/nvram/sun_nvram.h" |
| 46 | #include "hw/core/qdev-properties.h" |
| 47 | #include "hw/nvram/chrp_nvram.h" |
| 48 | #include "hw/nvram/fw_cfg.h" |
| 49 | #include "hw/char/escc.h" |
| 50 | #include "hw/misc/empty_slot.h" |
| 51 | #include "hw/misc/unimp.h" |
| 52 | #include "hw/core/irq.h" |
| 53 | #include "hw/core/or-irq.h" |
| 54 | #include "hw/core/loader.h" |
| 55 | #include "elf.h" |
| 56 | #include "trace.h" |
| 57 | #include "qom/object.h" |
| 58 | |
| 59 | /* |
| 60 | * Sun4m architecture was used in the following machines: |
| 61 | * |
| 62 | * SPARCserver 6xxMP/xx |
| 63 | * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), |
| 64 | * SPARCclassic X (4/10) |
| 65 | * SPARCstation LX/ZX (4/30) |
| 66 | * SPARCstation Voyager |
| 67 | * SPARCstation 10/xx, SPARCserver 10/xx |
| 68 | * SPARCstation 5, SPARCserver 5 |
| 69 | * SPARCstation 20/xx, SPARCserver 20 |
| 70 | * SPARCstation 4 |
| 71 | * |
| 72 | * See for example: http://www.sunhelp.org/faq/sunref1.html |
| 73 | */ |
| 74 | |
| 75 | #define KERNEL_LOAD_ADDR 0x00004000 |
| 76 | #define CMDLINE_ADDR 0x007ff000 |
| 77 | #define INITRD_LOAD_ADDR 0x00800000 |
| 78 | #define PROM_SIZE_MAX (1 * MiB) |
| 79 | #define PROM_VADDR 0xffd00000 |
| 80 | #define PROM_FILENAME "openbios-sparc32" |
| 81 | #define CFG_ADDR 0xd00000510ULL |
| 82 | #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00) |
| 83 | #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01) |
| 84 | #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02) |
| 85 | |
| 86 | #define MAX_CPUS 16 |
| 87 | #define MAX_PILS 16 |
| 88 | #define MAX_VSIMMS 4 |
| 89 | |
| 90 | #define ESCC_CLOCK 4915200 |
| 91 | |
| 92 | struct sun4m_hwdef { |
| 93 | hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base; |
| 94 | hwaddr intctl_base, counter_base, nvram_base, ms_kb_base; |
| 95 | hwaddr serial_base, fd_base; |
| 96 | hwaddr afx_base, idreg_base, dma_base, esp_base, le_base; |
| 97 | hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base; |
| 98 | hwaddr bpp_base, dbri_base, sx_base; |
| 99 | struct { |
| 100 | hwaddr reg_base, vram_base; |
| 101 | } vsimm[MAX_VSIMMS]; |
| 102 | hwaddr ecc_base; |
| 103 | uint64_t max_mem; |
| 104 | uint32_t ecc_version; |
| 105 | uint32_t iommu_version; |
| 106 | uint16_t machine_id; |
| 107 | uint8_t nvram_machine_id; |
| 108 | }; |
| 109 | |
| 110 | struct Sun4mMachineClass { |
| 111 | /*< private >*/ |
| 112 | MachineClass parent_obj; |
| 113 | /*< public >*/ |
| 114 | const struct sun4m_hwdef *hwdef; |
| 115 | }; |
| 116 | typedef struct Sun4mMachineClass Sun4mMachineClass; |
| 117 | |
| 118 | #define TYPE_SUN4M_MACHINE MACHINE_TYPE_NAME("sun4m-common") |
| 119 | DECLARE_CLASS_CHECKERS(Sun4mMachineClass, SUN4M_MACHINE, TYPE_SUN4M_MACHINE) |
| 120 | |
| 121 | const char *fw_cfg_arch_key_name(uint16_t key) |
| 122 | { |
| 123 | static const struct { |
| 124 | uint16_t key; |
| 125 | const char *name; |
| 126 | } fw_cfg_arch_wellknown_keys[] = { |
| 127 | {FW_CFG_SUN4M_DEPTH, "depth"}, |
| 128 | {FW_CFG_SUN4M_WIDTH, "width"}, |
| 129 | {FW_CFG_SUN4M_HEIGHT, "height"}, |
| 130 | }; |
| 131 | |
| 132 | for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) { |
| 133 | if (fw_cfg_arch_wellknown_keys[i].key == key) { |
| 134 | return fw_cfg_arch_wellknown_keys[i].name; |
| 135 | } |
| 136 | } |
| 137 | return NULL; |
| 138 | } |
| 139 | |
| 140 | static void fw_cfg_boot_set(void *opaque, const char *boot_device, |
| 141 | Error **errp) |
| 142 | { |
| 143 | fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); |
| 144 | } |
| 145 | |
| 146 | static void nvram_init(Nvram *nvram, uint8_t *macaddr, |
| 147 | const char *cmdline, const char *boot_devices, |
| 148 | ram_addr_t RAM_size, uint32_t kernel_size, |
| 149 | int width, int height, int depth, |
| 150 | int nvram_machine_id, const char *arch) |
| 151 | { |
| 152 | unsigned int i; |
| 153 | int sysp_end; |
| 154 | uint8_t image[0x1ff0]; |
| 155 | NvramClass *k = NVRAM_GET_CLASS(nvram); |
| 156 | |
| 157 | memset(image, '\0', sizeof(image)); |
| 158 | |
| 159 | /* OpenBIOS nvram variables partition */ |
| 160 | sysp_end = chrp_nvram_create_system_partition(image, 0, 0x1fd0); |
| 161 | |
| 162 | /* Free space partition */ |
| 163 | chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end); |
| 164 | |
| 165 | Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, |
| 166 | nvram_machine_id); |
| 167 | |
| 168 | for (i = 0; i < sizeof(image); i++) { |
| 169 | (k->write)(nvram, i, image[i]); |
| 170 | } |
| 171 | } |
| 172 | |
| 173 | static void cpu_kick_irq(SPARCCPU *cpu) |
| 174 | { |
| 175 | CPUSPARCState *env = &cpu->env; |
| 176 | CPUState *cs = CPU(cpu); |
| 177 | |
| 178 | cs->halted = 0; |
| 179 | cpu_check_irqs(env); |
| 180 | qemu_cpu_kick(cs); |
| 181 | } |
| 182 | |
| 183 | static void cpu_set_irq(void *opaque, int irq, int level) |
| 184 | { |
| 185 | SPARCCPU *cpu = opaque; |
| 186 | CPUSPARCState *env = &cpu->env; |
| 187 | |
| 188 | if (level) { |
| 189 | trace_sun4m_cpu_set_irq_raise(irq); |
| 190 | env->pil_in |= 1 << irq; |
| 191 | cpu_kick_irq(cpu); |
| 192 | } else { |
| 193 | trace_sun4m_cpu_set_irq_lower(irq); |
| 194 | env->pil_in &= ~(1 << irq); |
| 195 | cpu_check_irqs(env); |
| 196 | } |
| 197 | } |
| 198 | |
| 199 | static void sun4m_cpu_reset(void *opaque) |
| 200 | { |
| 201 | SPARCCPU *cpu = opaque; |
| 202 | CPUState *cs = CPU(cpu); |
| 203 | |
| 204 | cpu_reset(cs); |
| 205 | } |
| 206 | |
| 207 | static void cpu_halt_signal(void *opaque, int irq, int level) |
| 208 | { |
| 209 | if (level && current_cpu) { |
| 210 | cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); |
| 211 | } |
| 212 | } |
| 213 | |
| 214 | static uint64_t translate_kernel_address(void *opaque, uint64_t addr) |
| 215 | { |
| 216 | return addr - 0xf0000000ULL; |
| 217 | } |
| 218 | |
| 219 | static unsigned long sun4m_load_kernel(const char *kernel_filename, |
| 220 | const char *initrd_filename, |
| 221 | ram_addr_t RAM_size, |
| 222 | uint32_t *initrd_size) |
| 223 | { |
| 224 | int linux_boot; |
| 225 | unsigned int i; |
| 226 | long kernel_size; |
| 227 | uint8_t *ptr; |
| 228 | |
| 229 | linux_boot = (kernel_filename != NULL); |
| 230 | |
| 231 | kernel_size = 0; |
| 232 | if (linux_boot) { |
| 233 | kernel_size = load_elf(kernel_filename, NULL, |
| 234 | translate_kernel_address, NULL, |
| 235 | NULL, NULL, NULL, NULL, |
| 236 | ELFDATA2MSB, EM_SPARC, 0, 0); |
| 237 | if (kernel_size < 0) |
| 238 | kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
| 239 | RAM_size - KERNEL_LOAD_ADDR, true, |
| 240 | TARGET_PAGE_SIZE); |
| 241 | if (kernel_size < 0) |
| 242 | kernel_size = load_image_targphys(kernel_filename, |
| 243 | KERNEL_LOAD_ADDR, |
| 244 | RAM_size - KERNEL_LOAD_ADDR, |
| 245 | NULL); |
| 246 | if (kernel_size < 0) { |
| 247 | error_report("could not load kernel '%s'", kernel_filename); |
| 248 | exit(1); |
| 249 | } |
| 250 | |
| 251 | /* load initrd */ |
| 252 | *initrd_size = 0; |
| 253 | if (initrd_filename) { |
| 254 | *initrd_size = load_image_targphys(initrd_filename, |
| 255 | INITRD_LOAD_ADDR, |
| 256 | RAM_size - INITRD_LOAD_ADDR, |
| 257 | NULL); |
| 258 | if ((int)*initrd_size < 0) { |
| 259 | error_report("could not load initial ram disk '%s'", |
| 260 | initrd_filename); |
| 261 | exit(1); |
| 262 | } |
| 263 | } |
| 264 | if (*initrd_size > 0) { |
| 265 | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
| 266 | ptr = rom_ptr(KERNEL_LOAD_ADDR + i, 24); |
| 267 | if (ptr && ldl_be_p(ptr) == 0x48647253) { /* HdrS */ |
| 268 | stl_be_p(ptr + 16, INITRD_LOAD_ADDR); |
| 269 | stl_be_p(ptr + 20, *initrd_size); |
| 270 | break; |
| 271 | } |
| 272 | } |
| 273 | } |
| 274 | } |
| 275 | return kernel_size; |
| 276 | } |
| 277 | |
| 278 | static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq) |
| 279 | { |
| 280 | DeviceState *dev; |
| 281 | SysBusDevice *s; |
| 282 | |
| 283 | dev = qdev_new(TYPE_SUN4M_IOMMU); |
| 284 | qdev_prop_set_uint32(dev, "version", version); |
| 285 | s = SYS_BUS_DEVICE(dev); |
| 286 | sysbus_realize_and_unref(s, &error_fatal); |
| 287 | sysbus_connect_irq(s, 0, irq); |
| 288 | sysbus_mmio_map(s, 0, addr); |
| 289 | |
| 290 | return s; |
| 291 | } |
| 292 | |
| 293 | static void *sparc32_dma_init(hwaddr dma_base, |
| 294 | hwaddr esp_base, qemu_irq espdma_irq, |
| 295 | hwaddr le_base, qemu_irq ledma_irq, |
| 296 | MACAddr *mac) |
| 297 | { |
| 298 | DeviceState *dma; |
| 299 | ESPDMADeviceState *espdma; |
| 300 | LEDMADeviceState *ledma; |
| 301 | SysBusESPState *esp; |
| 302 | SysBusPCNetState *lance; |
| 303 | NICInfo *nd = qemu_find_nic_info("lance", true, NULL); |
| 304 | |
| 305 | dma = qdev_new(TYPE_SPARC32_DMA); |
| 306 | espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component( |
| 307 | OBJECT(dma), "espdma")); |
| 308 | |
| 309 | esp = SYSBUS_ESP(object_resolve_path_component(OBJECT(espdma), "esp")); |
| 310 | |
| 311 | ledma = SPARC32_LEDMA_DEVICE(object_resolve_path_component( |
| 312 | OBJECT(dma), "ledma")); |
| 313 | |
| 314 | lance = SYSBUS_PCNET(object_resolve_path_component( |
| 315 | OBJECT(ledma), "lance")); |
| 316 | |
| 317 | if (nd) { |
| 318 | qdev_set_nic_properties(DEVICE(lance), nd); |
| 319 | memcpy(mac->a, nd->macaddr.a, sizeof(mac->a)); |
| 320 | } else { |
| 321 | qemu_macaddr_default_if_unset(mac); |
| 322 | qdev_prop_set_macaddr(DEVICE(lance), "mac", mac->a); |
| 323 | } |
| 324 | |
| 325 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal); |
| 326 | |
| 327 | sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq); |
| 328 | |
| 329 | sysbus_connect_irq(SYS_BUS_DEVICE(ledma), 0, ledma_irq); |
| 330 | |
| 331 | sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base); |
| 332 | |
| 333 | sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base); |
| 334 | scsi_bus_legacy_handle_cmdline(&esp->esp.bus); |
| 335 | |
| 336 | sysbus_mmio_map(SYS_BUS_DEVICE(lance), 0, le_base); |
| 337 | |
| 338 | return dma; |
| 339 | } |
| 340 | |
| 341 | static DeviceState *slavio_intctl_init(hwaddr addr, |
| 342 | hwaddr addrg, |
| 343 | unsigned int smp_cpus, |
| 344 | DeviceState **cpus) |
| 345 | { |
| 346 | DeviceState *dev; |
| 347 | SysBusDevice *s; |
| 348 | unsigned int i, j; |
| 349 | |
| 350 | dev = qdev_new("slavio_intctl"); |
| 351 | |
| 352 | s = SYS_BUS_DEVICE(dev); |
| 353 | sysbus_realize_and_unref(s, &error_fatal); |
| 354 | |
| 355 | for (i = 0; i < smp_cpus; i++) { |
| 356 | for (j = 0; j < MAX_PILS; j++) { |
| 357 | sysbus_connect_irq(s, i * MAX_PILS + j, |
| 358 | qdev_get_gpio_in_named(cpus[i], "pil", j)); |
| 359 | } |
| 360 | } |
| 361 | sysbus_mmio_map(s, 0, addrg); |
| 362 | for (i = 0; i < MAX_CPUS; i++) { |
| 363 | sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE); |
| 364 | } |
| 365 | |
| 366 | return dev; |
| 367 | } |
| 368 | |
| 369 | #define SYS_TIMER_OFFSET 0x10000ULL |
| 370 | #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) |
| 371 | |
| 372 | static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq, |
| 373 | qemu_irq *cpu_irqs, unsigned int num_cpus) |
| 374 | { |
| 375 | DeviceState *dev; |
| 376 | SysBusDevice *s; |
| 377 | unsigned int i; |
| 378 | |
| 379 | dev = qdev_new("slavio_timer"); |
| 380 | qdev_prop_set_uint32(dev, "num_cpus", num_cpus); |
| 381 | s = SYS_BUS_DEVICE(dev); |
| 382 | sysbus_realize_and_unref(s, &error_fatal); |
| 383 | sysbus_connect_irq(s, 0, master_irq); |
| 384 | sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET); |
| 385 | |
| 386 | for (i = 0; i < MAX_CPUS; i++) { |
| 387 | sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i)); |
| 388 | sysbus_connect_irq(s, i + 1, cpu_irqs[i]); |
| 389 | } |
| 390 | } |
| 391 | |
| 392 | static qemu_irq slavio_system_powerdown; |
| 393 | |
| 394 | static void slavio_powerdown_req(Notifier *n, void *opaque) |
| 395 | { |
| 396 | qemu_irq_raise(slavio_system_powerdown); |
| 397 | } |
| 398 | |
| 399 | static Notifier slavio_system_powerdown_notifier = { |
| 400 | .notify = slavio_powerdown_req |
| 401 | }; |
| 402 | |
| 403 | #define MISC_LEDS 0x01600000 |
| 404 | #define MISC_CFG 0x01800000 |
| 405 | #define MISC_DIAG 0x01a00000 |
| 406 | #define MISC_MDM 0x01b00000 |
| 407 | #define MISC_SYS 0x01f00000 |
| 408 | |
| 409 | static void slavio_misc_init(hwaddr base, |
| 410 | hwaddr aux1_base, |
| 411 | hwaddr aux2_base, qemu_irq irq, |
| 412 | qemu_irq fdc_tc) |
| 413 | { |
| 414 | DeviceState *dev; |
| 415 | SysBusDevice *s; |
| 416 | |
| 417 | dev = qdev_new("slavio_misc"); |
| 418 | s = SYS_BUS_DEVICE(dev); |
| 419 | sysbus_realize_and_unref(s, &error_fatal); |
| 420 | if (base) { |
| 421 | /* 8 bit registers */ |
| 422 | /* Slavio control */ |
| 423 | sysbus_mmio_map(s, 0, base + MISC_CFG); |
| 424 | /* Diagnostics */ |
| 425 | sysbus_mmio_map(s, 1, base + MISC_DIAG); |
| 426 | /* Modem control */ |
| 427 | sysbus_mmio_map(s, 2, base + MISC_MDM); |
| 428 | /* 16 bit registers */ |
| 429 | /* ss600mp diag LEDs */ |
| 430 | sysbus_mmio_map(s, 3, base + MISC_LEDS); |
| 431 | /* 32 bit registers */ |
| 432 | /* System control */ |
| 433 | sysbus_mmio_map(s, 4, base + MISC_SYS); |
| 434 | } |
| 435 | if (aux1_base) { |
| 436 | /* AUX 1 (Misc System Functions) */ |
| 437 | sysbus_mmio_map(s, 5, aux1_base); |
| 438 | } |
| 439 | if (aux2_base) { |
| 440 | /* AUX 2 (Software Powerdown Control) */ |
| 441 | sysbus_mmio_map(s, 6, aux2_base); |
| 442 | } |
| 443 | sysbus_connect_irq(s, 0, irq); |
| 444 | sysbus_connect_irq(s, 1, fdc_tc); |
| 445 | slavio_system_powerdown = qdev_get_gpio_in(dev, 0); |
| 446 | qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier); |
| 447 | } |
| 448 | |
| 449 | static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version) |
| 450 | { |
| 451 | DeviceState *dev; |
| 452 | SysBusDevice *s; |
| 453 | |
| 454 | dev = qdev_new("eccmemctl"); |
| 455 | qdev_prop_set_uint32(dev, "version", version); |
| 456 | s = SYS_BUS_DEVICE(dev); |
| 457 | sysbus_realize_and_unref(s, &error_fatal); |
| 458 | sysbus_connect_irq(s, 0, irq); |
| 459 | sysbus_mmio_map(s, 0, base); |
| 460 | if (version == 0) { // SS-600MP only |
| 461 | sysbus_mmio_map(s, 1, base + 0x1000); |
| 462 | } |
| 463 | } |
| 464 | |
| 465 | static void apc_init(hwaddr power_base, qemu_irq cpu_halt) |
| 466 | { |
| 467 | DeviceState *dev; |
| 468 | SysBusDevice *s; |
| 469 | |
| 470 | dev = qdev_new("apc"); |
| 471 | s = SYS_BUS_DEVICE(dev); |
| 472 | sysbus_realize_and_unref(s, &error_fatal); |
| 473 | /* Power management (APC) XXX: not a Slavio device */ |
| 474 | sysbus_mmio_map(s, 0, power_base); |
| 475 | sysbus_connect_irq(s, 0, cpu_halt); |
| 476 | } |
| 477 | |
| 478 | static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width, |
| 479 | int height, int depth) |
| 480 | { |
| 481 | DeviceState *dev; |
| 482 | SysBusDevice *s; |
| 483 | |
| 484 | dev = qdev_new("sun-tcx"); |
| 485 | qdev_prop_set_uint32(dev, "vram_size", vram_size); |
| 486 | qdev_prop_set_uint16(dev, "width", width); |
| 487 | qdev_prop_set_uint16(dev, "height", height); |
| 488 | qdev_prop_set_uint16(dev, "depth", depth); |
| 489 | s = SYS_BUS_DEVICE(dev); |
| 490 | sysbus_realize_and_unref(s, &error_fatal); |
| 491 | |
| 492 | /* 10/ROM : FCode ROM */ |
| 493 | sysbus_mmio_map(s, 0, addr); |
| 494 | /* 2/STIP : Stipple */ |
| 495 | sysbus_mmio_map(s, 1, addr + 0x04000000ULL); |
| 496 | /* 3/BLIT : Blitter */ |
| 497 | sysbus_mmio_map(s, 2, addr + 0x06000000ULL); |
| 498 | /* 5/RSTIP : Raw Stipple */ |
| 499 | sysbus_mmio_map(s, 3, addr + 0x0c000000ULL); |
| 500 | /* 6/RBLIT : Raw Blitter */ |
| 501 | sysbus_mmio_map(s, 4, addr + 0x0e000000ULL); |
| 502 | /* 7/TEC : Transform Engine */ |
| 503 | sysbus_mmio_map(s, 5, addr + 0x00700000ULL); |
| 504 | /* 8/CMAP : DAC */ |
| 505 | sysbus_mmio_map(s, 6, addr + 0x00200000ULL); |
| 506 | /* 9/THC : */ |
| 507 | if (depth == 8) { |
| 508 | sysbus_mmio_map(s, 7, addr + 0x00300000ULL); |
| 509 | } else { |
| 510 | sysbus_mmio_map(s, 7, addr + 0x00301000ULL); |
| 511 | } |
| 512 | /* 11/DHC : */ |
| 513 | sysbus_mmio_map(s, 8, addr + 0x00240000ULL); |
| 514 | /* 12/ALT : */ |
| 515 | sysbus_mmio_map(s, 9, addr + 0x00280000ULL); |
| 516 | /* 0/DFB8 : 8-bit plane */ |
| 517 | sysbus_mmio_map(s, 10, addr + 0x00800000ULL); |
| 518 | /* 1/DFB24 : 24bit plane */ |
| 519 | sysbus_mmio_map(s, 11, addr + 0x02000000ULL); |
| 520 | /* 4/RDFB32: Raw framebuffer. Control plane */ |
| 521 | sysbus_mmio_map(s, 12, addr + 0x0a000000ULL); |
| 522 | /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */ |
| 523 | if (depth == 8) { |
| 524 | sysbus_mmio_map(s, 13, addr + 0x00301000ULL); |
| 525 | } |
| 526 | |
| 527 | sysbus_connect_irq(s, 0, irq); |
| 528 | } |
| 529 | |
| 530 | static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width, |
| 531 | int height, int depth) |
| 532 | { |
| 533 | DeviceState *dev; |
| 534 | SysBusDevice *s; |
| 535 | |
| 536 | dev = qdev_new("cgthree"); |
| 537 | qdev_prop_set_uint32(dev, "vram-size", vram_size); |
| 538 | qdev_prop_set_uint16(dev, "width", width); |
| 539 | qdev_prop_set_uint16(dev, "height", height); |
| 540 | qdev_prop_set_uint16(dev, "depth", depth); |
| 541 | s = SYS_BUS_DEVICE(dev); |
| 542 | sysbus_realize_and_unref(s, &error_fatal); |
| 543 | |
| 544 | /* FCode ROM */ |
| 545 | sysbus_mmio_map(s, 0, addr); |
| 546 | /* DAC */ |
| 547 | sysbus_mmio_map(s, 1, addr + 0x400000ULL); |
| 548 | /* 8-bit plane */ |
| 549 | sysbus_mmio_map(s, 2, addr + 0x800000ULL); |
| 550 | |
| 551 | sysbus_connect_irq(s, 0, irq); |
| 552 | } |
| 553 | |
| 554 | /* NCR89C100/MACIO Internal ID register */ |
| 555 | |
| 556 | #define TYPE_MACIO_ID_REGISTER "macio_idreg" |
| 557 | |
| 558 | static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; |
| 559 | |
| 560 | static void idreg_init(hwaddr addr) |
| 561 | { |
| 562 | DeviceState *dev; |
| 563 | SysBusDevice *s; |
| 564 | |
| 565 | dev = qdev_new(TYPE_MACIO_ID_REGISTER); |
| 566 | s = SYS_BUS_DEVICE(dev); |
| 567 | sysbus_realize_and_unref(s, &error_fatal); |
| 568 | |
| 569 | sysbus_mmio_map(s, 0, addr); |
| 570 | address_space_write_rom(&address_space_memory, addr, |
| 571 | MEMTXATTRS_UNSPECIFIED, |
| 572 | idreg_data, sizeof(idreg_data)); |
| 573 | } |
| 574 | |
| 575 | OBJECT_DECLARE_SIMPLE_TYPE(IDRegState, MACIO_ID_REGISTER) |
| 576 | |
| 577 | struct IDRegState { |
| 578 | SysBusDevice parent_obj; |
| 579 | |
| 580 | MemoryRegion mem; |
| 581 | }; |
| 582 | |
| 583 | static void idreg_realize(DeviceState *ds, Error **errp) |
| 584 | { |
| 585 | IDRegState *s = MACIO_ID_REGISTER(ds); |
| 586 | SysBusDevice *dev = SYS_BUS_DEVICE(ds); |
| 587 | |
| 588 | if (!memory_region_init_rom(&s->mem, OBJECT(ds), "sun4m.idreg", |
| 589 | sizeof(idreg_data), errp)) { |
| 590 | return; |
| 591 | } |
| 592 | sysbus_init_mmio(dev, &s->mem); |
| 593 | } |
| 594 | |
| 595 | static void idreg_class_init(ObjectClass *oc, const void *data) |
| 596 | { |
| 597 | DeviceClass *dc = DEVICE_CLASS(oc); |
| 598 | |
| 599 | dc->realize = idreg_realize; |
| 600 | } |
| 601 | |
| 602 | static const TypeInfo idreg_info = { |
| 603 | .name = TYPE_MACIO_ID_REGISTER, |
| 604 | .parent = TYPE_SYS_BUS_DEVICE, |
| 605 | .instance_size = sizeof(IDRegState), |
| 606 | .class_init = idreg_class_init, |
| 607 | }; |
| 608 | |
| 609 | #define TYPE_TCX_AFX "tcx_afx" |
| 610 | OBJECT_DECLARE_SIMPLE_TYPE(AFXState, TCX_AFX) |
| 611 | |
| 612 | struct AFXState { |
| 613 | SysBusDevice parent_obj; |
| 614 | |
| 615 | MemoryRegion mem; |
| 616 | }; |
| 617 | |
| 618 | /* SS-5 TCX AFX register */ |
| 619 | static void afx_init(hwaddr addr) |
| 620 | { |
| 621 | DeviceState *dev; |
| 622 | SysBusDevice *s; |
| 623 | |
| 624 | dev = qdev_new(TYPE_TCX_AFX); |
| 625 | s = SYS_BUS_DEVICE(dev); |
| 626 | sysbus_realize_and_unref(s, &error_fatal); |
| 627 | |
| 628 | sysbus_mmio_map(s, 0, addr); |
| 629 | } |
| 630 | |
| 631 | static void afx_realize(DeviceState *ds, Error **errp) |
| 632 | { |
| 633 | AFXState *s = TCX_AFX(ds); |
| 634 | SysBusDevice *dev = SYS_BUS_DEVICE(ds); |
| 635 | |
| 636 | if (!memory_region_init_ram(&s->mem, OBJECT(ds), "sun4m.afx", 4, errp)) { |
| 637 | return; |
| 638 | } |
| 639 | sysbus_init_mmio(dev, &s->mem); |
| 640 | } |
| 641 | |
| 642 | static void afx_class_init(ObjectClass *oc, const void *data) |
| 643 | { |
| 644 | DeviceClass *dc = DEVICE_CLASS(oc); |
| 645 | |
| 646 | dc->realize = afx_realize; |
| 647 | } |
| 648 | |
| 649 | static const TypeInfo afx_info = { |
| 650 | .name = TYPE_TCX_AFX, |
| 651 | .parent = TYPE_SYS_BUS_DEVICE, |
| 652 | .instance_size = sizeof(AFXState), |
| 653 | .class_init = afx_class_init, |
| 654 | }; |
| 655 | |
| 656 | #define TYPE_OPENPROM "openprom" |
| 657 | typedef struct PROMState PROMState; |
| 658 | DECLARE_INSTANCE_CHECKER(PROMState, OPENPROM, |
| 659 | TYPE_OPENPROM) |
| 660 | |
| 661 | struct PROMState { |
| 662 | SysBusDevice parent_obj; |
| 663 | |
| 664 | MemoryRegion prom; |
| 665 | }; |
| 666 | |
| 667 | /* Boot PROM (OpenBIOS) */ |
| 668 | static uint64_t translate_prom_address(void *opaque, uint64_t addr) |
| 669 | { |
| 670 | hwaddr *base_addr = (hwaddr *)opaque; |
| 671 | return addr + *base_addr - PROM_VADDR; |
| 672 | } |
| 673 | |
| 674 | static void prom_init(hwaddr addr, const char *bios_name) |
| 675 | { |
| 676 | DeviceState *dev; |
| 677 | SysBusDevice *s; |
| 678 | char *filename; |
| 679 | int ret; |
| 680 | |
| 681 | dev = qdev_new(TYPE_OPENPROM); |
| 682 | s = SYS_BUS_DEVICE(dev); |
| 683 | sysbus_realize_and_unref(s, &error_fatal); |
| 684 | |
| 685 | sysbus_mmio_map(s, 0, addr); |
| 686 | |
| 687 | /* load boot prom */ |
| 688 | if (bios_name == NULL) { |
| 689 | bios_name = PROM_FILENAME; |
| 690 | } |
| 691 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
| 692 | if (filename) { |
| 693 | ret = load_elf(filename, NULL, |
| 694 | translate_prom_address, &addr, NULL, |
| 695 | NULL, NULL, NULL, ELFDATA2MSB, EM_SPARC, 0, 0); |
| 696 | if (ret < 0 || ret > PROM_SIZE_MAX) { |
| 697 | ret = load_image_targphys(filename, addr, PROM_SIZE_MAX, NULL); |
| 698 | } |
| 699 | g_free(filename); |
| 700 | } else { |
| 701 | ret = -1; |
| 702 | } |
| 703 | if (ret < 0 || ret > PROM_SIZE_MAX) { |
| 704 | error_report("could not load prom '%s'", bios_name); |
| 705 | exit(1); |
| 706 | } |
| 707 | } |
| 708 | |
| 709 | static void prom_realize(DeviceState *ds, Error **errp) |
| 710 | { |
| 711 | PROMState *s = OPENPROM(ds); |
| 712 | SysBusDevice *dev = SYS_BUS_DEVICE(ds); |
| 713 | |
| 714 | if (!memory_region_init_rom(&s->prom, OBJECT(ds), "sun4m.prom", |
| 715 | PROM_SIZE_MAX, errp)) { |
| 716 | return; |
| 717 | } |
| 718 | sysbus_init_mmio(dev, &s->prom); |
| 719 | } |
| 720 | |
| 721 | static void prom_class_init(ObjectClass *klass, const void *data) |
| 722 | { |
| 723 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 724 | |
| 725 | dc->realize = prom_realize; |
| 726 | } |
| 727 | |
| 728 | static const TypeInfo prom_info = { |
| 729 | .name = TYPE_OPENPROM, |
| 730 | .parent = TYPE_SYS_BUS_DEVICE, |
| 731 | .instance_size = sizeof(PROMState), |
| 732 | .class_init = prom_class_init, |
| 733 | }; |
| 734 | |
| 735 | #define TYPE_SUN4M_MEMORY "memory" |
| 736 | typedef struct RamDevice RamDevice; |
| 737 | DECLARE_INSTANCE_CHECKER(RamDevice, SUN4M_RAM, |
| 738 | TYPE_SUN4M_MEMORY) |
| 739 | |
| 740 | struct RamDevice { |
| 741 | SysBusDevice parent_obj; |
| 742 | HostMemoryBackend *memdev; |
| 743 | }; |
| 744 | |
| 745 | /* System RAM */ |
| 746 | static void ram_realize(DeviceState *dev, Error **errp) |
| 747 | { |
| 748 | RamDevice *d = SUN4M_RAM(dev); |
| 749 | MemoryRegion *ram = host_memory_backend_get_memory(d->memdev); |
| 750 | |
| 751 | sysbus_init_mmio(SYS_BUS_DEVICE(dev), ram); |
| 752 | } |
| 753 | |
| 754 | static void ram_initfn(Object *obj) |
| 755 | { |
| 756 | RamDevice *d = SUN4M_RAM(obj); |
| 757 | object_property_add_link(obj, "memdev", TYPE_MEMORY_BACKEND, |
| 758 | (Object **)&d->memdev, |
| 759 | object_property_allow_set_link, |
| 760 | OBJ_PROP_LINK_STRONG); |
| 761 | object_property_set_description(obj, "memdev", "Set RAM backend" |
| 762 | "Valid value is ID of a hostmem backend"); |
| 763 | } |
| 764 | |
| 765 | static void ram_class_init(ObjectClass *klass, const void *data) |
| 766 | { |
| 767 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 768 | |
| 769 | dc->realize = ram_realize; |
| 770 | } |
| 771 | |
| 772 | static const TypeInfo ram_info = { |
| 773 | .name = TYPE_SUN4M_MEMORY, |
| 774 | .parent = TYPE_SYS_BUS_DEVICE, |
| 775 | .instance_size = sizeof(RamDevice), |
| 776 | .instance_init = ram_initfn, |
| 777 | .class_init = ram_class_init, |
| 778 | }; |
| 779 | |
| 780 | static DeviceState *cpu_devinit(const char *cpu_type, unsigned int id, |
| 781 | uint64_t prom_addr) |
| 782 | { |
| 783 | SPARCCPU *cpu; |
| 784 | CPUSPARCState *env; |
| 785 | DeviceState *cpudev; |
| 786 | |
| 787 | cpu = SPARC_CPU(object_new(cpu_type)); |
| 788 | env = &cpu->env; |
| 789 | cpudev = DEVICE(cpu); |
| 790 | |
| 791 | qemu_register_reset(sun4m_cpu_reset, cpu); |
| 792 | object_property_set_bool(OBJECT(cpu), "start-powered-off", id != 0, |
| 793 | &error_abort); |
| 794 | qdev_init_gpio_in_named(cpudev, cpu_set_irq, "pil", MAX_PILS); |
| 795 | qdev_realize_and_unref(cpudev, NULL, &error_fatal); |
| 796 | cpu_sparc_set_id(env, id); |
| 797 | env->prom_addr = prom_addr; |
| 798 | return cpudev; |
| 799 | } |
| 800 | |
| 801 | static void dummy_fdc_tc(void *opaque, int irq, int level) |
| 802 | { |
| 803 | } |
| 804 | |
| 805 | static void sun4m_hw_init(MachineState *machine) |
| 806 | { |
| 807 | const struct sun4m_hwdef *hwdef = SUN4M_MACHINE_GET_CLASS(machine)->hwdef; |
| 808 | DeviceState *slavio_intctl; |
| 809 | unsigned int i; |
| 810 | Nvram *nvram; |
| 811 | qemu_irq slavio_irq[32], slavio_cpu_irq[MAX_CPUS]; |
| 812 | qemu_irq fdc_tc; |
| 813 | unsigned long kernel_size; |
| 814 | uint32_t initrd_size; |
| 815 | DriveInfo *fd[MAX_FD]; |
| 816 | FWCfgState *fw_cfg; |
| 817 | DeviceState *dev, *ms_kb_orgate, *serial_orgate; |
| 818 | DeviceState *cpus[MAX_CPUS]; |
| 819 | SysBusDevice *s; |
| 820 | unsigned int smp_cpus = machine->smp.cpus; |
| 821 | unsigned int max_cpus = machine->smp.max_cpus; |
| 822 | HostMemoryBackend *ram_memdev = machine->memdev; |
| 823 | MACAddr hostid; |
| 824 | |
| 825 | if (machine->ram_size > hwdef->max_mem) { |
| 826 | error_report("Too much memory for this machine: %" PRId64 "," |
| 827 | " maximum %" PRId64, |
| 828 | machine->ram_size / MiB, hwdef->max_mem / MiB); |
| 829 | exit(1); |
| 830 | } |
| 831 | |
| 832 | /* init CPUs */ |
| 833 | for(i = 0; i < smp_cpus; i++) { |
| 834 | cpus[i] = cpu_devinit(machine->cpu_type, i, hwdef->slavio_base); |
| 835 | } |
| 836 | |
| 837 | /* Create and map RAM frontend */ |
| 838 | dev = qdev_new("memory"); |
| 839 | object_property_set_link(OBJECT(dev), "memdev", OBJECT(ram_memdev), &error_fatal); |
| 840 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
| 841 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0); |
| 842 | |
| 843 | /* models without ECC don't trap when missing ram is accessed */ |
| 844 | if (!hwdef->ecc_base) { |
| 845 | empty_slot_init("ecc", machine->ram_size, |
| 846 | hwdef->max_mem - machine->ram_size); |
| 847 | } |
| 848 | |
| 849 | prom_init(hwdef->slavio_base, machine->firmware); |
| 850 | |
| 851 | slavio_intctl = slavio_intctl_init(hwdef->intctl_base, |
| 852 | hwdef->intctl_base + 0x10000ULL, |
| 853 | smp_cpus, |
| 854 | cpus); |
| 855 | |
| 856 | for (i = 0; i < 32; i++) { |
| 857 | slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i); |
| 858 | } |
| 859 | for (i = 0; i < MAX_CPUS; i++) { |
| 860 | slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i); |
| 861 | } |
| 862 | |
| 863 | if (hwdef->idreg_base) { |
| 864 | idreg_init(hwdef->idreg_base); |
| 865 | } |
| 866 | |
| 867 | if (hwdef->afx_base) { |
| 868 | afx_init(hwdef->afx_base); |
| 869 | } |
| 870 | |
| 871 | iommu_init(hwdef->iommu_base, hwdef->iommu_version, slavio_irq[30]); |
| 872 | |
| 873 | if (hwdef->iommu_pad_base) { |
| 874 | /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased. |
| 875 | Software shouldn't use aliased addresses, neither should it crash |
| 876 | when does. Using empty_slot instead of aliasing can help with |
| 877 | debugging such accesses */ |
| 878 | empty_slot_init("iommu.alias", |
| 879 | hwdef->iommu_pad_base, hwdef->iommu_pad_len); |
| 880 | } |
| 881 | |
| 882 | sparc32_dma_init(hwdef->dma_base, |
| 883 | hwdef->esp_base, slavio_irq[18], |
| 884 | hwdef->le_base, slavio_irq[16], &hostid); |
| 885 | |
| 886 | if (!graphic_width) { |
| 887 | graphic_width = 1024; |
| 888 | } |
| 889 | if (!graphic_height) { |
| 890 | graphic_height = 768; |
| 891 | } |
| 892 | if (!graphic_depth) { |
| 893 | graphic_depth = 8; |
| 894 | } |
| 895 | if (graphic_depth != 8 && graphic_depth != 24) { |
| 896 | error_report("Unsupported depth: %d", graphic_depth); |
| 897 | exit (1); |
| 898 | } |
| 899 | if (vga_interface_type != VGA_NONE) { |
| 900 | if (vga_interface_type == VGA_CG3) { |
| 901 | if (graphic_depth != 8) { |
| 902 | error_report("Unsupported depth: %d", graphic_depth); |
| 903 | exit(1); |
| 904 | } |
| 905 | |
| 906 | if (!(graphic_width == 1024 && graphic_height == 768) && |
| 907 | !(graphic_width == 1152 && graphic_height == 900)) { |
| 908 | error_report("Unsupported resolution: %d x %d", graphic_width, |
| 909 | graphic_height); |
| 910 | exit(1); |
| 911 | } |
| 912 | |
| 913 | /* sbus irq 5 */ |
| 914 | cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, |
| 915 | graphic_width, graphic_height, graphic_depth); |
| 916 | vga_interface_created = true; |
| 917 | } else { |
| 918 | /* If no display specified, default to TCX */ |
| 919 | if (graphic_depth != 8 && graphic_depth != 24) { |
| 920 | error_report("Unsupported depth: %d", graphic_depth); |
| 921 | exit(1); |
| 922 | } |
| 923 | |
| 924 | if (!(graphic_width == 1024 && graphic_height == 768)) { |
| 925 | error_report("Unsupported resolution: %d x %d", |
| 926 | graphic_width, graphic_height); |
| 927 | exit(1); |
| 928 | } |
| 929 | |
| 930 | tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, |
| 931 | graphic_width, graphic_height, graphic_depth); |
| 932 | vga_interface_created = true; |
| 933 | } |
| 934 | } |
| 935 | |
| 936 | for (i = 0; i < MAX_VSIMMS; i++) { |
| 937 | /* vsimm registers probed by OBP */ |
| 938 | if (hwdef->vsimm[i].reg_base) { |
| 939 | char *name = g_strdup_printf("vsimm[%d]", i); |
| 940 | empty_slot_init(name, hwdef->vsimm[i].reg_base, 0x2000); |
| 941 | g_free(name); |
| 942 | } |
| 943 | } |
| 944 | |
| 945 | if (hwdef->sx_base) { |
| 946 | create_unimplemented_device("sun-sx", hwdef->sx_base, 0x2000); |
| 947 | } |
| 948 | |
| 949 | dev = qdev_new("sysbus-m48t08"); |
| 950 | qdev_prop_set_int32(dev, "base-year", 1968); |
| 951 | s = SYS_BUS_DEVICE(dev); |
| 952 | sysbus_realize_and_unref(s, &error_fatal); |
| 953 | sysbus_connect_irq(s, 0, slavio_irq[0]); |
| 954 | sysbus_mmio_map(s, 0, hwdef->nvram_base); |
| 955 | nvram = NVRAM(dev); |
| 956 | |
| 957 | slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus); |
| 958 | |
| 959 | /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device |
| 960 | Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */ |
| 961 | dev = qdev_new(TYPE_ESCC); |
| 962 | qdev_prop_set_uint32(dev, "disabled", !machine->enable_graphics); |
| 963 | qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK); |
| 964 | qdev_prop_set_uint32(dev, "it_shift", 1); |
| 965 | qdev_prop_set_chr(dev, "chrB", NULL); |
| 966 | qdev_prop_set_chr(dev, "chrA", NULL); |
| 967 | qdev_prop_set_uint32(dev, "chnBtype", escc_mouse); |
| 968 | qdev_prop_set_uint32(dev, "chnAtype", escc_kbd); |
| 969 | s = SYS_BUS_DEVICE(dev); |
| 970 | sysbus_realize_and_unref(s, &error_fatal); |
| 971 | sysbus_mmio_map(s, 0, hwdef->ms_kb_base); |
| 972 | |
| 973 | /* Logically OR both its IRQs together */ |
| 974 | ms_kb_orgate = qdev_new(TYPE_OR_IRQ); |
| 975 | object_property_set_int(OBJECT(ms_kb_orgate), "num-lines", 2, &error_fatal); |
| 976 | qdev_realize_and_unref(ms_kb_orgate, NULL, &error_fatal); |
| 977 | sysbus_connect_irq(s, 0, qdev_get_gpio_in(ms_kb_orgate, 0)); |
| 978 | sysbus_connect_irq(s, 1, qdev_get_gpio_in(ms_kb_orgate, 1)); |
| 979 | qdev_connect_gpio_out(ms_kb_orgate, 0, slavio_irq[14]); |
| 980 | |
| 981 | dev = qdev_new(TYPE_ESCC); |
| 982 | qdev_prop_set_uint32(dev, "disabled", 0); |
| 983 | qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK); |
| 984 | qdev_prop_set_uint32(dev, "it_shift", 1); |
| 985 | qdev_prop_set_chr(dev, "chrB", serial_hd(1)); |
| 986 | qdev_prop_set_chr(dev, "chrA", serial_hd(0)); |
| 987 | qdev_prop_set_uint32(dev, "chnBtype", escc_serial); |
| 988 | qdev_prop_set_uint32(dev, "chnAtype", escc_serial); |
| 989 | |
| 990 | s = SYS_BUS_DEVICE(dev); |
| 991 | sysbus_realize_and_unref(s, &error_fatal); |
| 992 | sysbus_mmio_map(s, 0, hwdef->serial_base); |
| 993 | |
| 994 | /* Logically OR both its IRQs together */ |
| 995 | serial_orgate = qdev_new(TYPE_OR_IRQ); |
| 996 | object_property_set_int(OBJECT(serial_orgate), "num-lines", 2, |
| 997 | &error_fatal); |
| 998 | qdev_realize_and_unref(serial_orgate, NULL, &error_fatal); |
| 999 | sysbus_connect_irq(s, 0, qdev_get_gpio_in(serial_orgate, 0)); |
| 1000 | sysbus_connect_irq(s, 1, qdev_get_gpio_in(serial_orgate, 1)); |
| 1001 | qdev_connect_gpio_out(serial_orgate, 0, slavio_irq[15]); |
| 1002 | |
| 1003 | if (hwdef->apc_base) { |
| 1004 | apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0)); |
| 1005 | } |
| 1006 | |
| 1007 | if (hwdef->fd_base) { |
| 1008 | /* there is zero or one floppy drive */ |
| 1009 | memset(fd, 0, sizeof(fd)); |
| 1010 | fd[0] = drive_get(IF_FLOPPY, 0, 0); |
| 1011 | sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd, |
| 1012 | &fdc_tc); |
| 1013 | } else { |
| 1014 | fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0); |
| 1015 | } |
| 1016 | |
| 1017 | slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base, |
| 1018 | slavio_irq[30], fdc_tc); |
| 1019 | |
| 1020 | if (hwdef->cs_base) { |
| 1021 | sysbus_create_simple("sun-CS4231", hwdef->cs_base, |
| 1022 | slavio_irq[5]); |
| 1023 | } |
| 1024 | |
| 1025 | if (hwdef->dbri_base) { |
| 1026 | /* ISDN chip with attached CS4215 audio codec */ |
| 1027 | /* prom space */ |
| 1028 | create_unimplemented_device("sun-DBRI.prom", |
| 1029 | hwdef->dbri_base + 0x1000, 0x30); |
| 1030 | /* reg space */ |
| 1031 | create_unimplemented_device("sun-DBRI", |
| 1032 | hwdef->dbri_base + 0x10000, 0x100); |
| 1033 | } |
| 1034 | |
| 1035 | if (hwdef->bpp_base) { |
| 1036 | /* parallel port */ |
| 1037 | create_unimplemented_device("sun-bpp", hwdef->bpp_base, 0x20); |
| 1038 | } |
| 1039 | |
| 1040 | initrd_size = 0; |
| 1041 | kernel_size = sun4m_load_kernel(machine->kernel_filename, |
| 1042 | machine->initrd_filename, |
| 1043 | machine->ram_size, &initrd_size); |
| 1044 | |
| 1045 | nvram_init(nvram, hostid.a, machine->kernel_cmdline, |
| 1046 | machine->boot_config.order, machine->ram_size, kernel_size, |
| 1047 | graphic_width, graphic_height, graphic_depth, |
| 1048 | hwdef->nvram_machine_id, "Sun4m"); |
| 1049 | |
| 1050 | if (hwdef->ecc_base) |
| 1051 | ecc_init(hwdef->ecc_base, slavio_irq[28], |
| 1052 | hwdef->ecc_version); |
| 1053 | |
| 1054 | dev = qdev_new(TYPE_FW_CFG_MEM); |
| 1055 | fw_cfg = FW_CFG(dev); |
| 1056 | qdev_prop_set_uint32(dev, "data_width", 1); |
| 1057 | qdev_prop_set_bit(dev, "dma_enabled", false); |
| 1058 | object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, |
| 1059 | OBJECT(fw_cfg)); |
| 1060 | s = SYS_BUS_DEVICE(dev); |
| 1061 | sysbus_realize_and_unref(s, &error_fatal); |
| 1062 | sysbus_mmio_map(s, 0, CFG_ADDR); |
| 1063 | sysbus_mmio_map(s, 1, CFG_ADDR + 2); |
| 1064 | |
| 1065 | fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); |
| 1066 | fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); |
| 1067 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size); |
| 1068 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
| 1069 | fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); |
| 1070 | fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width); |
| 1071 | fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height); |
| 1072 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
| 1073 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
| 1074 | if (machine->kernel_cmdline) { |
| 1075 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); |
| 1076 | pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, |
| 1077 | machine->kernel_cmdline); |
| 1078 | fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); |
| 1079 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, |
| 1080 | strlen(machine->kernel_cmdline) + 1); |
| 1081 | } else { |
| 1082 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); |
| 1083 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); |
| 1084 | } |
| 1085 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); |
| 1086 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); |
| 1087 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_config.order[0]); |
| 1088 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
| 1089 | } |
| 1090 | |
| 1091 | enum { |
| 1092 | ss5_id = 32, |
| 1093 | vger_id, |
| 1094 | lx_id, |
| 1095 | ss4_id, |
| 1096 | scls_id, |
| 1097 | sbook_id, |
| 1098 | ss10_id = 64, |
| 1099 | ss20_id, |
| 1100 | ss600mp_id, |
| 1101 | }; |
| 1102 | |
| 1103 | static void sun4m_machine_class_init(ObjectClass *oc, const void *data) |
| 1104 | { |
| 1105 | MachineClass *mc = MACHINE_CLASS(oc); |
| 1106 | |
| 1107 | mc->init = sun4m_hw_init; |
| 1108 | mc->block_default_type = IF_SCSI; |
| 1109 | mc->default_boot_order = "c"; |
| 1110 | mc->default_display = "tcx"; |
| 1111 | mc->default_ram_id = "sun4m.ram"; |
| 1112 | } |
| 1113 | |
| 1114 | static void ss5_class_init(ObjectClass *oc, const void *data) |
| 1115 | { |
| 1116 | MachineClass *mc = MACHINE_CLASS(oc); |
| 1117 | Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); |
| 1118 | static const struct sun4m_hwdef ss5_hwdef = { |
| 1119 | .iommu_base = 0x10000000, |
| 1120 | .iommu_pad_base = 0x10004000, |
| 1121 | .iommu_pad_len = 0x0fffb000, |
| 1122 | .tcx_base = 0x50000000, |
| 1123 | .cs_base = 0x6c000000, |
| 1124 | .slavio_base = 0x70000000, |
| 1125 | .ms_kb_base = 0x71000000, |
| 1126 | .serial_base = 0x71100000, |
| 1127 | .nvram_base = 0x71200000, |
| 1128 | .fd_base = 0x71400000, |
| 1129 | .counter_base = 0x71d00000, |
| 1130 | .intctl_base = 0x71e00000, |
| 1131 | .idreg_base = 0x78000000, |
| 1132 | .dma_base = 0x78400000, |
| 1133 | .esp_base = 0x78800000, |
| 1134 | .le_base = 0x78c00000, |
| 1135 | .apc_base = 0x6a000000, |
| 1136 | .afx_base = 0x6e000000, |
| 1137 | .aux1_base = 0x71900000, |
| 1138 | .aux2_base = 0x71910000, |
| 1139 | .nvram_machine_id = 0x80, |
| 1140 | .machine_id = ss5_id, |
| 1141 | .iommu_version = 0x05000000, |
| 1142 | .max_mem = 0x10000000, |
| 1143 | }; |
| 1144 | |
| 1145 | mc->desc = "Sun4m platform, SPARCstation 5"; |
| 1146 | mc->is_default = true; |
| 1147 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); |
| 1148 | smc->hwdef = &ss5_hwdef; |
| 1149 | } |
| 1150 | |
| 1151 | static void ss10_class_init(ObjectClass *oc, const void *data) |
| 1152 | { |
| 1153 | MachineClass *mc = MACHINE_CLASS(oc); |
| 1154 | Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); |
| 1155 | static const struct sun4m_hwdef ss10_hwdef = { |
| 1156 | .iommu_base = 0xfe0000000ULL, |
| 1157 | .tcx_base = 0xe20000000ULL, |
| 1158 | .slavio_base = 0xff0000000ULL, |
| 1159 | .ms_kb_base = 0xff1000000ULL, |
| 1160 | .serial_base = 0xff1100000ULL, |
| 1161 | .nvram_base = 0xff1200000ULL, |
| 1162 | .fd_base = 0xff1700000ULL, |
| 1163 | .counter_base = 0xff1300000ULL, |
| 1164 | .intctl_base = 0xff1400000ULL, |
| 1165 | .idreg_base = 0xef0000000ULL, |
| 1166 | .dma_base = 0xef0400000ULL, |
| 1167 | .esp_base = 0xef0800000ULL, |
| 1168 | .le_base = 0xef0c00000ULL, |
| 1169 | .apc_base = 0xefa000000ULL, /* XXX should not exist */ |
| 1170 | .aux1_base = 0xff1800000ULL, |
| 1171 | .aux2_base = 0xff1a01000ULL, |
| 1172 | .ecc_base = 0xf00000000ULL, |
| 1173 | .ecc_version = 0x10000000, /* version 0, implementation 1 */ |
| 1174 | .nvram_machine_id = 0x72, |
| 1175 | .machine_id = ss10_id, |
| 1176 | .iommu_version = 0x03000000, |
| 1177 | .max_mem = 0xf00000000ULL, |
| 1178 | }; |
| 1179 | |
| 1180 | mc->desc = "Sun4m platform, SPARCstation 10"; |
| 1181 | mc->max_cpus = 4; |
| 1182 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); |
| 1183 | smc->hwdef = &ss10_hwdef; |
| 1184 | } |
| 1185 | |
| 1186 | static void ss600mp_class_init(ObjectClass *oc, const void *data) |
| 1187 | { |
| 1188 | MachineClass *mc = MACHINE_CLASS(oc); |
| 1189 | Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); |
| 1190 | static const struct sun4m_hwdef ss600mp_hwdef = { |
| 1191 | .iommu_base = 0xfe0000000ULL, |
| 1192 | .tcx_base = 0xe20000000ULL, |
| 1193 | .slavio_base = 0xff0000000ULL, |
| 1194 | .ms_kb_base = 0xff1000000ULL, |
| 1195 | .serial_base = 0xff1100000ULL, |
| 1196 | .nvram_base = 0xff1200000ULL, |
| 1197 | .counter_base = 0xff1300000ULL, |
| 1198 | .intctl_base = 0xff1400000ULL, |
| 1199 | .dma_base = 0xef0081000ULL, |
| 1200 | .esp_base = 0xef0080000ULL, |
| 1201 | .le_base = 0xef0060000ULL, |
| 1202 | .apc_base = 0xefa000000ULL, /* XXX should not exist */ |
| 1203 | .aux1_base = 0xff1800000ULL, |
| 1204 | .aux2_base = 0xff1a01000ULL, /* XXX should not exist */ |
| 1205 | .ecc_base = 0xf00000000ULL, |
| 1206 | .ecc_version = 0x00000000, /* version 0, implementation 0 */ |
| 1207 | .nvram_machine_id = 0x71, |
| 1208 | .machine_id = ss600mp_id, |
| 1209 | .iommu_version = 0x01000000, |
| 1210 | .max_mem = 0xf00000000ULL, |
| 1211 | }; |
| 1212 | |
| 1213 | mc->desc = "Sun4m platform, SPARCserver 600MP"; |
| 1214 | mc->max_cpus = 4; |
| 1215 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); |
| 1216 | smc->hwdef = &ss600mp_hwdef; |
| 1217 | } |
| 1218 | |
| 1219 | static void ss20_class_init(ObjectClass *oc, const void *data) |
| 1220 | { |
| 1221 | MachineClass *mc = MACHINE_CLASS(oc); |
| 1222 | Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); |
| 1223 | static const struct sun4m_hwdef ss20_hwdef = { |
| 1224 | .iommu_base = 0xfe0000000ULL, |
| 1225 | .tcx_base = 0xe20000000ULL, |
| 1226 | .slavio_base = 0xff0000000ULL, |
| 1227 | .ms_kb_base = 0xff1000000ULL, |
| 1228 | .serial_base = 0xff1100000ULL, |
| 1229 | .nvram_base = 0xff1200000ULL, |
| 1230 | .fd_base = 0xff1700000ULL, |
| 1231 | .counter_base = 0xff1300000ULL, |
| 1232 | .intctl_base = 0xff1400000ULL, |
| 1233 | .idreg_base = 0xef0000000ULL, |
| 1234 | .dma_base = 0xef0400000ULL, |
| 1235 | .esp_base = 0xef0800000ULL, |
| 1236 | .le_base = 0xef0c00000ULL, |
| 1237 | .bpp_base = 0xef4800000ULL, |
| 1238 | .apc_base = 0xefa000000ULL, /* XXX should not exist */ |
| 1239 | .aux1_base = 0xff1800000ULL, |
| 1240 | .aux2_base = 0xff1a01000ULL, |
| 1241 | .dbri_base = 0xee0000000ULL, |
| 1242 | .sx_base = 0xf80000000ULL, |
| 1243 | .vsimm = { |
| 1244 | { |
| 1245 | .reg_base = 0x9c000000ULL, |
| 1246 | .vram_base = 0xfc000000ULL |
| 1247 | }, { |
| 1248 | .reg_base = 0x90000000ULL, |
| 1249 | .vram_base = 0xf0000000ULL |
| 1250 | }, { |
| 1251 | .reg_base = 0x94000000ULL |
| 1252 | }, { |
| 1253 | .reg_base = 0x98000000ULL |
| 1254 | } |
| 1255 | }, |
| 1256 | .ecc_base = 0xf00000000ULL, |
| 1257 | .ecc_version = 0x20000000, /* version 0, implementation 2 */ |
| 1258 | .nvram_machine_id = 0x72, |
| 1259 | .machine_id = ss20_id, |
| 1260 | .iommu_version = 0x13000000, |
| 1261 | .max_mem = 0xf00000000ULL, |
| 1262 | }; |
| 1263 | |
| 1264 | mc->desc = "Sun4m platform, SPARCstation 20"; |
| 1265 | mc->max_cpus = 4; |
| 1266 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); |
| 1267 | smc->hwdef = &ss20_hwdef; |
| 1268 | } |
| 1269 | |
| 1270 | static void voyager_class_init(ObjectClass *oc, const void *data) |
| 1271 | { |
| 1272 | MachineClass *mc = MACHINE_CLASS(oc); |
| 1273 | Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); |
| 1274 | static const struct sun4m_hwdef voyager_hwdef = { |
| 1275 | .iommu_base = 0x10000000, |
| 1276 | .tcx_base = 0x50000000, |
| 1277 | .slavio_base = 0x70000000, |
| 1278 | .ms_kb_base = 0x71000000, |
| 1279 | .serial_base = 0x71100000, |
| 1280 | .nvram_base = 0x71200000, |
| 1281 | .fd_base = 0x71400000, |
| 1282 | .counter_base = 0x71d00000, |
| 1283 | .intctl_base = 0x71e00000, |
| 1284 | .idreg_base = 0x78000000, |
| 1285 | .dma_base = 0x78400000, |
| 1286 | .esp_base = 0x78800000, |
| 1287 | .le_base = 0x78c00000, |
| 1288 | .apc_base = 0x71300000, /* pmc */ |
| 1289 | .aux1_base = 0x71900000, |
| 1290 | .aux2_base = 0x71910000, |
| 1291 | .nvram_machine_id = 0x80, |
| 1292 | .machine_id = vger_id, |
| 1293 | .iommu_version = 0x05000000, |
| 1294 | .max_mem = 0x10000000, |
| 1295 | }; |
| 1296 | |
| 1297 | mc->desc = "Sun4m platform, SPARCstation Voyager"; |
| 1298 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); |
| 1299 | smc->hwdef = &voyager_hwdef; |
| 1300 | } |
| 1301 | |
| 1302 | static void ss_lx_class_init(ObjectClass *oc, const void *data) |
| 1303 | { |
| 1304 | MachineClass *mc = MACHINE_CLASS(oc); |
| 1305 | Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); |
| 1306 | static const struct sun4m_hwdef ss_lx_hwdef = { |
| 1307 | .iommu_base = 0x10000000, |
| 1308 | .iommu_pad_base = 0x10004000, |
| 1309 | .iommu_pad_len = 0x0fffb000, |
| 1310 | .tcx_base = 0x50000000, |
| 1311 | .slavio_base = 0x70000000, |
| 1312 | .ms_kb_base = 0x71000000, |
| 1313 | .serial_base = 0x71100000, |
| 1314 | .nvram_base = 0x71200000, |
| 1315 | .fd_base = 0x71400000, |
| 1316 | .counter_base = 0x71d00000, |
| 1317 | .intctl_base = 0x71e00000, |
| 1318 | .idreg_base = 0x78000000, |
| 1319 | .dma_base = 0x78400000, |
| 1320 | .esp_base = 0x78800000, |
| 1321 | .le_base = 0x78c00000, |
| 1322 | .aux1_base = 0x71900000, |
| 1323 | .aux2_base = 0x71910000, |
| 1324 | .nvram_machine_id = 0x80, |
| 1325 | .machine_id = lx_id, |
| 1326 | .iommu_version = 0x04000000, |
| 1327 | .max_mem = 0x10000000, |
| 1328 | }; |
| 1329 | |
| 1330 | mc->desc = "Sun4m platform, SPARCstation LX"; |
| 1331 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); |
| 1332 | smc->hwdef = &ss_lx_hwdef; |
| 1333 | } |
| 1334 | |
| 1335 | static void ss4_class_init(ObjectClass *oc, const void *data) |
| 1336 | { |
| 1337 | MachineClass *mc = MACHINE_CLASS(oc); |
| 1338 | Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); |
| 1339 | static const struct sun4m_hwdef ss4_hwdef = { |
| 1340 | .iommu_base = 0x10000000, |
| 1341 | .tcx_base = 0x50000000, |
| 1342 | .cs_base = 0x6c000000, |
| 1343 | .slavio_base = 0x70000000, |
| 1344 | .ms_kb_base = 0x71000000, |
| 1345 | .serial_base = 0x71100000, |
| 1346 | .nvram_base = 0x71200000, |
| 1347 | .fd_base = 0x71400000, |
| 1348 | .counter_base = 0x71d00000, |
| 1349 | .intctl_base = 0x71e00000, |
| 1350 | .idreg_base = 0x78000000, |
| 1351 | .dma_base = 0x78400000, |
| 1352 | .esp_base = 0x78800000, |
| 1353 | .le_base = 0x78c00000, |
| 1354 | .apc_base = 0x6a000000, |
| 1355 | .aux1_base = 0x71900000, |
| 1356 | .aux2_base = 0x71910000, |
| 1357 | .nvram_machine_id = 0x80, |
| 1358 | .machine_id = ss4_id, |
| 1359 | .iommu_version = 0x05000000, |
| 1360 | .max_mem = 0x10000000, |
| 1361 | }; |
| 1362 | |
| 1363 | mc->desc = "Sun4m platform, SPARCstation 4"; |
| 1364 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); |
| 1365 | smc->hwdef = &ss4_hwdef; |
| 1366 | } |
| 1367 | |
| 1368 | static void scls_class_init(ObjectClass *oc, const void *data) |
| 1369 | { |
| 1370 | MachineClass *mc = MACHINE_CLASS(oc); |
| 1371 | Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); |
| 1372 | static const struct sun4m_hwdef scls_hwdef = { |
| 1373 | .iommu_base = 0x10000000, |
| 1374 | .tcx_base = 0x50000000, |
| 1375 | .slavio_base = 0x70000000, |
| 1376 | .ms_kb_base = 0x71000000, |
| 1377 | .serial_base = 0x71100000, |
| 1378 | .nvram_base = 0x71200000, |
| 1379 | .fd_base = 0x71400000, |
| 1380 | .counter_base = 0x71d00000, |
| 1381 | .intctl_base = 0x71e00000, |
| 1382 | .idreg_base = 0x78000000, |
| 1383 | .dma_base = 0x78400000, |
| 1384 | .esp_base = 0x78800000, |
| 1385 | .le_base = 0x78c00000, |
| 1386 | .apc_base = 0x6a000000, |
| 1387 | .aux1_base = 0x71900000, |
| 1388 | .aux2_base = 0x71910000, |
| 1389 | .nvram_machine_id = 0x80, |
| 1390 | .machine_id = scls_id, |
| 1391 | .iommu_version = 0x05000000, |
| 1392 | .max_mem = 0x10000000, |
| 1393 | }; |
| 1394 | |
| 1395 | mc->desc = "Sun4m platform, SPARCClassic"; |
| 1396 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); |
| 1397 | smc->hwdef = &scls_hwdef; |
| 1398 | } |
| 1399 | |
| 1400 | static void sbook_class_init(ObjectClass *oc, const void *data) |
| 1401 | { |
| 1402 | MachineClass *mc = MACHINE_CLASS(oc); |
| 1403 | Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); |
| 1404 | static const struct sun4m_hwdef sbook_hwdef = { |
| 1405 | .iommu_base = 0x10000000, |
| 1406 | .tcx_base = 0x50000000, /* XXX */ |
| 1407 | .slavio_base = 0x70000000, |
| 1408 | .ms_kb_base = 0x71000000, |
| 1409 | .serial_base = 0x71100000, |
| 1410 | .nvram_base = 0x71200000, |
| 1411 | .fd_base = 0x71400000, |
| 1412 | .counter_base = 0x71d00000, |
| 1413 | .intctl_base = 0x71e00000, |
| 1414 | .idreg_base = 0x78000000, |
| 1415 | .dma_base = 0x78400000, |
| 1416 | .esp_base = 0x78800000, |
| 1417 | .le_base = 0x78c00000, |
| 1418 | .apc_base = 0x6a000000, |
| 1419 | .aux1_base = 0x71900000, |
| 1420 | .aux2_base = 0x71910000, |
| 1421 | .nvram_machine_id = 0x80, |
| 1422 | .machine_id = sbook_id, |
| 1423 | .iommu_version = 0x05000000, |
| 1424 | .max_mem = 0x10000000, |
| 1425 | }; |
| 1426 | |
| 1427 | mc->desc = "Sun4m platform, SPARCbook"; |
| 1428 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); |
| 1429 | smc->hwdef = &sbook_hwdef; |
| 1430 | } |
| 1431 | |
| 1432 | static const TypeInfo sun4m_machine_types[] = { |
| 1433 | { |
| 1434 | .name = MACHINE_TYPE_NAME("SS-5"), |
| 1435 | .parent = TYPE_SUN4M_MACHINE, |
| 1436 | .class_init = ss5_class_init, |
| 1437 | }, { |
| 1438 | .name = MACHINE_TYPE_NAME("SS-10"), |
| 1439 | .parent = TYPE_SUN4M_MACHINE, |
| 1440 | .class_init = ss10_class_init, |
| 1441 | }, { |
| 1442 | .name = MACHINE_TYPE_NAME("SS-600MP"), |
| 1443 | .parent = TYPE_SUN4M_MACHINE, |
| 1444 | .class_init = ss600mp_class_init, |
| 1445 | }, { |
| 1446 | .name = MACHINE_TYPE_NAME("SS-20"), |
| 1447 | .parent = TYPE_SUN4M_MACHINE, |
| 1448 | .class_init = ss20_class_init, |
| 1449 | }, { |
| 1450 | .name = MACHINE_TYPE_NAME("Voyager"), |
| 1451 | .parent = TYPE_SUN4M_MACHINE, |
| 1452 | .class_init = voyager_class_init, |
| 1453 | }, { |
| 1454 | .name = MACHINE_TYPE_NAME("LX"), |
| 1455 | .parent = TYPE_SUN4M_MACHINE, |
| 1456 | .class_init = ss_lx_class_init, |
| 1457 | }, { |
| 1458 | .name = MACHINE_TYPE_NAME("SS-4"), |
| 1459 | .parent = TYPE_SUN4M_MACHINE, |
| 1460 | .class_init = ss4_class_init, |
| 1461 | }, { |
| 1462 | .name = MACHINE_TYPE_NAME("SPARCClassic"), |
| 1463 | .parent = TYPE_SUN4M_MACHINE, |
| 1464 | .class_init = scls_class_init, |
| 1465 | }, { |
| 1466 | .name = MACHINE_TYPE_NAME("SPARCbook"), |
| 1467 | .parent = TYPE_SUN4M_MACHINE, |
| 1468 | .class_init = sbook_class_init, |
| 1469 | }, { |
| 1470 | .name = TYPE_SUN4M_MACHINE, |
| 1471 | .parent = TYPE_MACHINE, |
| 1472 | .class_size = sizeof(Sun4mMachineClass), |
| 1473 | .class_init = sun4m_machine_class_init, |
| 1474 | .abstract = true, |
| 1475 | } |
| 1476 | }; |
| 1477 | |
| 1478 | DEFINE_TYPES(sun4m_machine_types) |
| 1479 | |
| 1480 | static void sun4m_register_types(void) |
| 1481 | { |
| 1482 | type_register_static(&idreg_info); |
| 1483 | type_register_static(&afx_info); |
| 1484 | type_register_static(&prom_info); |
| 1485 | type_register_static(&ram_info); |
| 1486 | } |
| 1487 | |
| 1488 | type_init(sun4m_register_types) |