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1 /*
2 * QEMU Sun4m iommu emulation
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "hw/core/irq.h"
27 #include "hw/core/qdev-properties.h"
28 #include "hw/sparc/sun4m_iommu.h"
29 #include "hw/core/sysbus.h"
30 #include "migration/vmstate.h"
31 #include "qemu/module.h"
32 #include "system/address-spaces.h"
33 #include "trace.h"
34
35 /*
36 * I/O MMU used by Sun4m systems
37 *
38 * Chipset docs:
39 * "Sun-4M System Architecture (revision 2.0) by Chuck Narad", 950-1373-01,
40 * http://mediacast.sun.com/users/Barton808/media/Sun4M_SystemArchitecture_edited2.pdf
41 */
42
43 #define IOMMU_CTRL (0x0000 >> 2)
44 #define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */
45 #define IOMMU_CTRL_VERS 0x0f000000 /* Version */
46 #define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */
47 #define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */
48 #define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */
49 #define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */
50 #define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */
51 #define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */
52 #define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */
53 #define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */
54 #define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */
55 #define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */
56 #define IOMMU_CTRL_MASK 0x0000001d
57
58 #define IOMMU_BASE (0x0004 >> 2)
59 #define IOMMU_BASE_MASK 0x07fffc00
60
61 #define IOMMU_TLBFLUSH (0x0014 >> 2)
62 #define IOMMU_TLBFLUSH_MASK 0xffffffff
63
64 #define IOMMU_PGFLUSH (0x0018 >> 2)
65 #define IOMMU_PGFLUSH_MASK 0xffffffff
66
67 #define IOMMU_AFSR (0x1000 >> 2)
68 #define IOMMU_AFSR_ERR 0x80000000 /* LE, TO, or BE asserted */
69 #define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after
70 transaction */
71 #define IOMMU_AFSR_TO 0x20000000 /* Write access took more than
72 12.8 us. */
73 #define IOMMU_AFSR_BE 0x10000000 /* Write access received error
74 acknowledge */
75 #define IOMMU_AFSR_SIZE 0x0e000000 /* Size of transaction causing error */
76 #define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */
77 #define IOMMU_AFSR_RESV 0x00800000 /* Reserved, forced to 0x8 by
78 hardware */
79 #define IOMMU_AFSR_ME 0x00080000 /* Multiple errors occurred */
80 #define IOMMU_AFSR_RD 0x00040000 /* A read operation was in progress */
81 #define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */
82 #define IOMMU_AFSR_MASK 0xff0fffff
83
84 #define IOMMU_AFAR (0x1004 >> 2)
85
86 #define IOMMU_AER (0x1008 >> 2) /* Arbiter Enable Register */
87 #define IOMMU_AER_EN_P0_ARB 0x00000001 /* MBus master 0x8 (Always 1) */
88 #define IOMMU_AER_EN_P1_ARB 0x00000002 /* MBus master 0x9 */
89 #define IOMMU_AER_EN_P2_ARB 0x00000004 /* MBus master 0xa */
90 #define IOMMU_AER_EN_P3_ARB 0x00000008 /* MBus master 0xb */
91 #define IOMMU_AER_EN_0 0x00010000 /* SBus slot 0 */
92 #define IOMMU_AER_EN_1 0x00020000 /* SBus slot 1 */
93 #define IOMMU_AER_EN_2 0x00040000 /* SBus slot 2 */
94 #define IOMMU_AER_EN_3 0x00080000 /* SBus slot 3 */
95 #define IOMMU_AER_EN_F 0x00100000 /* SBus on-board */
96 #define IOMMU_AER_SBW 0x80000000 /* S-to-M asynchronous writes */
97 #define IOMMU_AER_MASK 0x801f000f
98
99 #define IOMMU_SBCFG0 (0x1010 >> 2) /* SBUS configuration per-slot */
100 #define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configuration per-slot */
101 #define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configuration per-slot */
102 #define IOMMU_SBCFG3 (0x101c >> 2) /* SBUS configuration per-slot */
103 #define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when
104 bypass enabled */
105 #define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */
106 #define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */
107 #define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses
108 produced by this device as pure
109 physical. */
110 #define IOMMU_SBCFG_MASK 0x00010003
111
112 #define IOMMU_ARBEN (0x2000 >> 2) /* SBUS arbitration enable */
113 #define IOMMU_ARBEN_MASK 0x001f0000
114 #define IOMMU_MID 0x00000008
115
116 #define IOMMU_MASK_ID (0x3018 >> 2) /* Mask ID */
117 #define IOMMU_MASK_ID_MASK 0x00ffffff
118
119 #define IOMMU_MSII_MASK 0x26000000 /* microSPARC II mask number */
120 #define IOMMU_TS_MASK 0x23000000 /* turboSPARC mask number */
121
122 /* The format of an iopte in the page tables */
123 #define IOPTE_PAGE 0xffffff00 /* Physical page number (PA[35:12]) */
124 #define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or
125 Viking/MXCC) */
126 #define IOPTE_WRITE 0x00000004 /* Writable */
127 #define IOPTE_VALID 0x00000002 /* IOPTE is valid */
128 #define IOPTE_WAZ 0x00000001 /* Write as zeros */
129
130 #define IOMMU_PAGE_SHIFT 12
131 #define IOMMU_PAGE_SIZE (1 << IOMMU_PAGE_SHIFT)
132 #define IOMMU_PAGE_MASK (~(IOMMU_PAGE_SIZE - 1))
133
134 static uint64_t iommu_mem_read(void *opaque, hwaddr addr,
135 unsigned size)
136 {
137 IOMMUState *s = opaque;
138 hwaddr saddr;
139 uint32_t ret;
140
141 saddr = addr >> 2;
142 switch (saddr) {
143 default:
144 ret = s->regs[saddr];
145 break;
146 case IOMMU_AFAR:
147 case IOMMU_AFSR:
148 ret = s->regs[saddr];
149 qemu_irq_lower(s->irq);
150 break;
151 }
152 trace_sun4m_iommu_mem_readl(saddr, ret);
153 return ret;
154 }
155
156 static void iommu_mem_write(void *opaque, hwaddr addr,
157 uint64_t val, unsigned size)
158 {
159 IOMMUState *s = opaque;
160 hwaddr saddr;
161
162 saddr = addr >> 2;
163 trace_sun4m_iommu_mem_writel(saddr, val);
164 switch (saddr) {
165 case IOMMU_CTRL:
166 switch (val & IOMMU_CTRL_RNGE) {
167 case IOMMU_RNGE_16MB:
168 s->iostart = 0xffffffffff000000ULL;
169 break;
170 case IOMMU_RNGE_32MB:
171 s->iostart = 0xfffffffffe000000ULL;
172 break;
173 case IOMMU_RNGE_64MB:
174 s->iostart = 0xfffffffffc000000ULL;
175 break;
176 case IOMMU_RNGE_128MB:
177 s->iostart = 0xfffffffff8000000ULL;
178 break;
179 case IOMMU_RNGE_256MB:
180 s->iostart = 0xfffffffff0000000ULL;
181 break;
182 case IOMMU_RNGE_512MB:
183 s->iostart = 0xffffffffe0000000ULL;
184 break;
185 case IOMMU_RNGE_1GB:
186 s->iostart = 0xffffffffc0000000ULL;
187 break;
188 default:
189 case IOMMU_RNGE_2GB:
190 s->iostart = 0xffffffff80000000ULL;
191 break;
192 }
193 trace_sun4m_iommu_mem_writel_ctrl(s->iostart);
194 s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | s->version);
195 break;
196 case IOMMU_BASE:
197 s->regs[saddr] = val & IOMMU_BASE_MASK;
198 break;
199 case IOMMU_TLBFLUSH:
200 trace_sun4m_iommu_mem_writel_tlbflush(val);
201 s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK;
202 break;
203 case IOMMU_PGFLUSH:
204 trace_sun4m_iommu_mem_writel_pgflush(val);
205 s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
206 break;
207 case IOMMU_AFAR:
208 s->regs[saddr] = val;
209 qemu_irq_lower(s->irq);
210 break;
211 case IOMMU_AER:
212 s->regs[saddr] = (val & IOMMU_AER_MASK) | IOMMU_AER_EN_P0_ARB;
213 break;
214 case IOMMU_AFSR:
215 s->regs[saddr] = (val & IOMMU_AFSR_MASK) | IOMMU_AFSR_RESV;
216 qemu_irq_lower(s->irq);
217 break;
218 case IOMMU_SBCFG0:
219 case IOMMU_SBCFG1:
220 case IOMMU_SBCFG2:
221 case IOMMU_SBCFG3:
222 s->regs[saddr] = val & IOMMU_SBCFG_MASK;
223 break;
224 case IOMMU_ARBEN:
225 /* XXX implement SBus probing: fault when reading unmapped
226 addresses, fault cause and address stored to MMU/IOMMU */
227 s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID;
228 break;
229 case IOMMU_MASK_ID:
230 s->regs[saddr] |= val & IOMMU_MASK_ID_MASK;
231 break;
232 default:
233 s->regs[saddr] = val;
234 break;
235 }
236 }
237
238 static const MemoryRegionOps iommu_mem_ops = {
239 .read = iommu_mem_read,
240 .write = iommu_mem_write,
241 .endianness = DEVICE_BIG_ENDIAN,
242 .valid = {
243 .min_access_size = 4,
244 .max_access_size = 4,
245 },
246 };
247
248 static uint32_t iommu_page_get_flags(IOMMUState *s, hwaddr addr)
249 {
250 uint32_t ret;
251 hwaddr iopte;
252 hwaddr pa = addr;
253
254 iopte = s->regs[IOMMU_BASE] << 4;
255 addr &= ~s->iostart;
256 iopte += (addr >> (IOMMU_PAGE_SHIFT - 2)) & ~3;
257 ret = address_space_ldl_be(&address_space_memory, iopte,
258 MEMTXATTRS_UNSPECIFIED, NULL);
259 trace_sun4m_iommu_page_get_flags(pa, iopte, ret);
260 return ret;
261 }
262
263 static hwaddr iommu_translate_pa(hwaddr addr,
264 uint32_t pte)
265 {
266 hwaddr pa;
267
268 pa = ((pte & IOPTE_PAGE) << 4) + (addr & ~IOMMU_PAGE_MASK);
269 trace_sun4m_iommu_translate_pa(addr, pa, pte);
270 return pa;
271 }
272
273 static void iommu_bad_addr(IOMMUState *s, hwaddr addr,
274 int is_write)
275 {
276 trace_sun4m_iommu_bad_addr(addr);
277 s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR | IOMMU_AFSR_LE | IOMMU_AFSR_RESV |
278 IOMMU_AFSR_FAV;
279 if (!is_write) {
280 s->regs[IOMMU_AFSR] |= IOMMU_AFSR_RD;
281 }
282 s->regs[IOMMU_AFAR] = addr;
283 qemu_irq_raise(s->irq);
284 }
285
286 /* Called from RCU critical section */
287 static IOMMUTLBEntry sun4m_translate_iommu(IOMMUMemoryRegion *iommu,
288 hwaddr addr,
289 IOMMUAccessFlags flags,
290 int iommu_idx)
291 {
292 IOMMUState *is = container_of(iommu, IOMMUState, iommu);
293 hwaddr page, pa;
294 int is_write = (flags & IOMMU_WO) ? 1 : 0;
295 uint32_t pte;
296 IOMMUTLBEntry ret = {
297 .target_as = &address_space_memory,
298 .iova = 0,
299 .translated_addr = 0,
300 .addr_mask = ~(hwaddr)0,
301 .perm = IOMMU_NONE,
302 };
303
304 page = addr & IOMMU_PAGE_MASK;
305 pte = iommu_page_get_flags(is, page);
306 if (!(pte & IOPTE_VALID)) {
307 iommu_bad_addr(is, page, is_write);
308 return ret;
309 }
310
311 pa = iommu_translate_pa(addr, pte);
312 if (is_write && !(pte & IOPTE_WRITE)) {
313 iommu_bad_addr(is, page, is_write);
314 return ret;
315 }
316
317 if (pte & IOPTE_WRITE) {
318 ret.perm = IOMMU_RW;
319 } else {
320 ret.perm = IOMMU_RO;
321 }
322
323 ret.iova = page;
324 ret.translated_addr = pa;
325 ret.addr_mask = ~IOMMU_PAGE_MASK;
326
327 return ret;
328 }
329
330 static const VMStateDescription vmstate_iommu = {
331 .name = "iommu",
332 .version_id = 2,
333 .minimum_version_id = 2,
334 .fields = (const VMStateField[]) {
335 VMSTATE_UINT32_ARRAY(regs, IOMMUState, IOMMU_NREGS),
336 VMSTATE_UINT64(iostart, IOMMUState),
337 VMSTATE_END_OF_LIST()
338 }
339 };
340
341 static void iommu_reset(DeviceState *d)
342 {
343 IOMMUState *s = SUN4M_IOMMU(d);
344
345 memset(s->regs, 0, IOMMU_NREGS * 4);
346 s->iostart = 0;
347 s->regs[IOMMU_CTRL] = s->version;
348 s->regs[IOMMU_ARBEN] = IOMMU_MID;
349 s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV;
350 s->regs[IOMMU_AER] = IOMMU_AER_EN_P0_ARB | IOMMU_AER_EN_P1_ARB;
351 s->regs[IOMMU_MASK_ID] = IOMMU_TS_MASK;
352 }
353
354 static void iommu_realize(DeviceState *ds, Error **errp)
355 {
356 IOMMUState *s = SUN4M_IOMMU(ds);
357 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
358 Object *obj = OBJECT(ds);
359
360 memory_region_init_iommu(&s->iommu, sizeof(s->iommu),
361 TYPE_SUN4M_IOMMU_MEMORY_REGION, obj,
362 "iommu-sun4m", UINT64_MAX);
363 address_space_init(&s->iommu_as, MEMORY_REGION(&s->iommu), "iommu-as");
364
365 sysbus_init_irq(dev, &s->irq);
366
367 memory_region_init_io(&s->iomem, obj, &iommu_mem_ops, s, "iommu",
368 IOMMU_NREGS * sizeof(uint32_t));
369 sysbus_init_mmio(dev, &s->iomem);
370 }
371
372 static const Property iommu_properties[] = {
373 DEFINE_PROP_UINT32("version", IOMMUState, version, 0),
374 };
375
376 static void iommu_class_init(ObjectClass *klass, const void *data)
377 {
378 DeviceClass *dc = DEVICE_CLASS(klass);
379
380 device_class_set_legacy_reset(dc, iommu_reset);
381 dc->realize = iommu_realize;
382 dc->vmsd = &vmstate_iommu;
383 device_class_set_props(dc, iommu_properties);
384 }
385
386 static const TypeInfo iommu_info = {
387 .name = TYPE_SUN4M_IOMMU,
388 .parent = TYPE_SYS_BUS_DEVICE,
389 .instance_size = sizeof(IOMMUState),
390 .class_init = iommu_class_init,
391 };
392
393 static void sun4m_iommu_memory_region_class_init(ObjectClass *klass,
394 const void *data)
395 {
396 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass);
397
398 imrc->translate = sun4m_translate_iommu;
399 }
400
401 static const TypeInfo sun4m_iommu_memory_region_info = {
402 .parent = TYPE_IOMMU_MEMORY_REGION,
403 .name = TYPE_SUN4M_IOMMU_MEMORY_REGION,
404 .class_init = sun4m_iommu_memory_region_class_init,
405 };
406
407 static void iommu_register_types(void)
408 {
409 type_register_static(&iommu_info);
410 type_register_static(&sun4m_iommu_memory_region_info);
411 }
412
413 type_init(iommu_register_types)