| 1 | /* |
| 2 | * QEMU Sun4u/Sun4v System Emulator |
| 3 | * |
| 4 | * Copyright (c) 2005 Fabrice Bellard |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
| 24 | |
| 25 | #include "qemu/osdep.h" |
| 26 | #include "qemu/units.h" |
| 27 | #include "qemu/error-report.h" |
| 28 | #include "qapi/error.h" |
| 29 | #include "qemu/datadir.h" |
| 30 | #include "target/sparc/cpu.h" |
| 31 | #include "exec/target_page.h" |
| 32 | #include "hw/core/irq.h" |
| 33 | #include "hw/pci/pci.h" |
| 34 | #include "hw/pci/pci_bridge.h" |
| 35 | #include "hw/pci/pci_host.h" |
| 36 | #include "hw/core/qdev-properties.h" |
| 37 | #include "hw/pci-host/sabre.h" |
| 38 | #include "hw/char/serial-isa.h" |
| 39 | #include "hw/char/serial-mm.h" |
| 40 | #include "hw/char/parallel-isa.h" |
| 41 | #include "hw/rtc/m48t59.h" |
| 42 | #include "migration/vmstate.h" |
| 43 | #include "hw/input/i8042.h" |
| 44 | #include "hw/block/fdc.h" |
| 45 | #include "net/net.h" |
| 46 | #include "qemu/timer.h" |
| 47 | #include "system/runstate.h" |
| 48 | #include "system/system.h" |
| 49 | #include "hw/core/boards.h" |
| 50 | #include "hw/nvram/sun_nvram.h" |
| 51 | #include "hw/nvram/chrp_nvram.h" |
| 52 | #include "hw/sparc/sparc64.h" |
| 53 | #include "hw/nvram/fw_cfg.h" |
| 54 | #include "hw/core/sysbus.h" |
| 55 | #include "hw/ide/pci.h" |
| 56 | #include "hw/core/loader.h" |
| 57 | #include "hw/core/fw-path-provider.h" |
| 58 | #include "elf.h" |
| 59 | #include "trace.h" |
| 60 | #include "qom/object.h" |
| 61 | |
| 62 | #define KERNEL_LOAD_ADDR 0x00404000 |
| 63 | #define CMDLINE_ADDR 0x003ff000 |
| 64 | #define PROM_SIZE_MAX (4 * MiB) |
| 65 | #define PROM_VADDR 0x000ffd00000ULL |
| 66 | #define PBM_SPECIAL_BASE 0x1fe00000000ULL |
| 67 | #define PBM_MEM_BASE 0x1ff00000000ULL |
| 68 | #define PBM_PCI_IO_BASE (PBM_SPECIAL_BASE + 0x02000000ULL) |
| 69 | #define PROM_FILENAME "openbios-sparc64" |
| 70 | #define NVRAM_SIZE 0x2000 |
| 71 | #define BIOS_CFG_IOPORT 0x510 |
| 72 | #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00) |
| 73 | #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) |
| 74 | #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) |
| 75 | |
| 76 | #define IVEC_MAX 0x40 |
| 77 | |
| 78 | struct hwdef { |
| 79 | uint16_t machine_id; |
| 80 | uint64_t prom_addr; |
| 81 | uint64_t console_serial_base; |
| 82 | }; |
| 83 | |
| 84 | struct EbusState { |
| 85 | /*< private >*/ |
| 86 | PCIDevice parent_obj; |
| 87 | |
| 88 | ISABus *isa_bus; |
| 89 | qemu_irq *isa_irqs_in; |
| 90 | qemu_irq isa_irqs_out[ISA_NUM_IRQS]; |
| 91 | uint64_t console_serial_base; |
| 92 | MemoryRegion bar0; |
| 93 | MemoryRegion bar1; |
| 94 | }; |
| 95 | |
| 96 | #define TYPE_EBUS "ebus" |
| 97 | OBJECT_DECLARE_SIMPLE_TYPE(EbusState, EBUS) |
| 98 | |
| 99 | const char *fw_cfg_arch_key_name(uint16_t key) |
| 100 | { |
| 101 | static const struct { |
| 102 | uint16_t key; |
| 103 | const char *name; |
| 104 | } fw_cfg_arch_wellknown_keys[] = { |
| 105 | {FW_CFG_SPARC64_WIDTH, "width"}, |
| 106 | {FW_CFG_SPARC64_HEIGHT, "height"}, |
| 107 | {FW_CFG_SPARC64_DEPTH, "depth"}, |
| 108 | }; |
| 109 | |
| 110 | for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) { |
| 111 | if (fw_cfg_arch_wellknown_keys[i].key == key) { |
| 112 | return fw_cfg_arch_wellknown_keys[i].name; |
| 113 | } |
| 114 | } |
| 115 | return NULL; |
| 116 | } |
| 117 | |
| 118 | static void fw_cfg_boot_set(void *opaque, const char *boot_device, |
| 119 | Error **errp) |
| 120 | { |
| 121 | fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); |
| 122 | } |
| 123 | |
| 124 | static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size, |
| 125 | const char *arch, ram_addr_t RAM_size, |
| 126 | const char *boot_devices, |
| 127 | uint32_t kernel_image, uint32_t kernel_size, |
| 128 | const char *cmdline, |
| 129 | uint32_t initrd_image, uint32_t initrd_size, |
| 130 | uint32_t NVRAM_image, |
| 131 | int width, int height, int depth, |
| 132 | const uint8_t *macaddr) |
| 133 | { |
| 134 | unsigned int i; |
| 135 | int sysp_end; |
| 136 | uint8_t image[0x1ff0]; |
| 137 | NvramClass *k = NVRAM_GET_CLASS(nvram); |
| 138 | |
| 139 | memset(image, '\0', sizeof(image)); |
| 140 | |
| 141 | /* OpenBIOS nvram variables partition */ |
| 142 | sysp_end = chrp_nvram_create_system_partition(image, 0, 0x1fd0); |
| 143 | |
| 144 | /* Free space partition */ |
| 145 | chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end); |
| 146 | |
| 147 | Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); |
| 148 | |
| 149 | for (i = 0; i < sizeof(image); i++) { |
| 150 | (k->write)(nvram, i, image[i]); |
| 151 | } |
| 152 | |
| 153 | return 0; |
| 154 | } |
| 155 | |
| 156 | static uint64_t sun4u_load_kernel(const char *kernel_filename, |
| 157 | const char *initrd_filename, |
| 158 | ram_addr_t RAM_size, uint64_t *initrd_size, |
| 159 | uint64_t *initrd_addr, uint64_t *kernel_addr, |
| 160 | uint64_t *kernel_entry) |
| 161 | { |
| 162 | int linux_boot; |
| 163 | unsigned int i; |
| 164 | long kernel_size; |
| 165 | uint8_t *ptr; |
| 166 | uint64_t kernel_top = 0; |
| 167 | |
| 168 | linux_boot = (kernel_filename != NULL); |
| 169 | |
| 170 | kernel_size = 0; |
| 171 | if (linux_boot) { |
| 172 | kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, kernel_entry, |
| 173 | kernel_addr, &kernel_top, NULL, |
| 174 | ELFDATA2MSB, EM_SPARCV9, 0, 0); |
| 175 | if (kernel_size < 0) { |
| 176 | *kernel_addr = KERNEL_LOAD_ADDR; |
| 177 | *kernel_entry = KERNEL_LOAD_ADDR; |
| 178 | kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
| 179 | RAM_size - KERNEL_LOAD_ADDR, true, |
| 180 | TARGET_PAGE_SIZE); |
| 181 | } |
| 182 | if (kernel_size < 0) { |
| 183 | kernel_size = load_image_targphys(kernel_filename, |
| 184 | KERNEL_LOAD_ADDR, |
| 185 | RAM_size - KERNEL_LOAD_ADDR, |
| 186 | NULL); |
| 187 | } |
| 188 | if (kernel_size < 0) { |
| 189 | error_report("could not load kernel '%s'", kernel_filename); |
| 190 | exit(1); |
| 191 | } |
| 192 | /* load initrd above kernel */ |
| 193 | *initrd_size = 0; |
| 194 | if (initrd_filename && kernel_top) { |
| 195 | *initrd_addr = TARGET_PAGE_ALIGN(kernel_top); |
| 196 | |
| 197 | *initrd_size = load_image_targphys(initrd_filename, |
| 198 | *initrd_addr, |
| 199 | RAM_size - *initrd_addr, NULL); |
| 200 | if ((int)*initrd_size < 0) { |
| 201 | error_report("could not load initial ram disk '%s'", |
| 202 | initrd_filename); |
| 203 | exit(1); |
| 204 | } |
| 205 | } |
| 206 | if (*initrd_size > 0) { |
| 207 | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
| 208 | ptr = rom_ptr(*kernel_addr + i, 32); |
| 209 | if (ptr && ldl_be_p(ptr + 8) == 0x48647253) { /* HdrS */ |
| 210 | stl_be_p(ptr + 24, *initrd_addr + *kernel_addr); |
| 211 | stl_be_p(ptr + 28, *initrd_size); |
| 212 | break; |
| 213 | } |
| 214 | } |
| 215 | } |
| 216 | } |
| 217 | return kernel_size; |
| 218 | } |
| 219 | |
| 220 | typedef struct ResetData { |
| 221 | SPARCCPU *cpu; |
| 222 | uint64_t prom_addr; |
| 223 | } ResetData; |
| 224 | |
| 225 | #define TYPE_SUN4U_POWER "power" |
| 226 | OBJECT_DECLARE_SIMPLE_TYPE(PowerDevice, SUN4U_POWER) |
| 227 | |
| 228 | struct PowerDevice { |
| 229 | SysBusDevice parent_obj; |
| 230 | |
| 231 | MemoryRegion power_mmio; |
| 232 | }; |
| 233 | |
| 234 | /* Power */ |
| 235 | static uint64_t power_mem_read(void *opaque, hwaddr addr, unsigned size) |
| 236 | { |
| 237 | return 0; |
| 238 | } |
| 239 | |
| 240 | static void power_mem_write(void *opaque, hwaddr addr, |
| 241 | uint64_t val, unsigned size) |
| 242 | { |
| 243 | /* According to a real Ultra 5, bit 24 controls the power */ |
| 244 | if (val & 0x1000000) { |
| 245 | qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); |
| 246 | } |
| 247 | } |
| 248 | |
| 249 | static const MemoryRegionOps power_mem_ops = { |
| 250 | .read = power_mem_read, |
| 251 | .write = power_mem_write, |
| 252 | .endianness = DEVICE_BIG_ENDIAN, |
| 253 | .valid = { |
| 254 | .min_access_size = 4, |
| 255 | .max_access_size = 4, |
| 256 | }, |
| 257 | }; |
| 258 | |
| 259 | static void power_realize(DeviceState *dev, Error **errp) |
| 260 | { |
| 261 | PowerDevice *d = SUN4U_POWER(dev); |
| 262 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
| 263 | |
| 264 | memory_region_init_io(&d->power_mmio, OBJECT(dev), &power_mem_ops, d, |
| 265 | "power", sizeof(uint32_t)); |
| 266 | |
| 267 | sysbus_init_mmio(sbd, &d->power_mmio); |
| 268 | } |
| 269 | |
| 270 | static void power_class_init(ObjectClass *klass, const void *data) |
| 271 | { |
| 272 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 273 | |
| 274 | dc->realize = power_realize; |
| 275 | } |
| 276 | |
| 277 | static const TypeInfo power_info = { |
| 278 | .name = TYPE_SUN4U_POWER, |
| 279 | .parent = TYPE_SYS_BUS_DEVICE, |
| 280 | .instance_size = sizeof(PowerDevice), |
| 281 | .class_init = power_class_init, |
| 282 | }; |
| 283 | |
| 284 | static void ebus_isa_irq_handler(void *opaque, int n, int level) |
| 285 | { |
| 286 | EbusState *s = EBUS(opaque); |
| 287 | qemu_irq irq = s->isa_irqs_out[n]; |
| 288 | |
| 289 | /* Pass ISA bus IRQs onto their gpio equivalent */ |
| 290 | trace_ebus_isa_irq_handler(n, level); |
| 291 | if (irq) { |
| 292 | qemu_set_irq(irq, level); |
| 293 | } |
| 294 | } |
| 295 | |
| 296 | /* EBUS (Eight bit bus) bridge */ |
| 297 | static void ebus_realize(PCIDevice *pci_dev, Error **errp) |
| 298 | { |
| 299 | EbusState *s = EBUS(pci_dev); |
| 300 | ISADevice *isa_dev; |
| 301 | SysBusDevice *sbd; |
| 302 | DeviceState *dev; |
| 303 | DriveInfo *fd[MAX_FD]; |
| 304 | int i; |
| 305 | |
| 306 | s->isa_bus = isa_bus_new(DEVICE(pci_dev), get_system_memory(), |
| 307 | pci_address_space_io(pci_dev), errp); |
| 308 | if (!s->isa_bus) { |
| 309 | error_setg(errp, "unable to instantiate EBUS ISA bus"); |
| 310 | return; |
| 311 | } |
| 312 | |
| 313 | /* ISA bus */ |
| 314 | s->isa_irqs_in = qemu_allocate_irqs(ebus_isa_irq_handler, s, ISA_NUM_IRQS); |
| 315 | isa_bus_register_input_irqs(s->isa_bus, s->isa_irqs_in); |
| 316 | qdev_init_gpio_out_named(DEVICE(s), s->isa_irqs_out, "isa-irq", |
| 317 | ISA_NUM_IRQS); |
| 318 | |
| 319 | /* Serial ports */ |
| 320 | i = 0; |
| 321 | if (s->console_serial_base) { |
| 322 | serial_mm_init(pci_address_space(pci_dev), s->console_serial_base, |
| 323 | 0, NULL, 115200, serial_hd(i), DEVICE_BIG_ENDIAN); |
| 324 | i++; |
| 325 | } |
| 326 | serial_hds_isa_init(s->isa_bus, i, MAX_ISA_SERIAL_PORTS); |
| 327 | |
| 328 | /* Parallel ports */ |
| 329 | parallel_hds_isa_init(s->isa_bus, MAX_PARALLEL_PORTS); |
| 330 | |
| 331 | /* Keyboard */ |
| 332 | isa_create_simple(s->isa_bus, TYPE_I8042); |
| 333 | |
| 334 | /* Floppy */ |
| 335 | for (i = 0; i < MAX_FD; i++) { |
| 336 | fd[i] = drive_get(IF_FLOPPY, 0, i); |
| 337 | } |
| 338 | isa_dev = isa_new(TYPE_ISA_FDC); |
| 339 | dev = DEVICE(isa_dev); |
| 340 | qdev_prop_set_uint32(dev, "dma", -1); |
| 341 | isa_realize_and_unref(isa_dev, s->isa_bus, &error_fatal); |
| 342 | isa_fdc_init_drives(isa_dev, fd); |
| 343 | |
| 344 | /* Power */ |
| 345 | dev = qdev_new(TYPE_SUN4U_POWER); |
| 346 | sbd = SYS_BUS_DEVICE(dev); |
| 347 | sysbus_realize_and_unref(sbd, &error_fatal); |
| 348 | memory_region_add_subregion(pci_address_space_io(pci_dev), 0x7240, |
| 349 | sysbus_mmio_get_region(sbd, 0)); |
| 350 | |
| 351 | /* PCI */ |
| 352 | pci_dev->config[0x04] = 0x06; // command = bus master, pci mem |
| 353 | pci_dev->config[0x05] = 0x00; |
| 354 | pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error |
| 355 | pci_dev->config[0x07] = 0x03; // status = medium devsel |
| 356 | pci_dev->config[0x09] = 0x00; // programming i/f |
| 357 | pci_dev->config[0x0D] = 0x0a; // latency_timer |
| 358 | |
| 359 | /* |
| 360 | * BAR0 is accessed by OpenBSD but not for ebus device access: allow any |
| 361 | * memory access to this region to succeed which allows the OpenBSD kernel |
| 362 | * to boot. |
| 363 | */ |
| 364 | memory_region_init_io(&s->bar0, OBJECT(s), &unassigned_io_ops, s, |
| 365 | "bar0", 0x1000000); |
| 366 | pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0); |
| 367 | memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", |
| 368 | pci_address_space_io(pci_dev), 0, 0x8000); |
| 369 | pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1); |
| 370 | } |
| 371 | |
| 372 | static const Property ebus_properties[] = { |
| 373 | DEFINE_PROP_UINT64("console-serial-base", EbusState, |
| 374 | console_serial_base, 0), |
| 375 | }; |
| 376 | |
| 377 | static void ebus_class_init(ObjectClass *klass, const void *data) |
| 378 | { |
| 379 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
| 380 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 381 | |
| 382 | k->realize = ebus_realize; |
| 383 | k->vendor_id = PCI_VENDOR_ID_SUN; |
| 384 | k->device_id = PCI_DEVICE_ID_SUN_EBUS; |
| 385 | k->revision = 0x01; |
| 386 | k->class_id = PCI_CLASS_BRIDGE_OTHER; |
| 387 | device_class_set_props(dc, ebus_properties); |
| 388 | } |
| 389 | |
| 390 | static const TypeInfo ebus_info = { |
| 391 | .name = TYPE_EBUS, |
| 392 | .parent = TYPE_PCI_DEVICE, |
| 393 | .class_init = ebus_class_init, |
| 394 | .instance_size = sizeof(EbusState), |
| 395 | .interfaces = (const InterfaceInfo[]) { |
| 396 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, |
| 397 | { }, |
| 398 | }, |
| 399 | }; |
| 400 | |
| 401 | #define TYPE_OPENPROM "openprom" |
| 402 | typedef struct PROMState PROMState; |
| 403 | DECLARE_INSTANCE_CHECKER(PROMState, OPENPROM, |
| 404 | TYPE_OPENPROM) |
| 405 | |
| 406 | struct PROMState { |
| 407 | SysBusDevice parent_obj; |
| 408 | |
| 409 | MemoryRegion prom; |
| 410 | }; |
| 411 | |
| 412 | static uint64_t translate_prom_address(void *opaque, uint64_t addr) |
| 413 | { |
| 414 | hwaddr *base_addr = (hwaddr *)opaque; |
| 415 | return addr + *base_addr - PROM_VADDR; |
| 416 | } |
| 417 | |
| 418 | /* Boot PROM (OpenBIOS) */ |
| 419 | static void prom_init(hwaddr addr, const char *bios_name) |
| 420 | { |
| 421 | DeviceState *dev; |
| 422 | SysBusDevice *s; |
| 423 | char *filename; |
| 424 | int ret; |
| 425 | |
| 426 | dev = qdev_new(TYPE_OPENPROM); |
| 427 | s = SYS_BUS_DEVICE(dev); |
| 428 | sysbus_realize_and_unref(s, &error_fatal); |
| 429 | |
| 430 | sysbus_mmio_map(s, 0, addr); |
| 431 | |
| 432 | /* load boot prom */ |
| 433 | if (bios_name == NULL) { |
| 434 | bios_name = PROM_FILENAME; |
| 435 | } |
| 436 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
| 437 | if (filename) { |
| 438 | ret = load_elf(filename, NULL, translate_prom_address, &addr, |
| 439 | NULL, NULL, NULL, NULL, ELFDATA2MSB, EM_SPARCV9, 0, 0); |
| 440 | if (ret < 0 || ret > PROM_SIZE_MAX) { |
| 441 | ret = load_image_targphys(filename, addr, PROM_SIZE_MAX, NULL); |
| 442 | } |
| 443 | g_free(filename); |
| 444 | } else { |
| 445 | ret = -1; |
| 446 | } |
| 447 | if (ret < 0 || ret > PROM_SIZE_MAX) { |
| 448 | error_report("could not load prom '%s'", bios_name); |
| 449 | exit(1); |
| 450 | } |
| 451 | } |
| 452 | |
| 453 | static void prom_realize(DeviceState *ds, Error **errp) |
| 454 | { |
| 455 | PROMState *s = OPENPROM(ds); |
| 456 | SysBusDevice *dev = SYS_BUS_DEVICE(ds); |
| 457 | |
| 458 | if (!memory_region_init_rom(&s->prom, OBJECT(ds), "sun4u.prom", |
| 459 | PROM_SIZE_MAX, errp)) { |
| 460 | return; |
| 461 | } |
| 462 | sysbus_init_mmio(dev, &s->prom); |
| 463 | } |
| 464 | |
| 465 | static void prom_class_init(ObjectClass *klass, const void *data) |
| 466 | { |
| 467 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 468 | |
| 469 | dc->realize = prom_realize; |
| 470 | } |
| 471 | |
| 472 | static const TypeInfo prom_info = { |
| 473 | .name = TYPE_OPENPROM, |
| 474 | .parent = TYPE_SYS_BUS_DEVICE, |
| 475 | .instance_size = sizeof(PROMState), |
| 476 | .class_init = prom_class_init, |
| 477 | }; |
| 478 | |
| 479 | |
| 480 | #define TYPE_SUN4U_MEMORY "memory" |
| 481 | typedef struct RamDevice RamDevice; |
| 482 | DECLARE_INSTANCE_CHECKER(RamDevice, SUN4U_RAM, |
| 483 | TYPE_SUN4U_MEMORY) |
| 484 | |
| 485 | struct RamDevice { |
| 486 | SysBusDevice parent_obj; |
| 487 | |
| 488 | MemoryRegion ram; |
| 489 | uint64_t size; |
| 490 | }; |
| 491 | |
| 492 | /* System RAM */ |
| 493 | static void ram_realize(DeviceState *dev, Error **errp) |
| 494 | { |
| 495 | RamDevice *d = SUN4U_RAM(dev); |
| 496 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
| 497 | |
| 498 | memory_region_init_ram(&d->ram, OBJECT(d), "sun4u.ram", d->size, |
| 499 | &error_fatal); |
| 500 | sysbus_init_mmio(sbd, &d->ram); |
| 501 | } |
| 502 | |
| 503 | static void ram_init(hwaddr addr, ram_addr_t RAM_size) |
| 504 | { |
| 505 | DeviceState *dev; |
| 506 | SysBusDevice *s; |
| 507 | RamDevice *d; |
| 508 | |
| 509 | /* allocate RAM */ |
| 510 | dev = qdev_new(TYPE_SUN4U_MEMORY); |
| 511 | s = SYS_BUS_DEVICE(dev); |
| 512 | |
| 513 | d = SUN4U_RAM(dev); |
| 514 | d->size = RAM_size; |
| 515 | sysbus_realize_and_unref(s, &error_fatal); |
| 516 | |
| 517 | sysbus_mmio_map(s, 0, addr); |
| 518 | } |
| 519 | |
| 520 | static const Property ram_properties[] = { |
| 521 | DEFINE_PROP_UINT64("size", RamDevice, size, 0), |
| 522 | }; |
| 523 | |
| 524 | static void ram_class_init(ObjectClass *klass, const void *data) |
| 525 | { |
| 526 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 527 | |
| 528 | dc->realize = ram_realize; |
| 529 | device_class_set_props(dc, ram_properties); |
| 530 | } |
| 531 | |
| 532 | static const TypeInfo ram_info = { |
| 533 | .name = TYPE_SUN4U_MEMORY, |
| 534 | .parent = TYPE_SYS_BUS_DEVICE, |
| 535 | .instance_size = sizeof(RamDevice), |
| 536 | .class_init = ram_class_init, |
| 537 | }; |
| 538 | |
| 539 | static void sun4uv_init(MemoryRegion *address_space_mem, |
| 540 | MachineState *machine, |
| 541 | const struct hwdef *hwdef) |
| 542 | { |
| 543 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
| 544 | SPARCCPU *cpu; |
| 545 | Nvram *nvram; |
| 546 | unsigned int i; |
| 547 | uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry; |
| 548 | SabreState *sabre; |
| 549 | PCIBus *pci_bus, *pci_busA, *pci_busB; |
| 550 | PCIDevice *ebus, *pci_dev; |
| 551 | SysBusDevice *s; |
| 552 | DeviceState *iommu, *dev; |
| 553 | FWCfgState *fw_cfg; |
| 554 | NICInfo *nd; |
| 555 | MACAddr macaddr; |
| 556 | bool onboard_nic; |
| 557 | |
| 558 | /* init CPUs */ |
| 559 | cpu = sparc64_cpu_devinit(machine->cpu_type, hwdef->prom_addr); |
| 560 | |
| 561 | /* IOMMU */ |
| 562 | iommu = qdev_new(TYPE_SUN4U_IOMMU); |
| 563 | sysbus_realize_and_unref(SYS_BUS_DEVICE(iommu), &error_fatal); |
| 564 | |
| 565 | /* set up devices */ |
| 566 | ram_init(0, machine->ram_size); |
| 567 | |
| 568 | prom_init(hwdef->prom_addr, machine->firmware); |
| 569 | |
| 570 | /* Init sabre (PCI host bridge) */ |
| 571 | sabre = SABRE(qdev_new(TYPE_SABRE)); |
| 572 | qdev_prop_set_uint64(DEVICE(sabre), "special-base", PBM_SPECIAL_BASE); |
| 573 | qdev_prop_set_uint64(DEVICE(sabre), "mem-base", PBM_MEM_BASE); |
| 574 | object_property_set_link(OBJECT(sabre), "iommu", OBJECT(iommu), |
| 575 | &error_abort); |
| 576 | sysbus_realize_and_unref(SYS_BUS_DEVICE(sabre), &error_fatal); |
| 577 | |
| 578 | /* sabre_config */ |
| 579 | sysbus_mmio_map(SYS_BUS_DEVICE(sabre), 0, PBM_SPECIAL_BASE); |
| 580 | /* PCI configuration space */ |
| 581 | sysbus_mmio_map(SYS_BUS_DEVICE(sabre), 1, PBM_SPECIAL_BASE + 0x1000000ULL); |
| 582 | /* pci_ioport */ |
| 583 | sysbus_mmio_map(SYS_BUS_DEVICE(sabre), 2, PBM_SPECIAL_BASE + 0x2000000ULL); |
| 584 | |
| 585 | /* Wire up PCI interrupts to CPU */ |
| 586 | for (i = 0; i < IVEC_MAX; i++) { |
| 587 | qdev_connect_gpio_out_named(DEVICE(sabre), "ivec-irq", i, |
| 588 | qdev_get_gpio_in_named(DEVICE(cpu), "ivec-irq", i)); |
| 589 | } |
| 590 | |
| 591 | pci_bus = PCI_HOST_BRIDGE(sabre)->bus; |
| 592 | pci_busA = pci_bridge_get_sec_bus(sabre->bridgeA); |
| 593 | pci_busB = pci_bridge_get_sec_bus(sabre->bridgeB); |
| 594 | |
| 595 | /* Only in-built Simba APBs can exist on the root bus, slot 0 on busA is |
| 596 | reserved (leaving no slots free after on-board devices) however slots |
| 597 | 0-3 are free on busB */ |
| 598 | pci_bus_set_slot_reserved_mask(pci_bus, 0xfffffffc); |
| 599 | pci_bus_set_slot_reserved_mask(pci_busA, 0xfffffff1); |
| 600 | pci_bus_set_slot_reserved_mask(pci_busB, 0xfffffff0); |
| 601 | |
| 602 | ebus = pci_new_multifunction(PCI_DEVFN(1, 0), TYPE_EBUS); |
| 603 | qdev_prop_set_uint64(DEVICE(ebus), "console-serial-base", |
| 604 | hwdef->console_serial_base); |
| 605 | pci_realize_and_unref(ebus, pci_busA, &error_fatal); |
| 606 | |
| 607 | /* Wire up "well-known" ISA IRQs to PBM legacy obio IRQs */ |
| 608 | qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 7, |
| 609 | qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_LPT_IRQ)); |
| 610 | qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 6, |
| 611 | qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_FDD_IRQ)); |
| 612 | qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 1, |
| 613 | qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_KBD_IRQ)); |
| 614 | qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 12, |
| 615 | qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_MSE_IRQ)); |
| 616 | qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 4, |
| 617 | qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_SER_IRQ)); |
| 618 | |
| 619 | switch (vga_interface_type) { |
| 620 | case VGA_STD: |
| 621 | pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA"); |
| 622 | vga_interface_created = true; |
| 623 | break; |
| 624 | case VGA_NONE: |
| 625 | break; |
| 626 | default: |
| 627 | abort(); /* Should not happen - types are checked in vl.c already */ |
| 628 | } |
| 629 | |
| 630 | memset(&macaddr, 0, sizeof(MACAddr)); |
| 631 | onboard_nic = false; |
| 632 | |
| 633 | nd = qemu_find_nic_info(mc->default_nic, true, NULL); |
| 634 | if (nd) { |
| 635 | pci_dev = pci_new_multifunction(PCI_DEVFN(1, 1), mc->default_nic); |
| 636 | dev = &pci_dev->qdev; |
| 637 | qdev_set_nic_properties(dev, nd); |
| 638 | pci_realize_and_unref(pci_dev, pci_busA, &error_fatal); |
| 639 | |
| 640 | memcpy(&macaddr, &nd->macaddr.a, sizeof(MACAddr)); |
| 641 | onboard_nic = true; |
| 642 | } |
| 643 | pci_init_nic_devices(pci_busB, mc->default_nic); |
| 644 | |
| 645 | /* If we don't have an onboard NIC, grab a default MAC address so that |
| 646 | * we have a valid machine id */ |
| 647 | if (!onboard_nic) { |
| 648 | qemu_macaddr_default_if_unset(&macaddr); |
| 649 | } |
| 650 | |
| 651 | pci_dev = pci_new(PCI_DEVFN(3, 0), "cmd646-ide"); |
| 652 | qdev_prop_set_uint32(&pci_dev->qdev, "secondary", 1); |
| 653 | pci_realize_and_unref(pci_dev, pci_busA, &error_fatal); |
| 654 | pci_ide_create_devs(pci_dev); |
| 655 | |
| 656 | /* Map NVRAM into I/O (ebus) space */ |
| 657 | dev = qdev_new("sysbus-m48t59"); |
| 658 | qdev_prop_set_int32(dev, "base-year", 1968); |
| 659 | s = SYS_BUS_DEVICE(dev); |
| 660 | sysbus_realize_and_unref(s, &error_fatal); |
| 661 | memory_region_add_subregion(pci_address_space_io(ebus), 0x2000, |
| 662 | sysbus_mmio_get_region(s, 0)); |
| 663 | nvram = NVRAM(dev); |
| 664 | |
| 665 | if (!graphic_width) { |
| 666 | graphic_width = 1024; |
| 667 | } |
| 668 | if (!graphic_height) { |
| 669 | graphic_height = 768; |
| 670 | } |
| 671 | if (!graphic_depth) { |
| 672 | graphic_depth = 8; |
| 673 | } |
| 674 | |
| 675 | initrd_size = 0; |
| 676 | initrd_addr = 0; |
| 677 | kernel_size = sun4u_load_kernel(machine->kernel_filename, |
| 678 | machine->initrd_filename, |
| 679 | machine->ram_size, &initrd_size, &initrd_addr, |
| 680 | &kernel_addr, &kernel_entry); |
| 681 | |
| 682 | sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size, |
| 683 | machine->boot_config.order, |
| 684 | kernel_addr, kernel_size, |
| 685 | machine->kernel_cmdline, |
| 686 | initrd_addr, initrd_size, |
| 687 | /* XXX: need an option to load a NVRAM image */ |
| 688 | 0, |
| 689 | graphic_width, graphic_height, graphic_depth, |
| 690 | (uint8_t *)&macaddr); |
| 691 | |
| 692 | dev = qdev_new(TYPE_FW_CFG_IO); |
| 693 | qdev_prop_set_bit(dev, "dma_enabled", false); |
| 694 | object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev)); |
| 695 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
| 696 | memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT, |
| 697 | &FW_CFG_IO(dev)->comb_iomem); |
| 698 | |
| 699 | fw_cfg = FW_CFG(dev); |
| 700 | fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)machine->smp.cpus); |
| 701 | fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus); |
| 702 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size); |
| 703 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
| 704 | fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry); |
| 705 | fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
| 706 | if (machine->kernel_cmdline) { |
| 707 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, |
| 708 | strlen(machine->kernel_cmdline) + 1); |
| 709 | fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); |
| 710 | } else { |
| 711 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); |
| 712 | } |
| 713 | fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); |
| 714 | fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); |
| 715 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_config.order[0]); |
| 716 | |
| 717 | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width); |
| 718 | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height); |
| 719 | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth); |
| 720 | |
| 721 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
| 722 | |
| 723 | /* |
| 724 | * Mark internal PCI busses as full so that the plugging of additional |
| 725 | * PCI devices happens on the right bus that still has free slots: |
| 726 | */ |
| 727 | qbus_mark_full(&pci_bus->qbus); |
| 728 | qbus_mark_full(&pci_busA->qbus); |
| 729 | } |
| 730 | |
| 731 | enum { |
| 732 | sun4u_id = 0, |
| 733 | sun4v_id = 64, |
| 734 | }; |
| 735 | |
| 736 | /* |
| 737 | * Implementation of an interface to adjust firmware path |
| 738 | * for the bootindex property handling. |
| 739 | */ |
| 740 | static char *sun4u_fw_dev_path(FWPathProvider *p, BusState *bus, |
| 741 | DeviceState *dev) |
| 742 | { |
| 743 | PCIDevice *pci; |
| 744 | |
| 745 | if (!strcmp(object_get_typename(OBJECT(dev)), "pbm-bridge")) { |
| 746 | pci = PCI_DEVICE(dev); |
| 747 | |
| 748 | if (PCI_FUNC(pci->devfn)) { |
| 749 | return g_strdup_printf("pci@%x,%x", PCI_SLOT(pci->devfn), |
| 750 | PCI_FUNC(pci->devfn)); |
| 751 | } else { |
| 752 | return g_strdup_printf("pci@%x", PCI_SLOT(pci->devfn)); |
| 753 | } |
| 754 | } |
| 755 | |
| 756 | if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) { |
| 757 | return g_strdup("disk"); |
| 758 | } |
| 759 | |
| 760 | if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) { |
| 761 | return g_strdup("cdrom"); |
| 762 | } |
| 763 | |
| 764 | if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) { |
| 765 | return g_strdup("disk"); |
| 766 | } |
| 767 | |
| 768 | return NULL; |
| 769 | } |
| 770 | |
| 771 | static const struct hwdef hwdefs[] = { |
| 772 | /* Sun4u generic PC-like machine */ |
| 773 | { |
| 774 | .machine_id = sun4u_id, |
| 775 | .prom_addr = 0x1fff0000000ULL, |
| 776 | .console_serial_base = 0, |
| 777 | }, |
| 778 | /* Sun4v generic PC-like machine */ |
| 779 | { |
| 780 | .machine_id = sun4v_id, |
| 781 | .prom_addr = 0x1fff0000000ULL, |
| 782 | .console_serial_base = 0, |
| 783 | }, |
| 784 | }; |
| 785 | |
| 786 | /* Sun4u hardware initialisation */ |
| 787 | static void sun4u_init(MachineState *machine) |
| 788 | { |
| 789 | sun4uv_init(get_system_memory(), machine, &hwdefs[0]); |
| 790 | } |
| 791 | |
| 792 | /* Sun4v hardware initialisation */ |
| 793 | static void sun4v_init(MachineState *machine) |
| 794 | { |
| 795 | sun4uv_init(get_system_memory(), machine, &hwdefs[1]); |
| 796 | } |
| 797 | |
| 798 | static GlobalProperty hw_compat_sparc64[] = { |
| 799 | { "virtio-pci", "disable-legacy", "on", .optional = true }, |
| 800 | { "virtio-device", "iommu_platform", "on" }, |
| 801 | }; |
| 802 | static const size_t hw_compat_sparc64_len = G_N_ELEMENTS(hw_compat_sparc64); |
| 803 | |
| 804 | static void sun4u_class_init(ObjectClass *oc, const void *data) |
| 805 | { |
| 806 | MachineClass *mc = MACHINE_CLASS(oc); |
| 807 | FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); |
| 808 | |
| 809 | mc->desc = "Sun4u platform"; |
| 810 | mc->init = sun4u_init; |
| 811 | mc->block_default_type = IF_IDE; |
| 812 | mc->max_cpus = 1; /* XXX for now */ |
| 813 | mc->is_default = true; |
| 814 | mc->default_boot_order = "c"; |
| 815 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-UltraSparc-IIi"); |
| 816 | mc->ignore_boot_device_suffixes = true; |
| 817 | mc->default_display = "std"; |
| 818 | mc->default_nic = "sunhme"; |
| 819 | mc->no_parallel = !module_object_class_by_name(TYPE_ISA_PARALLEL); |
| 820 | fwc->get_dev_path = sun4u_fw_dev_path; |
| 821 | compat_props_add(mc->compat_props, hw_compat_sparc64, hw_compat_sparc64_len); |
| 822 | } |
| 823 | |
| 824 | static const TypeInfo sun4u_type = { |
| 825 | .name = MACHINE_TYPE_NAME("sun4u"), |
| 826 | .parent = TYPE_MACHINE, |
| 827 | .class_init = sun4u_class_init, |
| 828 | .interfaces = (const InterfaceInfo[]) { |
| 829 | { TYPE_FW_PATH_PROVIDER }, |
| 830 | { } |
| 831 | }, |
| 832 | }; |
| 833 | |
| 834 | static void sun4v_class_init(ObjectClass *oc, const void *data) |
| 835 | { |
| 836 | MachineClass *mc = MACHINE_CLASS(oc); |
| 837 | |
| 838 | mc->desc = "Sun4v platform"; |
| 839 | mc->init = sun4v_init; |
| 840 | mc->block_default_type = IF_IDE; |
| 841 | mc->max_cpus = 1; /* XXX for now */ |
| 842 | mc->default_boot_order = "c"; |
| 843 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1"); |
| 844 | mc->default_display = "std"; |
| 845 | mc->default_nic = "sunhme"; |
| 846 | mc->no_parallel = !module_object_class_by_name(TYPE_ISA_PARALLEL); |
| 847 | } |
| 848 | |
| 849 | static const TypeInfo sun4v_type = { |
| 850 | .name = MACHINE_TYPE_NAME("sun4v"), |
| 851 | .parent = TYPE_MACHINE, |
| 852 | .class_init = sun4v_class_init, |
| 853 | }; |
| 854 | |
| 855 | static void sun4u_register_types(void) |
| 856 | { |
| 857 | type_register_static(&power_info); |
| 858 | type_register_static(&ebus_info); |
| 859 | type_register_static(&prom_info); |
| 860 | type_register_static(&ram_info); |
| 861 | |
| 862 | type_register_static(&sun4u_type); |
| 863 | type_register_static(&sun4v_type); |
| 864 | } |
| 865 | |
| 866 | type_init(sun4u_register_types) |