| 1 | /* |
| 2 | * ASPEED AST2400 SMC Controller (SPI Flash Only) |
| 3 | * |
| 4 | * Copyright (C) 2016 IBM Corp. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
| 24 | |
| 25 | #include "qemu/osdep.h" |
| 26 | #include "hw/block/flash.h" |
| 27 | #include "hw/core/sysbus.h" |
| 28 | #include "migration/vmstate.h" |
| 29 | #include "qemu/log.h" |
| 30 | #include "qemu/module.h" |
| 31 | #include "qemu/error-report.h" |
| 32 | #include "qapi/error.h" |
| 33 | #include "qemu/units.h" |
| 34 | #include "trace.h" |
| 35 | |
| 36 | #include "hw/core/irq.h" |
| 37 | #include "hw/core/qdev-properties.h" |
| 38 | #include "hw/ssi/aspeed_smc.h" |
| 39 | |
| 40 | /* CE Type Setting Register */ |
| 41 | #define R_CONF (0x00 / 4) |
| 42 | #define CONF_LEGACY_DISABLE (1 << 31) |
| 43 | #define CONF_ENABLE_W4 20 |
| 44 | #define CONF_ENABLE_W3 19 |
| 45 | #define CONF_ENABLE_W2 18 |
| 46 | #define CONF_ENABLE_W1 17 |
| 47 | #define CONF_ENABLE_W0 16 |
| 48 | #define CONF_FLASH_TYPE4 8 |
| 49 | #define CONF_FLASH_TYPE3 6 |
| 50 | #define CONF_FLASH_TYPE2 4 |
| 51 | #define CONF_FLASH_TYPE1 2 |
| 52 | #define CONF_FLASH_TYPE0 0 |
| 53 | #define CONF_FLASH_TYPE_NOR 0x0 |
| 54 | #define CONF_FLASH_TYPE_NAND 0x1 |
| 55 | #define CONF_FLASH_TYPE_SPI 0x2 /* AST2600 is SPI only */ |
| 56 | |
| 57 | /* CE Control Register */ |
| 58 | #define R_CE_CTRL (0x04 / 4) |
| 59 | #define CTRL_EXTENDED4 4 /* 32 bit addressing for SPI */ |
| 60 | #define CTRL_EXTENDED3 3 /* 32 bit addressing for SPI */ |
| 61 | #define CTRL_EXTENDED2 2 /* 32 bit addressing for SPI */ |
| 62 | #define CTRL_EXTENDED1 1 /* 32 bit addressing for SPI */ |
| 63 | #define CTRL_EXTENDED0 0 /* 32 bit addressing for SPI */ |
| 64 | |
| 65 | /* Interrupt Control and Status Register */ |
| 66 | #define R_INTR_CTRL (0x08 / 4) |
| 67 | #define INTR_CTRL_DMA_STATUS (1 << 11) |
| 68 | #define INTR_CTRL_CMD_ABORT_STATUS (1 << 10) |
| 69 | #define INTR_CTRL_WRITE_PROTECT_STATUS (1 << 9) |
| 70 | #define INTR_CTRL_DMA_EN (1 << 3) |
| 71 | #define INTR_CTRL_CMD_ABORT_EN (1 << 2) |
| 72 | #define INTR_CTRL_WRITE_PROTECT_EN (1 << 1) |
| 73 | |
| 74 | /* Command Control Register */ |
| 75 | #define R_CE_CMD_CTRL (0x0C / 4) |
| 76 | #define CTRL_ADDR_BYTE0_DISABLE_SHIFT 4 |
| 77 | #define CTRL_DATA_BYTE0_DISABLE_SHIFT 0 |
| 78 | |
| 79 | #define aspeed_smc_addr_byte_enabled(s, i) \ |
| 80 | (!((s)->regs[R_CE_CMD_CTRL] & (1 << (CTRL_ADDR_BYTE0_DISABLE_SHIFT + (i))))) |
| 81 | #define aspeed_smc_data_byte_enabled(s, i) \ |
| 82 | (!((s)->regs[R_CE_CMD_CTRL] & (1 << (CTRL_DATA_BYTE0_DISABLE_SHIFT + (i))))) |
| 83 | |
| 84 | /* CEx Control Register */ |
| 85 | #define R_CTRL0 (0x10 / 4) |
| 86 | #define CTRL_IO_QPI (1 << 31) |
| 87 | #define CTRL_IO_QUAD_DATA (1 << 30) |
| 88 | #define CTRL_IO_DUAL_DATA (1 << 29) |
| 89 | #define CTRL_IO_DUAL_ADDR_DATA (1 << 28) /* Includes dummies */ |
| 90 | #define CTRL_IO_QUAD_ADDR_DATA (1 << 28) /* Includes dummies */ |
| 91 | #define CTRL_CMD_SHIFT 16 |
| 92 | #define CTRL_CMD_MASK 0xff |
| 93 | #define CTRL_DUMMY_HIGH_SHIFT 14 |
| 94 | #define CTRL_AST2400_SPI_4BYTE (1 << 13) |
| 95 | #define CE_CTRL_CLOCK_FREQ_SHIFT 8 |
| 96 | #define CE_CTRL_CLOCK_FREQ_MASK 0xf |
| 97 | #define CE_CTRL_CLOCK_FREQ(div) \ |
| 98 | (((div) & CE_CTRL_CLOCK_FREQ_MASK) << CE_CTRL_CLOCK_FREQ_SHIFT) |
| 99 | #define CTRL_DUMMY_LOW_SHIFT 6 /* 2 bits [7:6] */ |
| 100 | #define CTRL_CE_STOP_ACTIVE (1 << 2) |
| 101 | #define CTRL_CMD_MODE_MASK 0x3 |
| 102 | #define CTRL_READMODE 0x0 |
| 103 | #define CTRL_FREADMODE 0x1 |
| 104 | #define CTRL_WRITEMODE 0x2 |
| 105 | #define CTRL_USERMODE 0x3 |
| 106 | #define R_CTRL1 (0x14 / 4) |
| 107 | #define R_CTRL2 (0x18 / 4) |
| 108 | #define R_CTRL3 (0x1C / 4) |
| 109 | #define R_CTRL4 (0x20 / 4) |
| 110 | |
| 111 | /* CEx Segment Address Register */ |
| 112 | #define R_SEG_ADDR0 (0x30 / 4) |
| 113 | #define SEG_END_SHIFT 24 /* 8MB units */ |
| 114 | #define SEG_END_MASK 0xff |
| 115 | #define SEG_START_SHIFT 16 /* address bit [A29-A23] */ |
| 116 | #define SEG_START_MASK 0xff |
| 117 | #define R_SEG_ADDR1 (0x34 / 4) |
| 118 | #define R_SEG_ADDR2 (0x38 / 4) |
| 119 | #define R_SEG_ADDR3 (0x3C / 4) |
| 120 | #define R_SEG_ADDR4 (0x40 / 4) |
| 121 | |
| 122 | /* Misc Control Register #1 */ |
| 123 | #define R_MISC_CTRL1 (0x50 / 4) |
| 124 | |
| 125 | /* SPI dummy cycle data */ |
| 126 | #define R_DUMMY_DATA (0x54 / 4) |
| 127 | |
| 128 | /* FMC_WDT2 Control/Status Register for Alternate Boot (AST2600) */ |
| 129 | #define R_FMC_WDT2_CTRL (0x64 / 4) |
| 130 | #define FMC_WDT2_CTRL_ALT_BOOT_MODE BIT(6) /* O: 2 chips 1: 1 chip */ |
| 131 | #define FMC_WDT2_CTRL_SINGLE_BOOT_MODE BIT(5) |
| 132 | #define FMC_WDT2_CTRL_BOOT_SOURCE BIT(4) /* O: primary 1: alternate */ |
| 133 | #define FMC_WDT2_CTRL_EN BIT(0) |
| 134 | |
| 135 | /* DMA DRAM Side Address High Part (AST2700) */ |
| 136 | #define R_DMA_DRAM_ADDR_HIGH (0x7c / 4) |
| 137 | |
| 138 | /* DMA Control/Status Register */ |
| 139 | #define R_DMA_CTRL (0x80 / 4) |
| 140 | #define DMA_CTRL_REQUEST (1 << 31) |
| 141 | #define DMA_CTRL_GRANT (1 << 30) |
| 142 | #define DMA_CTRL_DELAY_MASK 0xf |
| 143 | #define DMA_CTRL_DELAY_SHIFT 8 |
| 144 | #define DMA_CTRL_FREQ_MASK 0xf |
| 145 | #define DMA_CTRL_FREQ_SHIFT 4 |
| 146 | #define DMA_CTRL_CALIB (1 << 3) |
| 147 | #define DMA_CTRL_CKSUM (1 << 2) |
| 148 | #define DMA_CTRL_WRITE (1 << 1) |
| 149 | #define DMA_CTRL_ENABLE (1 << 0) |
| 150 | |
| 151 | /* DMA Flash Side Address */ |
| 152 | #define R_DMA_FLASH_ADDR (0x84 / 4) |
| 153 | |
| 154 | /* DMA DRAM Side Address */ |
| 155 | #define R_DMA_DRAM_ADDR (0x88 / 4) |
| 156 | |
| 157 | /* DMA Length Register */ |
| 158 | #define R_DMA_LEN (0x8C / 4) |
| 159 | |
| 160 | /* Checksum Calculation Result */ |
| 161 | #define R_DMA_CHECKSUM (0x90 / 4) |
| 162 | |
| 163 | /* Read Timing Compensation Register */ |
| 164 | #define R_TIMINGS (0x94 / 4) |
| 165 | |
| 166 | /* Data fifo */ |
| 167 | #define R_DATA_FIFO (0x200 / 4) |
| 168 | |
| 169 | /* SPI controller registers and bits (AST2400) */ |
| 170 | #define R_SPI_CONF (0x00 / 4) |
| 171 | #define SPI_CONF_ENABLE_W0 0 |
| 172 | #define R_SPI_CTRL0 (0x4 / 4) |
| 173 | #define R_SPI_MISC_CTRL (0x10 / 4) |
| 174 | #define R_SPI_TIMINGS (0x14 / 4) |
| 175 | |
| 176 | #define ASPEED_SMC_R_SPI_MAX (0x20 / 4) |
| 177 | #define ASPEED_SMC_R_SMC_MAX (0x20 / 4) |
| 178 | |
| 179 | /* |
| 180 | * DMA DRAM addresses should be 4 bytes aligned and the valid address |
| 181 | * range is 0x40000000 - 0x5FFFFFFF (AST2400) |
| 182 | * 0x80000000 - 0xBFFFFFFF (AST2500) |
| 183 | * |
| 184 | * DMA flash addresses should be 4 bytes aligned and the valid address |
| 185 | * range is 0x20000000 - 0x2FFFFFFF. |
| 186 | * |
| 187 | * DMA length is from 4 bytes to 32MB (AST2500) |
| 188 | * 0: 4 bytes |
| 189 | * 0x1FFFFFC: 32M bytes |
| 190 | * |
| 191 | * DMA length is from 1 byte to 32MB (AST2600, AST10x0 and AST2700) |
| 192 | * 0: 1 byte |
| 193 | * 0x1FFFFFF: 32M bytes |
| 194 | */ |
| 195 | #define DMA_DRAM_ADDR(asc, val) ((val) & (asc)->dma_dram_mask) |
| 196 | #define DMA_DRAM_ADDR_HIGH(val) ((val) & 0xf) |
| 197 | #define DMA_FLASH_ADDR(asc, val) ((val) & (asc)->dma_flash_mask) |
| 198 | #define DMA_LENGTH(val) ((val) & 0x01FFFFFF) |
| 199 | |
| 200 | /* Flash opcodes. */ |
| 201 | #define SPI_OP_READ 0x03 /* Read data bytes (low frequency) */ |
| 202 | |
| 203 | /* |
| 204 | * Default segments mapping addresses and size for each peripheral per |
| 205 | * controller. These can be changed when board is initialized with the |
| 206 | * Segment Address Registers. |
| 207 | */ |
| 208 | static const AspeedSegments aspeed_2500_spi1_segments[]; |
| 209 | static const AspeedSegments aspeed_2500_spi2_segments[]; |
| 210 | |
| 211 | #define ASPEED_SMC_FEATURE_DMA 0x1 |
| 212 | #define ASPEED_SMC_FEATURE_DMA_GRANT 0x2 |
| 213 | #define ASPEED_SMC_FEATURE_WDT_CONTROL 0x4 |
| 214 | #define ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH 0x08 |
| 215 | #define ASPEED_SMC_FEATURE_DATA_FIFO 0x10 |
| 216 | |
| 217 | static inline bool aspeed_smc_has_dma(const AspeedSMCClass *asc) |
| 218 | { |
| 219 | return !!(asc->features & ASPEED_SMC_FEATURE_DMA); |
| 220 | } |
| 221 | |
| 222 | static inline bool aspeed_smc_has_wdt_control(const AspeedSMCClass *asc) |
| 223 | { |
| 224 | return !!(asc->features & ASPEED_SMC_FEATURE_WDT_CONTROL); |
| 225 | } |
| 226 | |
| 227 | static inline bool aspeed_smc_has_dma64(const AspeedSMCClass *asc) |
| 228 | { |
| 229 | return !!(asc->features & ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH); |
| 230 | } |
| 231 | |
| 232 | static inline bool aspeed_smc_has_data_fifo(const AspeedSMCClass *asc) |
| 233 | { |
| 234 | return !!(asc->features & ASPEED_SMC_FEATURE_DATA_FIFO); |
| 235 | } |
| 236 | |
| 237 | #define aspeed_smc_error(fmt, ...) \ |
| 238 | qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt "\n", __func__, ## __VA_ARGS__) |
| 239 | |
| 240 | static bool aspeed_smc_flash_overlap(const AspeedSMCState *s, |
| 241 | const AspeedSegments *new, |
| 242 | int cs) |
| 243 | { |
| 244 | AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); |
| 245 | AspeedSegments seg; |
| 246 | int i; |
| 247 | |
| 248 | for (i = 0; i < asc->cs_num_max; i++) { |
| 249 | if (i == cs) { |
| 250 | continue; |
| 251 | } |
| 252 | |
| 253 | asc->reg_to_segment(s, s->regs[R_SEG_ADDR0 + i], &seg); |
| 254 | |
| 255 | if (new->addr + new->size > seg.addr && |
| 256 | new->addr < seg.addr + seg.size) { |
| 257 | aspeed_smc_error("new segment CS%d [ 0x%" |
| 258 | HWADDR_PRIx" - 0x%"HWADDR_PRIx" ] overlaps with " |
| 259 | "CS%d [ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]", |
| 260 | cs, new->addr, new->addr + new->size, |
| 261 | i, seg.addr, seg.addr + seg.size); |
| 262 | return true; |
| 263 | } |
| 264 | } |
| 265 | return false; |
| 266 | } |
| 267 | |
| 268 | static void aspeed_smc_flash_set_segment_region(AspeedSMCState *s, int cs, |
| 269 | uint64_t regval) |
| 270 | { |
| 271 | AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); |
| 272 | AspeedSMCFlash *fl = &s->flashes[cs]; |
| 273 | AspeedSegments seg; |
| 274 | |
| 275 | asc->reg_to_segment(s, regval, &seg); |
| 276 | |
| 277 | memory_region_transaction_begin(); |
| 278 | memory_region_set_size(&fl->mmio, seg.size); |
| 279 | memory_region_set_address(&fl->mmio, seg.addr - asc->flash_window_base); |
| 280 | memory_region_set_enabled(&fl->mmio, !!seg.size); |
| 281 | memory_region_transaction_commit(); |
| 282 | |
| 283 | if (asc->segment_addr_mask) { |
| 284 | regval &= asc->segment_addr_mask; |
| 285 | } |
| 286 | |
| 287 | s->regs[R_SEG_ADDR0 + cs] = regval; |
| 288 | } |
| 289 | |
| 290 | static void aspeed_smc_flash_set_segment(AspeedSMCState *s, int cs, |
| 291 | uint64_t new) |
| 292 | { |
| 293 | AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); |
| 294 | AspeedSegments seg; |
| 295 | |
| 296 | asc->reg_to_segment(s, new, &seg); |
| 297 | |
| 298 | trace_aspeed_smc_flash_set_segment(cs, new, seg.addr, seg.addr + seg.size); |
| 299 | |
| 300 | /* The start address of CS0 is read-only */ |
| 301 | if (cs == 0 && seg.addr != asc->flash_window_base) { |
| 302 | aspeed_smc_error("Tried to change CS0 start address to 0x%" |
| 303 | HWADDR_PRIx, seg.addr); |
| 304 | seg.addr = asc->flash_window_base; |
| 305 | new = asc->segment_to_reg(s, &seg); |
| 306 | } |
| 307 | |
| 308 | /* |
| 309 | * The end address of the AST2500 spi controllers is also |
| 310 | * read-only. |
| 311 | */ |
| 312 | if ((asc->segments == aspeed_2500_spi1_segments || |
| 313 | asc->segments == aspeed_2500_spi2_segments) && |
| 314 | cs == asc->cs_num_max && |
| 315 | seg.addr + seg.size != asc->segments[cs].addr + |
| 316 | asc->segments[cs].size) { |
| 317 | aspeed_smc_error("Tried to change CS%d end address to 0x%" |
| 318 | HWADDR_PRIx, cs, seg.addr + seg.size); |
| 319 | seg.size = asc->segments[cs].addr + asc->segments[cs].size - |
| 320 | seg.addr; |
| 321 | new = asc->segment_to_reg(s, &seg); |
| 322 | } |
| 323 | |
| 324 | /* Keep the segment in the overall flash window */ |
| 325 | if (seg.size && |
| 326 | (seg.addr + seg.size <= asc->flash_window_base || |
| 327 | seg.addr > asc->flash_window_base + asc->flash_window_size)) { |
| 328 | aspeed_smc_error("new segment for CS%d is invalid : " |
| 329 | "[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]", |
| 330 | cs, seg.addr, seg.addr + seg.size); |
| 331 | return; |
| 332 | } |
| 333 | |
| 334 | /* Check start address vs. alignment */ |
| 335 | if (seg.size && !QEMU_IS_ALIGNED(seg.addr, seg.size)) { |
| 336 | aspeed_smc_error("new segment for CS%d is not " |
| 337 | "aligned : [ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]", |
| 338 | cs, seg.addr, seg.addr + seg.size); |
| 339 | } |
| 340 | |
| 341 | /* And segments should not overlap (in the specs) */ |
| 342 | aspeed_smc_flash_overlap(s, &seg, cs); |
| 343 | |
| 344 | /* All should be fine now to move the region */ |
| 345 | aspeed_smc_flash_set_segment_region(s, cs, new); |
| 346 | } |
| 347 | |
| 348 | static uint64_t aspeed_smc_flash_default_read(void *opaque, hwaddr addr, |
| 349 | unsigned size) |
| 350 | { |
| 351 | aspeed_smc_error("To 0x%" HWADDR_PRIx " of size %u", addr, size); |
| 352 | return 0; |
| 353 | } |
| 354 | |
| 355 | static void aspeed_smc_flash_default_write(void *opaque, hwaddr addr, |
| 356 | uint64_t data, unsigned size) |
| 357 | { |
| 358 | aspeed_smc_error("To 0x%" HWADDR_PRIx " of size %u: 0x%" PRIx64, |
| 359 | addr, size, data); |
| 360 | } |
| 361 | |
| 362 | static const MemoryRegionOps aspeed_smc_flash_default_ops = { |
| 363 | .read = aspeed_smc_flash_default_read, |
| 364 | .write = aspeed_smc_flash_default_write, |
| 365 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 366 | .valid = { |
| 367 | .min_access_size = 1, |
| 368 | .max_access_size = 8, |
| 369 | }, |
| 370 | }; |
| 371 | |
| 372 | static inline int aspeed_smc_flash_mode(const AspeedSMCFlash *fl) |
| 373 | { |
| 374 | const AspeedSMCState *s = fl->controller; |
| 375 | |
| 376 | return s->regs[s->r_ctrl0 + fl->cs] & CTRL_CMD_MODE_MASK; |
| 377 | } |
| 378 | |
| 379 | static inline bool aspeed_smc_is_writable(const AspeedSMCFlash *fl) |
| 380 | { |
| 381 | const AspeedSMCState *s = fl->controller; |
| 382 | |
| 383 | return s->regs[s->r_conf] & (1 << (s->conf_enable_w0 + fl->cs)); |
| 384 | } |
| 385 | |
| 386 | static inline int aspeed_smc_flash_cmd(const AspeedSMCFlash *fl) |
| 387 | { |
| 388 | const AspeedSMCState *s = fl->controller; |
| 389 | int cmd = (s->regs[s->r_ctrl0 + fl->cs] >> CTRL_CMD_SHIFT) & CTRL_CMD_MASK; |
| 390 | |
| 391 | /* |
| 392 | * In read mode, the default SPI command is READ (0x3). In other |
| 393 | * modes, the command should necessarily be defined |
| 394 | * |
| 395 | * TODO: add support for READ4 (0x13) on AST2600 |
| 396 | */ |
| 397 | if (aspeed_smc_flash_mode(fl) == CTRL_READMODE) { |
| 398 | cmd = SPI_OP_READ; |
| 399 | } |
| 400 | |
| 401 | if (!cmd) { |
| 402 | aspeed_smc_error("no command defined for mode %d", |
| 403 | aspeed_smc_flash_mode(fl)); |
| 404 | } |
| 405 | |
| 406 | return cmd; |
| 407 | } |
| 408 | |
| 409 | static inline int aspeed_smc_flash_addr_width(const AspeedSMCFlash *fl) |
| 410 | { |
| 411 | const AspeedSMCState *s = fl->controller; |
| 412 | AspeedSMCClass *asc = fl->asc; |
| 413 | |
| 414 | if (asc->addr_width) { |
| 415 | return asc->addr_width(s); |
| 416 | } else { |
| 417 | return s->regs[s->r_ce_ctrl] & (1 << (CTRL_EXTENDED0 + fl->cs)) ? 4 : 3; |
| 418 | } |
| 419 | } |
| 420 | |
| 421 | static void aspeed_smc_flash_do_select(AspeedSMCFlash *fl, bool unselect) |
| 422 | { |
| 423 | AspeedSMCState *s = fl->controller; |
| 424 | |
| 425 | trace_aspeed_smc_flash_select(fl->cs, unselect ? "un" : ""); |
| 426 | s->unselect = unselect; |
| 427 | qemu_set_irq(s->cs_lines[fl->cs], unselect); |
| 428 | } |
| 429 | |
| 430 | static void aspeed_smc_flash_select(AspeedSMCFlash *fl) |
| 431 | { |
| 432 | aspeed_smc_flash_do_select(fl, false); |
| 433 | } |
| 434 | |
| 435 | static void aspeed_smc_flash_unselect(AspeedSMCFlash *fl) |
| 436 | { |
| 437 | aspeed_smc_flash_do_select(fl, true); |
| 438 | } |
| 439 | |
| 440 | static uint32_t aspeed_smc_check_segment_addr(const AspeedSMCFlash *fl, |
| 441 | uint32_t addr) |
| 442 | { |
| 443 | const AspeedSMCState *s = fl->controller; |
| 444 | AspeedSMCClass *asc = fl->asc; |
| 445 | AspeedSegments seg; |
| 446 | |
| 447 | asc->reg_to_segment(s, s->regs[R_SEG_ADDR0 + fl->cs], &seg); |
| 448 | if ((addr % seg.size) != addr) { |
| 449 | aspeed_smc_error("invalid address 0x%08x for CS%d segment : " |
| 450 | "[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]", |
| 451 | addr, fl->cs, seg.addr, seg.addr + seg.size); |
| 452 | addr %= seg.size; |
| 453 | } |
| 454 | |
| 455 | return addr; |
| 456 | } |
| 457 | |
| 458 | static int aspeed_smc_flash_dummy_bytes(const AspeedSMCFlash *fl) |
| 459 | { |
| 460 | const AspeedSMCState *s = fl->controller; |
| 461 | uint32_t r_ctrl0 = s->regs[s->r_ctrl0 + fl->cs]; |
| 462 | uint32_t dummy_high = (r_ctrl0 >> CTRL_DUMMY_HIGH_SHIFT) & 0x1; |
| 463 | uint32_t dummy_low = (r_ctrl0 >> CTRL_DUMMY_LOW_SHIFT) & 0x3; |
| 464 | uint32_t dummy_bytes = (dummy_high << 2) | dummy_low; |
| 465 | |
| 466 | /* |
| 467 | * Scale the controller dummy field to SSI byte transfers using the |
| 468 | * direct-read dummy/address bus width. |
| 469 | */ |
| 470 | if ((r_ctrl0 & CTRL_IO_QPI) || |
| 471 | ((r_ctrl0 & CTRL_IO_QUAD_DATA) && |
| 472 | (r_ctrl0 & CTRL_IO_QUAD_ADDR_DATA))) { |
| 473 | dummy_bytes *= 4; |
| 474 | } else if ((r_ctrl0 & CTRL_IO_DUAL_DATA) && |
| 475 | (r_ctrl0 & CTRL_IO_DUAL_ADDR_DATA)) { |
| 476 | dummy_bytes *= 2; |
| 477 | } |
| 478 | |
| 479 | return dummy_bytes; |
| 480 | } |
| 481 | |
| 482 | static void aspeed_smc_flash_setup(AspeedSMCFlash *fl, uint32_t addr) |
| 483 | { |
| 484 | const AspeedSMCState *s = fl->controller; |
| 485 | uint8_t cmd = aspeed_smc_flash_cmd(fl); |
| 486 | int i = aspeed_smc_flash_addr_width(fl); |
| 487 | |
| 488 | /* Flash access can not exceed CS segment */ |
| 489 | addr = aspeed_smc_check_segment_addr(fl, addr); |
| 490 | |
| 491 | ssi_transfer(s->spi, cmd); |
| 492 | while (i--) { |
| 493 | if (aspeed_smc_addr_byte_enabled(s, i)) { |
| 494 | ssi_transfer(s->spi, (addr >> (i * 8)) & 0xff); |
| 495 | } |
| 496 | } |
| 497 | |
| 498 | /* |
| 499 | * Use fake transfers to model dummy bytes. The value should |
| 500 | * be configured to some non-zero value in fast read mode and |
| 501 | * zero in read mode. But, as the HW allows inconsistent |
| 502 | * settings, let's check for fast read mode. |
| 503 | */ |
| 504 | if (aspeed_smc_flash_mode(fl) == CTRL_FREADMODE) { |
| 505 | for (i = 0; i < aspeed_smc_flash_dummy_bytes(fl); i++) { |
| 506 | ssi_transfer(fl->controller->spi, s->regs[R_DUMMY_DATA] & 0xff); |
| 507 | } |
| 508 | } |
| 509 | } |
| 510 | |
| 511 | static MemTxResult aspeed_smc_flash_read(void *opaque, hwaddr addr, |
| 512 | uint64_t *data, unsigned size, MemTxAttrs attrs) |
| 513 | { |
| 514 | AspeedSMCFlash *fl = opaque; |
| 515 | AspeedSMCState *s = fl->controller; |
| 516 | int i; |
| 517 | |
| 518 | *data = 0; |
| 519 | switch (aspeed_smc_flash_mode(fl)) { |
| 520 | case CTRL_USERMODE: |
| 521 | for (i = 0; i < size; i++) { |
| 522 | *data |= (uint64_t) ssi_transfer(s->spi, 0x0) << (8 * i); |
| 523 | } |
| 524 | break; |
| 525 | case CTRL_READMODE: |
| 526 | case CTRL_FREADMODE: |
| 527 | aspeed_smc_flash_select(fl); |
| 528 | aspeed_smc_flash_setup(fl, addr); |
| 529 | |
| 530 | for (i = 0; i < size; i++) { |
| 531 | *data |= (uint64_t) ssi_transfer(s->spi, 0x0) << (8 * i); |
| 532 | } |
| 533 | |
| 534 | aspeed_smc_flash_unselect(fl); |
| 535 | break; |
| 536 | default: |
| 537 | aspeed_smc_error("invalid flash mode %d", aspeed_smc_flash_mode(fl)); |
| 538 | return MEMTX_ERROR; |
| 539 | } |
| 540 | |
| 541 | trace_aspeed_smc_flash_read(fl->cs, addr, size, *data, |
| 542 | aspeed_smc_flash_mode(fl)); |
| 543 | return MEMTX_OK; |
| 544 | } |
| 545 | |
| 546 | static MemTxResult aspeed_smc_flash_write(void *opaque, hwaddr addr, |
| 547 | uint64_t data, unsigned size, MemTxAttrs attrs) |
| 548 | { |
| 549 | AspeedSMCFlash *fl = opaque; |
| 550 | AspeedSMCState *s = fl->controller; |
| 551 | int i; |
| 552 | |
| 553 | trace_aspeed_smc_flash_write(fl->cs, addr, size, data, |
| 554 | aspeed_smc_flash_mode(fl)); |
| 555 | |
| 556 | if (!aspeed_smc_is_writable(fl)) { |
| 557 | aspeed_smc_error("flash is not writable at 0x%" HWADDR_PRIx, addr); |
| 558 | return MEMTX_ERROR; |
| 559 | } |
| 560 | |
| 561 | switch (aspeed_smc_flash_mode(fl)) { |
| 562 | case CTRL_USERMODE: |
| 563 | for (i = 0; i < size; i++) { |
| 564 | ssi_transfer(s->spi, (data >> (8 * i)) & 0xff); |
| 565 | } |
| 566 | break; |
| 567 | case CTRL_WRITEMODE: |
| 568 | aspeed_smc_flash_select(fl); |
| 569 | aspeed_smc_flash_setup(fl, addr); |
| 570 | |
| 571 | for (i = 0; i < size; i++) { |
| 572 | ssi_transfer(s->spi, (data >> (8 * i)) & 0xff); |
| 573 | } |
| 574 | |
| 575 | aspeed_smc_flash_unselect(fl); |
| 576 | break; |
| 577 | default: |
| 578 | aspeed_smc_error("invalid flash mode %d", aspeed_smc_flash_mode(fl)); |
| 579 | return MEMTX_ERROR; |
| 580 | } |
| 581 | |
| 582 | return MEMTX_OK; |
| 583 | } |
| 584 | |
| 585 | static const MemoryRegionOps aspeed_smc_flash_ops = { |
| 586 | .read_with_attrs = aspeed_smc_flash_read, |
| 587 | .write_with_attrs = aspeed_smc_flash_write, |
| 588 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 589 | .valid = { |
| 590 | .min_access_size = 1, |
| 591 | .max_access_size = 8, |
| 592 | }, |
| 593 | }; |
| 594 | |
| 595 | static void aspeed_smc_flash_update_ctrl(AspeedSMCFlash *fl, uint32_t value) |
| 596 | { |
| 597 | AspeedSMCState *s = fl->controller; |
| 598 | bool unselect = false; |
| 599 | uint32_t old_mode; |
| 600 | uint32_t new_mode; |
| 601 | |
| 602 | old_mode = s->regs[s->r_ctrl0 + fl->cs] & CTRL_CMD_MODE_MASK; |
| 603 | new_mode = value & CTRL_CMD_MODE_MASK; |
| 604 | |
| 605 | if (old_mode == CTRL_USERMODE) { |
| 606 | if (new_mode != CTRL_USERMODE) { |
| 607 | unselect = true; |
| 608 | } |
| 609 | |
| 610 | /* A change of CTRL_CE_STOP_ACTIVE from 0 to 1, unselects the CS */ |
| 611 | if (!(s->regs[s->r_ctrl0 + fl->cs] & CTRL_CE_STOP_ACTIVE) && |
| 612 | value & CTRL_CE_STOP_ACTIVE) { |
| 613 | unselect = true; |
| 614 | } |
| 615 | } else { |
| 616 | if (new_mode != CTRL_USERMODE) { |
| 617 | unselect = true; |
| 618 | } |
| 619 | } |
| 620 | |
| 621 | s->regs[s->r_ctrl0 + fl->cs] = value; |
| 622 | |
| 623 | if (unselect != s->unselect) { |
| 624 | aspeed_smc_flash_do_select(fl, unselect); |
| 625 | } |
| 626 | } |
| 627 | |
| 628 | static void aspeed_smc_reset_hold(Object *obj, ResetType type) |
| 629 | { |
| 630 | AspeedSMCState *s = ASPEED_SMC(obj); |
| 631 | AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); |
| 632 | int i; |
| 633 | |
| 634 | if (asc->resets) { |
| 635 | memcpy(s->regs, asc->resets, sizeof s->regs); |
| 636 | } else { |
| 637 | memset(s->regs, 0, sizeof s->regs); |
| 638 | } |
| 639 | |
| 640 | for (i = 0; i < asc->cs_num_max; i++) { |
| 641 | DeviceState *dev = ssi_get_cs(s->spi, i); |
| 642 | if (dev) { |
| 643 | Object *o = OBJECT(dev); |
| 644 | |
| 645 | if (!object_dynamic_cast(o, TYPE_M25P80)) { |
| 646 | warn_report("Aspeed SMC %s.%d : Invalid %s device type", |
| 647 | BUS(s->spi)->name, i, object_get_typename(o)); |
| 648 | continue; |
| 649 | } |
| 650 | |
| 651 | qemu_irq cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0); |
| 652 | qdev_connect_gpio_out_named(DEVICE(s), "cs", i, cs_line); |
| 653 | } |
| 654 | } |
| 655 | |
| 656 | /* Unselect all peripherals */ |
| 657 | for (i = 0; i < asc->cs_num_max; ++i) { |
| 658 | s->regs[s->r_ctrl0 + i] |= CTRL_CE_STOP_ACTIVE; |
| 659 | qemu_set_irq(s->cs_lines[i], true); |
| 660 | } |
| 661 | |
| 662 | s->unselect = true; |
| 663 | |
| 664 | /* setup the default segment register values and regions for all */ |
| 665 | for (i = 0; i < asc->cs_num_max; ++i) { |
| 666 | aspeed_smc_flash_set_segment_region(s, i, |
| 667 | asc->segment_to_reg(s, &asc->segments[i])); |
| 668 | } |
| 669 | } |
| 670 | |
| 671 | static MemTxResult aspeed_smc_read(void *opaque, hwaddr addr, uint64_t *data, |
| 672 | unsigned int size, MemTxAttrs attrs) |
| 673 | { |
| 674 | AspeedSMCState *s = ASPEED_SMC(opaque); |
| 675 | AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(opaque); |
| 676 | int cs; |
| 677 | |
| 678 | addr >>= 2; |
| 679 | |
| 680 | if (addr == s->r_conf || |
| 681 | (addr >= s->r_timings && |
| 682 | addr < s->r_timings + asc->nregs_timings) || |
| 683 | addr == s->r_ce_ctrl || |
| 684 | addr == R_CE_CMD_CTRL || |
| 685 | addr == R_INTR_CTRL || |
| 686 | addr == R_DUMMY_DATA || |
| 687 | (aspeed_smc_has_wdt_control(asc) && addr == R_FMC_WDT2_CTRL) || |
| 688 | (aspeed_smc_has_dma(asc) && addr == R_DMA_CTRL) || |
| 689 | (aspeed_smc_has_dma(asc) && addr == R_DMA_FLASH_ADDR) || |
| 690 | (aspeed_smc_has_dma(asc) && addr == R_DMA_DRAM_ADDR) || |
| 691 | (aspeed_smc_has_dma(asc) && aspeed_smc_has_dma64(asc) && |
| 692 | addr == R_DMA_DRAM_ADDR_HIGH) || |
| 693 | (aspeed_smc_has_dma(asc) && addr == R_DMA_LEN) || |
| 694 | (aspeed_smc_has_dma(asc) && addr == R_DMA_CHECKSUM) || |
| 695 | (addr >= R_SEG_ADDR0 && |
| 696 | addr < R_SEG_ADDR0 + asc->cs_num_max) || |
| 697 | (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + asc->cs_num_max)) { |
| 698 | |
| 699 | trace_aspeed_smc_read(addr << 2, size, s->regs[addr]); |
| 700 | |
| 701 | *data = s->regs[addr]; |
| 702 | } else if (aspeed_smc_has_data_fifo(asc) && addr >= R_DATA_FIFO) { |
| 703 | cs = asc->data_fifo_offset_to_cs(s, addr << 2); |
| 704 | if (cs >= 0) { |
| 705 | /* |
| 706 | * Data fifo mode only supports SPI user mode. |
| 707 | * The flash address is provided by the SPI command/address cycles, |
| 708 | * the MMIO addr parameter is ignored. |
| 709 | */ |
| 710 | return aspeed_smc_flash_read(&s->flashes[cs], 0, data, size, attrs); |
| 711 | } |
| 712 | aspeed_smc_error("Invalid data fifo offset %" HWADDR_PRIx, addr << 2); |
| 713 | return MEMTX_ERROR; |
| 714 | } else { |
| 715 | qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n", |
| 716 | __func__, addr); |
| 717 | *data = -1; |
| 718 | } |
| 719 | return MEMTX_OK; |
| 720 | } |
| 721 | |
| 722 | static uint8_t aspeed_smc_hclk_divisor(uint8_t hclk_mask) |
| 723 | { |
| 724 | /* HCLK/1 .. HCLK/16 */ |
| 725 | const uint8_t hclk_divisors[] = { |
| 726 | 15, 7, 14, 6, 13, 5, 12, 4, 11, 3, 10, 2, 9, 1, 8, 0 |
| 727 | }; |
| 728 | int i; |
| 729 | |
| 730 | for (i = 0; i < ARRAY_SIZE(hclk_divisors); i++) { |
| 731 | if (hclk_mask == hclk_divisors[i]) { |
| 732 | return i + 1; |
| 733 | } |
| 734 | } |
| 735 | |
| 736 | g_assert_not_reached(); |
| 737 | } |
| 738 | |
| 739 | /* |
| 740 | * When doing calibration, the SPI clock rate in the CE0 Control |
| 741 | * Register and the read delay cycles in the Read Timing Compensation |
| 742 | * Register are set using bit[11:4] of the DMA Control Register. |
| 743 | */ |
| 744 | static void aspeed_smc_dma_calibration(AspeedSMCState *s) |
| 745 | { |
| 746 | uint8_t delay = |
| 747 | (s->regs[R_DMA_CTRL] >> DMA_CTRL_DELAY_SHIFT) & DMA_CTRL_DELAY_MASK; |
| 748 | uint8_t hclk_mask = |
| 749 | (s->regs[R_DMA_CTRL] >> DMA_CTRL_FREQ_SHIFT) & DMA_CTRL_FREQ_MASK; |
| 750 | uint8_t hclk_div = aspeed_smc_hclk_divisor(hclk_mask); |
| 751 | uint32_t hclk_shift = (hclk_div - 1) << 2; |
| 752 | uint8_t cs; |
| 753 | |
| 754 | /* |
| 755 | * The Read Timing Compensation Register values apply to all CS on |
| 756 | * the SPI bus and only HCLK/1 - HCLK/5 can have tunable delays |
| 757 | */ |
| 758 | if (hclk_div && hclk_div < 6) { |
| 759 | s->regs[s->r_timings] &= ~(0xf << hclk_shift); |
| 760 | s->regs[s->r_timings] |= delay << hclk_shift; |
| 761 | } |
| 762 | |
| 763 | /* |
| 764 | * TODO: compute the CS from the DMA address and the segment |
| 765 | * registers. This is not really a problem for now because the |
| 766 | * Timing Register values apply to all CS and software uses CS0 to |
| 767 | * do calibration. |
| 768 | */ |
| 769 | cs = 0; |
| 770 | s->regs[s->r_ctrl0 + cs] &= |
| 771 | ~(CE_CTRL_CLOCK_FREQ_MASK << CE_CTRL_CLOCK_FREQ_SHIFT); |
| 772 | s->regs[s->r_ctrl0 + cs] |= CE_CTRL_CLOCK_FREQ(hclk_div); |
| 773 | } |
| 774 | |
| 775 | /* |
| 776 | * Emulate read errors in the DMA Checksum Register for high |
| 777 | * frequencies and optimistic settings of the Read Timing Compensation |
| 778 | * Register. This will help in tuning the SPI timing calibration |
| 779 | * algorithm. |
| 780 | */ |
| 781 | static bool aspeed_smc_inject_read_failure(AspeedSMCState *s) |
| 782 | { |
| 783 | uint8_t delay = |
| 784 | (s->regs[R_DMA_CTRL] >> DMA_CTRL_DELAY_SHIFT) & DMA_CTRL_DELAY_MASK; |
| 785 | uint8_t hclk_mask = |
| 786 | (s->regs[R_DMA_CTRL] >> DMA_CTRL_FREQ_SHIFT) & DMA_CTRL_FREQ_MASK; |
| 787 | |
| 788 | /* |
| 789 | * Typical values of a palmetto-bmc machine. |
| 790 | */ |
| 791 | switch (aspeed_smc_hclk_divisor(hclk_mask)) { |
| 792 | case 4 ... 16: |
| 793 | return false; |
| 794 | case 3: /* at least one HCLK cycle delay */ |
| 795 | return (delay & 0x7) < 1; |
| 796 | case 2: /* at least two HCLK cycle delay */ |
| 797 | return (delay & 0x7) < 2; |
| 798 | case 1: /* (> 100MHz) is above the max freq of the controller */ |
| 799 | return true; |
| 800 | default: |
| 801 | g_assert_not_reached(); |
| 802 | } |
| 803 | } |
| 804 | |
| 805 | static uint64_t aspeed_smc_dma_dram_addr(AspeedSMCState *s) |
| 806 | { |
| 807 | return s->regs[R_DMA_DRAM_ADDR] | |
| 808 | ((uint64_t) s->regs[R_DMA_DRAM_ADDR_HIGH] << 32); |
| 809 | } |
| 810 | |
| 811 | static uint32_t aspeed_smc_dma_len(AspeedSMCState *s) |
| 812 | { |
| 813 | AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); |
| 814 | |
| 815 | return QEMU_ALIGN_UP(s->regs[R_DMA_LEN] + asc->dma_start_length, 4); |
| 816 | } |
| 817 | |
| 818 | /* |
| 819 | * Accumulate the result of the reads to provide a checksum that will |
| 820 | * be used to validate the read timing settings. |
| 821 | */ |
| 822 | static void aspeed_smc_dma_checksum(AspeedSMCState *s) |
| 823 | { |
| 824 | MemTxResult result; |
| 825 | uint32_t dma_len; |
| 826 | uint32_t data; |
| 827 | |
| 828 | if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) { |
| 829 | aspeed_smc_error("invalid direction for DMA checksum"); |
| 830 | return; |
| 831 | } |
| 832 | |
| 833 | if (s->regs[R_DMA_CTRL] & DMA_CTRL_CALIB) { |
| 834 | aspeed_smc_dma_calibration(s); |
| 835 | } |
| 836 | |
| 837 | dma_len = aspeed_smc_dma_len(s); |
| 838 | |
| 839 | while (dma_len) { |
| 840 | data = address_space_ldl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR], |
| 841 | MEMTXATTRS_UNSPECIFIED, &result); |
| 842 | if (result != MEMTX_OK) { |
| 843 | aspeed_smc_error("Flash read failed @%08x", |
| 844 | s->regs[R_DMA_FLASH_ADDR]); |
| 845 | return; |
| 846 | } |
| 847 | trace_aspeed_smc_dma_checksum(s->regs[R_DMA_FLASH_ADDR], data); |
| 848 | |
| 849 | /* |
| 850 | * When the DMA is on-going, the DMA registers are updated |
| 851 | * with the current working addresses and length. |
| 852 | */ |
| 853 | s->regs[R_DMA_CHECKSUM] += data; |
| 854 | s->regs[R_DMA_FLASH_ADDR] += 4; |
| 855 | dma_len -= 4; |
| 856 | s->regs[R_DMA_LEN] = dma_len; |
| 857 | } |
| 858 | |
| 859 | if (s->inject_failure && aspeed_smc_inject_read_failure(s)) { |
| 860 | s->regs[R_DMA_CHECKSUM] = 0xbadc0de; |
| 861 | } |
| 862 | |
| 863 | } |
| 864 | |
| 865 | static void aspeed_smc_dma_rw(AspeedSMCState *s) |
| 866 | { |
| 867 | AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); |
| 868 | uint64_t dma_dram_offset; |
| 869 | uint64_t dma_dram_addr; |
| 870 | MemTxResult result; |
| 871 | uint32_t dma_len; |
| 872 | uint32_t data; |
| 873 | |
| 874 | dma_len = aspeed_smc_dma_len(s); |
| 875 | dma_dram_addr = aspeed_smc_dma_dram_addr(s); |
| 876 | |
| 877 | if (aspeed_smc_has_dma64(asc)) { |
| 878 | dma_dram_offset = dma_dram_addr - s->dram_base; |
| 879 | } else { |
| 880 | dma_dram_offset = dma_dram_addr; |
| 881 | } |
| 882 | |
| 883 | trace_aspeed_smc_dma_rw(s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE ? |
| 884 | "write" : "read", |
| 885 | s->regs[R_DMA_FLASH_ADDR], |
| 886 | dma_dram_offset, |
| 887 | dma_len); |
| 888 | while (dma_len) { |
| 889 | if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) { |
| 890 | data = address_space_ldl_le(&s->dram_as, dma_dram_offset, |
| 891 | MEMTXATTRS_UNSPECIFIED, &result); |
| 892 | if (result != MEMTX_OK) { |
| 893 | aspeed_smc_error("DRAM read failed @%" PRIx64, |
| 894 | dma_dram_offset); |
| 895 | return; |
| 896 | } |
| 897 | |
| 898 | address_space_stl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR], |
| 899 | data, MEMTXATTRS_UNSPECIFIED, &result); |
| 900 | if (result != MEMTX_OK) { |
| 901 | aspeed_smc_error("Flash write failed @%08x", |
| 902 | s->regs[R_DMA_FLASH_ADDR]); |
| 903 | return; |
| 904 | } |
| 905 | } else { |
| 906 | data = address_space_ldl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR], |
| 907 | MEMTXATTRS_UNSPECIFIED, &result); |
| 908 | if (result != MEMTX_OK) { |
| 909 | aspeed_smc_error("Flash read failed @%08x", |
| 910 | s->regs[R_DMA_FLASH_ADDR]); |
| 911 | return; |
| 912 | } |
| 913 | |
| 914 | address_space_stl_le(&s->dram_as, dma_dram_offset, |
| 915 | data, MEMTXATTRS_UNSPECIFIED, &result); |
| 916 | if (result != MEMTX_OK) { |
| 917 | aspeed_smc_error("DRAM write failed @%" PRIx64, |
| 918 | dma_dram_offset); |
| 919 | return; |
| 920 | } |
| 921 | } |
| 922 | |
| 923 | /* |
| 924 | * When the DMA is on-going, the DMA registers are updated |
| 925 | * with the current working addresses and length. |
| 926 | */ |
| 927 | dma_dram_offset += 4; |
| 928 | dma_dram_addr += 4; |
| 929 | |
| 930 | s->regs[R_DMA_DRAM_ADDR_HIGH] = dma_dram_addr >> 32; |
| 931 | s->regs[R_DMA_DRAM_ADDR] = dma_dram_addr & 0xffffffff; |
| 932 | s->regs[R_DMA_FLASH_ADDR] += 4; |
| 933 | dma_len -= 4; |
| 934 | s->regs[R_DMA_LEN] = dma_len; |
| 935 | s->regs[R_DMA_CHECKSUM] += data; |
| 936 | } |
| 937 | } |
| 938 | |
| 939 | static void aspeed_smc_dma_stop(AspeedSMCState *s) |
| 940 | { |
| 941 | /* |
| 942 | * When the DMA is disabled, INTR_CTRL_DMA_STATUS=0 means the |
| 943 | * engine is idle |
| 944 | */ |
| 945 | s->regs[R_INTR_CTRL] &= ~INTR_CTRL_DMA_STATUS; |
| 946 | s->regs[R_DMA_CHECKSUM] = 0; |
| 947 | |
| 948 | /* |
| 949 | * Lower the DMA irq in any case. The IRQ control register could |
| 950 | * have been cleared before disabling the DMA. |
| 951 | */ |
| 952 | qemu_irq_lower(s->irq); |
| 953 | } |
| 954 | |
| 955 | /* |
| 956 | * When INTR_CTRL_DMA_STATUS=1, the DMA has completed and a new DMA |
| 957 | * can start even if the result of the previous was not collected. |
| 958 | */ |
| 959 | static bool aspeed_smc_dma_in_progress(AspeedSMCState *s) |
| 960 | { |
| 961 | return s->regs[R_DMA_CTRL] & DMA_CTRL_ENABLE && |
| 962 | !(s->regs[R_INTR_CTRL] & INTR_CTRL_DMA_STATUS); |
| 963 | } |
| 964 | |
| 965 | static void aspeed_smc_dma_done(AspeedSMCState *s) |
| 966 | { |
| 967 | s->regs[R_INTR_CTRL] |= INTR_CTRL_DMA_STATUS; |
| 968 | if (s->regs[R_INTR_CTRL] & INTR_CTRL_DMA_EN) { |
| 969 | qemu_irq_raise(s->irq); |
| 970 | } |
| 971 | } |
| 972 | |
| 973 | static void aspeed_smc_dma_ctrl(AspeedSMCState *s, uint32_t dma_ctrl) |
| 974 | { |
| 975 | if (!(dma_ctrl & DMA_CTRL_ENABLE)) { |
| 976 | s->regs[R_DMA_CTRL] = dma_ctrl; |
| 977 | |
| 978 | aspeed_smc_dma_stop(s); |
| 979 | return; |
| 980 | } |
| 981 | |
| 982 | if (aspeed_smc_dma_in_progress(s)) { |
| 983 | aspeed_smc_error("DMA in progress !"); |
| 984 | return; |
| 985 | } |
| 986 | |
| 987 | s->regs[R_DMA_CTRL] = dma_ctrl; |
| 988 | |
| 989 | if (s->regs[R_DMA_CTRL] & DMA_CTRL_CKSUM) { |
| 990 | aspeed_smc_dma_checksum(s); |
| 991 | } else { |
| 992 | aspeed_smc_dma_rw(s); |
| 993 | } |
| 994 | |
| 995 | aspeed_smc_dma_done(s); |
| 996 | } |
| 997 | |
| 998 | static inline bool aspeed_smc_dma_granted(AspeedSMCState *s) |
| 999 | { |
| 1000 | AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); |
| 1001 | |
| 1002 | if (!(asc->features & ASPEED_SMC_FEATURE_DMA_GRANT)) { |
| 1003 | return true; |
| 1004 | } |
| 1005 | |
| 1006 | if (!(s->regs[R_DMA_CTRL] & DMA_CTRL_GRANT)) { |
| 1007 | aspeed_smc_error("DMA not granted"); |
| 1008 | return false; |
| 1009 | } |
| 1010 | |
| 1011 | return true; |
| 1012 | } |
| 1013 | |
| 1014 | static void aspeed_2600_smc_dma_ctrl(AspeedSMCState *s, uint32_t dma_ctrl) |
| 1015 | { |
| 1016 | /* Preserve DMA bits */ |
| 1017 | dma_ctrl |= s->regs[R_DMA_CTRL] & (DMA_CTRL_REQUEST | DMA_CTRL_GRANT); |
| 1018 | |
| 1019 | if (dma_ctrl == 0xAEED0000) { |
| 1020 | /* automatically grant request */ |
| 1021 | s->regs[R_DMA_CTRL] |= (DMA_CTRL_REQUEST | DMA_CTRL_GRANT); |
| 1022 | return; |
| 1023 | } |
| 1024 | |
| 1025 | /* clear request */ |
| 1026 | if (dma_ctrl == 0xDEEA0000) { |
| 1027 | s->regs[R_DMA_CTRL] &= ~(DMA_CTRL_REQUEST | DMA_CTRL_GRANT); |
| 1028 | return; |
| 1029 | } |
| 1030 | |
| 1031 | if (!aspeed_smc_dma_granted(s)) { |
| 1032 | aspeed_smc_error("DMA not granted"); |
| 1033 | return; |
| 1034 | } |
| 1035 | |
| 1036 | aspeed_smc_dma_ctrl(s, dma_ctrl); |
| 1037 | s->regs[R_DMA_CTRL] &= ~(DMA_CTRL_REQUEST | DMA_CTRL_GRANT); |
| 1038 | } |
| 1039 | |
| 1040 | static MemTxResult aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data, |
| 1041 | unsigned int size, MemTxAttrs attrs) |
| 1042 | { |
| 1043 | AspeedSMCState *s = ASPEED_SMC(opaque); |
| 1044 | AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); |
| 1045 | uint32_t value = data; |
| 1046 | |
| 1047 | trace_aspeed_smc_write(addr, size, data); |
| 1048 | |
| 1049 | addr >>= 2; |
| 1050 | |
| 1051 | if (addr == s->r_conf || |
| 1052 | (addr >= s->r_timings && |
| 1053 | addr < s->r_timings + asc->nregs_timings) || |
| 1054 | addr == s->r_ce_ctrl) { |
| 1055 | s->regs[addr] = value; |
| 1056 | } else if (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + asc->cs_num_max) { |
| 1057 | int cs = addr - s->r_ctrl0; |
| 1058 | aspeed_smc_flash_update_ctrl(&s->flashes[cs], value); |
| 1059 | } else if (addr >= R_SEG_ADDR0 && |
| 1060 | addr < R_SEG_ADDR0 + asc->cs_num_max) { |
| 1061 | int cs = addr - R_SEG_ADDR0; |
| 1062 | |
| 1063 | if (value != s->regs[R_SEG_ADDR0 + cs]) { |
| 1064 | aspeed_smc_flash_set_segment(s, cs, value); |
| 1065 | } |
| 1066 | } else if (addr == R_CE_CMD_CTRL) { |
| 1067 | s->regs[addr] = value & 0xff; |
| 1068 | } else if (addr == R_DUMMY_DATA) { |
| 1069 | s->regs[addr] = value & 0xff; |
| 1070 | } else if (aspeed_smc_has_wdt_control(asc) && addr == R_FMC_WDT2_CTRL) { |
| 1071 | s->regs[addr] = value & FMC_WDT2_CTRL_EN; |
| 1072 | } else if (addr == R_INTR_CTRL) { |
| 1073 | s->regs[addr] = value; |
| 1074 | } else if (aspeed_smc_has_dma(asc) && addr == R_DMA_CTRL) { |
| 1075 | asc->dma_ctrl(s, value); |
| 1076 | } else if (aspeed_smc_has_dma(asc) && addr == R_DMA_DRAM_ADDR && |
| 1077 | aspeed_smc_dma_granted(s)) { |
| 1078 | s->regs[addr] = DMA_DRAM_ADDR(asc, value); |
| 1079 | } else if (aspeed_smc_has_dma(asc) && addr == R_DMA_FLASH_ADDR && |
| 1080 | aspeed_smc_dma_granted(s)) { |
| 1081 | s->regs[addr] = DMA_FLASH_ADDR(asc, value); |
| 1082 | } else if (aspeed_smc_has_dma(asc) && addr == R_DMA_LEN && |
| 1083 | aspeed_smc_dma_granted(s)) { |
| 1084 | s->regs[addr] = DMA_LENGTH(value); |
| 1085 | } else if (aspeed_smc_has_dma(asc) && aspeed_smc_has_dma64(asc) && |
| 1086 | addr == R_DMA_DRAM_ADDR_HIGH) { |
| 1087 | s->regs[addr] = DMA_DRAM_ADDR_HIGH(value); |
| 1088 | } else if (aspeed_smc_has_data_fifo(asc) && addr >= R_DATA_FIFO) { |
| 1089 | int cs = asc->data_fifo_offset_to_cs(s, addr << 2); |
| 1090 | if (cs >= 0) { |
| 1091 | /* |
| 1092 | * Data fifo mode only supports SPI user mode. |
| 1093 | * The flash address is provided by the SPI command/address cycles, |
| 1094 | * the MMIO addr parameter is ignored. |
| 1095 | */ |
| 1096 | return aspeed_smc_flash_write(&s->flashes[cs], 0, data, size, |
| 1097 | attrs); |
| 1098 | } |
| 1099 | aspeed_smc_error("Invalid data fifo offset %" HWADDR_PRIx, addr << 2); |
| 1100 | return MEMTX_ERROR; |
| 1101 | } else { |
| 1102 | qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n", |
| 1103 | __func__, addr); |
| 1104 | } |
| 1105 | return MEMTX_OK; |
| 1106 | } |
| 1107 | |
| 1108 | static const MemoryRegionOps aspeed_smc_ops = { |
| 1109 | .read_with_attrs = aspeed_smc_read, |
| 1110 | .write_with_attrs = aspeed_smc_write, |
| 1111 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 1112 | }; |
| 1113 | |
| 1114 | static void aspeed_smc_instance_init(Object *obj) |
| 1115 | { |
| 1116 | AspeedSMCState *s = ASPEED_SMC(obj); |
| 1117 | AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); |
| 1118 | int i; |
| 1119 | |
| 1120 | for (i = 0; i < asc->cs_num_max; i++) { |
| 1121 | object_initialize_child(obj, "flash[*]", &s->flashes[i], |
| 1122 | TYPE_ASPEED_SMC_FLASH); |
| 1123 | } |
| 1124 | } |
| 1125 | |
| 1126 | /* |
| 1127 | * Initialize the custom address spaces for DMAs |
| 1128 | */ |
| 1129 | static void aspeed_smc_dma_setup(AspeedSMCState *s, Error **errp) |
| 1130 | { |
| 1131 | if (!s->dram_mr) { |
| 1132 | error_setg(errp, TYPE_ASPEED_SMC ": 'dram' link not set"); |
| 1133 | return; |
| 1134 | } |
| 1135 | |
| 1136 | address_space_init(&s->flash_as, &s->mmio_flash, |
| 1137 | TYPE_ASPEED_SMC ".dma-flash"); |
| 1138 | address_space_init(&s->dram_as, s->dram_mr, |
| 1139 | TYPE_ASPEED_SMC ".dma-dram"); |
| 1140 | } |
| 1141 | |
| 1142 | static void aspeed_smc_realize(DeviceState *dev, Error **errp) |
| 1143 | { |
| 1144 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
| 1145 | AspeedSMCState *s = ASPEED_SMC(dev); |
| 1146 | AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); |
| 1147 | int i; |
| 1148 | hwaddr offset = 0; |
| 1149 | |
| 1150 | /* keep a copy under AspeedSMCState to speed up accesses */ |
| 1151 | s->r_conf = asc->r_conf; |
| 1152 | s->r_ce_ctrl = asc->r_ce_ctrl; |
| 1153 | s->r_ctrl0 = asc->r_ctrl0; |
| 1154 | s->r_timings = asc->r_timings; |
| 1155 | s->conf_enable_w0 = asc->conf_enable_w0; |
| 1156 | |
| 1157 | /* DMA irq. Keep it first for the initialization in the SoC */ |
| 1158 | sysbus_init_irq(sbd, &s->irq); |
| 1159 | |
| 1160 | s->spi = ssi_create_bus(dev, NULL); |
| 1161 | |
| 1162 | /* Setup cs_lines for peripherals */ |
| 1163 | s->cs_lines = g_new0(qemu_irq, asc->cs_num_max); |
| 1164 | qdev_init_gpio_out_named(DEVICE(s), s->cs_lines, "cs", asc->cs_num_max); |
| 1165 | |
| 1166 | /* The memory region for the controller registers */ |
| 1167 | memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_smc_ops, s, |
| 1168 | TYPE_ASPEED_SMC, asc->nregs * 4); |
| 1169 | sysbus_init_mmio(sbd, &s->mmio); |
| 1170 | |
| 1171 | /* |
| 1172 | * The container memory region representing the address space |
| 1173 | * window in which the flash modules are mapped. The size and |
| 1174 | * address depends on the SoC model and controller type. |
| 1175 | */ |
| 1176 | memory_region_init(&s->mmio_flash_container, OBJECT(s), |
| 1177 | TYPE_ASPEED_SMC ".container", |
| 1178 | asc->flash_window_size); |
| 1179 | sysbus_init_mmio(sbd, &s->mmio_flash_container); |
| 1180 | |
| 1181 | memory_region_init_io(&s->mmio_flash, OBJECT(s), |
| 1182 | &aspeed_smc_flash_default_ops, s, |
| 1183 | TYPE_ASPEED_SMC ".flash", |
| 1184 | asc->flash_window_size); |
| 1185 | memory_region_add_subregion(&s->mmio_flash_container, 0x0, |
| 1186 | &s->mmio_flash); |
| 1187 | |
| 1188 | /* |
| 1189 | * Let's create a sub memory region for each possible peripheral. All |
| 1190 | * have a configurable memory segment in the overall flash mapping |
| 1191 | * window of the controller but, there is not necessarily a flash |
| 1192 | * module behind to handle the memory accesses. This depends on |
| 1193 | * the board configuration. |
| 1194 | */ |
| 1195 | for (i = 0; i < asc->cs_num_max; ++i) { |
| 1196 | AspeedSMCFlash *fl = &s->flashes[i]; |
| 1197 | |
| 1198 | if (!object_property_set_link(OBJECT(fl), "controller", OBJECT(s), |
| 1199 | errp)) { |
| 1200 | return; |
| 1201 | } |
| 1202 | if (!object_property_set_uint(OBJECT(fl), "cs", i, errp)) { |
| 1203 | return; |
| 1204 | } |
| 1205 | if (!sysbus_realize(SYS_BUS_DEVICE(fl), errp)) { |
| 1206 | return; |
| 1207 | } |
| 1208 | |
| 1209 | memory_region_add_subregion(&s->mmio_flash, offset, &fl->mmio); |
| 1210 | offset += asc->segments[i].size; |
| 1211 | } |
| 1212 | |
| 1213 | /* DMA support */ |
| 1214 | if (aspeed_smc_has_dma(asc)) { |
| 1215 | aspeed_smc_dma_setup(s, errp); |
| 1216 | } |
| 1217 | } |
| 1218 | |
| 1219 | static const VMStateDescription vmstate_aspeed_smc = { |
| 1220 | .name = "aspeed.smc", |
| 1221 | .version_id = 4, |
| 1222 | .minimum_version_id = 2, |
| 1223 | .fields = (const VMStateField[]) { |
| 1224 | VMSTATE_UINT32_ARRAY(regs, AspeedSMCState, ASPEED_SMC_R_MAX), |
| 1225 | VMSTATE_UNUSED_V(2, 2), /* was snoop_index/snoop_dummies */ |
| 1226 | VMSTATE_BOOL_V(unselect, AspeedSMCState, 3), |
| 1227 | VMSTATE_END_OF_LIST() |
| 1228 | } |
| 1229 | }; |
| 1230 | |
| 1231 | static const Property aspeed_smc_properties[] = { |
| 1232 | DEFINE_PROP_BOOL("inject-failure", AspeedSMCState, inject_failure, false), |
| 1233 | DEFINE_PROP_UINT64("dram-base", AspeedSMCState, dram_base, 0), |
| 1234 | DEFINE_PROP_LINK("dram", AspeedSMCState, dram_mr, |
| 1235 | TYPE_MEMORY_REGION, MemoryRegion *), |
| 1236 | }; |
| 1237 | |
| 1238 | static void aspeed_smc_class_init(ObjectClass *klass, const void *data) |
| 1239 | { |
| 1240 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 1241 | ResettableClass *rc = RESETTABLE_CLASS(klass); |
| 1242 | |
| 1243 | dc->realize = aspeed_smc_realize; |
| 1244 | rc->phases.hold = aspeed_smc_reset_hold; |
| 1245 | device_class_set_props(dc, aspeed_smc_properties); |
| 1246 | dc->vmsd = &vmstate_aspeed_smc; |
| 1247 | } |
| 1248 | |
| 1249 | static void aspeed_smc_flash_realize(DeviceState *dev, Error **errp) |
| 1250 | { |
| 1251 | AspeedSMCFlash *s = ASPEED_SMC_FLASH(dev); |
| 1252 | g_autofree char *name = g_strdup_printf(TYPE_ASPEED_SMC_FLASH ".%d", s->cs); |
| 1253 | |
| 1254 | if (!s->controller) { |
| 1255 | error_setg(errp, TYPE_ASPEED_SMC_FLASH ": 'controller' link not set"); |
| 1256 | return; |
| 1257 | } |
| 1258 | |
| 1259 | s->asc = ASPEED_SMC_GET_CLASS(s->controller); |
| 1260 | |
| 1261 | /* |
| 1262 | * Use the default segment value to size the memory region. This |
| 1263 | * can be changed by FW at runtime. |
| 1264 | */ |
| 1265 | memory_region_init_io(&s->mmio, OBJECT(s), s->asc->reg_ops, |
| 1266 | s, name, s->asc->segments[s->cs].size); |
| 1267 | sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio); |
| 1268 | } |
| 1269 | |
| 1270 | static const Property aspeed_smc_flash_properties[] = { |
| 1271 | DEFINE_PROP_UINT8("cs", AspeedSMCFlash, cs, 0), |
| 1272 | DEFINE_PROP_LINK("controller", AspeedSMCFlash, controller, TYPE_ASPEED_SMC, |
| 1273 | AspeedSMCState *), |
| 1274 | }; |
| 1275 | |
| 1276 | static void aspeed_smc_flash_class_init(ObjectClass *klass, const void *data) |
| 1277 | { |
| 1278 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 1279 | |
| 1280 | dc->desc = "Aspeed SMC Flash device region"; |
| 1281 | dc->realize = aspeed_smc_flash_realize; |
| 1282 | device_class_set_props(dc, aspeed_smc_flash_properties); |
| 1283 | } |
| 1284 | |
| 1285 | /* |
| 1286 | * The Segment Registers of the AST2400 and AST2500 have a 8MB |
| 1287 | * unit. The address range of a flash SPI peripheral is encoded with |
| 1288 | * absolute addresses which should be part of the overall controller |
| 1289 | * window. |
| 1290 | */ |
| 1291 | static uint32_t aspeed_smc_segment_to_reg(const AspeedSMCState *s, |
| 1292 | const AspeedSegments *seg) |
| 1293 | { |
| 1294 | uint32_t reg = 0; |
| 1295 | reg |= ((seg->addr >> 23) & SEG_START_MASK) << SEG_START_SHIFT; |
| 1296 | reg |= (((seg->addr + seg->size) >> 23) & SEG_END_MASK) << SEG_END_SHIFT; |
| 1297 | return reg; |
| 1298 | } |
| 1299 | |
| 1300 | static void aspeed_smc_reg_to_segment(const AspeedSMCState *s, |
| 1301 | uint32_t reg, AspeedSegments *seg) |
| 1302 | { |
| 1303 | seg->addr = ((reg >> SEG_START_SHIFT) & SEG_START_MASK) << 23; |
| 1304 | seg->size = (((reg >> SEG_END_SHIFT) & SEG_END_MASK) << 23) - seg->addr; |
| 1305 | } |
| 1306 | |
| 1307 | static const AspeedSegments aspeed_2400_smc_segments[] = { |
| 1308 | { 0x10000000, 32 * MiB }, |
| 1309 | }; |
| 1310 | |
| 1311 | static void aspeed_2400_smc_class_init(ObjectClass *klass, const void *data) |
| 1312 | { |
| 1313 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 1314 | AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); |
| 1315 | |
| 1316 | dc->desc = "Aspeed 2400 SMC Controller"; |
| 1317 | asc->r_conf = R_CONF; |
| 1318 | asc->r_ce_ctrl = R_CE_CTRL; |
| 1319 | asc->r_ctrl0 = R_CTRL0; |
| 1320 | asc->r_timings = R_TIMINGS; |
| 1321 | asc->nregs_timings = 1; |
| 1322 | asc->conf_enable_w0 = CONF_ENABLE_W0; |
| 1323 | asc->cs_num_max = 1; |
| 1324 | asc->segments = aspeed_2400_smc_segments; |
| 1325 | asc->flash_window_base = 0x10000000; |
| 1326 | asc->flash_window_size = 0x6000000; |
| 1327 | asc->features = 0x0; |
| 1328 | asc->nregs = ASPEED_SMC_R_SMC_MAX; |
| 1329 | asc->segment_to_reg = aspeed_smc_segment_to_reg; |
| 1330 | asc->reg_to_segment = aspeed_smc_reg_to_segment; |
| 1331 | asc->dma_ctrl = aspeed_smc_dma_ctrl; |
| 1332 | asc->reg_ops = &aspeed_smc_flash_ops; |
| 1333 | } |
| 1334 | |
| 1335 | static const uint32_t aspeed_2400_fmc_resets[ASPEED_SMC_R_MAX] = { |
| 1336 | /* |
| 1337 | * CE0 and CE1 types are HW strapped in SCU70. Do it here to |
| 1338 | * simplify the model. |
| 1339 | */ |
| 1340 | [R_CONF] = CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0, |
| 1341 | }; |
| 1342 | |
| 1343 | static const AspeedSegments aspeed_2400_fmc_segments[] = { |
| 1344 | { 0x20000000, 64 * MiB }, /* start address is readonly */ |
| 1345 | { 0x24000000, 32 * MiB }, |
| 1346 | { 0x26000000, 32 * MiB }, |
| 1347 | { 0x28000000, 32 * MiB }, |
| 1348 | { 0x2A000000, 32 * MiB } |
| 1349 | }; |
| 1350 | |
| 1351 | static void aspeed_2400_fmc_class_init(ObjectClass *klass, const void *data) |
| 1352 | { |
| 1353 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 1354 | AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); |
| 1355 | |
| 1356 | dc->desc = "Aspeed 2400 FMC Controller"; |
| 1357 | asc->r_conf = R_CONF; |
| 1358 | asc->r_ce_ctrl = R_CE_CTRL; |
| 1359 | asc->r_ctrl0 = R_CTRL0; |
| 1360 | asc->r_timings = R_TIMINGS; |
| 1361 | asc->nregs_timings = 1; |
| 1362 | asc->conf_enable_w0 = CONF_ENABLE_W0; |
| 1363 | asc->cs_num_max = 5; |
| 1364 | asc->segments = aspeed_2400_fmc_segments; |
| 1365 | asc->segment_addr_mask = 0xffff0000; |
| 1366 | asc->resets = aspeed_2400_fmc_resets; |
| 1367 | asc->flash_window_base = 0x20000000; |
| 1368 | asc->flash_window_size = 0x10000000; |
| 1369 | asc->features = ASPEED_SMC_FEATURE_DMA; |
| 1370 | asc->dma_flash_mask = 0x0FFFFFFC; |
| 1371 | asc->dma_dram_mask = 0x1FFFFFFC; |
| 1372 | asc->dma_start_length = 4; |
| 1373 | asc->nregs = ASPEED_SMC_R_MAX; |
| 1374 | asc->segment_to_reg = aspeed_smc_segment_to_reg; |
| 1375 | asc->reg_to_segment = aspeed_smc_reg_to_segment; |
| 1376 | asc->dma_ctrl = aspeed_smc_dma_ctrl; |
| 1377 | asc->reg_ops = &aspeed_smc_flash_ops; |
| 1378 | } |
| 1379 | |
| 1380 | static const AspeedSegments aspeed_2400_spi1_segments[] = { |
| 1381 | { 0x30000000, 64 * MiB }, |
| 1382 | }; |
| 1383 | |
| 1384 | static int aspeed_2400_spi1_addr_width(const AspeedSMCState *s) |
| 1385 | { |
| 1386 | return s->regs[R_SPI_CTRL0] & CTRL_AST2400_SPI_4BYTE ? 4 : 3; |
| 1387 | } |
| 1388 | |
| 1389 | static void aspeed_2400_spi1_class_init(ObjectClass *klass, const void *data) |
| 1390 | { |
| 1391 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 1392 | AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); |
| 1393 | |
| 1394 | dc->desc = "Aspeed 2400 SPI1 Controller"; |
| 1395 | asc->r_conf = R_SPI_CONF; |
| 1396 | asc->r_ce_ctrl = 0xff; |
| 1397 | asc->r_ctrl0 = R_SPI_CTRL0; |
| 1398 | asc->r_timings = R_SPI_TIMINGS; |
| 1399 | asc->nregs_timings = 1; |
| 1400 | asc->conf_enable_w0 = SPI_CONF_ENABLE_W0; |
| 1401 | asc->cs_num_max = 1; |
| 1402 | asc->segments = aspeed_2400_spi1_segments; |
| 1403 | asc->flash_window_base = 0x30000000; |
| 1404 | asc->flash_window_size = 0x10000000; |
| 1405 | asc->features = 0x0; |
| 1406 | asc->nregs = ASPEED_SMC_R_SPI_MAX; |
| 1407 | asc->segment_to_reg = aspeed_smc_segment_to_reg; |
| 1408 | asc->reg_to_segment = aspeed_smc_reg_to_segment; |
| 1409 | asc->dma_ctrl = aspeed_smc_dma_ctrl; |
| 1410 | asc->addr_width = aspeed_2400_spi1_addr_width; |
| 1411 | asc->reg_ops = &aspeed_smc_flash_ops; |
| 1412 | } |
| 1413 | |
| 1414 | static const uint32_t aspeed_2500_fmc_resets[ASPEED_SMC_R_MAX] = { |
| 1415 | [R_CONF] = (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0 | |
| 1416 | CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1), |
| 1417 | }; |
| 1418 | |
| 1419 | static const AspeedSegments aspeed_2500_fmc_segments[] = { |
| 1420 | { 0x20000000, 128 * MiB }, /* start address is readonly */ |
| 1421 | { 0x28000000, 32 * MiB }, |
| 1422 | { 0x2A000000, 32 * MiB }, |
| 1423 | }; |
| 1424 | |
| 1425 | static void aspeed_2500_fmc_class_init(ObjectClass *klass, const void *data) |
| 1426 | { |
| 1427 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 1428 | AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); |
| 1429 | |
| 1430 | dc->desc = "Aspeed 2500 FMC Controller"; |
| 1431 | asc->r_conf = R_CONF; |
| 1432 | asc->r_ce_ctrl = R_CE_CTRL; |
| 1433 | asc->r_ctrl0 = R_CTRL0; |
| 1434 | asc->r_timings = R_TIMINGS; |
| 1435 | asc->nregs_timings = 1; |
| 1436 | asc->conf_enable_w0 = CONF_ENABLE_W0; |
| 1437 | asc->cs_num_max = 3; |
| 1438 | asc->segments = aspeed_2500_fmc_segments; |
| 1439 | asc->segment_addr_mask = 0xffff0000; |
| 1440 | asc->resets = aspeed_2500_fmc_resets; |
| 1441 | asc->flash_window_base = 0x20000000; |
| 1442 | asc->flash_window_size = 0x10000000; |
| 1443 | asc->features = ASPEED_SMC_FEATURE_DMA; |
| 1444 | asc->dma_flash_mask = 0x0FFFFFFC; |
| 1445 | asc->dma_dram_mask = 0x3FFFFFFC; |
| 1446 | asc->dma_start_length = 4; |
| 1447 | asc->nregs = ASPEED_SMC_R_MAX; |
| 1448 | asc->segment_to_reg = aspeed_smc_segment_to_reg; |
| 1449 | asc->reg_to_segment = aspeed_smc_reg_to_segment; |
| 1450 | asc->dma_ctrl = aspeed_smc_dma_ctrl; |
| 1451 | asc->reg_ops = &aspeed_smc_flash_ops; |
| 1452 | } |
| 1453 | |
| 1454 | static const AspeedSegments aspeed_2500_spi1_segments[] = { |
| 1455 | { 0x30000000, 32 * MiB }, /* start address is readonly */ |
| 1456 | { 0x32000000, 96 * MiB }, /* end address is readonly */ |
| 1457 | }; |
| 1458 | |
| 1459 | static void aspeed_2500_spi1_class_init(ObjectClass *klass, const void *data) |
| 1460 | { |
| 1461 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 1462 | AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); |
| 1463 | |
| 1464 | dc->desc = "Aspeed 2500 SPI1 Controller"; |
| 1465 | asc->r_conf = R_CONF; |
| 1466 | asc->r_ce_ctrl = R_CE_CTRL; |
| 1467 | asc->r_ctrl0 = R_CTRL0; |
| 1468 | asc->r_timings = R_TIMINGS; |
| 1469 | asc->nregs_timings = 1; |
| 1470 | asc->conf_enable_w0 = CONF_ENABLE_W0; |
| 1471 | asc->cs_num_max = 2; |
| 1472 | asc->segments = aspeed_2500_spi1_segments; |
| 1473 | asc->segment_addr_mask = 0xffff0000; |
| 1474 | asc->flash_window_base = 0x30000000; |
| 1475 | asc->flash_window_size = 0x8000000; |
| 1476 | asc->features = 0x0; |
| 1477 | asc->nregs = ASPEED_SMC_R_MAX; |
| 1478 | asc->segment_to_reg = aspeed_smc_segment_to_reg; |
| 1479 | asc->reg_to_segment = aspeed_smc_reg_to_segment; |
| 1480 | asc->dma_ctrl = aspeed_smc_dma_ctrl; |
| 1481 | asc->reg_ops = &aspeed_smc_flash_ops; |
| 1482 | } |
| 1483 | |
| 1484 | static const AspeedSegments aspeed_2500_spi2_segments[] = { |
| 1485 | { 0x38000000, 32 * MiB }, /* start address is readonly */ |
| 1486 | { 0x3A000000, 96 * MiB }, /* end address is readonly */ |
| 1487 | }; |
| 1488 | |
| 1489 | static void aspeed_2500_spi2_class_init(ObjectClass *klass, const void *data) |
| 1490 | { |
| 1491 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 1492 | AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); |
| 1493 | |
| 1494 | dc->desc = "Aspeed 2500 SPI2 Controller"; |
| 1495 | asc->r_conf = R_CONF; |
| 1496 | asc->r_ce_ctrl = R_CE_CTRL; |
| 1497 | asc->r_ctrl0 = R_CTRL0; |
| 1498 | asc->r_timings = R_TIMINGS; |
| 1499 | asc->nregs_timings = 1; |
| 1500 | asc->conf_enable_w0 = CONF_ENABLE_W0; |
| 1501 | asc->cs_num_max = 2; |
| 1502 | asc->segments = aspeed_2500_spi2_segments; |
| 1503 | asc->segment_addr_mask = 0xffff0000; |
| 1504 | asc->flash_window_base = 0x38000000; |
| 1505 | asc->flash_window_size = 0x8000000; |
| 1506 | asc->features = 0x0; |
| 1507 | asc->nregs = ASPEED_SMC_R_MAX; |
| 1508 | asc->segment_to_reg = aspeed_smc_segment_to_reg; |
| 1509 | asc->reg_to_segment = aspeed_smc_reg_to_segment; |
| 1510 | asc->dma_ctrl = aspeed_smc_dma_ctrl; |
| 1511 | asc->reg_ops = &aspeed_smc_flash_ops; |
| 1512 | } |
| 1513 | |
| 1514 | /* |
| 1515 | * The Segment Registers of the AST2600 have a 1MB unit. The address |
| 1516 | * range of a flash SPI peripheral is encoded with offsets in the overall |
| 1517 | * controller window. The previous SoC AST2400 and AST2500 used |
| 1518 | * absolute addresses. Only bits [27:20] are relevant and the end |
| 1519 | * address is an upper bound limit. |
| 1520 | */ |
| 1521 | #define AST2600_SEG_ADDR_MASK 0x0ff00000 |
| 1522 | |
| 1523 | static uint32_t aspeed_2600_smc_segment_to_reg(const AspeedSMCState *s, |
| 1524 | const AspeedSegments *seg) |
| 1525 | { |
| 1526 | uint32_t reg = 0; |
| 1527 | |
| 1528 | /* Disabled segments have a nil register */ |
| 1529 | if (!seg->size) { |
| 1530 | return 0; |
| 1531 | } |
| 1532 | |
| 1533 | reg |= (seg->addr & AST2600_SEG_ADDR_MASK) >> 16; /* start offset */ |
| 1534 | reg |= (seg->addr + seg->size - 1) & AST2600_SEG_ADDR_MASK; /* end offset */ |
| 1535 | return reg; |
| 1536 | } |
| 1537 | |
| 1538 | static void aspeed_2600_smc_reg_to_segment(const AspeedSMCState *s, |
| 1539 | uint32_t reg, AspeedSegments *seg) |
| 1540 | { |
| 1541 | uint32_t start_offset = (reg << 16) & AST2600_SEG_ADDR_MASK; |
| 1542 | uint32_t end_offset = reg & AST2600_SEG_ADDR_MASK; |
| 1543 | AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); |
| 1544 | |
| 1545 | if (reg) { |
| 1546 | seg->addr = asc->flash_window_base + start_offset; |
| 1547 | seg->size = end_offset + MiB - start_offset; |
| 1548 | } else { |
| 1549 | seg->addr = asc->flash_window_base; |
| 1550 | seg->size = 0; |
| 1551 | } |
| 1552 | } |
| 1553 | |
| 1554 | static const uint32_t aspeed_2600_fmc_resets[ASPEED_SMC_R_MAX] = { |
| 1555 | [R_CONF] = (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0 | |
| 1556 | CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1 | |
| 1557 | CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE2), |
| 1558 | }; |
| 1559 | |
| 1560 | static const AspeedSegments aspeed_2600_fmc_segments[] = { |
| 1561 | { 0x0, 128 * MiB }, /* start address is readonly */ |
| 1562 | { 128 * MiB, 128 * MiB }, /* default is disabled but needed for -kernel */ |
| 1563 | { 0x0, 0 }, /* disabled */ |
| 1564 | }; |
| 1565 | |
| 1566 | static void aspeed_2600_fmc_class_init(ObjectClass *klass, const void *data) |
| 1567 | { |
| 1568 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 1569 | AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); |
| 1570 | |
| 1571 | dc->desc = "Aspeed 2600 FMC Controller"; |
| 1572 | asc->r_conf = R_CONF; |
| 1573 | asc->r_ce_ctrl = R_CE_CTRL; |
| 1574 | asc->r_ctrl0 = R_CTRL0; |
| 1575 | asc->r_timings = R_TIMINGS; |
| 1576 | asc->nregs_timings = 1; |
| 1577 | asc->conf_enable_w0 = CONF_ENABLE_W0; |
| 1578 | asc->cs_num_max = 3; |
| 1579 | asc->segments = aspeed_2600_fmc_segments; |
| 1580 | asc->segment_addr_mask = 0x0ff00ff0; |
| 1581 | asc->resets = aspeed_2600_fmc_resets; |
| 1582 | asc->flash_window_base = 0x20000000; |
| 1583 | asc->flash_window_size = 0x10000000; |
| 1584 | asc->features = ASPEED_SMC_FEATURE_DMA | |
| 1585 | ASPEED_SMC_FEATURE_WDT_CONTROL; |
| 1586 | asc->dma_flash_mask = 0x0FFFFFFC; |
| 1587 | asc->dma_dram_mask = 0x3FFFFFFC; |
| 1588 | asc->dma_start_length = 1; |
| 1589 | asc->nregs = ASPEED_SMC_R_MAX; |
| 1590 | asc->segment_to_reg = aspeed_2600_smc_segment_to_reg; |
| 1591 | asc->reg_to_segment = aspeed_2600_smc_reg_to_segment; |
| 1592 | asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; |
| 1593 | asc->reg_ops = &aspeed_smc_flash_ops; |
| 1594 | } |
| 1595 | |
| 1596 | static const AspeedSegments aspeed_2600_spi1_segments[] = { |
| 1597 | { 0x0, 128 * MiB }, /* start address is readonly */ |
| 1598 | { 0x0, 0 }, /* disabled */ |
| 1599 | }; |
| 1600 | |
| 1601 | static void aspeed_2600_spi1_class_init(ObjectClass *klass, const void *data) |
| 1602 | { |
| 1603 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 1604 | AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); |
| 1605 | |
| 1606 | dc->desc = "Aspeed 2600 SPI1 Controller"; |
| 1607 | asc->r_conf = R_CONF; |
| 1608 | asc->r_ce_ctrl = R_CE_CTRL; |
| 1609 | asc->r_ctrl0 = R_CTRL0; |
| 1610 | asc->r_timings = R_TIMINGS; |
| 1611 | asc->nregs_timings = 2; |
| 1612 | asc->conf_enable_w0 = CONF_ENABLE_W0; |
| 1613 | asc->cs_num_max = 2; |
| 1614 | asc->segments = aspeed_2600_spi1_segments; |
| 1615 | asc->segment_addr_mask = 0x0ff00ff0; |
| 1616 | asc->flash_window_base = 0x30000000; |
| 1617 | asc->flash_window_size = 0x10000000; |
| 1618 | asc->features = ASPEED_SMC_FEATURE_DMA | |
| 1619 | ASPEED_SMC_FEATURE_DMA_GRANT; |
| 1620 | asc->dma_flash_mask = 0x0FFFFFFC; |
| 1621 | asc->dma_dram_mask = 0x3FFFFFFC; |
| 1622 | asc->dma_start_length = 1; |
| 1623 | asc->nregs = ASPEED_SMC_R_MAX; |
| 1624 | asc->segment_to_reg = aspeed_2600_smc_segment_to_reg; |
| 1625 | asc->reg_to_segment = aspeed_2600_smc_reg_to_segment; |
| 1626 | asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; |
| 1627 | asc->reg_ops = &aspeed_smc_flash_ops; |
| 1628 | } |
| 1629 | |
| 1630 | static const AspeedSegments aspeed_2600_spi2_segments[] = { |
| 1631 | { 0x0, 128 * MiB }, /* start address is readonly */ |
| 1632 | { 0x0, 0 }, /* disabled */ |
| 1633 | { 0x0, 0 }, /* disabled */ |
| 1634 | }; |
| 1635 | |
| 1636 | static void aspeed_2600_spi2_class_init(ObjectClass *klass, const void *data) |
| 1637 | { |
| 1638 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 1639 | AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); |
| 1640 | |
| 1641 | dc->desc = "Aspeed 2600 SPI2 Controller"; |
| 1642 | asc->r_conf = R_CONF; |
| 1643 | asc->r_ce_ctrl = R_CE_CTRL; |
| 1644 | asc->r_ctrl0 = R_CTRL0; |
| 1645 | asc->r_timings = R_TIMINGS; |
| 1646 | asc->nregs_timings = 3; |
| 1647 | asc->conf_enable_w0 = CONF_ENABLE_W0; |
| 1648 | asc->cs_num_max = 3; |
| 1649 | asc->segments = aspeed_2600_spi2_segments; |
| 1650 | asc->segment_addr_mask = 0x0ff00ff0; |
| 1651 | asc->flash_window_base = 0x50000000; |
| 1652 | asc->flash_window_size = 0x10000000; |
| 1653 | asc->features = ASPEED_SMC_FEATURE_DMA | |
| 1654 | ASPEED_SMC_FEATURE_DMA_GRANT; |
| 1655 | asc->dma_flash_mask = 0x0FFFFFFC; |
| 1656 | asc->dma_dram_mask = 0x3FFFFFFC; |
| 1657 | asc->dma_start_length = 1; |
| 1658 | asc->nregs = ASPEED_SMC_R_MAX; |
| 1659 | asc->segment_to_reg = aspeed_2600_smc_segment_to_reg; |
| 1660 | asc->reg_to_segment = aspeed_2600_smc_reg_to_segment; |
| 1661 | asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; |
| 1662 | asc->reg_ops = &aspeed_smc_flash_ops; |
| 1663 | } |
| 1664 | |
| 1665 | /* |
| 1666 | * The FMC Segment Registers of the AST1030 have a 512KB unit. |
| 1667 | * Only bits [27:19] are used for decoding. |
| 1668 | */ |
| 1669 | #define AST1030_SEG_ADDR_MASK 0x0ff80000 |
| 1670 | |
| 1671 | static uint32_t aspeed_1030_smc_segment_to_reg(const AspeedSMCState *s, |
| 1672 | const AspeedSegments *seg) |
| 1673 | { |
| 1674 | uint32_t reg = 0; |
| 1675 | |
| 1676 | /* Disabled segments have a nil register */ |
| 1677 | if (!seg->size) { |
| 1678 | return 0; |
| 1679 | } |
| 1680 | |
| 1681 | reg |= (seg->addr & AST1030_SEG_ADDR_MASK) >> 16; /* start offset */ |
| 1682 | reg |= (seg->addr + seg->size - 1) & AST1030_SEG_ADDR_MASK; /* end offset */ |
| 1683 | return reg; |
| 1684 | } |
| 1685 | |
| 1686 | static void aspeed_1030_smc_reg_to_segment(const AspeedSMCState *s, |
| 1687 | uint32_t reg, AspeedSegments *seg) |
| 1688 | { |
| 1689 | uint32_t start_offset = (reg << 16) & AST1030_SEG_ADDR_MASK; |
| 1690 | uint32_t end_offset = reg & AST1030_SEG_ADDR_MASK; |
| 1691 | AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); |
| 1692 | |
| 1693 | if (reg) { |
| 1694 | seg->addr = asc->flash_window_base + start_offset; |
| 1695 | seg->size = end_offset + (512 * KiB) - start_offset; |
| 1696 | } else { |
| 1697 | seg->addr = asc->flash_window_base; |
| 1698 | seg->size = 0; |
| 1699 | } |
| 1700 | } |
| 1701 | |
| 1702 | static const uint32_t aspeed_1030_fmc_resets[ASPEED_SMC_R_MAX] = { |
| 1703 | [R_CONF] = (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0 | |
| 1704 | CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1), |
| 1705 | }; |
| 1706 | |
| 1707 | static const AspeedSegments aspeed_1030_fmc_segments[] = { |
| 1708 | { 0x0, 128 * MiB }, /* start address is readonly */ |
| 1709 | { 128 * MiB, 128 * MiB }, /* default is disabled but needed for -kernel */ |
| 1710 | { 0x0, 0 }, /* disabled */ |
| 1711 | }; |
| 1712 | |
| 1713 | static void aspeed_1030_fmc_class_init(ObjectClass *klass, const void *data) |
| 1714 | { |
| 1715 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 1716 | AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); |
| 1717 | |
| 1718 | dc->desc = "Aspeed 1030 FMC Controller"; |
| 1719 | asc->r_conf = R_CONF; |
| 1720 | asc->r_ce_ctrl = R_CE_CTRL; |
| 1721 | asc->r_ctrl0 = R_CTRL0; |
| 1722 | asc->r_timings = R_TIMINGS; |
| 1723 | asc->nregs_timings = 2; |
| 1724 | asc->conf_enable_w0 = CONF_ENABLE_W0; |
| 1725 | asc->cs_num_max = 2; |
| 1726 | asc->segments = aspeed_1030_fmc_segments; |
| 1727 | asc->segment_addr_mask = 0x0ff80ff8; |
| 1728 | asc->resets = aspeed_1030_fmc_resets; |
| 1729 | asc->flash_window_base = 0x80000000; |
| 1730 | asc->flash_window_size = 0x10000000; |
| 1731 | asc->features = ASPEED_SMC_FEATURE_DMA | |
| 1732 | ASPEED_SMC_FEATURE_WDT_CONTROL; |
| 1733 | asc->dma_flash_mask = 0x0FFFFFFC; |
| 1734 | asc->dma_dram_mask = 0x000BFFFC; |
| 1735 | asc->dma_start_length = 1; |
| 1736 | asc->nregs = ASPEED_SMC_R_MAX; |
| 1737 | asc->segment_to_reg = aspeed_1030_smc_segment_to_reg; |
| 1738 | asc->reg_to_segment = aspeed_1030_smc_reg_to_segment; |
| 1739 | asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; |
| 1740 | asc->reg_ops = &aspeed_smc_flash_ops; |
| 1741 | } |
| 1742 | |
| 1743 | static const AspeedSegments aspeed_1030_spi1_segments[] = { |
| 1744 | { 0x0, 128 * MiB }, /* start address is readonly */ |
| 1745 | { 0x0, 0 }, /* disabled */ |
| 1746 | }; |
| 1747 | |
| 1748 | static void aspeed_1030_spi1_class_init(ObjectClass *klass, const void *data) |
| 1749 | { |
| 1750 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 1751 | AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); |
| 1752 | |
| 1753 | dc->desc = "Aspeed 1030 SPI1 Controller"; |
| 1754 | asc->r_conf = R_CONF; |
| 1755 | asc->r_ce_ctrl = R_CE_CTRL; |
| 1756 | asc->r_ctrl0 = R_CTRL0; |
| 1757 | asc->r_timings = R_TIMINGS; |
| 1758 | asc->nregs_timings = 2; |
| 1759 | asc->conf_enable_w0 = CONF_ENABLE_W0; |
| 1760 | asc->cs_num_max = 2; |
| 1761 | asc->segments = aspeed_1030_spi1_segments; |
| 1762 | asc->segment_addr_mask = 0x0ff00ff0; |
| 1763 | asc->flash_window_base = 0x90000000; |
| 1764 | asc->flash_window_size = 0x10000000; |
| 1765 | asc->features = ASPEED_SMC_FEATURE_DMA; |
| 1766 | asc->dma_flash_mask = 0x0FFFFFFC; |
| 1767 | asc->dma_dram_mask = 0x000BFFFC; |
| 1768 | asc->dma_start_length = 1; |
| 1769 | asc->nregs = ASPEED_SMC_R_MAX; |
| 1770 | asc->segment_to_reg = aspeed_2600_smc_segment_to_reg; |
| 1771 | asc->reg_to_segment = aspeed_2600_smc_reg_to_segment; |
| 1772 | asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; |
| 1773 | asc->reg_ops = &aspeed_smc_flash_ops; |
| 1774 | } |
| 1775 | |
| 1776 | static const AspeedSegments aspeed_1030_spi2_segments[] = { |
| 1777 | { 0x0, 128 * MiB }, /* start address is readonly */ |
| 1778 | { 0x0, 0 }, /* disabled */ |
| 1779 | }; |
| 1780 | |
| 1781 | static void aspeed_1030_spi2_class_init(ObjectClass *klass, const void *data) |
| 1782 | { |
| 1783 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 1784 | AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); |
| 1785 | |
| 1786 | dc->desc = "Aspeed 1030 SPI2 Controller"; |
| 1787 | asc->r_conf = R_CONF; |
| 1788 | asc->r_ce_ctrl = R_CE_CTRL; |
| 1789 | asc->r_ctrl0 = R_CTRL0; |
| 1790 | asc->r_timings = R_TIMINGS; |
| 1791 | asc->nregs_timings = 2; |
| 1792 | asc->conf_enable_w0 = CONF_ENABLE_W0; |
| 1793 | asc->cs_num_max = 2; |
| 1794 | asc->segments = aspeed_1030_spi2_segments; |
| 1795 | asc->segment_addr_mask = 0x0ff00ff0; |
| 1796 | asc->flash_window_base = 0xb0000000; |
| 1797 | asc->flash_window_size = 0x10000000; |
| 1798 | asc->features = ASPEED_SMC_FEATURE_DMA; |
| 1799 | asc->dma_flash_mask = 0x0FFFFFFC; |
| 1800 | asc->dma_dram_mask = 0x000BFFFC; |
| 1801 | asc->dma_start_length = 1; |
| 1802 | asc->nregs = ASPEED_SMC_R_MAX; |
| 1803 | asc->segment_to_reg = aspeed_2600_smc_segment_to_reg; |
| 1804 | asc->reg_to_segment = aspeed_2600_smc_reg_to_segment; |
| 1805 | asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; |
| 1806 | asc->reg_ops = &aspeed_smc_flash_ops; |
| 1807 | } |
| 1808 | |
| 1809 | /* |
| 1810 | * The FMC Segment Registers of the AST2700 have a 64KB unit. |
| 1811 | * Only bits [31:16] are used for decoding. |
| 1812 | */ |
| 1813 | #define AST2700_SEG_ADDR_MASK 0xffff0000 |
| 1814 | |
| 1815 | static uint32_t aspeed_2700_smc_segment_to_reg(const AspeedSMCState *s, |
| 1816 | const AspeedSegments *seg) |
| 1817 | { |
| 1818 | uint32_t reg = 0; |
| 1819 | |
| 1820 | /* Disabled segments have a nil register */ |
| 1821 | if (!seg->size) { |
| 1822 | return 0; |
| 1823 | } |
| 1824 | |
| 1825 | reg |= (seg->addr & AST2700_SEG_ADDR_MASK) >> 16; /* start offset */ |
| 1826 | reg |= (seg->addr + seg->size - 1) & AST2700_SEG_ADDR_MASK; /* end offset */ |
| 1827 | return reg; |
| 1828 | } |
| 1829 | |
| 1830 | static void aspeed_2700_smc_reg_to_segment(const AspeedSMCState *s, |
| 1831 | uint32_t reg, AspeedSegments *seg) |
| 1832 | { |
| 1833 | uint32_t start_offset = (reg << 16) & AST2700_SEG_ADDR_MASK; |
| 1834 | uint32_t end_offset = reg & AST2700_SEG_ADDR_MASK; |
| 1835 | AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); |
| 1836 | |
| 1837 | if (reg) { |
| 1838 | seg->addr = asc->flash_window_base + start_offset; |
| 1839 | seg->size = end_offset + (64 * KiB) - start_offset; |
| 1840 | } else { |
| 1841 | seg->addr = asc->flash_window_base; |
| 1842 | seg->size = 0; |
| 1843 | } |
| 1844 | } |
| 1845 | |
| 1846 | /* |
| 1847 | * Convert a data fifo offset to a chip select (CS). |
| 1848 | * |
| 1849 | * Data fifo access starts at 0x200. The data fifo offset index is |
| 1850 | * calculated by subtracting the data fifo base offset from the MMIO address. |
| 1851 | * |
| 1852 | * The data fifo offset index increments by 1 for every 16MB of flash address |
| 1853 | * space. Each offset step therefore represents a 16MB address decode range. |
| 1854 | * |
| 1855 | * The CS is determined by matching the data fifo offset index against the |
| 1856 | * segment start address of each CS. |
| 1857 | * |
| 1858 | * Returns the CS index on success, or -1 if the offset is invalid. |
| 1859 | */ |
| 1860 | static int aspeed_2700_smc_data_fifo_offset_to_cs(const AspeedSMCState *s, |
| 1861 | uint32_t offset) |
| 1862 | { |
| 1863 | AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); |
| 1864 | uint32_t start_offset; |
| 1865 | uint32_t fifo_offset; |
| 1866 | int i; |
| 1867 | |
| 1868 | for (i = 0; i < asc->cs_num_max; i++) { |
| 1869 | start_offset = (s->regs[R_SEG_ADDR0 + i] & 0x0000ffff) << 16; |
| 1870 | fifo_offset = start_offset / 0x1000000; |
| 1871 | if (fifo_offset == offset - (R_DATA_FIFO << 2)) { |
| 1872 | return i; |
| 1873 | } |
| 1874 | } |
| 1875 | |
| 1876 | return -1; |
| 1877 | } |
| 1878 | |
| 1879 | static const uint32_t aspeed_2700_fmc_resets[ASPEED_SMC_R_MAX] = { |
| 1880 | [R_CONF] = (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0 | |
| 1881 | CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1), |
| 1882 | [R_CE_CTRL] = 0x0000aa00, |
| 1883 | [R_CTRL0] = 0x406b0641, |
| 1884 | [R_CTRL1] = 0x00000400, |
| 1885 | [R_CTRL2] = 0x00000400, |
| 1886 | [R_CTRL3] = 0x00000400, |
| 1887 | [R_SEG_ADDR0] = 0x08000000, |
| 1888 | [R_SEG_ADDR1] = 0x10000800, |
| 1889 | [R_SEG_ADDR2] = 0x00000000, |
| 1890 | [R_SEG_ADDR3] = 0x00000000, |
| 1891 | [R_DUMMY_DATA] = 0x00010000, |
| 1892 | [R_DMA_DRAM_ADDR_HIGH] = 0x00000000, |
| 1893 | [R_TIMINGS] = 0x007b0000, |
| 1894 | }; |
| 1895 | |
| 1896 | static const MemoryRegionOps aspeed_2700_smc_flash_ops = { |
| 1897 | .read_with_attrs = aspeed_smc_flash_read, |
| 1898 | .write_with_attrs = aspeed_smc_flash_write, |
| 1899 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 1900 | .valid = { |
| 1901 | .min_access_size = 1, |
| 1902 | .max_access_size = 8, |
| 1903 | }, |
| 1904 | }; |
| 1905 | |
| 1906 | static const AspeedSegments aspeed_2700_fmc_segments[] = { |
| 1907 | { 0x0, 128 * MiB }, /* start address is readonly */ |
| 1908 | { 128 * MiB, 128 * MiB }, /* default is disabled but needed for -kernel */ |
| 1909 | { 256 * MiB, 128 * MiB }, /* default is disabled but needed for -kernel */ |
| 1910 | { 0x0, 0 }, /* disabled */ |
| 1911 | }; |
| 1912 | |
| 1913 | /* |
| 1914 | * AST2700 supports data fifo mode with a base data fifo start offset of 0x200. |
| 1915 | * |
| 1916 | * The data fifo start offset increments by 1 for every 16MB of flash address |
| 1917 | * space. Each offset step therefore represents a 16MB address decode range. |
| 1918 | * |
| 1919 | * Assuming each chip select (CS) can use the maximum flash size of 256MB: |
| 1920 | * 256MB / 16MB = 0x10 offset steps per CS. |
| 1921 | * |
| 1922 | * Data fifo start offset for CSn: |
| 1923 | * 0x200 + (n * 0x10) |
| 1924 | * |
| 1925 | * Examples: |
| 1926 | * CS0: 0x200 |
| 1927 | * CS1: 0x210 |
| 1928 | * CS2: 0x220 |
| 1929 | * CS3: 0x230 |
| 1930 | * |
| 1931 | * asc->nregs should be set to: 0x200 + (asc->cs_num_max * 0x10) |
| 1932 | * to cover all possible data fifo regions. |
| 1933 | */ |
| 1934 | static void aspeed_2700_fmc_class_init(ObjectClass *klass, const void *data) |
| 1935 | { |
| 1936 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 1937 | AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); |
| 1938 | |
| 1939 | dc->desc = "Aspeed 2700 FMC Controller"; |
| 1940 | asc->r_conf = R_CONF; |
| 1941 | asc->r_ce_ctrl = R_CE_CTRL; |
| 1942 | asc->r_ctrl0 = R_CTRL0; |
| 1943 | asc->r_timings = R_TIMINGS; |
| 1944 | asc->nregs_timings = 3; |
| 1945 | asc->conf_enable_w0 = CONF_ENABLE_W0; |
| 1946 | asc->cs_num_max = 3; |
| 1947 | asc->segments = aspeed_2700_fmc_segments; |
| 1948 | asc->segment_addr_mask = 0xffffffff; |
| 1949 | asc->resets = aspeed_2700_fmc_resets; |
| 1950 | asc->flash_window_base = 0x100000000; |
| 1951 | asc->flash_window_size = 1 * GiB; |
| 1952 | asc->features = ASPEED_SMC_FEATURE_DMA | |
| 1953 | ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH | |
| 1954 | ASPEED_SMC_FEATURE_DATA_FIFO; |
| 1955 | asc->dma_flash_mask = 0x2FFFFFFC; |
| 1956 | asc->dma_dram_mask = 0xFFFFFFFC; |
| 1957 | asc->dma_start_length = 1; |
| 1958 | asc->nregs = (0x200 + (asc->cs_num_max * 0x10)) >> 2; |
| 1959 | asc->segment_to_reg = aspeed_2700_smc_segment_to_reg; |
| 1960 | asc->reg_to_segment = aspeed_2700_smc_reg_to_segment; |
| 1961 | asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; |
| 1962 | asc->data_fifo_offset_to_cs = aspeed_2700_smc_data_fifo_offset_to_cs; |
| 1963 | asc->reg_ops = &aspeed_2700_smc_flash_ops; |
| 1964 | } |
| 1965 | |
| 1966 | static const AspeedSegments aspeed_2700_spi0_segments[] = { |
| 1967 | { 0x0, 128 * MiB }, /* start address is readonly */ |
| 1968 | { 128 * MiB, 128 * MiB }, /* start address is readonly */ |
| 1969 | { 0x0, 0 }, /* disabled */ |
| 1970 | }; |
| 1971 | |
| 1972 | static void aspeed_2700_spi0_class_init(ObjectClass *klass, const void *data) |
| 1973 | { |
| 1974 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 1975 | AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); |
| 1976 | |
| 1977 | dc->desc = "Aspeed 2700 SPI0 Controller"; |
| 1978 | asc->r_conf = R_CONF; |
| 1979 | asc->r_ce_ctrl = R_CE_CTRL; |
| 1980 | asc->r_ctrl0 = R_CTRL0; |
| 1981 | asc->r_timings = R_TIMINGS; |
| 1982 | asc->nregs_timings = 2; |
| 1983 | asc->conf_enable_w0 = CONF_ENABLE_W0; |
| 1984 | asc->cs_num_max = 2; |
| 1985 | asc->segments = aspeed_2700_spi0_segments; |
| 1986 | asc->segment_addr_mask = 0xffffffff; |
| 1987 | asc->flash_window_base = 0x180000000; |
| 1988 | asc->flash_window_size = 1 * GiB; |
| 1989 | asc->features = ASPEED_SMC_FEATURE_DMA | |
| 1990 | ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH | |
| 1991 | ASPEED_SMC_FEATURE_DATA_FIFO; |
| 1992 | asc->dma_flash_mask = 0x2FFFFFFC; |
| 1993 | asc->dma_dram_mask = 0xFFFFFFFC; |
| 1994 | asc->dma_start_length = 1; |
| 1995 | asc->nregs = (0x200 + (asc->cs_num_max * 0x10)) >> 2; |
| 1996 | asc->segment_to_reg = aspeed_2700_smc_segment_to_reg; |
| 1997 | asc->reg_to_segment = aspeed_2700_smc_reg_to_segment; |
| 1998 | asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; |
| 1999 | asc->data_fifo_offset_to_cs = aspeed_2700_smc_data_fifo_offset_to_cs; |
| 2000 | asc->reg_ops = &aspeed_2700_smc_flash_ops; |
| 2001 | } |
| 2002 | |
| 2003 | static const AspeedSegments aspeed_2700_spi1_segments[] = { |
| 2004 | { 0x0, 128 * MiB }, /* start address is readonly */ |
| 2005 | { 0x0, 0 }, /* disabled */ |
| 2006 | }; |
| 2007 | |
| 2008 | static void aspeed_2700_spi1_class_init(ObjectClass *klass, const void *data) |
| 2009 | { |
| 2010 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 2011 | AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); |
| 2012 | |
| 2013 | dc->desc = "Aspeed 2700 SPI1 Controller"; |
| 2014 | asc->r_conf = R_CONF; |
| 2015 | asc->r_ce_ctrl = R_CE_CTRL; |
| 2016 | asc->r_ctrl0 = R_CTRL0; |
| 2017 | asc->r_timings = R_TIMINGS; |
| 2018 | asc->nregs_timings = 2; |
| 2019 | asc->conf_enable_w0 = CONF_ENABLE_W0; |
| 2020 | asc->cs_num_max = 2; |
| 2021 | asc->segments = aspeed_2700_spi1_segments; |
| 2022 | asc->segment_addr_mask = 0xffffffff; |
| 2023 | asc->flash_window_base = 0x200000000; |
| 2024 | asc->flash_window_size = 1 * GiB; |
| 2025 | asc->features = ASPEED_SMC_FEATURE_DMA | |
| 2026 | ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH | |
| 2027 | ASPEED_SMC_FEATURE_DATA_FIFO; |
| 2028 | asc->dma_flash_mask = 0x2FFFFFFC; |
| 2029 | asc->dma_dram_mask = 0xFFFFFFFC; |
| 2030 | asc->dma_start_length = 1; |
| 2031 | asc->nregs = (0x200 + (asc->cs_num_max * 0x10)) >> 2; |
| 2032 | asc->segment_to_reg = aspeed_2700_smc_segment_to_reg; |
| 2033 | asc->reg_to_segment = aspeed_2700_smc_reg_to_segment; |
| 2034 | asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; |
| 2035 | asc->data_fifo_offset_to_cs = aspeed_2700_smc_data_fifo_offset_to_cs; |
| 2036 | asc->reg_ops = &aspeed_2700_smc_flash_ops; |
| 2037 | } |
| 2038 | |
| 2039 | static const AspeedSegments aspeed_2700_spi2_segments[] = { |
| 2040 | { 0x0, 128 * MiB }, /* start address is readonly */ |
| 2041 | { 0x0, 0 }, /* disabled */ |
| 2042 | }; |
| 2043 | |
| 2044 | static void aspeed_2700_spi2_class_init(ObjectClass *klass, const void *data) |
| 2045 | { |
| 2046 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 2047 | AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); |
| 2048 | |
| 2049 | dc->desc = "Aspeed 2700 SPI2 Controller"; |
| 2050 | asc->r_conf = R_CONF; |
| 2051 | asc->r_ce_ctrl = R_CE_CTRL; |
| 2052 | asc->r_ctrl0 = R_CTRL0; |
| 2053 | asc->r_timings = R_TIMINGS; |
| 2054 | asc->nregs_timings = 2; |
| 2055 | asc->conf_enable_w0 = CONF_ENABLE_W0; |
| 2056 | asc->cs_num_max = 2; |
| 2057 | asc->segments = aspeed_2700_spi2_segments; |
| 2058 | asc->segment_addr_mask = 0xffffffff; |
| 2059 | asc->flash_window_base = 0x280000000; |
| 2060 | asc->flash_window_size = 1 * GiB; |
| 2061 | asc->features = ASPEED_SMC_FEATURE_DMA | |
| 2062 | ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH | |
| 2063 | ASPEED_SMC_FEATURE_DATA_FIFO; |
| 2064 | asc->dma_flash_mask = 0x0FFFFFFC; |
| 2065 | asc->dma_dram_mask = 0xFFFFFFFC; |
| 2066 | asc->dma_start_length = 1; |
| 2067 | asc->nregs = (0x200 + (asc->cs_num_max * 0x10)) >> 2; |
| 2068 | asc->segment_to_reg = aspeed_2700_smc_segment_to_reg; |
| 2069 | asc->reg_to_segment = aspeed_2700_smc_reg_to_segment; |
| 2070 | asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; |
| 2071 | asc->data_fifo_offset_to_cs = aspeed_2700_smc_data_fifo_offset_to_cs; |
| 2072 | asc->reg_ops = &aspeed_2700_smc_flash_ops; |
| 2073 | } |
| 2074 | |
| 2075 | static const TypeInfo aspeed_smc_types[] = { |
| 2076 | { |
| 2077 | .name = TYPE_ASPEED_SMC_FLASH, |
| 2078 | .parent = TYPE_SYS_BUS_DEVICE, |
| 2079 | .instance_size = sizeof(AspeedSMCFlash), |
| 2080 | .class_init = aspeed_smc_flash_class_init, |
| 2081 | }, |
| 2082 | { |
| 2083 | .name = TYPE_ASPEED_SMC, |
| 2084 | .parent = TYPE_SYS_BUS_DEVICE, |
| 2085 | .instance_init = aspeed_smc_instance_init, |
| 2086 | .instance_size = sizeof(AspeedSMCState), |
| 2087 | .class_size = sizeof(AspeedSMCClass), |
| 2088 | .class_init = aspeed_smc_class_init, |
| 2089 | .abstract = true, |
| 2090 | }, |
| 2091 | { |
| 2092 | .name = "aspeed.fmc-ast1030", |
| 2093 | .parent = TYPE_ASPEED_SMC, |
| 2094 | .class_init = aspeed_1030_fmc_class_init, |
| 2095 | }, |
| 2096 | { |
| 2097 | .name = "aspeed.spi1-ast1030", |
| 2098 | .parent = TYPE_ASPEED_SMC, |
| 2099 | .class_init = aspeed_1030_spi1_class_init, |
| 2100 | }, |
| 2101 | { |
| 2102 | .name = "aspeed.spi2-ast1030", |
| 2103 | .parent = TYPE_ASPEED_SMC, |
| 2104 | .class_init = aspeed_1030_spi2_class_init, |
| 2105 | }, |
| 2106 | { |
| 2107 | .name = "aspeed.smc-ast2400", |
| 2108 | .parent = TYPE_ASPEED_SMC, |
| 2109 | .class_init = aspeed_2400_smc_class_init, |
| 2110 | }, |
| 2111 | { |
| 2112 | .name = "aspeed.fmc-ast2400", |
| 2113 | .parent = TYPE_ASPEED_SMC, |
| 2114 | .class_init = aspeed_2400_fmc_class_init, |
| 2115 | }, |
| 2116 | { |
| 2117 | .name = "aspeed.spi1-ast2400", |
| 2118 | .parent = TYPE_ASPEED_SMC, |
| 2119 | .class_init = aspeed_2400_spi1_class_init, |
| 2120 | }, |
| 2121 | { |
| 2122 | .name = "aspeed.fmc-ast2500", |
| 2123 | .parent = TYPE_ASPEED_SMC, |
| 2124 | .class_init = aspeed_2500_fmc_class_init, |
| 2125 | }, |
| 2126 | { |
| 2127 | .name = "aspeed.spi1-ast2500", |
| 2128 | .parent = TYPE_ASPEED_SMC, |
| 2129 | .class_init = aspeed_2500_spi1_class_init, |
| 2130 | }, |
| 2131 | { |
| 2132 | .name = "aspeed.spi2-ast2500", |
| 2133 | .parent = TYPE_ASPEED_SMC, |
| 2134 | .class_init = aspeed_2500_spi2_class_init, |
| 2135 | }, |
| 2136 | { |
| 2137 | .name = "aspeed.fmc-ast2600", |
| 2138 | .parent = TYPE_ASPEED_SMC, |
| 2139 | .class_init = aspeed_2600_fmc_class_init, |
| 2140 | }, |
| 2141 | { |
| 2142 | .name = "aspeed.spi1-ast2600", |
| 2143 | .parent = TYPE_ASPEED_SMC, |
| 2144 | .class_init = aspeed_2600_spi1_class_init, |
| 2145 | }, |
| 2146 | { |
| 2147 | .name = "aspeed.spi2-ast2600", |
| 2148 | .parent = TYPE_ASPEED_SMC, |
| 2149 | .class_init = aspeed_2600_spi2_class_init, |
| 2150 | }, |
| 2151 | { |
| 2152 | .name = "aspeed.fmc-ast2700", |
| 2153 | .parent = TYPE_ASPEED_SMC, |
| 2154 | .class_init = aspeed_2700_fmc_class_init, |
| 2155 | }, |
| 2156 | { |
| 2157 | .name = "aspeed.spi0-ast2700", |
| 2158 | .parent = TYPE_ASPEED_SMC, |
| 2159 | .class_init = aspeed_2700_spi0_class_init, |
| 2160 | }, |
| 2161 | { |
| 2162 | .name = "aspeed.spi1-ast2700", |
| 2163 | .parent = TYPE_ASPEED_SMC, |
| 2164 | .class_init = aspeed_2700_spi1_class_init, |
| 2165 | }, |
| 2166 | { |
| 2167 | .name = "aspeed.spi2-ast2700", |
| 2168 | .parent = TYPE_ASPEED_SMC, |
| 2169 | .class_init = aspeed_2700_spi2_class_init, |
| 2170 | } |
| 2171 | }; |
| 2172 | |
| 2173 | DEFINE_TYPES(aspeed_smc_types) |