| 1 | /* |
| 2 | * Nuvoton NPCM7xx Flash Interface Unit (FIU) |
| 3 | * |
| 4 | * Copyright 2020 Google LLC |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License as published by the |
| 8 | * Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 14 | * for more details. |
| 15 | */ |
| 16 | |
| 17 | #include "qemu/osdep.h" |
| 18 | |
| 19 | #include "hw/core/irq.h" |
| 20 | #include "hw/core/qdev-properties.h" |
| 21 | #include "hw/ssi/npcm7xx_fiu.h" |
| 22 | #include "migration/vmstate.h" |
| 23 | #include "qapi/error.h" |
| 24 | #include "qemu/error-report.h" |
| 25 | #include "qemu/log.h" |
| 26 | #include "qemu/module.h" |
| 27 | #include "qemu/units.h" |
| 28 | |
| 29 | #include "trace.h" |
| 30 | |
| 31 | /* Up to 128 MiB of flash may be accessed directly as memory. */ |
| 32 | #define NPCM7XX_FIU_MAX_FLASH_WINDOW_SIZE (128 * MiB) |
| 33 | |
| 34 | /* Each module has 4 KiB of register space. Only a fraction of it is used. */ |
| 35 | #define NPCM7XX_FIU_CTRL_REGS_SIZE (4 * KiB) |
| 36 | |
| 37 | /* 32-bit FIU register indices. */ |
| 38 | enum NPCM7xxFIURegister { |
| 39 | NPCM7XX_FIU_DRD_CFG, |
| 40 | NPCM7XX_FIU_DWR_CFG, |
| 41 | NPCM7XX_FIU_UMA_CFG, |
| 42 | NPCM7XX_FIU_UMA_CTS, |
| 43 | NPCM7XX_FIU_UMA_CMD, |
| 44 | NPCM7XX_FIU_UMA_ADDR, |
| 45 | NPCM7XX_FIU_PRT_CFG, |
| 46 | NPCM7XX_FIU_UMA_DW0 = 0x0020 / sizeof(uint32_t), |
| 47 | NPCM7XX_FIU_UMA_DW1, |
| 48 | NPCM7XX_FIU_UMA_DW2, |
| 49 | NPCM7XX_FIU_UMA_DW3, |
| 50 | NPCM7XX_FIU_UMA_DR0, |
| 51 | NPCM7XX_FIU_UMA_DR1, |
| 52 | NPCM7XX_FIU_UMA_DR2, |
| 53 | NPCM7XX_FIU_UMA_DR3, |
| 54 | NPCM7XX_FIU_PRT_CMD0, |
| 55 | NPCM7XX_FIU_PRT_CMD1, |
| 56 | NPCM7XX_FIU_PRT_CMD2, |
| 57 | NPCM7XX_FIU_PRT_CMD3, |
| 58 | NPCM7XX_FIU_PRT_CMD4, |
| 59 | NPCM7XX_FIU_PRT_CMD5, |
| 60 | NPCM7XX_FIU_PRT_CMD6, |
| 61 | NPCM7XX_FIU_PRT_CMD7, |
| 62 | NPCM7XX_FIU_PRT_CMD8, |
| 63 | NPCM7XX_FIU_PRT_CMD9, |
| 64 | NPCM7XX_FIU_CFG = 0x78 / sizeof(uint32_t), |
| 65 | NPCM7XX_FIU_REGS_END, |
| 66 | }; |
| 67 | |
| 68 | /* FIU_{DRD,DWR,UMA,PTR}_CFG cannot be written when this bit is set. */ |
| 69 | #define NPCM7XX_FIU_CFG_LCK BIT(31) |
| 70 | |
| 71 | /* Direct Read configuration register fields. */ |
| 72 | #define FIU_DRD_CFG_ADDSIZ(rv) extract32(rv, 16, 2) |
| 73 | #define FIU_ADDSIZ_3BYTES 0 |
| 74 | #define FIU_ADDSIZ_4BYTES 1 |
| 75 | #define FIU_DRD_CFG_DBW(rv) extract32(rv, 12, 2) |
| 76 | #define FIU_DRD_CFG_ACCTYPE(rv) extract32(rv, 8, 2) |
| 77 | #define FIU_DRD_CFG_RDCMD(rv) extract32(rv, 0, 8) |
| 78 | |
| 79 | /* Direct Write configuration register fields. */ |
| 80 | #define FIU_DWR_CFG_ADDSIZ(rv) extract32(rv, 16, 2) |
| 81 | #define FIU_DWR_CFG_WRCMD(rv) extract32(rv, 0, 8) |
| 82 | |
| 83 | /* User-Mode Access register fields. */ |
| 84 | |
| 85 | /* Command Mode Lock and the bits protected by it. */ |
| 86 | #define FIU_UMA_CFG_CMMLCK BIT(30) |
| 87 | #define FIU_UMA_CFG_CMMLCK_MASK 0x00000403 |
| 88 | |
| 89 | #define FIU_UMA_CFG_RDATSIZ(rv) extract32(rv, 24, 5) |
| 90 | #define FIU_UMA_CFG_DBSIZ(rv) extract32(rv, 21, 3) |
| 91 | #define FIU_UMA_CFG_WDATSIZ(rv) extract32(rv, 16, 5) |
| 92 | #define FIU_UMA_CFG_ADDSIZ(rv) extract32(rv, 11, 3) |
| 93 | #define FIU_UMA_CFG_CMDSIZ(rv) extract32(rv, 10, 1) |
| 94 | #define FIU_UMA_CFG_DBPCK(rv) extract32(rv, 6, 2) |
| 95 | |
| 96 | #define FIU_UMA_CTS_RDYIE BIT(25) |
| 97 | #define FIU_UMA_CTS_RDYST BIT(24) |
| 98 | #define FIU_UMA_CTS_SW_CS BIT(16) |
| 99 | #define FIU_UMA_CTS_DEV_NUM(rv) extract32(rv, 8, 2) |
| 100 | #define FIU_UMA_CTS_EXEC_DONE BIT(0) |
| 101 | |
| 102 | /* |
| 103 | * Returns the index of flash in the fiu->flash array. This corresponds to the |
| 104 | * chip select ID of the flash. |
| 105 | */ |
| 106 | static unsigned npcm7xx_fiu_cs_index(NPCM7xxFIUState *fiu, |
| 107 | NPCM7xxFIUFlash *flash) |
| 108 | { |
| 109 | int index = flash - fiu->flash; |
| 110 | |
| 111 | g_assert(index >= 0 && index < fiu->cs_count); |
| 112 | |
| 113 | return index; |
| 114 | } |
| 115 | |
| 116 | /* Assert the chip select specified in the UMA Control/Status Register. */ |
| 117 | static void npcm7xx_fiu_select(NPCM7xxFIUState *s, unsigned cs_id) |
| 118 | { |
| 119 | trace_npcm7xx_fiu_select(DEVICE(s)->canonical_path, cs_id); |
| 120 | |
| 121 | if (cs_id < s->cs_count) { |
| 122 | qemu_irq_lower(s->cs_lines[cs_id]); |
| 123 | s->active_cs = cs_id; |
| 124 | } else { |
| 125 | qemu_log_mask(LOG_GUEST_ERROR, |
| 126 | "%s: UMA to CS%d; this module has only %d chip selects", |
| 127 | DEVICE(s)->canonical_path, cs_id, s->cs_count); |
| 128 | s->active_cs = -1; |
| 129 | } |
| 130 | } |
| 131 | |
| 132 | /* Deassert the currently active chip select. */ |
| 133 | static void npcm7xx_fiu_deselect(NPCM7xxFIUState *s) |
| 134 | { |
| 135 | if (s->active_cs < 0) { |
| 136 | return; |
| 137 | } |
| 138 | |
| 139 | trace_npcm7xx_fiu_deselect(DEVICE(s)->canonical_path, s->active_cs); |
| 140 | |
| 141 | qemu_irq_raise(s->cs_lines[s->active_cs]); |
| 142 | s->active_cs = -1; |
| 143 | } |
| 144 | |
| 145 | /* Direct flash memory read handler. */ |
| 146 | static uint64_t npcm7xx_fiu_flash_read(void *opaque, hwaddr addr, |
| 147 | unsigned int size) |
| 148 | { |
| 149 | NPCM7xxFIUFlash *f = opaque; |
| 150 | NPCM7xxFIUState *fiu = f->fiu; |
| 151 | uint64_t value = 0; |
| 152 | uint32_t drd_cfg; |
| 153 | int dummy_bytes; |
| 154 | int i; |
| 155 | |
| 156 | if (fiu->active_cs != -1) { |
| 157 | qemu_log_mask(LOG_GUEST_ERROR, |
| 158 | "%s: direct flash read with CS%d already active", |
| 159 | DEVICE(fiu)->canonical_path, fiu->active_cs); |
| 160 | } |
| 161 | |
| 162 | npcm7xx_fiu_select(fiu, npcm7xx_fiu_cs_index(fiu, f)); |
| 163 | |
| 164 | drd_cfg = fiu->regs[NPCM7XX_FIU_DRD_CFG]; |
| 165 | ssi_transfer(fiu->spi, FIU_DRD_CFG_RDCMD(drd_cfg)); |
| 166 | |
| 167 | switch (FIU_DRD_CFG_ADDSIZ(drd_cfg)) { |
| 168 | case FIU_ADDSIZ_4BYTES: |
| 169 | ssi_transfer(fiu->spi, extract32(addr, 24, 8)); |
| 170 | /* fall through */ |
| 171 | case FIU_ADDSIZ_3BYTES: |
| 172 | ssi_transfer(fiu->spi, extract32(addr, 16, 8)); |
| 173 | ssi_transfer(fiu->spi, extract32(addr, 8, 8)); |
| 174 | ssi_transfer(fiu->spi, extract32(addr, 0, 8)); |
| 175 | break; |
| 176 | |
| 177 | default: |
| 178 | qemu_log_mask(LOG_GUEST_ERROR, "%s: bad address size %d\n", |
| 179 | DEVICE(fiu)->canonical_path, FIU_DRD_CFG_ADDSIZ(drd_cfg)); |
| 180 | break; |
| 181 | } |
| 182 | |
| 183 | dummy_bytes = FIU_DRD_CFG_DBW(drd_cfg); |
| 184 | for (i = 0; i < dummy_bytes; i++) { |
| 185 | ssi_transfer(fiu->spi, 0); |
| 186 | } |
| 187 | |
| 188 | for (i = 0; i < size; i++) { |
| 189 | value = deposit64(value, 8 * i, 8, ssi_transfer(fiu->spi, 0)); |
| 190 | } |
| 191 | |
| 192 | trace_npcm7xx_fiu_flash_read(DEVICE(fiu)->canonical_path, fiu->active_cs, |
| 193 | addr, size, value); |
| 194 | |
| 195 | npcm7xx_fiu_deselect(fiu); |
| 196 | |
| 197 | return value; |
| 198 | } |
| 199 | |
| 200 | /* Direct flash memory write handler. */ |
| 201 | static void npcm7xx_fiu_flash_write(void *opaque, hwaddr addr, uint64_t v, |
| 202 | unsigned int size) |
| 203 | { |
| 204 | NPCM7xxFIUFlash *f = opaque; |
| 205 | NPCM7xxFIUState *fiu = f->fiu; |
| 206 | uint32_t dwr_cfg; |
| 207 | unsigned cs_id; |
| 208 | int i; |
| 209 | |
| 210 | if (fiu->active_cs != -1) { |
| 211 | qemu_log_mask(LOG_GUEST_ERROR, |
| 212 | "%s: direct flash write with CS%d already active", |
| 213 | DEVICE(fiu)->canonical_path, fiu->active_cs); |
| 214 | } |
| 215 | |
| 216 | cs_id = npcm7xx_fiu_cs_index(fiu, f); |
| 217 | trace_npcm7xx_fiu_flash_write(DEVICE(fiu)->canonical_path, cs_id, addr, |
| 218 | size, v); |
| 219 | npcm7xx_fiu_select(fiu, cs_id); |
| 220 | |
| 221 | dwr_cfg = fiu->regs[NPCM7XX_FIU_DWR_CFG]; |
| 222 | ssi_transfer(fiu->spi, FIU_DWR_CFG_WRCMD(dwr_cfg)); |
| 223 | |
| 224 | switch (FIU_DWR_CFG_ADDSIZ(dwr_cfg)) { |
| 225 | case FIU_ADDSIZ_4BYTES: |
| 226 | ssi_transfer(fiu->spi, extract32(addr, 24, 8)); |
| 227 | /* fall through */ |
| 228 | case FIU_ADDSIZ_3BYTES: |
| 229 | ssi_transfer(fiu->spi, extract32(addr, 16, 8)); |
| 230 | ssi_transfer(fiu->spi, extract32(addr, 8, 8)); |
| 231 | ssi_transfer(fiu->spi, extract32(addr, 0, 8)); |
| 232 | break; |
| 233 | |
| 234 | default: |
| 235 | qemu_log_mask(LOG_GUEST_ERROR, "%s: bad address size %d\n", |
| 236 | DEVICE(fiu)->canonical_path, FIU_DWR_CFG_ADDSIZ(dwr_cfg)); |
| 237 | break; |
| 238 | } |
| 239 | |
| 240 | for (i = 0; i < size; i++) { |
| 241 | ssi_transfer(fiu->spi, extract64(v, i * 8, 8)); |
| 242 | } |
| 243 | |
| 244 | npcm7xx_fiu_deselect(fiu); |
| 245 | } |
| 246 | |
| 247 | static const MemoryRegionOps npcm7xx_fiu_flash_ops = { |
| 248 | .read = npcm7xx_fiu_flash_read, |
| 249 | .write = npcm7xx_fiu_flash_write, |
| 250 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 251 | .impl = { |
| 252 | .min_access_size = 1, |
| 253 | .max_access_size = 8, |
| 254 | .unaligned = true, |
| 255 | }, |
| 256 | .valid = { |
| 257 | .min_access_size = 1, |
| 258 | .max_access_size = 8, |
| 259 | .unaligned = true, |
| 260 | }, |
| 261 | }; |
| 262 | |
| 263 | /* Control register read handler. */ |
| 264 | static uint64_t npcm7xx_fiu_ctrl_read(void *opaque, hwaddr addr, |
| 265 | unsigned int size) |
| 266 | { |
| 267 | hwaddr reg = addr / sizeof(uint32_t); |
| 268 | NPCM7xxFIUState *s = opaque; |
| 269 | uint32_t value; |
| 270 | |
| 271 | if (reg < NPCM7XX_FIU_NR_REGS) { |
| 272 | value = s->regs[reg]; |
| 273 | } else { |
| 274 | qemu_log_mask(LOG_GUEST_ERROR, |
| 275 | "%s: read from invalid offset 0x%" PRIx64 "\n", |
| 276 | DEVICE(s)->canonical_path, addr); |
| 277 | value = 0; |
| 278 | } |
| 279 | |
| 280 | trace_npcm7xx_fiu_ctrl_read(DEVICE(s)->canonical_path, addr, value); |
| 281 | |
| 282 | return value; |
| 283 | } |
| 284 | |
| 285 | /* Send the specified number of address bytes from the UMA address register. */ |
| 286 | static void send_address(SSIBus *spi, unsigned int addsiz, uint32_t addr) |
| 287 | { |
| 288 | switch (addsiz) { |
| 289 | case 4: |
| 290 | ssi_transfer(spi, extract32(addr, 24, 8)); |
| 291 | /* fall through */ |
| 292 | case 3: |
| 293 | ssi_transfer(spi, extract32(addr, 16, 8)); |
| 294 | /* fall through */ |
| 295 | case 2: |
| 296 | ssi_transfer(spi, extract32(addr, 8, 8)); |
| 297 | /* fall through */ |
| 298 | case 1: |
| 299 | ssi_transfer(spi, extract32(addr, 0, 8)); |
| 300 | /* fall through */ |
| 301 | case 0: |
| 302 | break; |
| 303 | } |
| 304 | } |
| 305 | |
| 306 | /* Send the number of dummy bytes specified in the UMA config register */ |
| 307 | static void send_dummy_bytes(SSIBus *spi, uint32_t uma_cfg) |
| 308 | { |
| 309 | unsigned int i; |
| 310 | |
| 311 | for (i = 0; i < FIU_UMA_CFG_DBSIZ(uma_cfg); i++) { |
| 312 | ssi_transfer(spi, 0); |
| 313 | } |
| 314 | } |
| 315 | |
| 316 | /* Perform a User-Mode Access transaction. */ |
| 317 | static void npcm7xx_fiu_uma_transaction(NPCM7xxFIUState *s) |
| 318 | { |
| 319 | uint32_t uma_cts = s->regs[NPCM7XX_FIU_UMA_CTS]; |
| 320 | uint32_t uma_cfg; |
| 321 | unsigned int i; |
| 322 | |
| 323 | /* SW_CS means the CS is already forced low, so don't touch it. */ |
| 324 | if (uma_cts & FIU_UMA_CTS_SW_CS) { |
| 325 | int cs_id = FIU_UMA_CTS_DEV_NUM(s->regs[NPCM7XX_FIU_UMA_CTS]); |
| 326 | npcm7xx_fiu_select(s, cs_id); |
| 327 | } |
| 328 | |
| 329 | /* Send command, if present. */ |
| 330 | uma_cfg = s->regs[NPCM7XX_FIU_UMA_CFG]; |
| 331 | if (FIU_UMA_CFG_CMDSIZ(uma_cfg) > 0) { |
| 332 | ssi_transfer(s->spi, extract32(s->regs[NPCM7XX_FIU_UMA_CMD], 0, 8)); |
| 333 | } |
| 334 | |
| 335 | /* Send address, if present. */ |
| 336 | send_address(s->spi, FIU_UMA_CFG_ADDSIZ(uma_cfg), |
| 337 | s->regs[NPCM7XX_FIU_UMA_ADDR]); |
| 338 | |
| 339 | /* Write data, if present. */ |
| 340 | for (i = 0; i < FIU_UMA_CFG_WDATSIZ(uma_cfg); i++) { |
| 341 | unsigned int reg = |
| 342 | (i < 16) ? (NPCM7XX_FIU_UMA_DW0 + i / 4) : NPCM7XX_FIU_UMA_DW3; |
| 343 | unsigned int field = (i % 4) * 8; |
| 344 | |
| 345 | ssi_transfer(s->spi, extract32(s->regs[reg], field, 8)); |
| 346 | } |
| 347 | |
| 348 | /* Send dummy bytes, if present */ |
| 349 | send_dummy_bytes(s->spi, uma_cfg); |
| 350 | |
| 351 | /* Read data, if present. */ |
| 352 | for (i = 0; i < FIU_UMA_CFG_RDATSIZ(uma_cfg); i++) { |
| 353 | unsigned int reg = NPCM7XX_FIU_UMA_DR0 + i / 4; |
| 354 | unsigned int field = (i % 4) * 8; |
| 355 | uint8_t c; |
| 356 | |
| 357 | c = ssi_transfer(s->spi, 0); |
| 358 | if (reg <= NPCM7XX_FIU_UMA_DR3) { |
| 359 | s->regs[reg] = deposit32(s->regs[reg], field, 8, c); |
| 360 | } |
| 361 | } |
| 362 | |
| 363 | /* Again, don't touch CS if the user is forcing it low. */ |
| 364 | if (uma_cts & FIU_UMA_CTS_SW_CS) { |
| 365 | npcm7xx_fiu_deselect(s); |
| 366 | } |
| 367 | |
| 368 | /* RDYST means a command has completed since it was cleared. */ |
| 369 | s->regs[NPCM7XX_FIU_UMA_CTS] |= FIU_UMA_CTS_RDYST; |
| 370 | /* EXEC_DONE means Execute Command / Not Done, so clear it here. */ |
| 371 | s->regs[NPCM7XX_FIU_UMA_CTS] &= ~FIU_UMA_CTS_EXEC_DONE; |
| 372 | } |
| 373 | |
| 374 | /* Control register write handler. */ |
| 375 | static void npcm7xx_fiu_ctrl_write(void *opaque, hwaddr addr, uint64_t v, |
| 376 | unsigned int size) |
| 377 | { |
| 378 | hwaddr reg = addr / sizeof(uint32_t); |
| 379 | NPCM7xxFIUState *s = opaque; |
| 380 | uint32_t value = v; |
| 381 | |
| 382 | trace_npcm7xx_fiu_ctrl_write(DEVICE(s)->canonical_path, addr, value); |
| 383 | |
| 384 | switch (reg) { |
| 385 | case NPCM7XX_FIU_UMA_CFG: |
| 386 | if (s->regs[reg] & FIU_UMA_CFG_CMMLCK) { |
| 387 | value &= ~FIU_UMA_CFG_CMMLCK_MASK; |
| 388 | value |= (s->regs[reg] & FIU_UMA_CFG_CMMLCK_MASK); |
| 389 | } |
| 390 | /* fall through */ |
| 391 | case NPCM7XX_FIU_DRD_CFG: |
| 392 | case NPCM7XX_FIU_DWR_CFG: |
| 393 | if (s->regs[reg] & NPCM7XX_FIU_CFG_LCK) { |
| 394 | qemu_log_mask(LOG_GUEST_ERROR, |
| 395 | "%s: write to locked register @ 0x%" PRIx64 "\n", |
| 396 | DEVICE(s)->canonical_path, addr); |
| 397 | return; |
| 398 | } |
| 399 | s->regs[reg] = value; |
| 400 | break; |
| 401 | |
| 402 | case NPCM7XX_FIU_UMA_CTS: |
| 403 | if (value & FIU_UMA_CTS_RDYST) { |
| 404 | value &= ~FIU_UMA_CTS_RDYST; |
| 405 | } else { |
| 406 | value |= s->regs[reg] & FIU_UMA_CTS_RDYST; |
| 407 | } |
| 408 | if ((s->regs[reg] ^ value) & FIU_UMA_CTS_SW_CS) { |
| 409 | if (value & FIU_UMA_CTS_SW_CS) { |
| 410 | /* |
| 411 | * Don't drop CS if there's a transfer in progress, or we're |
| 412 | * about to start one. |
| 413 | */ |
| 414 | if (!((value | s->regs[reg]) & FIU_UMA_CTS_EXEC_DONE)) { |
| 415 | npcm7xx_fiu_deselect(s); |
| 416 | } |
| 417 | } else { |
| 418 | int cs_id = FIU_UMA_CTS_DEV_NUM(s->regs[NPCM7XX_FIU_UMA_CTS]); |
| 419 | npcm7xx_fiu_select(s, cs_id); |
| 420 | } |
| 421 | } |
| 422 | s->regs[reg] = value | (s->regs[reg] & FIU_UMA_CTS_EXEC_DONE); |
| 423 | if (value & FIU_UMA_CTS_EXEC_DONE) { |
| 424 | npcm7xx_fiu_uma_transaction(s); |
| 425 | } |
| 426 | break; |
| 427 | |
| 428 | case NPCM7XX_FIU_UMA_DR0 ... NPCM7XX_FIU_UMA_DR3: |
| 429 | qemu_log_mask(LOG_GUEST_ERROR, |
| 430 | "%s: write to read-only register @ 0x%" PRIx64 "\n", |
| 431 | DEVICE(s)->canonical_path, addr); |
| 432 | return; |
| 433 | |
| 434 | case NPCM7XX_FIU_PRT_CFG: |
| 435 | case NPCM7XX_FIU_PRT_CMD0 ... NPCM7XX_FIU_PRT_CMD9: |
| 436 | qemu_log_mask(LOG_UNIMP, "%s: PRT is not implemented\n", __func__); |
| 437 | break; |
| 438 | |
| 439 | case NPCM7XX_FIU_UMA_CMD: |
| 440 | case NPCM7XX_FIU_UMA_ADDR: |
| 441 | case NPCM7XX_FIU_UMA_DW0 ... NPCM7XX_FIU_UMA_DW3: |
| 442 | case NPCM7XX_FIU_CFG: |
| 443 | s->regs[reg] = value; |
| 444 | break; |
| 445 | |
| 446 | default: |
| 447 | qemu_log_mask(LOG_GUEST_ERROR, |
| 448 | "%s: write to invalid offset 0x%" PRIx64 "\n", |
| 449 | DEVICE(s)->canonical_path, addr); |
| 450 | return; |
| 451 | } |
| 452 | } |
| 453 | |
| 454 | static const MemoryRegionOps npcm7xx_fiu_ctrl_ops = { |
| 455 | .read = npcm7xx_fiu_ctrl_read, |
| 456 | .write = npcm7xx_fiu_ctrl_write, |
| 457 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 458 | .valid = { |
| 459 | .min_access_size = 4, |
| 460 | .max_access_size = 4, |
| 461 | .unaligned = false, |
| 462 | }, |
| 463 | }; |
| 464 | |
| 465 | static void npcm7xx_fiu_enter_reset(Object *obj, ResetType type) |
| 466 | { |
| 467 | NPCM7xxFIUState *s = NPCM7XX_FIU(obj); |
| 468 | |
| 469 | trace_npcm7xx_fiu_enter_reset(DEVICE(obj)->canonical_path, type); |
| 470 | |
| 471 | memset(s->regs, 0, sizeof(s->regs)); |
| 472 | |
| 473 | s->regs[NPCM7XX_FIU_DRD_CFG] = 0x0300100b; |
| 474 | s->regs[NPCM7XX_FIU_DWR_CFG] = 0x03000002; |
| 475 | s->regs[NPCM7XX_FIU_UMA_CFG] = 0x00000400; |
| 476 | s->regs[NPCM7XX_FIU_UMA_CTS] = 0x00010000; |
| 477 | s->regs[NPCM7XX_FIU_UMA_CMD] = 0x0000000b; |
| 478 | s->regs[NPCM7XX_FIU_PRT_CFG] = 0x00000400; |
| 479 | s->regs[NPCM7XX_FIU_CFG] = 0x0000000b; |
| 480 | } |
| 481 | |
| 482 | static void npcm7xx_fiu_hold_reset(Object *obj, ResetType type) |
| 483 | { |
| 484 | NPCM7xxFIUState *s = NPCM7XX_FIU(obj); |
| 485 | int i; |
| 486 | |
| 487 | trace_npcm7xx_fiu_hold_reset(DEVICE(obj)->canonical_path); |
| 488 | |
| 489 | for (i = 0; i < s->cs_count; i++) { |
| 490 | qemu_irq_raise(s->cs_lines[i]); |
| 491 | } |
| 492 | } |
| 493 | |
| 494 | static void npcm7xx_fiu_realize(DeviceState *dev, Error **errp) |
| 495 | { |
| 496 | NPCM7xxFIUState *s = NPCM7XX_FIU(dev); |
| 497 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
| 498 | int i; |
| 499 | |
| 500 | if (s->cs_count <= 0) { |
| 501 | error_setg(errp, "%s: %d chip selects specified, need at least one", |
| 502 | dev->canonical_path, s->cs_count); |
| 503 | return; |
| 504 | } |
| 505 | |
| 506 | if (s->flash_size == 0) { |
| 507 | error_setg(errp, "%s: flash size must be set", dev->canonical_path); |
| 508 | return; |
| 509 | } |
| 510 | |
| 511 | if (s->flash_size > NPCM7XX_FIU_MAX_FLASH_WINDOW_SIZE) { |
| 512 | error_setg(errp, "%s: flash size should not exceed 128 MiB", |
| 513 | dev->canonical_path); |
| 514 | return; |
| 515 | } |
| 516 | |
| 517 | s->spi = ssi_create_bus(dev, "spi"); |
| 518 | s->cs_lines = g_new0(qemu_irq, s->cs_count); |
| 519 | qdev_init_gpio_out_named(DEVICE(s), s->cs_lines, "cs", s->cs_count); |
| 520 | s->flash = g_new0(NPCM7xxFIUFlash, s->cs_count); |
| 521 | |
| 522 | /* |
| 523 | * Register the control registers region first. It may be followed by one |
| 524 | * or more direct flash access regions. |
| 525 | */ |
| 526 | memory_region_init_io(&s->mmio, OBJECT(s), &npcm7xx_fiu_ctrl_ops, s, "ctrl", |
| 527 | NPCM7XX_FIU_CTRL_REGS_SIZE); |
| 528 | sysbus_init_mmio(sbd, &s->mmio); |
| 529 | |
| 530 | for (i = 0; i < s->cs_count; i++) { |
| 531 | NPCM7xxFIUFlash *flash = &s->flash[i]; |
| 532 | flash->fiu = s; |
| 533 | memory_region_init_io(&flash->direct_access, OBJECT(s), |
| 534 | &npcm7xx_fiu_flash_ops, &s->flash[i], "flash", |
| 535 | s->flash_size); |
| 536 | sysbus_init_mmio(sbd, &flash->direct_access); |
| 537 | } |
| 538 | } |
| 539 | |
| 540 | static const VMStateDescription vmstate_npcm7xx_fiu = { |
| 541 | .name = "npcm7xx-fiu", |
| 542 | .version_id = 0, |
| 543 | .minimum_version_id = 0, |
| 544 | .fields = (const VMStateField[]) { |
| 545 | VMSTATE_INT32(active_cs, NPCM7xxFIUState), |
| 546 | VMSTATE_UINT32_ARRAY(regs, NPCM7xxFIUState, NPCM7XX_FIU_NR_REGS), |
| 547 | VMSTATE_END_OF_LIST(), |
| 548 | }, |
| 549 | }; |
| 550 | |
| 551 | static const Property npcm7xx_fiu_properties[] = { |
| 552 | DEFINE_PROP_INT32("cs-count", NPCM7xxFIUState, cs_count, 0), |
| 553 | DEFINE_PROP_SIZE("flash-size", NPCM7xxFIUState, flash_size, 0), |
| 554 | }; |
| 555 | |
| 556 | static void npcm7xx_fiu_class_init(ObjectClass *klass, const void *data) |
| 557 | { |
| 558 | ResettableClass *rc = RESETTABLE_CLASS(klass); |
| 559 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 560 | |
| 561 | QEMU_BUILD_BUG_ON(NPCM7XX_FIU_REGS_END > NPCM7XX_FIU_NR_REGS); |
| 562 | |
| 563 | dc->desc = "NPCM7xx Flash Interface Unit"; |
| 564 | dc->realize = npcm7xx_fiu_realize; |
| 565 | dc->vmsd = &vmstate_npcm7xx_fiu; |
| 566 | rc->phases.enter = npcm7xx_fiu_enter_reset; |
| 567 | rc->phases.hold = npcm7xx_fiu_hold_reset; |
| 568 | device_class_set_props(dc, npcm7xx_fiu_properties); |
| 569 | } |
| 570 | |
| 571 | static const TypeInfo npcm7xx_fiu_types[] = { |
| 572 | { |
| 573 | .name = TYPE_NPCM7XX_FIU, |
| 574 | .parent = TYPE_SYS_BUS_DEVICE, |
| 575 | .instance_size = sizeof(NPCM7xxFIUState), |
| 576 | .class_init = npcm7xx_fiu_class_init, |
| 577 | }, |
| 578 | }; |
| 579 | DEFINE_TYPES(npcm7xx_fiu_types); |