| 1 | /* |
| 2 | * QEMU model of the Xilinx Zynq SPI controller |
| 3 | * |
| 4 | * Copyright (c) 2012 Peter A. G. Crosthwaite |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
| 24 | |
| 25 | #include "qemu/osdep.h" |
| 26 | #include "hw/core/sysbus.h" |
| 27 | #include "hw/core/irq.h" |
| 28 | #include "hw/core/ptimer.h" |
| 29 | #include "hw/core/qdev-properties.h" |
| 30 | #include "qemu/log.h" |
| 31 | #include "qemu/module.h" |
| 32 | #include "qemu/bitops.h" |
| 33 | #include "hw/ssi/xilinx_spips.h" |
| 34 | #include "qapi/error.h" |
| 35 | #include "hw/core/register.h" |
| 36 | #include "system/dma.h" |
| 37 | #include "migration/blocker.h" |
| 38 | #include "migration/vmstate.h" |
| 39 | |
| 40 | #ifndef XILINX_SPIPS_ERR_DEBUG |
| 41 | #define XILINX_SPIPS_ERR_DEBUG 0 |
| 42 | #endif |
| 43 | |
| 44 | #define DB_PRINT_L(level, ...) do { \ |
| 45 | if (XILINX_SPIPS_ERR_DEBUG > (level)) { \ |
| 46 | fprintf(stderr, ": %s: ", __func__); \ |
| 47 | fprintf(stderr, ## __VA_ARGS__); \ |
| 48 | } \ |
| 49 | } while (0) |
| 50 | |
| 51 | /* config register */ |
| 52 | #define R_CONFIG (0x00 / 4) |
| 53 | #define IFMODE (1U << 31) |
| 54 | #define R_CONFIG_ENDIAN (1 << 26) |
| 55 | #define MODEFAIL_GEN_EN (1 << 17) |
| 56 | #define MAN_START_COM (1 << 16) |
| 57 | #define MAN_START_EN (1 << 15) |
| 58 | #define MANUAL_CS (1 << 14) |
| 59 | #define CS (0xF << 10) |
| 60 | #define CS_SHIFT (10) |
| 61 | #define PERI_SEL (1 << 9) |
| 62 | #define REF_CLK (1 << 8) |
| 63 | #define FIFO_WIDTH (3 << 6) |
| 64 | #define BAUD_RATE_DIV (7 << 3) |
| 65 | #define CLK_PH (1 << 2) |
| 66 | #define CLK_POL (1 << 1) |
| 67 | #define MODE_SEL (1 << 0) |
| 68 | #define R_CONFIG_RSVD (0x7bf40000) |
| 69 | |
| 70 | /* interrupt mechanism */ |
| 71 | #define R_INTR_STATUS (0x04 / 4) |
| 72 | #define R_INTR_STATUS_RESET (0x104) |
| 73 | #define R_INTR_EN (0x08 / 4) |
| 74 | #define R_INTR_DIS (0x0C / 4) |
| 75 | #define R_INTR_MASK (0x10 / 4) |
| 76 | #define IXR_TX_FIFO_UNDERFLOW (1 << 6) |
| 77 | /* Poll timeout not implemented */ |
| 78 | #define IXR_RX_FIFO_EMPTY (1 << 11) |
| 79 | #define IXR_GENERIC_FIFO_FULL (1 << 10) |
| 80 | #define IXR_GENERIC_FIFO_NOT_FULL (1 << 9) |
| 81 | #define IXR_TX_FIFO_EMPTY (1 << 8) |
| 82 | #define IXR_GENERIC_FIFO_EMPTY (1 << 7) |
| 83 | #define IXR_RX_FIFO_FULL (1 << 5) |
| 84 | #define IXR_RX_FIFO_NOT_EMPTY (1 << 4) |
| 85 | #define IXR_TX_FIFO_FULL (1 << 3) |
| 86 | #define IXR_TX_FIFO_NOT_FULL (1 << 2) |
| 87 | #define IXR_TX_FIFO_MODE_FAIL (1 << 1) |
| 88 | #define IXR_RX_FIFO_OVERFLOW (1 << 0) |
| 89 | #define IXR_ALL ((1 << 13) - 1) |
| 90 | #define GQSPI_IXR_MASK 0xFBE |
| 91 | #define IXR_SELF_CLEAR \ |
| 92 | (IXR_GENERIC_FIFO_EMPTY \ |
| 93 | | IXR_GENERIC_FIFO_FULL \ |
| 94 | | IXR_GENERIC_FIFO_NOT_FULL \ |
| 95 | | IXR_TX_FIFO_EMPTY \ |
| 96 | | IXR_TX_FIFO_FULL \ |
| 97 | | IXR_TX_FIFO_NOT_FULL \ |
| 98 | | IXR_RX_FIFO_EMPTY \ |
| 99 | | IXR_RX_FIFO_FULL \ |
| 100 | | IXR_RX_FIFO_NOT_EMPTY) |
| 101 | |
| 102 | #define R_EN (0x14 / 4) |
| 103 | #define R_DELAY (0x18 / 4) |
| 104 | #define R_TX_DATA (0x1C / 4) |
| 105 | #define R_RX_DATA (0x20 / 4) |
| 106 | #define R_SLAVE_IDLE_COUNT (0x24 / 4) |
| 107 | #define R_TX_THRES (0x28 / 4) |
| 108 | #define R_RX_THRES (0x2C / 4) |
| 109 | #define R_GPIO (0x30 / 4) |
| 110 | #define R_LPBK_DLY_ADJ (0x38 / 4) |
| 111 | #define R_LPBK_DLY_ADJ_RESET (0x33) |
| 112 | #define R_IOU_TAPDLY_BYPASS (0x3C / 4) |
| 113 | #define R_TXD1 (0x80 / 4) |
| 114 | #define R_TXD2 (0x84 / 4) |
| 115 | #define R_TXD3 (0x88 / 4) |
| 116 | |
| 117 | #define R_LQSPI_CFG (0xa0 / 4) |
| 118 | #define R_LQSPI_CFG_RESET 0x03A002EB |
| 119 | #define LQSPI_CFG_LQ_MODE (1U << 31) |
| 120 | #define LQSPI_CFG_TWO_MEM (1 << 30) |
| 121 | #define LQSPI_CFG_SEP_BUS (1 << 29) |
| 122 | #define LQSPI_CFG_U_PAGE (1 << 28) |
| 123 | #define LQSPI_CFG_ADDR4 (1 << 27) |
| 124 | #define LQSPI_CFG_MODE_EN (1 << 25) |
| 125 | #define LQSPI_CFG_MODE_WIDTH 8 |
| 126 | #define LQSPI_CFG_MODE_SHIFT 16 |
| 127 | #define LQSPI_CFG_DUMMY_WIDTH 3 |
| 128 | #define LQSPI_CFG_DUMMY_SHIFT 8 |
| 129 | #define LQSPI_CFG_INST_CODE 0xFF |
| 130 | |
| 131 | #define R_CMND (0xc0 / 4) |
| 132 | #define R_CMND_RXFIFO_DRAIN (1 << 19) |
| 133 | FIELD(CMND, PARTIAL_BYTE_LEN, 16, 3) |
| 134 | #define R_CMND_EXT_ADD (1 << 15) |
| 135 | FIELD(CMND, RX_DISCARD, 8, 7) |
| 136 | FIELD(CMND, DUMMY_CYCLES, 2, 6) |
| 137 | #define R_CMND_DMA_EN (1 << 1) |
| 138 | #define R_CMND_PUSH_WAIT (1 << 0) |
| 139 | #define R_TRANSFER_SIZE (0xc4 / 4) |
| 140 | #define R_LQSPI_STS (0xA4 / 4) |
| 141 | #define LQSPI_STS_WR_RECVD (1 << 1) |
| 142 | |
| 143 | #define R_DUMMY_CYCLE_EN (0xC8 / 4) |
| 144 | #define R_ECO (0xF8 / 4) |
| 145 | #define R_MOD_ID (0xFC / 4) |
| 146 | |
| 147 | #define R_GQSPI_SELECT (0x144 / 4) |
| 148 | FIELD(GQSPI_SELECT, GENERIC_QSPI_EN, 0, 1) |
| 149 | #define R_GQSPI_ISR (0x104 / 4) |
| 150 | #define R_GQSPI_IER (0x108 / 4) |
| 151 | #define R_GQSPI_IDR (0x10c / 4) |
| 152 | #define R_GQSPI_IMR (0x110 / 4) |
| 153 | #define R_GQSPI_IMR_RESET (0xfbe) |
| 154 | #define R_GQSPI_TX_THRESH (0x128 / 4) |
| 155 | #define R_GQSPI_RX_THRESH (0x12c / 4) |
| 156 | #define R_GQSPI_GPIO (0x130 / 4) |
| 157 | #define R_GQSPI_LPBK_DLY_ADJ (0x138 / 4) |
| 158 | #define R_GQSPI_LPBK_DLY_ADJ_RESET (0x33) |
| 159 | #define R_GQSPI_CNFG (0x100 / 4) |
| 160 | FIELD(GQSPI_CNFG, MODE_EN, 30, 2) |
| 161 | FIELD(GQSPI_CNFG, GEN_FIFO_START_MODE, 29, 1) |
| 162 | FIELD(GQSPI_CNFG, GEN_FIFO_START, 28, 1) |
| 163 | FIELD(GQSPI_CNFG, ENDIAN, 26, 1) |
| 164 | /* Poll timeout not implemented */ |
| 165 | FIELD(GQSPI_CNFG, EN_POLL_TIMEOUT, 20, 1) |
| 166 | /* QEMU doesn't care about any of these last three */ |
| 167 | FIELD(GQSPI_CNFG, BR, 3, 3) |
| 168 | FIELD(GQSPI_CNFG, CPH, 2, 1) |
| 169 | FIELD(GQSPI_CNFG, CPL, 1, 1) |
| 170 | #define R_GQSPI_GEN_FIFO (0x140 / 4) |
| 171 | #define R_GQSPI_TXD (0x11c / 4) |
| 172 | #define R_GQSPI_RXD (0x120 / 4) |
| 173 | #define R_GQSPI_FIFO_CTRL (0x14c / 4) |
| 174 | FIELD(GQSPI_FIFO_CTRL, RX_FIFO_RESET, 2, 1) |
| 175 | FIELD(GQSPI_FIFO_CTRL, TX_FIFO_RESET, 1, 1) |
| 176 | FIELD(GQSPI_FIFO_CTRL, GENERIC_FIFO_RESET, 0, 1) |
| 177 | #define R_GQSPI_GFIFO_THRESH (0x150 / 4) |
| 178 | #define R_GQSPI_DATA_STS (0x15c / 4) |
| 179 | /* |
| 180 | * We use the snapshot register to hold the core state for the currently |
| 181 | * or most recently executed command. So the generic fifo format is defined |
| 182 | * for the snapshot register |
| 183 | */ |
| 184 | #define R_GQSPI_GF_SNAPSHOT (0x160 / 4) |
| 185 | FIELD(GQSPI_GF_SNAPSHOT, POLL, 19, 1) |
| 186 | FIELD(GQSPI_GF_SNAPSHOT, STRIPE, 18, 1) |
| 187 | FIELD(GQSPI_GF_SNAPSHOT, RECIEVE, 17, 1) |
| 188 | FIELD(GQSPI_GF_SNAPSHOT, TRANSMIT, 16, 1) |
| 189 | FIELD(GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT, 14, 2) |
| 190 | FIELD(GQSPI_GF_SNAPSHOT, CHIP_SELECT, 12, 2) |
| 191 | FIELD(GQSPI_GF_SNAPSHOT, SPI_MODE, 10, 2) |
| 192 | FIELD(GQSPI_GF_SNAPSHOT, EXPONENT, 9, 1) |
| 193 | FIELD(GQSPI_GF_SNAPSHOT, DATA_XFER, 8, 1) |
| 194 | FIELD(GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA, 0, 8) |
| 195 | #define GQSPI_GF_MODE_SPI 1 |
| 196 | #define GQSPI_GF_MODE_DSPI 2 |
| 197 | #define GQSPI_GF_MODE_QSPI 3 |
| 198 | |
| 199 | #define R_GQSPI_MOD_ID (0x1fc / 4) |
| 200 | #define R_GQSPI_MOD_ID_RESET (0x10a0000) |
| 201 | |
| 202 | /* size of TXRX FIFOs */ |
| 203 | #define RXFF_A (128) |
| 204 | #define TXFF_A (128) |
| 205 | |
| 206 | #define RXFF_A_Q (64 * 4) |
| 207 | #define TXFF_A_Q (64 * 4) |
| 208 | |
| 209 | /* 16MB per linear region */ |
| 210 | #define LQSPI_ADDRESS_BITS 24 |
| 211 | |
| 212 | #define SNOOP_CHECKING 0xFF |
| 213 | #define SNOOP_ADDR 0xF0 |
| 214 | #define SNOOP_NONE 0xEE |
| 215 | #define SNOOP_STRIPING 0 |
| 216 | |
| 217 | #define MIN_NUM_BUSSES 1 |
| 218 | #define MAX_NUM_BUSSES 2 |
| 219 | |
| 220 | static inline int num_effective_busses(XilinxSPIPS *s) |
| 221 | { |
| 222 | return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS && |
| 223 | s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1; |
| 224 | } |
| 225 | |
| 226 | static void xilinx_spips_update_cs(XilinxSPIPS *s, int field) |
| 227 | { |
| 228 | int i; |
| 229 | |
| 230 | for (i = 0; i < s->num_cs * s->num_busses; i++) { |
| 231 | bool old_state = s->cs_lines_state[i]; |
| 232 | bool new_state = field & (1 << i); |
| 233 | |
| 234 | if (old_state != new_state) { |
| 235 | s->cs_lines_state[i] = new_state; |
| 236 | s->rx_discard = ARRAY_FIELD_EX32(s->regs, CMND, RX_DISCARD); |
| 237 | DB_PRINT_L(1, "%sselecting peripheral %d\n", |
| 238 | new_state ? "" : "de", i); |
| 239 | } |
| 240 | qemu_set_irq(s->cs_lines[i], !new_state); |
| 241 | } |
| 242 | if (!(field & ((1 << (s->num_cs * s->num_busses)) - 1))) { |
| 243 | s->snoop_state = SNOOP_CHECKING; |
| 244 | s->cmd_dummy_bytes = 0; |
| 245 | s->link_state = 1; |
| 246 | s->link_state_next = 1; |
| 247 | s->link_state_next_when = 0; |
| 248 | DB_PRINT_L(1, "moving to snoop check state\n"); |
| 249 | } |
| 250 | } |
| 251 | |
| 252 | static void xlnx_zynqmp_qspips_update_cs_lines(XlnxZynqMPQSPIPS *s) |
| 253 | { |
| 254 | if (s->regs[R_GQSPI_GF_SNAPSHOT]) { |
| 255 | int field = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, CHIP_SELECT); |
| 256 | bool upper_cs_sel = field & (1 << 1); |
| 257 | bool lower_cs_sel = field & 1; |
| 258 | bool bus0_enabled; |
| 259 | bool bus1_enabled; |
| 260 | uint8_t buses; |
| 261 | int cs = 0; |
| 262 | |
| 263 | buses = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT); |
| 264 | bus0_enabled = buses & 1; |
| 265 | bus1_enabled = buses & (1 << 1); |
| 266 | |
| 267 | if (bus0_enabled && bus1_enabled) { |
| 268 | if (lower_cs_sel) { |
| 269 | cs |= 1; |
| 270 | } |
| 271 | if (upper_cs_sel) { |
| 272 | cs |= 1 << 3; |
| 273 | } |
| 274 | } else if (bus0_enabled) { |
| 275 | if (lower_cs_sel) { |
| 276 | cs |= 1; |
| 277 | } |
| 278 | if (upper_cs_sel) { |
| 279 | cs |= 1 << 1; |
| 280 | } |
| 281 | } else if (bus1_enabled) { |
| 282 | if (lower_cs_sel) { |
| 283 | cs |= 1 << 2; |
| 284 | } |
| 285 | if (upper_cs_sel) { |
| 286 | cs |= 1 << 3; |
| 287 | } |
| 288 | } |
| 289 | xilinx_spips_update_cs(XILINX_SPIPS(s), cs); |
| 290 | } |
| 291 | } |
| 292 | |
| 293 | static void xilinx_spips_update_cs_lines(XilinxSPIPS *s) |
| 294 | { |
| 295 | int field = ~((s->regs[R_CONFIG] & CS) >> CS_SHIFT); |
| 296 | |
| 297 | /* In dual parallel, mirror low CS to both */ |
| 298 | if (num_effective_busses(s) == 2) { |
| 299 | /* Single bit chip-select for qspi */ |
| 300 | field &= 0x1; |
| 301 | field |= field << 3; |
| 302 | /* Dual stack U-Page */ |
| 303 | } else if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM && |
| 304 | s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE) { |
| 305 | /* Single bit chip-select for qspi */ |
| 306 | field &= 0x1; |
| 307 | /* change from CS0 to CS1 */ |
| 308 | field <<= 1; |
| 309 | } |
| 310 | /* Auto CS */ |
| 311 | if (!(s->regs[R_CONFIG] & MANUAL_CS) && |
| 312 | fifo8_is_empty(&s->tx_fifo)) { |
| 313 | field = 0; |
| 314 | } |
| 315 | xilinx_spips_update_cs(s, field); |
| 316 | } |
| 317 | |
| 318 | static void xilinx_spips_update_ixr(XilinxSPIPS *s) |
| 319 | { |
| 320 | if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) { |
| 321 | s->regs[R_INTR_STATUS] &= ~IXR_SELF_CLEAR; |
| 322 | s->regs[R_INTR_STATUS] |= |
| 323 | (fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) | |
| 324 | (s->rx_fifo.num >= s->regs[R_RX_THRES] ? |
| 325 | IXR_RX_FIFO_NOT_EMPTY : 0) | |
| 326 | (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) | |
| 327 | (fifo8_is_empty(&s->tx_fifo) ? IXR_TX_FIFO_EMPTY : 0) | |
| 328 | (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0); |
| 329 | } |
| 330 | int new_irqline = !!(s->regs[R_INTR_MASK] & s->regs[R_INTR_STATUS] & |
| 331 | IXR_ALL); |
| 332 | if (new_irqline != s->irqline) { |
| 333 | s->irqline = new_irqline; |
| 334 | qemu_set_irq(s->irq, s->irqline); |
| 335 | } |
| 336 | } |
| 337 | |
| 338 | static void xlnx_zynqmp_qspips_update_ixr(XlnxZynqMPQSPIPS *s) |
| 339 | { |
| 340 | uint32_t gqspi_int; |
| 341 | int new_irqline; |
| 342 | |
| 343 | s->regs[R_GQSPI_ISR] &= ~IXR_SELF_CLEAR; |
| 344 | s->regs[R_GQSPI_ISR] |= |
| 345 | (fifo32_is_empty(&s->fifo_g) ? IXR_GENERIC_FIFO_EMPTY : 0) | |
| 346 | (fifo32_is_full(&s->fifo_g) ? IXR_GENERIC_FIFO_FULL : 0) | |
| 347 | (s->fifo_g.fifo.num < s->regs[R_GQSPI_GFIFO_THRESH] ? |
| 348 | IXR_GENERIC_FIFO_NOT_FULL : 0) | |
| 349 | (fifo8_is_empty(&s->rx_fifo_g) ? IXR_RX_FIFO_EMPTY : 0) | |
| 350 | (fifo8_is_full(&s->rx_fifo_g) ? IXR_RX_FIFO_FULL : 0) | |
| 351 | (s->rx_fifo_g.num >= s->regs[R_GQSPI_RX_THRESH] ? |
| 352 | IXR_RX_FIFO_NOT_EMPTY : 0) | |
| 353 | (fifo8_is_empty(&s->tx_fifo_g) ? IXR_TX_FIFO_EMPTY : 0) | |
| 354 | (fifo8_is_full(&s->tx_fifo_g) ? IXR_TX_FIFO_FULL : 0) | |
| 355 | (s->tx_fifo_g.num < s->regs[R_GQSPI_TX_THRESH] ? |
| 356 | IXR_TX_FIFO_NOT_FULL : 0); |
| 357 | |
| 358 | /* GQSPI Interrupt Trigger Status */ |
| 359 | gqspi_int = (~s->regs[R_GQSPI_IMR]) & s->regs[R_GQSPI_ISR] & GQSPI_IXR_MASK; |
| 360 | new_irqline = !!(gqspi_int & IXR_ALL); |
| 361 | |
| 362 | /* drive external interrupt pin */ |
| 363 | if (new_irqline != s->gqspi_irqline) { |
| 364 | s->gqspi_irqline = new_irqline; |
| 365 | qemu_set_irq(XILINX_SPIPS(s)->irq, s->gqspi_irqline); |
| 366 | } |
| 367 | } |
| 368 | |
| 369 | static void xilinx_spips_reset(DeviceState *d) |
| 370 | { |
| 371 | XilinxSPIPS *s = XILINX_SPIPS(d); |
| 372 | |
| 373 | memset(s->regs, 0, sizeof(s->regs)); |
| 374 | |
| 375 | fifo8_reset(&s->rx_fifo); |
| 376 | fifo8_reset(&s->tx_fifo); |
| 377 | /* non zero resets */ |
| 378 | s->regs[R_CONFIG] |= MODEFAIL_GEN_EN; |
| 379 | s->regs[R_SLAVE_IDLE_COUNT] = 0xFF; |
| 380 | s->regs[R_TX_THRES] = 1; |
| 381 | s->regs[R_RX_THRES] = 1; |
| 382 | /* FIXME: move magic number definition somewhere sensible */ |
| 383 | s->regs[R_MOD_ID] = 0x01090106; |
| 384 | s->regs[R_LQSPI_CFG] = R_LQSPI_CFG_RESET; |
| 385 | s->link_state = 1; |
| 386 | s->link_state_next = 1; |
| 387 | s->link_state_next_when = 0; |
| 388 | s->snoop_state = SNOOP_CHECKING; |
| 389 | s->cmd_dummy_bytes = 0; |
| 390 | s->man_start_com = false; |
| 391 | xilinx_spips_update_ixr(s); |
| 392 | xilinx_spips_update_cs_lines(s); |
| 393 | } |
| 394 | |
| 395 | static void xlnx_zynqmp_qspips_reset(DeviceState *d) |
| 396 | { |
| 397 | XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(d); |
| 398 | |
| 399 | xilinx_spips_reset(d); |
| 400 | |
| 401 | memset(s->regs, 0, sizeof(s->regs)); |
| 402 | |
| 403 | fifo8_reset(&s->rx_fifo_g); |
| 404 | fifo8_reset(&s->tx_fifo_g); |
| 405 | fifo32_reset(&s->fifo_g); |
| 406 | s->regs[R_INTR_STATUS] = R_INTR_STATUS_RESET; |
| 407 | s->regs[R_GPIO] = 1; |
| 408 | s->regs[R_LPBK_DLY_ADJ] = R_LPBK_DLY_ADJ_RESET; |
| 409 | s->regs[R_GQSPI_GFIFO_THRESH] = 0x10; |
| 410 | s->regs[R_MOD_ID] = 0x01090101; |
| 411 | s->regs[R_GQSPI_IMR] = R_GQSPI_IMR_RESET; |
| 412 | s->regs[R_GQSPI_TX_THRESH] = 1; |
| 413 | s->regs[R_GQSPI_RX_THRESH] = 1; |
| 414 | s->regs[R_GQSPI_GPIO] = 1; |
| 415 | s->regs[R_GQSPI_LPBK_DLY_ADJ] = R_GQSPI_LPBK_DLY_ADJ_RESET; |
| 416 | s->regs[R_GQSPI_MOD_ID] = R_GQSPI_MOD_ID_RESET; |
| 417 | s->man_start_com_g = false; |
| 418 | s->gqspi_irqline = 0; |
| 419 | xlnx_zynqmp_qspips_update_ixr(s); |
| 420 | } |
| 421 | |
| 422 | /* |
| 423 | * N way (num) in place bit striper. Lay out row wise bits (MSB to LSB) |
| 424 | * column wise (from element 0 to N-1). num is the length of x, and dir |
| 425 | * reverses the direction of the transform. Best illustrated by example: |
| 426 | * Each digit in the below array is a single bit (num == 3): |
| 427 | * |
| 428 | * {{ 76543210, } ----- stripe (dir == false) -----> {{ 741gdaFC, } |
| 429 | * { hgfedcba, } { 630fcHEB, } |
| 430 | * { HGFEDCBA, }} <---- upstripe (dir == true) ----- { 52hebGDA, }} |
| 431 | */ |
| 432 | |
| 433 | static inline void stripe8(uint8_t *x, int num, bool dir) |
| 434 | { |
| 435 | uint8_t r[MAX_NUM_BUSSES]; |
| 436 | int idx[2] = {0, 0}; |
| 437 | int bit[2] = {0, 7}; |
| 438 | int d = dir; |
| 439 | |
| 440 | assert(num <= MAX_NUM_BUSSES); |
| 441 | memset(r, 0, sizeof(uint8_t) * num); |
| 442 | |
| 443 | for (idx[0] = 0; idx[0] < num; ++idx[0]) { |
| 444 | for (bit[0] = 7; bit[0] >= 0; bit[0]--) { |
| 445 | r[idx[!d]] |= x[idx[d]] & 1 << bit[d] ? 1 << bit[!d] : 0; |
| 446 | idx[1] = (idx[1] + 1) % num; |
| 447 | if (!idx[1]) { |
| 448 | bit[1]--; |
| 449 | } |
| 450 | } |
| 451 | } |
| 452 | memcpy(x, r, sizeof(uint8_t) * num); |
| 453 | } |
| 454 | |
| 455 | static void xlnx_zynqmp_qspips_flush_fifo_g(XlnxZynqMPQSPIPS *s) |
| 456 | { |
| 457 | while (s->regs[R_GQSPI_DATA_STS] || !fifo32_is_empty(&s->fifo_g)) { |
| 458 | uint8_t tx_rx[2] = { 0 }; |
| 459 | int num_stripes = 1; |
| 460 | uint8_t busses; |
| 461 | int i; |
| 462 | |
| 463 | if (!s->regs[R_GQSPI_DATA_STS]) { |
| 464 | uint32_t prev_gf_snapshot = s->regs[R_GQSPI_GF_SNAPSHOT]; |
| 465 | uint8_t imm; |
| 466 | |
| 467 | s->regs[R_GQSPI_GF_SNAPSHOT] = fifo32_pop(&s->fifo_g); |
| 468 | DB_PRINT_L(0, "GQSPI command: %x\n", s->regs[R_GQSPI_GF_SNAPSHOT]); |
| 469 | if (!s->regs[R_GQSPI_GF_SNAPSHOT]) { |
| 470 | DB_PRINT_L(0, "Dummy GQSPI Delay Command Entry, Do nothing"); |
| 471 | continue; |
| 472 | } |
| 473 | xlnx_zynqmp_qspips_update_cs_lines(s); |
| 474 | |
| 475 | imm = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA); |
| 476 | if (!ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_XFER)) { |
| 477 | /* immediate transfer */ |
| 478 | if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT) || |
| 479 | ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE)) { |
| 480 | s->regs[R_GQSPI_DATA_STS] = 1; |
| 481 | /* CS setup/hold - do nothing */ |
| 482 | } else { |
| 483 | s->regs[R_GQSPI_DATA_STS] = 0; |
| 484 | } |
| 485 | } else if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, EXPONENT)) { |
| 486 | if (imm > 31) { |
| 487 | qemu_log_mask(LOG_UNIMP, "QSPI exponential transfer too" |
| 488 | " long - 2 ^ %" PRId8 " requested\n", imm); |
| 489 | } |
| 490 | s->regs[R_GQSPI_DATA_STS] = 1ul << imm; |
| 491 | } else { |
| 492 | /* |
| 493 | * When [receive, transmit, data_xfer] = [0,0,1], it represents |
| 494 | * the number of dummy cycle sent on the SPI interface. We need |
| 495 | * to convert the number of dummy cycles to bytes according to |
| 496 | * the SPI mode being used. |
| 497 | * |
| 498 | * Ref: ug1085 v2.2 (December 2020) table 24‐22, an example of |
| 499 | * Generic FIFO Contents for Quad I/O Read Command (EBh) |
| 500 | */ |
| 501 | if (!ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT) && |
| 502 | !ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE)) { |
| 503 | uint8_t spi_mode = ARRAY_FIELD_EX32(s->regs, |
| 504 | GQSPI_GF_SNAPSHOT, |
| 505 | SPI_MODE); |
| 506 | /* |
| 507 | * Some ZynqMP GQSPI drivers, such as Linux, use the data |
| 508 | * bus width in the dummy GENFIFO entry only to configure |
| 509 | * the controller mode. The immediate value is already |
| 510 | * the number of dummy cycles for the dummy phase, which |
| 511 | * follows the address bus width. Reuse the previous TX |
| 512 | * phase mode to convert cycles to SSI bytes. |
| 513 | * |
| 514 | * This does not make the model Linux-only. U-Boot emits |
| 515 | * the dummy entry with op->dummy.buswidth, so the entry |
| 516 | * mode already matches the dummy phase. Its opcode and |
| 517 | * address phases are immediate entries, not DATA_XFER TX |
| 518 | * entries, so the override below is not taken for U-Boot. |
| 519 | */ |
| 520 | if (FIELD_EX32(prev_gf_snapshot, GQSPI_GF_SNAPSHOT, |
| 521 | DATA_XFER) && |
| 522 | FIELD_EX32(prev_gf_snapshot, GQSPI_GF_SNAPSHOT, |
| 523 | TRANSMIT) && |
| 524 | !FIELD_EX32(prev_gf_snapshot, GQSPI_GF_SNAPSHOT, |
| 525 | RECIEVE)) { |
| 526 | spi_mode = FIELD_EX32(prev_gf_snapshot, |
| 527 | GQSPI_GF_SNAPSHOT, SPI_MODE); |
| 528 | } |
| 529 | |
| 530 | if (spi_mode == GQSPI_GF_MODE_QSPI) { |
| 531 | s->regs[R_GQSPI_DATA_STS] = ROUND_UP(imm * 4, 8) / 8; |
| 532 | } else if (spi_mode == GQSPI_GF_MODE_DSPI) { |
| 533 | s->regs[R_GQSPI_DATA_STS] = ROUND_UP(imm * 2, 8) / 8; |
| 534 | } else if (spi_mode == GQSPI_GF_MODE_SPI) { |
| 535 | s->regs[R_GQSPI_DATA_STS] = ROUND_UP(imm * 1, 8) / 8; |
| 536 | } else { |
| 537 | qemu_log_mask(LOG_GUEST_ERROR, |
| 538 | "Unknown SPI MODE: 0x%x ", spi_mode); |
| 539 | } |
| 540 | } else { |
| 541 | s->regs[R_GQSPI_DATA_STS] = imm; |
| 542 | } |
| 543 | } |
| 544 | } |
| 545 | /* Zero length transfer check */ |
| 546 | if (!s->regs[R_GQSPI_DATA_STS]) { |
| 547 | continue; |
| 548 | } |
| 549 | if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE) && |
| 550 | fifo8_is_full(&s->rx_fifo_g)) { |
| 551 | /* No space in RX fifo for transfer - try again later */ |
| 552 | return; |
| 553 | } |
| 554 | if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, STRIPE) && |
| 555 | (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT) || |
| 556 | ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE))) { |
| 557 | num_stripes = 2; |
| 558 | } |
| 559 | if (!ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_XFER)) { |
| 560 | tx_rx[0] = ARRAY_FIELD_EX32(s->regs, |
| 561 | GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA); |
| 562 | } else if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT)) { |
| 563 | for (i = 0; i < num_stripes; ++i) { |
| 564 | if (!fifo8_is_empty(&s->tx_fifo_g)) { |
| 565 | tx_rx[i] = fifo8_pop(&s->tx_fifo_g); |
| 566 | s->tx_fifo_g_align++; |
| 567 | } else { |
| 568 | return; |
| 569 | } |
| 570 | } |
| 571 | } |
| 572 | if (num_stripes == 1) { |
| 573 | /* mirror */ |
| 574 | tx_rx[1] = tx_rx[0]; |
| 575 | } |
| 576 | busses = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT); |
| 577 | for (i = 0; i < 2; ++i) { |
| 578 | DB_PRINT_L(1, "bus %d tx = %02x\n", i, tx_rx[i]); |
| 579 | tx_rx[i] = ssi_transfer(XILINX_SPIPS(s)->spi[i], tx_rx[i]); |
| 580 | DB_PRINT_L(1, "bus %d rx = %02x\n", i, tx_rx[i]); |
| 581 | } |
| 582 | if (s->regs[R_GQSPI_DATA_STS] > 1 && |
| 583 | busses == 0x3 && num_stripes == 2) { |
| 584 | s->regs[R_GQSPI_DATA_STS] -= 2; |
| 585 | } else if (s->regs[R_GQSPI_DATA_STS] > 0) { |
| 586 | s->regs[R_GQSPI_DATA_STS]--; |
| 587 | } |
| 588 | if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE)) { |
| 589 | for (i = 0; i < 2; ++i) { |
| 590 | if (busses & (1 << i)) { |
| 591 | DB_PRINT_L(1, "bus %d push_byte = %02x\n", i, tx_rx[i]); |
| 592 | fifo8_push(&s->rx_fifo_g, tx_rx[i]); |
| 593 | s->rx_fifo_g_align++; |
| 594 | } |
| 595 | } |
| 596 | } |
| 597 | if (!s->regs[R_GQSPI_DATA_STS]) { |
| 598 | for (; s->tx_fifo_g_align % 4; s->tx_fifo_g_align++) { |
| 599 | fifo8_pop(&s->tx_fifo_g); |
| 600 | } |
| 601 | for (; s->rx_fifo_g_align % 4; s->rx_fifo_g_align++) { |
| 602 | fifo8_push(&s->rx_fifo_g, 0); |
| 603 | } |
| 604 | } |
| 605 | } |
| 606 | } |
| 607 | |
| 608 | static int xilinx_spips_num_dummy_bytes(XilinxQSPIPS *qs, uint8_t command) |
| 609 | { |
| 610 | if (!qs) { |
| 611 | /* The SPI device is not a QSPI device */ |
| 612 | return -1; |
| 613 | } |
| 614 | |
| 615 | switch (command) { /* check for dummies */ |
| 616 | case READ: /* no dummy bytes/cycles */ |
| 617 | case PP: |
| 618 | case DPP: |
| 619 | case QPP: |
| 620 | case READ_4: |
| 621 | case PP_4: |
| 622 | case QPP_4: |
| 623 | return 0; |
| 624 | case FAST_READ: |
| 625 | case FAST_READ_4: |
| 626 | return 1; |
| 627 | case DOR: |
| 628 | case DOR_4: |
| 629 | case QOR: |
| 630 | case QOR_4: |
| 631 | return 1; |
| 632 | case DIOR: |
| 633 | case DIOR_4: |
| 634 | return 2; |
| 635 | case QIOR: |
| 636 | case QIOR_4: |
| 637 | return 4; |
| 638 | default: |
| 639 | return -1; |
| 640 | } |
| 641 | } |
| 642 | |
| 643 | static inline uint8_t get_addr_length(XilinxSPIPS *s, uint8_t cmd) |
| 644 | { |
| 645 | switch (cmd) { |
| 646 | case PP_4: |
| 647 | case QPP_4: |
| 648 | case READ_4: |
| 649 | case QIOR_4: |
| 650 | case FAST_READ_4: |
| 651 | case DOR_4: |
| 652 | case QOR_4: |
| 653 | case DIOR_4: |
| 654 | return 4; |
| 655 | default: |
| 656 | return (s->regs[R_CMND] & R_CMND_EXT_ADD) ? 4 : 3; |
| 657 | } |
| 658 | } |
| 659 | |
| 660 | static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) |
| 661 | { |
| 662 | int debug_level = 0; |
| 663 | XilinxQSPIPS *q = (XilinxQSPIPS *) object_dynamic_cast(OBJECT(s), |
| 664 | TYPE_XILINX_QSPIPS); |
| 665 | |
| 666 | for (;;) { |
| 667 | int i; |
| 668 | uint8_t tx = 0; |
| 669 | uint8_t tx_rx[MAX_NUM_BUSSES] = { 0 }; |
| 670 | uint8_t addr_length; |
| 671 | |
| 672 | if (fifo8_is_empty(&s->tx_fifo)) { |
| 673 | xilinx_spips_update_ixr(s); |
| 674 | return; |
| 675 | } else if (s->snoop_state == SNOOP_STRIPING || |
| 676 | s->snoop_state == SNOOP_NONE) { |
| 677 | for (i = 0; i < num_effective_busses(s); ++i) { |
| 678 | if (!fifo8_is_empty(&s->tx_fifo)) { |
| 679 | tx_rx[i] = fifo8_pop(&s->tx_fifo); |
| 680 | } |
| 681 | } |
| 682 | stripe8(tx_rx, num_effective_busses(s), false); |
| 683 | } else if (s->snoop_state >= SNOOP_ADDR) { |
| 684 | tx = fifo8_pop(&s->tx_fifo); |
| 685 | for (i = 0; i < num_effective_busses(s); ++i) { |
| 686 | tx_rx[i] = tx; |
| 687 | } |
| 688 | } else { |
| 689 | tx = fifo8_pop(&s->tx_fifo); |
| 690 | for (i = 0; i < num_effective_busses(s); ++i) { |
| 691 | tx_rx[i] = tx; |
| 692 | } |
| 693 | } |
| 694 | |
| 695 | for (i = 0; i < num_effective_busses(s); ++i) { |
| 696 | int bus = num_effective_busses(s) - 1 - i; |
| 697 | |
| 698 | DB_PRINT_L(debug_level, "tx = %02x\n", tx_rx[i]); |
| 699 | tx_rx[i] = ssi_transfer(s->spi[bus], (uint32_t)tx_rx[i]); |
| 700 | DB_PRINT_L(debug_level, "rx = %02x\n", tx_rx[i]); |
| 701 | } |
| 702 | |
| 703 | if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) { |
| 704 | DB_PRINT_L(debug_level, "dircarding drained rx byte\n"); |
| 705 | /* Do nothing */ |
| 706 | } else if (s->rx_discard) { |
| 707 | DB_PRINT_L(debug_level, "dircarding discarded rx byte\n"); |
| 708 | s->rx_discard -= 8 / s->link_state; |
| 709 | } else if (fifo8_is_full(&s->rx_fifo)) { |
| 710 | s->regs[R_INTR_STATUS] |= IXR_RX_FIFO_OVERFLOW; |
| 711 | DB_PRINT_L(0, "rx FIFO overflow"); |
| 712 | } else if (s->snoop_state == SNOOP_STRIPING) { |
| 713 | stripe8(tx_rx, num_effective_busses(s), true); |
| 714 | for (i = 0; i < num_effective_busses(s); ++i) { |
| 715 | fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[i]); |
| 716 | DB_PRINT_L(debug_level, "pushing striped rx byte\n"); |
| 717 | } |
| 718 | } else { |
| 719 | DB_PRINT_L(debug_level, "pushing unstriped rx byte\n"); |
| 720 | fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[0]); |
| 721 | } |
| 722 | |
| 723 | if (s->link_state_next_when) { |
| 724 | s->link_state_next_when--; |
| 725 | if (!s->link_state_next_when) { |
| 726 | s->link_state = s->link_state_next; |
| 727 | } |
| 728 | } |
| 729 | |
| 730 | DB_PRINT_L(debug_level, "initial snoop state: %x\n", |
| 731 | (unsigned)s->snoop_state); |
| 732 | switch (s->snoop_state) { |
| 733 | case (SNOOP_CHECKING): |
| 734 | /* Store the count of dummy bytes in the txfifo */ |
| 735 | s->cmd_dummy_bytes = xilinx_spips_num_dummy_bytes(q, tx); |
| 736 | addr_length = get_addr_length(s, tx); |
| 737 | if (s->cmd_dummy_bytes < 0) { |
| 738 | s->snoop_state = SNOOP_NONE; |
| 739 | } else { |
| 740 | s->snoop_state = SNOOP_ADDR + addr_length - 1; |
| 741 | } |
| 742 | switch (tx) { |
| 743 | case DPP: |
| 744 | case DOR: |
| 745 | case DOR_4: |
| 746 | s->link_state_next = 2; |
| 747 | s->link_state_next_when = addr_length + s->cmd_dummy_bytes; |
| 748 | break; |
| 749 | case QPP: |
| 750 | case QPP_4: |
| 751 | case QOR: |
| 752 | case QOR_4: |
| 753 | s->link_state_next = 4; |
| 754 | s->link_state_next_when = addr_length + s->cmd_dummy_bytes; |
| 755 | break; |
| 756 | case DIOR: |
| 757 | case DIOR_4: |
| 758 | s->link_state = 2; |
| 759 | break; |
| 760 | case QIOR: |
| 761 | case QIOR_4: |
| 762 | s->link_state = 4; |
| 763 | break; |
| 764 | } |
| 765 | break; |
| 766 | case (SNOOP_ADDR): |
| 767 | /* |
| 768 | * Address has been transmitted, transmit dummy cycles now if needed |
| 769 | */ |
| 770 | if (s->cmd_dummy_bytes < 0) { |
| 771 | s->snoop_state = SNOOP_NONE; |
| 772 | } else { |
| 773 | s->snoop_state = s->cmd_dummy_bytes; |
| 774 | } |
| 775 | break; |
| 776 | case (SNOOP_STRIPING): |
| 777 | case (SNOOP_NONE): |
| 778 | /* Once we hit the boring stuff - squelch debug noise */ |
| 779 | if (!debug_level) { |
| 780 | DB_PRINT_L(0, "squelching debug info ....\n"); |
| 781 | debug_level = 1; |
| 782 | } |
| 783 | break; |
| 784 | default: |
| 785 | s->snoop_state--; |
| 786 | } |
| 787 | DB_PRINT_L(debug_level, "final snoop state: %x\n", |
| 788 | (unsigned)s->snoop_state); |
| 789 | } |
| 790 | } |
| 791 | |
| 792 | static inline void tx_data_bytes(Fifo8 *fifo, uint32_t value, int num, bool be) |
| 793 | { |
| 794 | int i; |
| 795 | for (i = 0; i < num && !fifo8_is_full(fifo); ++i) { |
| 796 | if (be) { |
| 797 | fifo8_push(fifo, (uint8_t)(value >> 24)); |
| 798 | value <<= 8; |
| 799 | } else { |
| 800 | fifo8_push(fifo, (uint8_t)value); |
| 801 | value >>= 8; |
| 802 | } |
| 803 | } |
| 804 | } |
| 805 | |
| 806 | static void xilinx_spips_check_zero_pump(XilinxSPIPS *s) |
| 807 | { |
| 808 | if (!s->regs[R_TRANSFER_SIZE]) { |
| 809 | return; |
| 810 | } |
| 811 | if (!fifo8_is_empty(&s->tx_fifo) && s->regs[R_CMND] & R_CMND_PUSH_WAIT) { |
| 812 | return; |
| 813 | } |
| 814 | /* |
| 815 | * The zero pump must never fill tx fifo such that rx overflow is |
| 816 | * possible |
| 817 | */ |
| 818 | while (s->regs[R_TRANSFER_SIZE] && |
| 819 | s->rx_fifo.num + s->tx_fifo.num < RXFF_A_Q - 3) { |
| 820 | /* endianness just doesn't matter when zero pumping */ |
| 821 | tx_data_bytes(&s->tx_fifo, 0, 4, false); |
| 822 | s->regs[R_TRANSFER_SIZE] &= ~0x03ull; |
| 823 | s->regs[R_TRANSFER_SIZE] -= 4; |
| 824 | } |
| 825 | } |
| 826 | |
| 827 | static void xilinx_spips_check_flush(XilinxSPIPS *s) |
| 828 | { |
| 829 | if (s->man_start_com || |
| 830 | (!fifo8_is_empty(&s->tx_fifo) && |
| 831 | !(s->regs[R_CONFIG] & MAN_START_EN))) { |
| 832 | xilinx_spips_check_zero_pump(s); |
| 833 | xilinx_spips_flush_txfifo(s); |
| 834 | } |
| 835 | if (fifo8_is_empty(&s->tx_fifo) && !s->regs[R_TRANSFER_SIZE]) { |
| 836 | s->man_start_com = false; |
| 837 | } |
| 838 | xilinx_spips_update_ixr(s); |
| 839 | } |
| 840 | |
| 841 | static void xlnx_zynqmp_qspips_check_flush(XlnxZynqMPQSPIPS *s) |
| 842 | { |
| 843 | bool gqspi_has_work = s->regs[R_GQSPI_DATA_STS] || |
| 844 | !fifo32_is_empty(&s->fifo_g); |
| 845 | |
| 846 | if (ARRAY_FIELD_EX32(s->regs, GQSPI_SELECT, GENERIC_QSPI_EN)) { |
| 847 | if (s->man_start_com_g || (gqspi_has_work && |
| 848 | !ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, GEN_FIFO_START_MODE))) { |
| 849 | xlnx_zynqmp_qspips_flush_fifo_g(s); |
| 850 | } |
| 851 | } else { |
| 852 | xilinx_spips_check_flush(XILINX_SPIPS(s)); |
| 853 | } |
| 854 | if (!gqspi_has_work) { |
| 855 | s->man_start_com_g = false; |
| 856 | } |
| 857 | xlnx_zynqmp_qspips_update_ixr(s); |
| 858 | } |
| 859 | |
| 860 | static inline int rx_data_bytes(Fifo8 *fifo, uint8_t *value, int max) |
| 861 | { |
| 862 | int i; |
| 863 | |
| 864 | for (i = 0; i < max && !fifo8_is_empty(fifo); ++i) { |
| 865 | value[i] = fifo8_pop(fifo); |
| 866 | } |
| 867 | return max - i; |
| 868 | } |
| 869 | |
| 870 | static const void *pop_buf(Fifo8 *fifo, uint32_t max, uint32_t *num) |
| 871 | { |
| 872 | void *ret; |
| 873 | |
| 874 | if (max == 0 || max > fifo->num) { |
| 875 | abort(); |
| 876 | } |
| 877 | *num = MIN(fifo->capacity - fifo->head, max); |
| 878 | ret = &fifo->data[fifo->head]; |
| 879 | fifo->head += *num; |
| 880 | fifo->head %= fifo->capacity; |
| 881 | fifo->num -= *num; |
| 882 | return ret; |
| 883 | } |
| 884 | |
| 885 | static void xlnx_zynqmp_qspips_notify(void *opaque) |
| 886 | { |
| 887 | XlnxZynqMPQSPIPS *rq = XLNX_ZYNQMP_QSPIPS(opaque); |
| 888 | XilinxSPIPS *s = XILINX_SPIPS(rq); |
| 889 | Fifo8 *recv_fifo; |
| 890 | |
| 891 | if (ARRAY_FIELD_EX32(rq->regs, GQSPI_SELECT, GENERIC_QSPI_EN)) { |
| 892 | if (!(ARRAY_FIELD_EX32(rq->regs, GQSPI_CNFG, MODE_EN) == 2)) { |
| 893 | return; |
| 894 | } |
| 895 | recv_fifo = &rq->rx_fifo_g; |
| 896 | } else { |
| 897 | if (!(s->regs[R_CMND] & R_CMND_DMA_EN)) { |
| 898 | return; |
| 899 | } |
| 900 | recv_fifo = &s->rx_fifo; |
| 901 | } |
| 902 | while (recv_fifo->num >= 4 |
| 903 | && stream_can_push(rq->dma, xlnx_zynqmp_qspips_notify, rq)) |
| 904 | { |
| 905 | size_t ret; |
| 906 | uint32_t num; |
| 907 | const void *rxd; |
| 908 | int len; |
| 909 | |
| 910 | len = recv_fifo->num >= rq->dma_burst_size ? rq->dma_burst_size : |
| 911 | recv_fifo->num; |
| 912 | rxd = pop_buf(recv_fifo, len, &num); |
| 913 | |
| 914 | memcpy(rq->dma_buf, rxd, num); |
| 915 | |
| 916 | ret = stream_push(rq->dma, rq->dma_buf, num, false); |
| 917 | assert(ret == num); |
| 918 | xlnx_zynqmp_qspips_check_flush(rq); |
| 919 | } |
| 920 | } |
| 921 | |
| 922 | static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, |
| 923 | unsigned size) |
| 924 | { |
| 925 | XilinxSPIPS *s = opaque; |
| 926 | uint32_t mask = ~0; |
| 927 | uint32_t ret; |
| 928 | uint8_t rx_buf[4]; |
| 929 | int shortfall; |
| 930 | |
| 931 | addr >>= 2; |
| 932 | switch (addr) { |
| 933 | case R_CONFIG: |
| 934 | mask = ~(R_CONFIG_RSVD | MAN_START_COM); |
| 935 | break; |
| 936 | case R_INTR_STATUS: |
| 937 | ret = s->regs[addr] & IXR_ALL; |
| 938 | s->regs[addr] = 0; |
| 939 | DB_PRINT_L(0, "addr=" HWADDR_FMT_plx " = %x\n", addr * 4, ret); |
| 940 | xilinx_spips_update_ixr(s); |
| 941 | return ret; |
| 942 | case R_INTR_MASK: |
| 943 | mask = IXR_ALL; |
| 944 | break; |
| 945 | case R_EN: |
| 946 | mask = 0x1; |
| 947 | break; |
| 948 | case R_SLAVE_IDLE_COUNT: |
| 949 | mask = 0xFF; |
| 950 | break; |
| 951 | case R_MOD_ID: |
| 952 | mask = 0x01FFFFFF; |
| 953 | break; |
| 954 | case R_INTR_EN: |
| 955 | case R_INTR_DIS: |
| 956 | case R_TX_DATA: |
| 957 | mask = 0; |
| 958 | break; |
| 959 | case R_RX_DATA: |
| 960 | memset(rx_buf, 0, sizeof(rx_buf)); |
| 961 | shortfall = rx_data_bytes(&s->rx_fifo, rx_buf, s->num_txrx_bytes); |
| 962 | ret = s->regs[R_CONFIG] & R_CONFIG_ENDIAN ? |
| 963 | cpu_to_be32(*(uint32_t *)rx_buf) : |
| 964 | cpu_to_le32(*(uint32_t *)rx_buf); |
| 965 | if (!(s->regs[R_CONFIG] & R_CONFIG_ENDIAN)) { |
| 966 | ret <<= 8 * shortfall; |
| 967 | } |
| 968 | DB_PRINT_L(0, "addr=" HWADDR_FMT_plx " = %x\n", addr * 4, ret); |
| 969 | xilinx_spips_check_flush(s); |
| 970 | xilinx_spips_update_ixr(s); |
| 971 | return ret; |
| 972 | } |
| 973 | DB_PRINT_L(0, "addr=" HWADDR_FMT_plx " = %x\n", addr * 4, |
| 974 | s->regs[addr] & mask); |
| 975 | return s->regs[addr] & mask; |
| 976 | |
| 977 | } |
| 978 | |
| 979 | static uint64_t xlnx_zynqmp_qspips_read(void *opaque, |
| 980 | hwaddr addr, unsigned size) |
| 981 | { |
| 982 | XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(opaque); |
| 983 | uint32_t reg = addr / 4; |
| 984 | uint32_t ret; |
| 985 | uint8_t rx_buf[4]; |
| 986 | int shortfall; |
| 987 | |
| 988 | if (reg <= R_MOD_ID) { |
| 989 | return xilinx_spips_read(opaque, addr, size); |
| 990 | } else { |
| 991 | switch (reg) { |
| 992 | case R_GQSPI_RXD: |
| 993 | if (fifo8_is_empty(&s->rx_fifo_g)) { |
| 994 | qemu_log_mask(LOG_GUEST_ERROR, |
| 995 | "Read from empty GQSPI RX FIFO\n"); |
| 996 | return 0; |
| 997 | } |
| 998 | memset(rx_buf, 0, sizeof(rx_buf)); |
| 999 | shortfall = rx_data_bytes(&s->rx_fifo_g, rx_buf, |
| 1000 | XILINX_SPIPS(s)->num_txrx_bytes); |
| 1001 | ret = ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN) ? |
| 1002 | cpu_to_be32(*(uint32_t *)rx_buf) : |
| 1003 | cpu_to_le32(*(uint32_t *)rx_buf); |
| 1004 | if (!ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN)) { |
| 1005 | ret <<= 8 * shortfall; |
| 1006 | } |
| 1007 | xlnx_zynqmp_qspips_check_flush(s); |
| 1008 | xlnx_zynqmp_qspips_update_ixr(s); |
| 1009 | return ret; |
| 1010 | default: |
| 1011 | return s->regs[reg]; |
| 1012 | } |
| 1013 | } |
| 1014 | } |
| 1015 | |
| 1016 | static void xilinx_spips_write(void *opaque, hwaddr addr, |
| 1017 | uint64_t value, unsigned size) |
| 1018 | { |
| 1019 | int mask = ~0; |
| 1020 | XilinxSPIPS *s = opaque; |
| 1021 | bool try_flush = true; |
| 1022 | |
| 1023 | DB_PRINT_L(0, "addr=" HWADDR_FMT_plx " = %x\n", addr, (unsigned)value); |
| 1024 | addr >>= 2; |
| 1025 | assert(addr < XLNX_SPIPS_R_MAX); |
| 1026 | |
| 1027 | switch (addr) { |
| 1028 | case R_CONFIG: |
| 1029 | mask = ~(R_CONFIG_RSVD | MAN_START_COM); |
| 1030 | if ((value & MAN_START_COM) && (s->regs[R_CONFIG] & MAN_START_EN)) { |
| 1031 | s->man_start_com = true; |
| 1032 | } |
| 1033 | break; |
| 1034 | case R_INTR_STATUS: |
| 1035 | mask = IXR_ALL; |
| 1036 | s->regs[R_INTR_STATUS] &= ~(mask & value); |
| 1037 | goto no_reg_update; |
| 1038 | case R_INTR_DIS: |
| 1039 | mask = IXR_ALL; |
| 1040 | s->regs[R_INTR_MASK] &= ~(mask & value); |
| 1041 | goto no_reg_update; |
| 1042 | case R_INTR_EN: |
| 1043 | mask = IXR_ALL; |
| 1044 | s->regs[R_INTR_MASK] |= mask & value; |
| 1045 | goto no_reg_update; |
| 1046 | case R_EN: |
| 1047 | mask = 0x1; |
| 1048 | break; |
| 1049 | case R_SLAVE_IDLE_COUNT: |
| 1050 | mask = 0xFF; |
| 1051 | break; |
| 1052 | case R_RX_DATA: |
| 1053 | case R_INTR_MASK: |
| 1054 | case R_MOD_ID: |
| 1055 | mask = 0; |
| 1056 | break; |
| 1057 | case R_TX_DATA: |
| 1058 | tx_data_bytes(&s->tx_fifo, (uint32_t)value, s->num_txrx_bytes, |
| 1059 | s->regs[R_CONFIG] & R_CONFIG_ENDIAN); |
| 1060 | goto no_reg_update; |
| 1061 | case R_TXD1: |
| 1062 | tx_data_bytes(&s->tx_fifo, (uint32_t)value, 1, |
| 1063 | s->regs[R_CONFIG] & R_CONFIG_ENDIAN); |
| 1064 | goto no_reg_update; |
| 1065 | case R_TXD2: |
| 1066 | tx_data_bytes(&s->tx_fifo, (uint32_t)value, 2, |
| 1067 | s->regs[R_CONFIG] & R_CONFIG_ENDIAN); |
| 1068 | goto no_reg_update; |
| 1069 | case R_TXD3: |
| 1070 | tx_data_bytes(&s->tx_fifo, (uint32_t)value, 3, |
| 1071 | s->regs[R_CONFIG] & R_CONFIG_ENDIAN); |
| 1072 | goto no_reg_update; |
| 1073 | /* Skip SPI bus update for below registers writes */ |
| 1074 | case R_GPIO: |
| 1075 | case R_LPBK_DLY_ADJ: |
| 1076 | case R_IOU_TAPDLY_BYPASS: |
| 1077 | case R_DUMMY_CYCLE_EN: |
| 1078 | case R_ECO: |
| 1079 | try_flush = false; |
| 1080 | break; |
| 1081 | } |
| 1082 | s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask); |
| 1083 | no_reg_update: |
| 1084 | if (try_flush) { |
| 1085 | xilinx_spips_update_cs_lines(s); |
| 1086 | xilinx_spips_check_flush(s); |
| 1087 | xilinx_spips_update_cs_lines(s); |
| 1088 | xilinx_spips_update_ixr(s); |
| 1089 | } |
| 1090 | } |
| 1091 | |
| 1092 | static const MemoryRegionOps spips_ops = { |
| 1093 | .read = xilinx_spips_read, |
| 1094 | .write = xilinx_spips_write, |
| 1095 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 1096 | }; |
| 1097 | |
| 1098 | static void xilinx_qspips_invalidate_mmio_ptr(XilinxQSPIPS *q) |
| 1099 | { |
| 1100 | q->lqspi_cached_addr = ~0ULL; |
| 1101 | } |
| 1102 | |
| 1103 | static void xilinx_qspips_write(void *opaque, hwaddr addr, |
| 1104 | uint64_t value, unsigned size) |
| 1105 | { |
| 1106 | XilinxQSPIPS *q = XILINX_QSPIPS(opaque); |
| 1107 | XilinxSPIPS *s = XILINX_SPIPS(opaque); |
| 1108 | |
| 1109 | xilinx_spips_write(opaque, addr, value, size); |
| 1110 | addr >>= 2; |
| 1111 | |
| 1112 | if (addr == R_LQSPI_CFG) { |
| 1113 | xilinx_qspips_invalidate_mmio_ptr(q); |
| 1114 | } |
| 1115 | if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) { |
| 1116 | fifo8_reset(&s->rx_fifo); |
| 1117 | } |
| 1118 | } |
| 1119 | |
| 1120 | static void xlnx_zynqmp_qspips_write(void *opaque, hwaddr addr, |
| 1121 | uint64_t value, unsigned size) |
| 1122 | { |
| 1123 | XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(opaque); |
| 1124 | uint32_t reg = addr / 4; |
| 1125 | |
| 1126 | if (reg <= R_MOD_ID) { |
| 1127 | xilinx_qspips_write(opaque, addr, value, size); |
| 1128 | } else { |
| 1129 | switch (reg) { |
| 1130 | case R_GQSPI_CNFG: |
| 1131 | if (FIELD_EX32(value, GQSPI_CNFG, GEN_FIFO_START) && |
| 1132 | ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, GEN_FIFO_START_MODE)) { |
| 1133 | s->man_start_com_g = true; |
| 1134 | } |
| 1135 | s->regs[reg] = value & ~(R_GQSPI_CNFG_GEN_FIFO_START_MASK); |
| 1136 | break; |
| 1137 | case R_GQSPI_GEN_FIFO: |
| 1138 | if (!fifo32_is_full(&s->fifo_g)) { |
| 1139 | fifo32_push(&s->fifo_g, value); |
| 1140 | } |
| 1141 | break; |
| 1142 | case R_GQSPI_TXD: |
| 1143 | tx_data_bytes(&s->tx_fifo_g, (uint32_t)value, 4, |
| 1144 | ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN)); |
| 1145 | break; |
| 1146 | case R_GQSPI_FIFO_CTRL: |
| 1147 | if (FIELD_EX32(value, GQSPI_FIFO_CTRL, GENERIC_FIFO_RESET)) { |
| 1148 | fifo32_reset(&s->fifo_g); |
| 1149 | } |
| 1150 | if (FIELD_EX32(value, GQSPI_FIFO_CTRL, TX_FIFO_RESET)) { |
| 1151 | fifo8_reset(&s->tx_fifo_g); |
| 1152 | } |
| 1153 | if (FIELD_EX32(value, GQSPI_FIFO_CTRL, RX_FIFO_RESET)) { |
| 1154 | fifo8_reset(&s->rx_fifo_g); |
| 1155 | } |
| 1156 | break; |
| 1157 | case R_GQSPI_IDR: |
| 1158 | s->regs[R_GQSPI_IMR] |= value; |
| 1159 | break; |
| 1160 | case R_GQSPI_IER: |
| 1161 | s->regs[R_GQSPI_IMR] &= ~value; |
| 1162 | break; |
| 1163 | case R_GQSPI_ISR: |
| 1164 | s->regs[R_GQSPI_ISR] &= ~value; |
| 1165 | break; |
| 1166 | case R_GQSPI_IMR: |
| 1167 | case R_GQSPI_RXD: |
| 1168 | case R_GQSPI_GF_SNAPSHOT: |
| 1169 | case R_GQSPI_MOD_ID: |
| 1170 | break; |
| 1171 | default: |
| 1172 | s->regs[reg] = value; |
| 1173 | break; |
| 1174 | } |
| 1175 | xlnx_zynqmp_qspips_update_cs_lines(s); |
| 1176 | xlnx_zynqmp_qspips_check_flush(s); |
| 1177 | xlnx_zynqmp_qspips_update_cs_lines(s); |
| 1178 | xlnx_zynqmp_qspips_update_ixr(s); |
| 1179 | } |
| 1180 | xlnx_zynqmp_qspips_notify(s); |
| 1181 | } |
| 1182 | |
| 1183 | static const MemoryRegionOps qspips_ops = { |
| 1184 | .read = xilinx_spips_read, |
| 1185 | .write = xilinx_qspips_write, |
| 1186 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 1187 | }; |
| 1188 | |
| 1189 | static const MemoryRegionOps xlnx_zynqmp_qspips_ops = { |
| 1190 | .read = xlnx_zynqmp_qspips_read, |
| 1191 | .write = xlnx_zynqmp_qspips_write, |
| 1192 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 1193 | }; |
| 1194 | |
| 1195 | #define LQSPI_CACHE_SIZE 1024 |
| 1196 | |
| 1197 | static void lqspi_load_cache(void *opaque, hwaddr addr) |
| 1198 | { |
| 1199 | XilinxQSPIPS *q = opaque; |
| 1200 | XilinxSPIPS *s = opaque; |
| 1201 | int i; |
| 1202 | int dummy_bytes; |
| 1203 | int flash_addr = ((addr & ~(LQSPI_CACHE_SIZE - 1)) |
| 1204 | / num_effective_busses(s)); |
| 1205 | int peripheral = flash_addr >> LQSPI_ADDRESS_BITS; |
| 1206 | int cache_entry = 0; |
| 1207 | uint32_t u_page_save = s->regs[R_LQSPI_STS] & ~LQSPI_CFG_U_PAGE; |
| 1208 | uint8_t command; |
| 1209 | |
| 1210 | if (addr < q->lqspi_cached_addr || |
| 1211 | addr > q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { |
| 1212 | xilinx_qspips_invalidate_mmio_ptr(q); |
| 1213 | s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE; |
| 1214 | s->regs[R_LQSPI_STS] |= peripheral ? LQSPI_CFG_U_PAGE : 0; |
| 1215 | |
| 1216 | DB_PRINT_L(0, "config reg status: %08x\n", s->regs[R_LQSPI_CFG]); |
| 1217 | |
| 1218 | fifo8_reset(&s->tx_fifo); |
| 1219 | fifo8_reset(&s->rx_fifo); |
| 1220 | |
| 1221 | /* instruction */ |
| 1222 | command = s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE; |
| 1223 | DB_PRINT_L(0, "pushing read instruction: %02x\n", |
| 1224 | (unsigned)command); |
| 1225 | fifo8_push(&s->tx_fifo, command); |
| 1226 | /* read address */ |
| 1227 | DB_PRINT_L(0, "pushing read address %06x\n", flash_addr); |
| 1228 | if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_ADDR4) { |
| 1229 | fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 24)); |
| 1230 | } |
| 1231 | fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 16)); |
| 1232 | fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 8)); |
| 1233 | fifo8_push(&s->tx_fifo, (uint8_t)flash_addr); |
| 1234 | /* mode bits */ |
| 1235 | dummy_bytes = xilinx_spips_num_dummy_bytes(q, command); |
| 1236 | if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_MODE_EN) { |
| 1237 | fifo8_push(&s->tx_fifo, extract32(s->regs[R_LQSPI_CFG], |
| 1238 | LQSPI_CFG_MODE_SHIFT, |
| 1239 | LQSPI_CFG_MODE_WIDTH)); |
| 1240 | if (dummy_bytes > 0) { |
| 1241 | dummy_bytes--; |
| 1242 | } |
| 1243 | } |
| 1244 | if (dummy_bytes < 0) { |
| 1245 | dummy_bytes = extract32(s->regs[R_LQSPI_CFG], |
| 1246 | LQSPI_CFG_DUMMY_SHIFT, |
| 1247 | LQSPI_CFG_DUMMY_WIDTH); |
| 1248 | } |
| 1249 | /* dummy bytes */ |
| 1250 | for (i = 0; i < dummy_bytes; ++i) { |
| 1251 | DB_PRINT_L(0, "pushing dummy byte\n"); |
| 1252 | fifo8_push(&s->tx_fifo, 0); |
| 1253 | } |
| 1254 | xilinx_spips_update_cs_lines(s); |
| 1255 | xilinx_spips_flush_txfifo(s); |
| 1256 | fifo8_reset(&s->rx_fifo); |
| 1257 | |
| 1258 | DB_PRINT_L(0, "starting QSPI data read\n"); |
| 1259 | |
| 1260 | while (cache_entry < LQSPI_CACHE_SIZE) { |
| 1261 | for (i = 0; i < 64; ++i) { |
| 1262 | tx_data_bytes(&s->tx_fifo, 0, 1, false); |
| 1263 | } |
| 1264 | xilinx_spips_flush_txfifo(s); |
| 1265 | for (i = 0; i < 64; ++i) { |
| 1266 | rx_data_bytes(&s->rx_fifo, &q->lqspi_buf[cache_entry++], 1); |
| 1267 | } |
| 1268 | } |
| 1269 | |
| 1270 | s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE; |
| 1271 | s->regs[R_LQSPI_STS] |= u_page_save; |
| 1272 | xilinx_spips_update_cs_lines(s); |
| 1273 | |
| 1274 | q->lqspi_cached_addr = flash_addr * num_effective_busses(s); |
| 1275 | } |
| 1276 | } |
| 1277 | |
| 1278 | static MemTxResult lqspi_read(void *opaque, hwaddr addr, uint64_t *value, |
| 1279 | unsigned size, MemTxAttrs attrs) |
| 1280 | { |
| 1281 | XilinxQSPIPS *q = XILINX_QSPIPS(opaque); |
| 1282 | |
| 1283 | if (addr >= q->lqspi_cached_addr && |
| 1284 | addr <= q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { |
| 1285 | uint8_t *retp = &q->lqspi_buf[addr - q->lqspi_cached_addr]; |
| 1286 | *value = cpu_to_le32(*(uint32_t *)retp); |
| 1287 | DB_PRINT_L(1, "addr: %08" HWADDR_PRIx ", data: %08" PRIx64 "\n", |
| 1288 | addr, *value); |
| 1289 | return MEMTX_OK; |
| 1290 | } |
| 1291 | |
| 1292 | lqspi_load_cache(opaque, addr); |
| 1293 | return lqspi_read(opaque, addr, value, size, attrs); |
| 1294 | } |
| 1295 | |
| 1296 | static MemTxResult lqspi_write(void *opaque, hwaddr offset, uint64_t value, |
| 1297 | unsigned size, MemTxAttrs attrs) |
| 1298 | { |
| 1299 | /* |
| 1300 | * From UG1085, Chapter 24 (Quad-SPI controllers): |
| 1301 | * - Writes are ignored |
| 1302 | * - AXI writes generate an external AXI slave error (SLVERR) |
| 1303 | */ |
| 1304 | qemu_log_mask(LOG_GUEST_ERROR, "%s Unexpected %u-bit access to 0x%" PRIx64 |
| 1305 | " (value: 0x%" PRIx64 "\n", |
| 1306 | __func__, size << 3, offset, value); |
| 1307 | |
| 1308 | return MEMTX_ERROR; |
| 1309 | } |
| 1310 | |
| 1311 | static const MemoryRegionOps lqspi_ops = { |
| 1312 | .read_with_attrs = lqspi_read, |
| 1313 | .write_with_attrs = lqspi_write, |
| 1314 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 1315 | .impl = { |
| 1316 | .min_access_size = 4, |
| 1317 | .max_access_size = 4, |
| 1318 | }, |
| 1319 | .valid = { |
| 1320 | .min_access_size = 1, |
| 1321 | .max_access_size = 4 |
| 1322 | } |
| 1323 | }; |
| 1324 | |
| 1325 | static void xilinx_spips_realize(DeviceState *dev, Error **errp) |
| 1326 | { |
| 1327 | XilinxSPIPS *s = XILINX_SPIPS(dev); |
| 1328 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
| 1329 | XilinxSPIPSClass *xsc = XILINX_SPIPS_GET_CLASS(s); |
| 1330 | int i; |
| 1331 | |
| 1332 | DB_PRINT_L(0, "realized spips\n"); |
| 1333 | |
| 1334 | if (s->num_busses > MAX_NUM_BUSSES) { |
| 1335 | error_setg(errp, |
| 1336 | "requested number of SPI busses %u exceeds maximum %d", |
| 1337 | s->num_busses, MAX_NUM_BUSSES); |
| 1338 | return; |
| 1339 | } |
| 1340 | if (s->num_busses < MIN_NUM_BUSSES) { |
| 1341 | error_setg(errp, |
| 1342 | "requested number of SPI busses %u is below minimum %d", |
| 1343 | s->num_busses, MIN_NUM_BUSSES); |
| 1344 | return; |
| 1345 | } |
| 1346 | |
| 1347 | s->spi = g_new(SSIBus *, s->num_busses); |
| 1348 | for (i = 0; i < s->num_busses; ++i) { |
| 1349 | char bus_name[16]; |
| 1350 | snprintf(bus_name, 16, "spi%d", i); |
| 1351 | s->spi[i] = ssi_create_bus(dev, bus_name); |
| 1352 | } |
| 1353 | |
| 1354 | s->cs_lines = g_new0(qemu_irq, s->num_cs * s->num_busses); |
| 1355 | s->cs_lines_state = g_new0(bool, s->num_cs * s->num_busses); |
| 1356 | |
| 1357 | sysbus_init_irq(sbd, &s->irq); |
| 1358 | for (i = 0; i < s->num_cs * s->num_busses; ++i) { |
| 1359 | sysbus_init_irq(sbd, &s->cs_lines[i]); |
| 1360 | } |
| 1361 | |
| 1362 | memory_region_init_io(&s->iomem, OBJECT(s), xsc->reg_ops, s, |
| 1363 | "spi", xsc->reg_size); |
| 1364 | sysbus_init_mmio(sbd, &s->iomem); |
| 1365 | |
| 1366 | s->irqline = -1; |
| 1367 | |
| 1368 | fifo8_create(&s->rx_fifo, xsc->rx_fifo_size); |
| 1369 | fifo8_create(&s->tx_fifo, xsc->tx_fifo_size); |
| 1370 | } |
| 1371 | |
| 1372 | static void xilinx_qspips_realize(DeviceState *dev, Error **errp) |
| 1373 | { |
| 1374 | XilinxSPIPS *s = XILINX_SPIPS(dev); |
| 1375 | XilinxQSPIPS *q = XILINX_QSPIPS(dev); |
| 1376 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
| 1377 | |
| 1378 | DB_PRINT_L(0, "realized qspips\n"); |
| 1379 | |
| 1380 | s->num_busses = 2; |
| 1381 | s->num_cs = 2; |
| 1382 | s->num_txrx_bytes = 4; |
| 1383 | |
| 1384 | xilinx_spips_realize(dev, errp); |
| 1385 | memory_region_init_io(&s->mmlqspi, OBJECT(s), &lqspi_ops, s, "lqspi", |
| 1386 | (1 << LQSPI_ADDRESS_BITS) * 2); |
| 1387 | sysbus_init_mmio(sbd, &s->mmlqspi); |
| 1388 | |
| 1389 | q->lqspi_cached_addr = ~0ULL; |
| 1390 | } |
| 1391 | |
| 1392 | static void xlnx_zynqmp_qspips_realize(DeviceState *dev, Error **errp) |
| 1393 | { |
| 1394 | XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(dev); |
| 1395 | XilinxSPIPSClass *xsc = XILINX_SPIPS_GET_CLASS(s); |
| 1396 | |
| 1397 | if (s->dma_burst_size > QSPI_DMA_MAX_BURST_SIZE) { |
| 1398 | error_setg(errp, |
| 1399 | "qspi dma burst size %u exceeds maximum limit %d", |
| 1400 | s->dma_burst_size, QSPI_DMA_MAX_BURST_SIZE); |
| 1401 | return; |
| 1402 | } |
| 1403 | xilinx_qspips_realize(dev, errp); |
| 1404 | fifo8_create(&s->rx_fifo_g, xsc->rx_fifo_size); |
| 1405 | fifo8_create(&s->tx_fifo_g, xsc->tx_fifo_size); |
| 1406 | fifo32_create(&s->fifo_g, 32); |
| 1407 | } |
| 1408 | |
| 1409 | static void xlnx_zynqmp_qspips_init(Object *obj) |
| 1410 | { |
| 1411 | XlnxZynqMPQSPIPS *rq = XLNX_ZYNQMP_QSPIPS(obj); |
| 1412 | |
| 1413 | object_property_add_link(obj, "stream-connected-dma", TYPE_STREAM_SINK, |
| 1414 | (Object **)&rq->dma, |
| 1415 | object_property_allow_set_link, |
| 1416 | OBJ_PROP_LINK_STRONG); |
| 1417 | } |
| 1418 | |
| 1419 | static int xilinx_spips_post_load(void *opaque, int version_id) |
| 1420 | { |
| 1421 | xilinx_spips_update_ixr((XilinxSPIPS *)opaque); |
| 1422 | xilinx_spips_update_cs_lines((XilinxSPIPS *)opaque); |
| 1423 | return 0; |
| 1424 | } |
| 1425 | |
| 1426 | static const VMStateDescription vmstate_xilinx_spips = { |
| 1427 | .name = "xilinx_spips", |
| 1428 | .version_id = 2, |
| 1429 | .minimum_version_id = 2, |
| 1430 | .post_load = xilinx_spips_post_load, |
| 1431 | .fields = (const VMStateField[]) { |
| 1432 | VMSTATE_FIFO8(tx_fifo, XilinxSPIPS), |
| 1433 | VMSTATE_FIFO8(rx_fifo, XilinxSPIPS), |
| 1434 | VMSTATE_UINT32_ARRAY(regs, XilinxSPIPS, XLNX_SPIPS_R_MAX), |
| 1435 | VMSTATE_UINT8(snoop_state, XilinxSPIPS), |
| 1436 | VMSTATE_END_OF_LIST() |
| 1437 | } |
| 1438 | }; |
| 1439 | |
| 1440 | static int xlnx_zynqmp_qspips_post_load(void *opaque, int version_id) |
| 1441 | { |
| 1442 | XlnxZynqMPQSPIPS *s = (XlnxZynqMPQSPIPS *)opaque; |
| 1443 | XilinxSPIPS *qs = XILINX_SPIPS(s); |
| 1444 | |
| 1445 | if (ARRAY_FIELD_EX32(s->regs, GQSPI_SELECT, GENERIC_QSPI_EN) && |
| 1446 | fifo8_is_empty(&qs->rx_fifo) && fifo8_is_empty(&qs->tx_fifo)) { |
| 1447 | xlnx_zynqmp_qspips_update_ixr(s); |
| 1448 | xlnx_zynqmp_qspips_update_cs_lines(s); |
| 1449 | } |
| 1450 | return 0; |
| 1451 | } |
| 1452 | |
| 1453 | static const VMStateDescription vmstate_xilinx_qspips = { |
| 1454 | .name = "xilinx_qspips", |
| 1455 | .version_id = 1, |
| 1456 | .minimum_version_id = 1, |
| 1457 | .fields = (const VMStateField[]) { |
| 1458 | VMSTATE_STRUCT(parent_obj, XilinxQSPIPS, 0, |
| 1459 | vmstate_xilinx_spips, XilinxSPIPS), |
| 1460 | VMSTATE_END_OF_LIST() |
| 1461 | } |
| 1462 | }; |
| 1463 | |
| 1464 | static const VMStateDescription vmstate_xlnx_zynqmp_qspips = { |
| 1465 | .name = "xlnx_zynqmp_qspips", |
| 1466 | .version_id = 1, |
| 1467 | .minimum_version_id = 1, |
| 1468 | .post_load = xlnx_zynqmp_qspips_post_load, |
| 1469 | .fields = (const VMStateField[]) { |
| 1470 | VMSTATE_STRUCT(parent_obj, XlnxZynqMPQSPIPS, 0, |
| 1471 | vmstate_xilinx_qspips, XilinxQSPIPS), |
| 1472 | VMSTATE_FIFO8(tx_fifo_g, XlnxZynqMPQSPIPS), |
| 1473 | VMSTATE_FIFO8(rx_fifo_g, XlnxZynqMPQSPIPS), |
| 1474 | VMSTATE_FIFO32(fifo_g, XlnxZynqMPQSPIPS), |
| 1475 | VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPQSPIPS, XLNX_ZYNQMP_SPIPS_R_MAX), |
| 1476 | VMSTATE_END_OF_LIST() |
| 1477 | } |
| 1478 | }; |
| 1479 | |
| 1480 | static const Property xilinx_zynqmp_qspips_properties[] = { |
| 1481 | DEFINE_PROP_UINT32("dma-burst-size", XlnxZynqMPQSPIPS, dma_burst_size, 64), |
| 1482 | }; |
| 1483 | |
| 1484 | static const Property xilinx_spips_properties[] = { |
| 1485 | DEFINE_PROP_UINT8("num-busses", XilinxSPIPS, num_busses, 1), |
| 1486 | DEFINE_PROP_UINT8("num-ss-bits", XilinxSPIPS, num_cs, 4), |
| 1487 | DEFINE_PROP_UINT8("num-txrx-bytes", XilinxSPIPS, num_txrx_bytes, 1), |
| 1488 | }; |
| 1489 | |
| 1490 | static void xilinx_qspips_class_init(ObjectClass *klass, const void *data) |
| 1491 | { |
| 1492 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 1493 | XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); |
| 1494 | |
| 1495 | dc->realize = xilinx_qspips_realize; |
| 1496 | xsc->reg_ops = &qspips_ops; |
| 1497 | xsc->reg_size = XLNX_SPIPS_R_MAX * 4; |
| 1498 | xsc->rx_fifo_size = RXFF_A_Q; |
| 1499 | xsc->tx_fifo_size = TXFF_A_Q; |
| 1500 | } |
| 1501 | |
| 1502 | static void xilinx_spips_class_init(ObjectClass *klass, const void *data) |
| 1503 | { |
| 1504 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 1505 | XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); |
| 1506 | |
| 1507 | dc->realize = xilinx_spips_realize; |
| 1508 | device_class_set_legacy_reset(dc, xilinx_spips_reset); |
| 1509 | device_class_set_props(dc, xilinx_spips_properties); |
| 1510 | dc->vmsd = &vmstate_xilinx_spips; |
| 1511 | |
| 1512 | xsc->reg_ops = &spips_ops; |
| 1513 | xsc->reg_size = XLNX_SPIPS_R_MAX * 4; |
| 1514 | xsc->rx_fifo_size = RXFF_A; |
| 1515 | xsc->tx_fifo_size = TXFF_A; |
| 1516 | } |
| 1517 | |
| 1518 | static void xlnx_zynqmp_qspips_class_init(ObjectClass *klass, const void *data) |
| 1519 | { |
| 1520 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 1521 | XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); |
| 1522 | |
| 1523 | dc->realize = xlnx_zynqmp_qspips_realize; |
| 1524 | device_class_set_legacy_reset(dc, xlnx_zynqmp_qspips_reset); |
| 1525 | dc->vmsd = &vmstate_xlnx_zynqmp_qspips; |
| 1526 | device_class_set_props(dc, xilinx_zynqmp_qspips_properties); |
| 1527 | xsc->reg_ops = &xlnx_zynqmp_qspips_ops; |
| 1528 | xsc->reg_size = XLNX_ZYNQMP_SPIPS_R_MAX * 4; |
| 1529 | xsc->rx_fifo_size = RXFF_A_Q; |
| 1530 | xsc->tx_fifo_size = TXFF_A_Q; |
| 1531 | } |
| 1532 | |
| 1533 | static const TypeInfo xilinx_spips_info = { |
| 1534 | .name = TYPE_XILINX_SPIPS, |
| 1535 | .parent = TYPE_SYS_BUS_DEVICE, |
| 1536 | .instance_size = sizeof(XilinxSPIPS), |
| 1537 | .class_init = xilinx_spips_class_init, |
| 1538 | .class_size = sizeof(XilinxSPIPSClass), |
| 1539 | }; |
| 1540 | |
| 1541 | static const TypeInfo xilinx_qspips_info = { |
| 1542 | .name = TYPE_XILINX_QSPIPS, |
| 1543 | .parent = TYPE_XILINX_SPIPS, |
| 1544 | .instance_size = sizeof(XilinxQSPIPS), |
| 1545 | .class_init = xilinx_qspips_class_init, |
| 1546 | }; |
| 1547 | |
| 1548 | static const TypeInfo xlnx_zynqmp_qspips_info = { |
| 1549 | .name = TYPE_XLNX_ZYNQMP_QSPIPS, |
| 1550 | .parent = TYPE_XILINX_QSPIPS, |
| 1551 | .instance_size = sizeof(XlnxZynqMPQSPIPS), |
| 1552 | .instance_init = xlnx_zynqmp_qspips_init, |
| 1553 | .class_init = xlnx_zynqmp_qspips_class_init, |
| 1554 | }; |
| 1555 | |
| 1556 | static void xilinx_spips_register_types(void) |
| 1557 | { |
| 1558 | type_register_static(&xilinx_spips_info); |
| 1559 | type_register_static(&xilinx_qspips_info); |
| 1560 | type_register_static(&xlnx_zynqmp_qspips_info); |
| 1561 | } |
| 1562 | |
| 1563 | type_init(xilinx_spips_register_types) |