| 1 | /* |
| 2 | * QEMU 8253/8254 interval timer emulation |
| 3 | * |
| 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
| 24 | |
| 25 | #include "qemu/osdep.h" |
| 26 | #include "hw/core/irq.h" |
| 27 | #include "qemu/module.h" |
| 28 | #include "qemu/timer.h" |
| 29 | #include "hw/timer/i8254.h" |
| 30 | #include "hw/timer/i8254_internal.h" |
| 31 | #include "qom/object.h" |
| 32 | #include "trace.h" |
| 33 | |
| 34 | //#define DEBUG_PIT |
| 35 | |
| 36 | #define RW_STATE_LSB 1 |
| 37 | #define RW_STATE_MSB 2 |
| 38 | #define RW_STATE_WORD0 3 |
| 39 | #define RW_STATE_WORD1 4 |
| 40 | |
| 41 | typedef struct PITClass PITClass; |
| 42 | DECLARE_CLASS_CHECKERS(PITClass, PIT, |
| 43 | TYPE_I8254) |
| 44 | |
| 45 | struct PITClass { |
| 46 | PITCommonClass parent_class; |
| 47 | |
| 48 | DeviceRealize parent_realize; |
| 49 | }; |
| 50 | |
| 51 | static void pit_irq_timer_update(PITChannelState *s, int64_t current_time); |
| 52 | |
| 53 | static int pit_get_count(PITChannelState *s) |
| 54 | { |
| 55 | uint64_t d; |
| 56 | int counter; |
| 57 | |
| 58 | d = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->count_load_time, PIT_FREQ, |
| 59 | NANOSECONDS_PER_SECOND); |
| 60 | switch(s->mode) { |
| 61 | case 0: |
| 62 | case 1: |
| 63 | case 4: |
| 64 | case 5: |
| 65 | counter = (s->count - d) & 0xffff; |
| 66 | break; |
| 67 | case 3: |
| 68 | /* XXX: may be incorrect for odd counts */ |
| 69 | counter = s->count - ((2 * d) % s->count); |
| 70 | break; |
| 71 | default: |
| 72 | counter = s->count - (d % s->count); |
| 73 | break; |
| 74 | } |
| 75 | return counter; |
| 76 | } |
| 77 | |
| 78 | /* val must be 0 or 1 */ |
| 79 | static void pit_set_channel_gate(PITCommonState *s, PITChannelState *sc, |
| 80 | int val) |
| 81 | { |
| 82 | switch (sc->mode) { |
| 83 | default: |
| 84 | case 0: |
| 85 | case 4: |
| 86 | /* XXX: just disable/enable counting */ |
| 87 | break; |
| 88 | case 1: |
| 89 | case 5: |
| 90 | if (sc->gate < val) { |
| 91 | /* restart counting on rising edge */ |
| 92 | sc->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
| 93 | pit_irq_timer_update(sc, sc->count_load_time); |
| 94 | } |
| 95 | break; |
| 96 | case 2: |
| 97 | case 3: |
| 98 | if (sc->gate < val) { |
| 99 | /* restart counting on rising edge */ |
| 100 | sc->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
| 101 | pit_irq_timer_update(sc, sc->count_load_time); |
| 102 | } |
| 103 | /* XXX: disable/enable counting */ |
| 104 | break; |
| 105 | } |
| 106 | sc->gate = val; |
| 107 | } |
| 108 | |
| 109 | static inline void pit_load_count(PITChannelState *s, int val) |
| 110 | { |
| 111 | if (val == 0) |
| 112 | val = 0x10000; |
| 113 | s->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
| 114 | s->count = val; |
| 115 | pit_irq_timer_update(s, s->count_load_time); |
| 116 | } |
| 117 | |
| 118 | /* if already latched, do not latch again */ |
| 119 | static void pit_latch_count(PITChannelState *s) |
| 120 | { |
| 121 | if (!s->count_latched) { |
| 122 | s->latched_count = pit_get_count(s); |
| 123 | s->count_latched = s->rw_mode; |
| 124 | } |
| 125 | } |
| 126 | |
| 127 | static void pit_ioport_write(void *opaque, hwaddr addr, |
| 128 | uint64_t val, unsigned size) |
| 129 | { |
| 130 | PITCommonState *pit = opaque; |
| 131 | int channel, access; |
| 132 | PITChannelState *s; |
| 133 | |
| 134 | trace_pit_ioport_write(addr, val); |
| 135 | |
| 136 | addr &= 3; |
| 137 | if (addr == 3) { |
| 138 | channel = val >> 6; |
| 139 | if (channel == 3) { |
| 140 | /* read back command */ |
| 141 | for(channel = 0; channel < 3; channel++) { |
| 142 | s = &pit->channels[channel]; |
| 143 | if (val & (2 << channel)) { |
| 144 | if (!(val & 0x20)) { |
| 145 | pit_latch_count(s); |
| 146 | } |
| 147 | if (!(val & 0x10) && !s->status_latched) { |
| 148 | /* status latch */ |
| 149 | /* XXX: add BCD and null count */ |
| 150 | s->status = |
| 151 | (pit_get_out(s, |
| 152 | qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) << 7) | |
| 153 | (s->rw_mode << 4) | |
| 154 | (s->mode << 1) | |
| 155 | s->bcd; |
| 156 | s->status_latched = 1; |
| 157 | } |
| 158 | } |
| 159 | } |
| 160 | } else { |
| 161 | s = &pit->channels[channel]; |
| 162 | access = (val >> 4) & 3; |
| 163 | if (access == 0) { |
| 164 | pit_latch_count(s); |
| 165 | } else { |
| 166 | s->rw_mode = access; |
| 167 | s->read_state = access; |
| 168 | s->write_state = access; |
| 169 | |
| 170 | s->mode = (val >> 1) & 7; |
| 171 | s->bcd = val & 1; |
| 172 | /* XXX: update irq timer ? */ |
| 173 | } |
| 174 | } |
| 175 | } else { |
| 176 | s = &pit->channels[addr]; |
| 177 | switch(s->write_state) { |
| 178 | default: |
| 179 | case RW_STATE_LSB: |
| 180 | pit_load_count(s, val); |
| 181 | break; |
| 182 | case RW_STATE_MSB: |
| 183 | pit_load_count(s, val << 8); |
| 184 | break; |
| 185 | case RW_STATE_WORD0: |
| 186 | s->write_latch = val; |
| 187 | s->write_state = RW_STATE_WORD1; |
| 188 | break; |
| 189 | case RW_STATE_WORD1: |
| 190 | pit_load_count(s, s->write_latch | (val << 8)); |
| 191 | s->write_state = RW_STATE_WORD0; |
| 192 | break; |
| 193 | } |
| 194 | } |
| 195 | } |
| 196 | |
| 197 | static uint64_t pit_ioport_read(void *opaque, hwaddr addr, |
| 198 | unsigned size) |
| 199 | { |
| 200 | PITCommonState *pit = opaque; |
| 201 | int ret, count; |
| 202 | PITChannelState *s; |
| 203 | |
| 204 | addr &= 3; |
| 205 | |
| 206 | if (addr == 3) { |
| 207 | /* Mode/Command register is write only, read is ignored */ |
| 208 | return 0; |
| 209 | } |
| 210 | |
| 211 | s = &pit->channels[addr]; |
| 212 | if (s->status_latched) { |
| 213 | s->status_latched = 0; |
| 214 | ret = s->status; |
| 215 | } else if (s->count_latched) { |
| 216 | switch(s->count_latched) { |
| 217 | default: |
| 218 | case RW_STATE_LSB: |
| 219 | ret = s->latched_count & 0xff; |
| 220 | s->count_latched = 0; |
| 221 | break; |
| 222 | case RW_STATE_MSB: |
| 223 | ret = s->latched_count >> 8; |
| 224 | s->count_latched = 0; |
| 225 | break; |
| 226 | case RW_STATE_WORD0: |
| 227 | ret = s->latched_count & 0xff; |
| 228 | s->count_latched = RW_STATE_MSB; |
| 229 | break; |
| 230 | } |
| 231 | } else { |
| 232 | switch(s->read_state) { |
| 233 | default: |
| 234 | case RW_STATE_LSB: |
| 235 | count = pit_get_count(s); |
| 236 | ret = count & 0xff; |
| 237 | break; |
| 238 | case RW_STATE_MSB: |
| 239 | count = pit_get_count(s); |
| 240 | ret = (count >> 8) & 0xff; |
| 241 | break; |
| 242 | case RW_STATE_WORD0: |
| 243 | count = pit_get_count(s); |
| 244 | ret = count & 0xff; |
| 245 | s->read_state = RW_STATE_WORD1; |
| 246 | break; |
| 247 | case RW_STATE_WORD1: |
| 248 | count = pit_get_count(s); |
| 249 | ret = (count >> 8) & 0xff; |
| 250 | s->read_state = RW_STATE_WORD0; |
| 251 | break; |
| 252 | } |
| 253 | } |
| 254 | |
| 255 | trace_pit_ioport_read(addr, ret); |
| 256 | |
| 257 | return ret; |
| 258 | } |
| 259 | |
| 260 | static void pit_irq_timer_update(PITChannelState *s, int64_t current_time) |
| 261 | { |
| 262 | int64_t expire_time; |
| 263 | int irq_level; |
| 264 | |
| 265 | if (!s->irq_timer || s->irq_disabled) { |
| 266 | return; |
| 267 | } |
| 268 | expire_time = pit_get_next_transition_time(s, current_time); |
| 269 | irq_level = pit_get_out(s, current_time); |
| 270 | qemu_set_irq(s->irq, irq_level); |
| 271 | #ifdef DEBUG_PIT |
| 272 | printf("irq_level=%d next_delay=%f\n", |
| 273 | irq_level, |
| 274 | (double)(expire_time - current_time) / NANOSECONDS_PER_SECOND); |
| 275 | #endif |
| 276 | s->next_transition_time = expire_time; |
| 277 | if (expire_time != -1) |
| 278 | timer_mod(s->irq_timer, expire_time); |
| 279 | else |
| 280 | timer_del(s->irq_timer); |
| 281 | } |
| 282 | |
| 283 | static void pit_irq_timer(void *opaque) |
| 284 | { |
| 285 | PITChannelState *s = opaque; |
| 286 | |
| 287 | pit_irq_timer_update(s, s->next_transition_time); |
| 288 | } |
| 289 | |
| 290 | static void pit_reset(DeviceState *dev) |
| 291 | { |
| 292 | PITCommonState *pit = PIT_COMMON(dev); |
| 293 | PITChannelState *s; |
| 294 | |
| 295 | pit_reset_common(pit); |
| 296 | |
| 297 | s = &pit->channels[0]; |
| 298 | if (!s->irq_disabled) { |
| 299 | timer_mod(s->irq_timer, s->next_transition_time); |
| 300 | } |
| 301 | } |
| 302 | |
| 303 | /* When HPET is operating in legacy mode, suppress the ignored timer IRQ, |
| 304 | * reenable it when legacy mode is left again. */ |
| 305 | static void pit_irq_control(void *opaque, int n, int enable) |
| 306 | { |
| 307 | PITCommonState *pit = opaque; |
| 308 | PITChannelState *s = &pit->channels[0]; |
| 309 | |
| 310 | if (enable) { |
| 311 | s->irq_disabled = 0; |
| 312 | pit_irq_timer_update(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); |
| 313 | } else { |
| 314 | s->irq_disabled = 1; |
| 315 | timer_del(s->irq_timer); |
| 316 | } |
| 317 | } |
| 318 | |
| 319 | static const MemoryRegionOps pit_ioport_ops = { |
| 320 | .read = pit_ioport_read, |
| 321 | .write = pit_ioport_write, |
| 322 | .impl = { |
| 323 | .min_access_size = 1, |
| 324 | .max_access_size = 1, |
| 325 | }, |
| 326 | .endianness = DEVICE_LITTLE_ENDIAN, |
| 327 | }; |
| 328 | |
| 329 | static void pit_post_load(PITCommonState *s) |
| 330 | { |
| 331 | PITChannelState *sc = &s->channels[0]; |
| 332 | |
| 333 | if (sc->next_transition_time != -1 && !sc->irq_disabled) { |
| 334 | timer_mod(sc->irq_timer, sc->next_transition_time); |
| 335 | } else { |
| 336 | timer_del(sc->irq_timer); |
| 337 | } |
| 338 | } |
| 339 | |
| 340 | static void pit_realizefn(DeviceState *dev, Error **errp) |
| 341 | { |
| 342 | PITCommonState *pit = PIT_COMMON(dev); |
| 343 | PITClass *pc = PIT_GET_CLASS(dev); |
| 344 | PITChannelState *s; |
| 345 | |
| 346 | s = &pit->channels[0]; |
| 347 | /* the timer 0 is connected to an IRQ */ |
| 348 | s->irq_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, pit_irq_timer, s); |
| 349 | qdev_init_gpio_out(dev, &s->irq, 1); |
| 350 | |
| 351 | memory_region_init_io(&pit->ioports, OBJECT(pit), &pit_ioport_ops, |
| 352 | pit, "pit", 4); |
| 353 | |
| 354 | qdev_init_gpio_in(dev, pit_irq_control, 1); |
| 355 | |
| 356 | pc->parent_realize(dev, errp); |
| 357 | } |
| 358 | |
| 359 | static void pit_class_initfn(ObjectClass *klass, const void *data) |
| 360 | { |
| 361 | PITClass *pc = PIT_CLASS(klass); |
| 362 | PITCommonClass *k = PIT_COMMON_CLASS(klass); |
| 363 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 364 | |
| 365 | device_class_set_parent_realize(dc, pit_realizefn, &pc->parent_realize); |
| 366 | k->set_channel_gate = pit_set_channel_gate; |
| 367 | k->get_channel_info = pit_get_channel_info_common; |
| 368 | k->post_load = pit_post_load; |
| 369 | device_class_set_legacy_reset(dc, pit_reset); |
| 370 | } |
| 371 | |
| 372 | static const TypeInfo pit_info = { |
| 373 | .name = TYPE_I8254, |
| 374 | .parent = TYPE_PIT_COMMON, |
| 375 | .instance_size = sizeof(PITCommonState), |
| 376 | .class_init = pit_class_initfn, |
| 377 | .class_size = sizeof(PITClass), |
| 378 | }; |
| 379 | |
| 380 | static void pit_register_types(void) |
| 381 | { |
| 382 | type_register_static(&pit_info); |
| 383 | } |
| 384 | |
| 385 | type_init(pit_register_types) |