| 1 | /* |
| 2 | * QEMU 8253/8254 - common bits of emulated and KVM kernel model |
| 3 | * |
| 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
| 5 | * Copyright (c) 2012 Jan Kiszka, Siemens AG |
| 6 | * |
| 7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 8 | * of this software and associated documentation files (the "Software"), to deal |
| 9 | * in the Software without restriction, including without limitation the rights |
| 10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 11 | * copies of the Software, and to permit persons to whom the Software is |
| 12 | * furnished to do so, subject to the following conditions: |
| 13 | * |
| 14 | * The above copyright notice and this permission notice shall be included in |
| 15 | * all copies or substantial portions of the Software. |
| 16 | * |
| 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 23 | * THE SOFTWARE. |
| 24 | */ |
| 25 | |
| 26 | #include "qemu/osdep.h" |
| 27 | #include "hw/isa/isa.h" |
| 28 | #include "qemu/module.h" |
| 29 | #include "qemu/timer.h" |
| 30 | #include "hw/timer/i8254.h" |
| 31 | #include "hw/timer/i8254_internal.h" |
| 32 | #include "migration/vmstate.h" |
| 33 | |
| 34 | /* val must be 0 or 1 */ |
| 35 | void pit_set_gate(PITCommonState *pit, int channel, int val) |
| 36 | { |
| 37 | PITChannelState *s = &pit->channels[channel]; |
| 38 | PITCommonClass *c = PIT_COMMON_GET_CLASS(pit); |
| 39 | |
| 40 | c->set_channel_gate(pit, s, val); |
| 41 | } |
| 42 | |
| 43 | /* get pit output bit */ |
| 44 | int pit_get_out(PITChannelState *s, int64_t current_time) |
| 45 | { |
| 46 | uint64_t d; |
| 47 | int out; |
| 48 | |
| 49 | d = muldiv64(current_time - s->count_load_time, PIT_FREQ, |
| 50 | NANOSECONDS_PER_SECOND); |
| 51 | switch (s->mode) { |
| 52 | default: |
| 53 | case 0: |
| 54 | case 1: |
| 55 | out = (d >= s->count); |
| 56 | break; |
| 57 | case 2: |
| 58 | if ((d % s->count) == 0 && d != 0) { |
| 59 | out = 1; |
| 60 | } else { |
| 61 | out = 0; |
| 62 | } |
| 63 | break; |
| 64 | case 3: |
| 65 | out = (d % s->count) < ((s->count + 1) >> 1); |
| 66 | break; |
| 67 | case 4: |
| 68 | case 5: |
| 69 | out = (d == s->count); |
| 70 | break; |
| 71 | } |
| 72 | return out; |
| 73 | } |
| 74 | |
| 75 | /* return -1 if no transition will occur. */ |
| 76 | int64_t pit_get_next_transition_time(PITChannelState *s, int64_t current_time) |
| 77 | { |
| 78 | uint64_t d, next_time, base; |
| 79 | int period2; |
| 80 | |
| 81 | d = muldiv64(current_time - s->count_load_time, PIT_FREQ, |
| 82 | NANOSECONDS_PER_SECOND); |
| 83 | switch (s->mode) { |
| 84 | default: |
| 85 | case 0: |
| 86 | case 1: |
| 87 | if (d < s->count) { |
| 88 | next_time = s->count; |
| 89 | } else { |
| 90 | return -1; |
| 91 | } |
| 92 | break; |
| 93 | case 2: |
| 94 | base = QEMU_ALIGN_DOWN(d, s->count); |
| 95 | if ((d - base) == 0 && d != 0) { |
| 96 | next_time = base + s->count; |
| 97 | } else { |
| 98 | next_time = base + s->count + 1; |
| 99 | } |
| 100 | break; |
| 101 | case 3: |
| 102 | base = QEMU_ALIGN_DOWN(d, s->count); |
| 103 | period2 = ((s->count + 1) >> 1); |
| 104 | if ((d - base) < period2) { |
| 105 | next_time = base + period2; |
| 106 | } else { |
| 107 | next_time = base + s->count; |
| 108 | } |
| 109 | break; |
| 110 | case 4: |
| 111 | case 5: |
| 112 | if (d < s->count) { |
| 113 | next_time = s->count; |
| 114 | } else if (d == s->count) { |
| 115 | next_time = s->count + 1; |
| 116 | } else { |
| 117 | return -1; |
| 118 | } |
| 119 | break; |
| 120 | } |
| 121 | /* convert to timer units */ |
| 122 | next_time = s->count_load_time + muldiv64(next_time, NANOSECONDS_PER_SECOND, |
| 123 | PIT_FREQ); |
| 124 | /* fix potential rounding problems */ |
| 125 | /* XXX: better solution: use a clock at PIT_FREQ Hz */ |
| 126 | if (next_time <= current_time) { |
| 127 | next_time = current_time + 1; |
| 128 | } |
| 129 | return next_time; |
| 130 | } |
| 131 | |
| 132 | void pit_get_channel_info_common(PITCommonState *s, PITChannelState *sc, |
| 133 | PITChannelInfo *info) |
| 134 | { |
| 135 | info->gate = sc->gate; |
| 136 | info->mode = sc->mode; |
| 137 | info->initial_count = sc->count; |
| 138 | info->out = pit_get_out(sc, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); |
| 139 | } |
| 140 | |
| 141 | void pit_get_channel_info(PITCommonState *pit, int channel, PITChannelInfo *info) |
| 142 | { |
| 143 | PITChannelState *s = &pit->channels[channel]; |
| 144 | PITCommonClass *c = PIT_COMMON_GET_CLASS(pit); |
| 145 | |
| 146 | c->get_channel_info(pit, s, info); |
| 147 | } |
| 148 | |
| 149 | void pit_reset_common(PITCommonState *pit) |
| 150 | { |
| 151 | PITChannelState *s; |
| 152 | int i; |
| 153 | |
| 154 | for (i = 0; i < 3; i++) { |
| 155 | s = &pit->channels[i]; |
| 156 | s->mode = 3; |
| 157 | s->gate = (i != 2); |
| 158 | s->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
| 159 | s->count = 0x10000; |
| 160 | if (i == 0 && !s->irq_disabled) { |
| 161 | s->next_transition_time = |
| 162 | pit_get_next_transition_time(s, s->count_load_time); |
| 163 | } |
| 164 | } |
| 165 | } |
| 166 | |
| 167 | static void pit_common_realize(DeviceState *dev, Error **errp) |
| 168 | { |
| 169 | ISADevice *isadev = ISA_DEVICE(dev); |
| 170 | PITCommonState *pit = PIT_COMMON(dev); |
| 171 | |
| 172 | isa_register_ioport(isadev, &pit->ioports, pit->iobase); |
| 173 | |
| 174 | qdev_set_legacy_instance_id(dev, pit->iobase, 2); |
| 175 | } |
| 176 | |
| 177 | static const VMStateDescription vmstate_pit_channel = { |
| 178 | .name = "pit channel", |
| 179 | .version_id = 2, |
| 180 | .minimum_version_id = 2, |
| 181 | .fields = (const VMStateField[]) { |
| 182 | VMSTATE_INT32(count, PITChannelState), |
| 183 | VMSTATE_UINT16(latched_count, PITChannelState), |
| 184 | VMSTATE_UINT8(count_latched, PITChannelState), |
| 185 | VMSTATE_UINT8(status_latched, PITChannelState), |
| 186 | VMSTATE_UINT8(status, PITChannelState), |
| 187 | VMSTATE_UINT8(read_state, PITChannelState), |
| 188 | VMSTATE_UINT8(write_state, PITChannelState), |
| 189 | VMSTATE_UINT8(write_latch, PITChannelState), |
| 190 | VMSTATE_UINT8(rw_mode, PITChannelState), |
| 191 | VMSTATE_UINT8(mode, PITChannelState), |
| 192 | VMSTATE_UINT8(bcd, PITChannelState), |
| 193 | VMSTATE_UINT8(gate, PITChannelState), |
| 194 | VMSTATE_INT64(count_load_time, PITChannelState), |
| 195 | VMSTATE_INT64(next_transition_time, PITChannelState), |
| 196 | VMSTATE_END_OF_LIST() |
| 197 | } |
| 198 | }; |
| 199 | |
| 200 | static int pit_dispatch_pre_save(void *opaque) |
| 201 | { |
| 202 | PITCommonState *s = opaque; |
| 203 | PITCommonClass *c = PIT_COMMON_GET_CLASS(s); |
| 204 | |
| 205 | if (c->pre_save) { |
| 206 | c->pre_save(s); |
| 207 | } |
| 208 | |
| 209 | return 0; |
| 210 | } |
| 211 | |
| 212 | static int pit_dispatch_post_load(void *opaque, int version_id) |
| 213 | { |
| 214 | PITCommonState *s = opaque; |
| 215 | PITCommonClass *c = PIT_COMMON_GET_CLASS(s); |
| 216 | |
| 217 | if (c->post_load) { |
| 218 | c->post_load(s); |
| 219 | } |
| 220 | return 0; |
| 221 | } |
| 222 | |
| 223 | static const VMStateDescription vmstate_pit_common = { |
| 224 | .name = "i8254", |
| 225 | .version_id = 3, |
| 226 | .minimum_version_id = 2, |
| 227 | .pre_save = pit_dispatch_pre_save, |
| 228 | .post_load = pit_dispatch_post_load, |
| 229 | .fields = (const VMStateField[]) { |
| 230 | VMSTATE_UINT32_V(channels[0].irq_disabled, PITCommonState, 3), |
| 231 | VMSTATE_STRUCT_ARRAY(channels, PITCommonState, 3, 2, |
| 232 | vmstate_pit_channel, PITChannelState), |
| 233 | VMSTATE_INT64(channels[0].next_transition_time, |
| 234 | PITCommonState), /* formerly irq_timer */ |
| 235 | VMSTATE_END_OF_LIST() |
| 236 | } |
| 237 | }; |
| 238 | |
| 239 | static const Property pit_common_properties[] = { |
| 240 | DEFINE_PROP_UINT32("iobase", PITCommonState, iobase, -1), |
| 241 | }; |
| 242 | |
| 243 | static void pit_common_class_init(ObjectClass *klass, const void *data) |
| 244 | { |
| 245 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 246 | |
| 247 | dc->realize = pit_common_realize; |
| 248 | dc->vmsd = &vmstate_pit_common; |
| 249 | /* |
| 250 | * Reason: unlike ordinary ISA devices, the PIT may need to be |
| 251 | * wired to the HPET, and because of that, some wiring is always |
| 252 | * done by board code. |
| 253 | */ |
| 254 | dc->user_creatable = false; |
| 255 | device_class_set_props(dc, pit_common_properties); |
| 256 | } |
| 257 | |
| 258 | static const TypeInfo pit_common_type = { |
| 259 | .name = TYPE_PIT_COMMON, |
| 260 | .parent = TYPE_ISA_DEVICE, |
| 261 | .instance_size = sizeof(PITCommonState), |
| 262 | .class_size = sizeof(PITCommonClass), |
| 263 | .class_init = pit_common_class_init, |
| 264 | .abstract = true, |
| 265 | }; |
| 266 | |
| 267 | static void register_devices(void) |
| 268 | { |
| 269 | type_register_static(&pit_common_type); |
| 270 | } |
| 271 | |
| 272 | type_init(register_devices); |