| 1 | /* |
| 2 | * IMX EPIT Timer |
| 3 | * |
| 4 | * Copyright (c) 2008 OK Labs |
| 5 | * Copyright (c) 2011 NICTA Pty Ltd |
| 6 | * Originally written by Hans Jiang |
| 7 | * Updated by Peter Chubb |
| 8 | * Updated by Jean-Christophe Dubois <jcd@tribudubois.net> |
| 9 | * Updated by Axel Heider |
| 10 | * |
| 11 | * This code is licensed under GPL version 2 or later. See |
| 12 | * the COPYING file in the top-level directory. |
| 13 | * |
| 14 | */ |
| 15 | |
| 16 | #include "qemu/osdep.h" |
| 17 | #include "hw/timer/imx_epit.h" |
| 18 | #include "migration/vmstate.h" |
| 19 | #include "hw/core/irq.h" |
| 20 | #include "hw/misc/imx_ccm.h" |
| 21 | #include "qemu/module.h" |
| 22 | #include "qemu/log.h" |
| 23 | #include "trace.h" |
| 24 | |
| 25 | static const char *imx_epit_reg_name(uint32_t reg) |
| 26 | { |
| 27 | switch (reg) { |
| 28 | case 0: |
| 29 | return "CR"; |
| 30 | case 1: |
| 31 | return "SR"; |
| 32 | case 2: |
| 33 | return "LR"; |
| 34 | case 3: |
| 35 | return "CMP"; |
| 36 | case 4: |
| 37 | return "CNT"; |
| 38 | default: |
| 39 | return "[?]"; |
| 40 | } |
| 41 | } |
| 42 | |
| 43 | /* |
| 44 | * Exact clock frequencies vary from board to board. |
| 45 | * These are typical. |
| 46 | */ |
| 47 | static const IMXClk imx_epit_clocks[] = { |
| 48 | CLK_NONE, /* 00 disabled */ |
| 49 | CLK_IPG, /* 01 ipg_clk, ~532MHz */ |
| 50 | CLK_IPG_HIGH, /* 10 ipg_clk_highfreq */ |
| 51 | CLK_32k, /* 11 ipg_clk_32k -- ~32kHz */ |
| 52 | }; |
| 53 | |
| 54 | /* |
| 55 | * Update interrupt status |
| 56 | */ |
| 57 | static void imx_epit_update_int(IMXEPITState *s) |
| 58 | { |
| 59 | if ((s->sr & SR_OCIF) && (s->cr & CR_OCIEN) && (s->cr & CR_EN)) { |
| 60 | qemu_irq_raise(s->irq); |
| 61 | } else { |
| 62 | qemu_irq_lower(s->irq); |
| 63 | } |
| 64 | } |
| 65 | |
| 66 | static uint32_t imx_epit_get_freq(IMXEPITState *s) |
| 67 | { |
| 68 | uint32_t clksrc = extract32(s->cr, CR_CLKSRC_SHIFT, CR_CLKSRC_BITS); |
| 69 | uint32_t prescaler = 1 + extract32(s->cr, CR_PRESCALE_SHIFT, CR_PRESCALE_BITS); |
| 70 | uint32_t f_in = imx_ccm_get_clock_frequency(s->ccm, imx_epit_clocks[clksrc]); |
| 71 | uint32_t freq = f_in / prescaler; |
| 72 | trace_imx_epit_get_freq(freq); |
| 73 | return freq; |
| 74 | } |
| 75 | |
| 76 | /* |
| 77 | * This is called both on hardware (device) reset and software reset. |
| 78 | */ |
| 79 | static void imx_epit_reset(IMXEPITState *s, bool is_hard_reset) |
| 80 | { |
| 81 | /* Soft reset doesn't touch some bits; hard reset clears them */ |
| 82 | if (is_hard_reset) { |
| 83 | s->cr = 0; |
| 84 | } else { |
| 85 | s->cr &= (CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN); |
| 86 | } |
| 87 | s->sr = 0; |
| 88 | s->lr = EPIT_TIMER_MAX; |
| 89 | s->cmp = 0; |
| 90 | ptimer_transaction_begin(s->timer_cmp); |
| 91 | ptimer_transaction_begin(s->timer_reload); |
| 92 | |
| 93 | /* |
| 94 | * The reset switches off the input clock, so even if the CR.EN is still |
| 95 | * set, the timers are no longer running. |
| 96 | */ |
| 97 | assert(imx_epit_get_freq(s) == 0); |
| 98 | ptimer_stop(s->timer_cmp); |
| 99 | ptimer_stop(s->timer_reload); |
| 100 | /* init both timers to EPIT_TIMER_MAX */ |
| 101 | ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1); |
| 102 | ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1); |
| 103 | ptimer_transaction_commit(s->timer_cmp); |
| 104 | ptimer_transaction_commit(s->timer_reload); |
| 105 | } |
| 106 | |
| 107 | static uint64_t imx_epit_read(void *opaque, hwaddr offset, unsigned size) |
| 108 | { |
| 109 | IMXEPITState *s = IMX_EPIT(opaque); |
| 110 | uint32_t reg_value = 0; |
| 111 | |
| 112 | switch (offset >> 2) { |
| 113 | case 0: /* Control Register */ |
| 114 | reg_value = s->cr; |
| 115 | break; |
| 116 | |
| 117 | case 1: /* Status Register */ |
| 118 | reg_value = s->sr; |
| 119 | break; |
| 120 | |
| 121 | case 2: /* LR - ticks*/ |
| 122 | reg_value = s->lr; |
| 123 | break; |
| 124 | |
| 125 | case 3: /* CMP */ |
| 126 | reg_value = s->cmp; |
| 127 | break; |
| 128 | |
| 129 | case 4: /* CNT */ |
| 130 | reg_value = ptimer_get_count(s->timer_reload); |
| 131 | break; |
| 132 | |
| 133 | default: |
| 134 | qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" |
| 135 | HWADDR_PRIx "\n", TYPE_IMX_EPIT, __func__, offset); |
| 136 | break; |
| 137 | } |
| 138 | trace_imx_epit_read(imx_epit_reg_name(offset >> 2), reg_value); |
| 139 | |
| 140 | return reg_value; |
| 141 | } |
| 142 | |
| 143 | /* |
| 144 | * Must be called from a ptimer_transaction_begin/commit block for |
| 145 | * s->timer_cmp, but outside of a transaction block of s->timer_reload, |
| 146 | * so the proper counter value is read. |
| 147 | */ |
| 148 | static void imx_epit_update_compare_timer(IMXEPITState *s) |
| 149 | { |
| 150 | uint64_t counter = 0; |
| 151 | bool is_oneshot = false; |
| 152 | /* |
| 153 | * The compare timer only has to run if the timer peripheral is active |
| 154 | * and there is an input clock, Otherwise it can be switched off. |
| 155 | */ |
| 156 | bool is_active = (s->cr & CR_EN) && imx_epit_get_freq(s); |
| 157 | if (is_active) { |
| 158 | /* |
| 159 | * Calculate next timeout for compare timer. Reading the reload |
| 160 | * counter returns proper results only if pending transactions |
| 161 | * on it are committed here. Otherwise stale values are be read. |
| 162 | */ |
| 163 | counter = ptimer_get_count(s->timer_reload); |
| 164 | uint64_t limit = ptimer_get_limit(s->timer_cmp); |
| 165 | /* |
| 166 | * The compare timer is a periodic timer if the limit is at least |
| 167 | * the compare value. Otherwise it may fire at most once in the |
| 168 | * current round. |
| 169 | */ |
| 170 | is_oneshot = (limit < s->cmp); |
| 171 | if (counter >= s->cmp) { |
| 172 | /* The compare timer fires in the current round. */ |
| 173 | counter -= s->cmp; |
| 174 | } else if (!is_oneshot) { |
| 175 | /* |
| 176 | * The compare timer fires after a reload, as it is below the |
| 177 | * compare value already in this round. Note that the counter |
| 178 | * value calculated below can be above the 32-bit limit, which |
| 179 | * is legal here because the compare timer is an internal |
| 180 | * helper ptimer only. |
| 181 | */ |
| 182 | counter += limit - s->cmp; |
| 183 | } else { |
| 184 | /* |
| 185 | * The compare timer won't fire in this round, and the limit is |
| 186 | * set to a value below the compare value. This practically means |
| 187 | * it will never fire, so it can be switched off. |
| 188 | */ |
| 189 | is_active = false; |
| 190 | } |
| 191 | } |
| 192 | |
| 193 | /* |
| 194 | * Set the compare timer and let it run, or stop it. This is agnostic |
| 195 | * of CR.OCIEN bit, as this bit affects interrupt generation only. The |
| 196 | * compare timer needs to run even if no interrupts are to be generated, |
| 197 | * because the SR.OCIF bit must be updated also. |
| 198 | * Note that the timer might already be stopped or be running with |
| 199 | * counter values. However, finding out when an update is needed and |
| 200 | * when not is not trivial. It's much easier applying the setting again, |
| 201 | * as this does not harm either and the overhead is negligible. |
| 202 | */ |
| 203 | if (is_active) { |
| 204 | ptimer_set_count(s->timer_cmp, counter); |
| 205 | ptimer_run(s->timer_cmp, is_oneshot ? 1 : 0); |
| 206 | } else { |
| 207 | ptimer_stop(s->timer_cmp); |
| 208 | } |
| 209 | |
| 210 | } |
| 211 | |
| 212 | static void imx_epit_write_cr(IMXEPITState *s, uint32_t value) |
| 213 | { |
| 214 | uint32_t oldcr = s->cr; |
| 215 | |
| 216 | s->cr = value & 0x03ffffff; |
| 217 | |
| 218 | if (s->cr & CR_SWR) { |
| 219 | /* |
| 220 | * Reset clears CR.SWR again. It does not touch CR.EN, but the timers |
| 221 | * are still stopped because the input clock is disabled. |
| 222 | */ |
| 223 | imx_epit_reset(s, false); |
| 224 | } else { |
| 225 | uint32_t freq; |
| 226 | uint32_t toggled_cr_bits = oldcr ^ s->cr; |
| 227 | /* re-initialize the limits if CR.RLD has changed */ |
| 228 | bool set_limit = toggled_cr_bits & CR_RLD; |
| 229 | /* set the counter if the timer got just enabled and CR.ENMOD is set */ |
| 230 | bool is_switched_on = (toggled_cr_bits & s->cr) & CR_EN; |
| 231 | bool set_counter = is_switched_on && (s->cr & CR_ENMOD); |
| 232 | |
| 233 | ptimer_transaction_begin(s->timer_cmp); |
| 234 | ptimer_transaction_begin(s->timer_reload); |
| 235 | freq = imx_epit_get_freq(s); |
| 236 | if (freq) { |
| 237 | ptimer_set_freq(s->timer_reload, freq); |
| 238 | ptimer_set_freq(s->timer_cmp, freq); |
| 239 | } |
| 240 | |
| 241 | if (set_limit || set_counter) { |
| 242 | uint64_t limit = (s->cr & CR_RLD) ? s->lr : EPIT_TIMER_MAX; |
| 243 | ptimer_set_limit(s->timer_reload, limit, set_counter ? 1 : 0); |
| 244 | if (set_limit) { |
| 245 | ptimer_set_limit(s->timer_cmp, limit, 0); |
| 246 | } |
| 247 | } |
| 248 | /* |
| 249 | * If there is an input clock and the peripheral is enabled, then |
| 250 | * ensure the wall clock timer is ticking. Otherwise stop the timers. |
| 251 | * The compare timer will be updated later. |
| 252 | */ |
| 253 | if (freq && (s->cr & CR_EN)) { |
| 254 | ptimer_run(s->timer_reload, 0); |
| 255 | } else { |
| 256 | ptimer_stop(s->timer_reload); |
| 257 | } |
| 258 | /* Commit changes to reload timer, so they can propagate. */ |
| 259 | ptimer_transaction_commit(s->timer_reload); |
| 260 | /* Update compare timer based on the committed reload timer value. */ |
| 261 | imx_epit_update_compare_timer(s); |
| 262 | ptimer_transaction_commit(s->timer_cmp); |
| 263 | } |
| 264 | |
| 265 | /* |
| 266 | * The interrupt state can change due to: |
| 267 | * - reset clears both SR.OCIF and CR.OCIE |
| 268 | * - write to CR.EN or CR.OCIE |
| 269 | */ |
| 270 | imx_epit_update_int(s); |
| 271 | } |
| 272 | |
| 273 | static void imx_epit_write_sr(IMXEPITState *s, uint32_t value) |
| 274 | { |
| 275 | /* writing 1 to SR.OCIF clears this bit and turns the interrupt off */ |
| 276 | if (value & SR_OCIF) { |
| 277 | s->sr = 0; /* SR.OCIF is the only bit in this register anyway */ |
| 278 | imx_epit_update_int(s); |
| 279 | } |
| 280 | } |
| 281 | |
| 282 | static void imx_epit_write_lr(IMXEPITState *s, uint32_t value) |
| 283 | { |
| 284 | s->lr = value; |
| 285 | |
| 286 | ptimer_transaction_begin(s->timer_cmp); |
| 287 | ptimer_transaction_begin(s->timer_reload); |
| 288 | if (s->cr & CR_RLD) { |
| 289 | /* Also set the limit if the LRD bit is set */ |
| 290 | /* If IOVW bit is set then set the timer value */ |
| 291 | ptimer_set_limit(s->timer_reload, s->lr, s->cr & CR_IOVW); |
| 292 | ptimer_set_limit(s->timer_cmp, s->lr, 0); |
| 293 | } else if (s->cr & CR_IOVW) { |
| 294 | /* If IOVW bit is set then set the timer value */ |
| 295 | ptimer_set_count(s->timer_reload, s->lr); |
| 296 | } |
| 297 | /* Commit the changes to s->timer_reload, so they can propagate. */ |
| 298 | ptimer_transaction_commit(s->timer_reload); |
| 299 | /* Update the compare timer based on the committed reload timer value. */ |
| 300 | imx_epit_update_compare_timer(s); |
| 301 | ptimer_transaction_commit(s->timer_cmp); |
| 302 | } |
| 303 | |
| 304 | static void imx_epit_write_cmp(IMXEPITState *s, uint32_t value) |
| 305 | { |
| 306 | s->cmp = value; |
| 307 | |
| 308 | /* Update the compare timer based on the committed reload timer value. */ |
| 309 | ptimer_transaction_begin(s->timer_cmp); |
| 310 | imx_epit_update_compare_timer(s); |
| 311 | ptimer_transaction_commit(s->timer_cmp); |
| 312 | } |
| 313 | |
| 314 | static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value, |
| 315 | unsigned size) |
| 316 | { |
| 317 | IMXEPITState *s = IMX_EPIT(opaque); |
| 318 | |
| 319 | trace_imx_epit_write(imx_epit_reg_name(offset >> 2), value); |
| 320 | |
| 321 | switch (offset >> 2) { |
| 322 | case 0: /* CR */ |
| 323 | imx_epit_write_cr(s, (uint32_t)value); |
| 324 | break; |
| 325 | |
| 326 | case 1: /* SR */ |
| 327 | imx_epit_write_sr(s, (uint32_t)value); |
| 328 | break; |
| 329 | |
| 330 | case 2: /* LR */ |
| 331 | imx_epit_write_lr(s, (uint32_t)value); |
| 332 | break; |
| 333 | |
| 334 | case 3: /* CMP */ |
| 335 | imx_epit_write_cmp(s, (uint32_t)value); |
| 336 | break; |
| 337 | |
| 338 | default: |
| 339 | qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" |
| 340 | HWADDR_PRIx "\n", TYPE_IMX_EPIT, __func__, offset); |
| 341 | break; |
| 342 | } |
| 343 | } |
| 344 | |
| 345 | static void imx_epit_cmp(void *opaque) |
| 346 | { |
| 347 | IMXEPITState *s = IMX_EPIT(opaque); |
| 348 | |
| 349 | /* The cmp ptimer can't be running when the peripheral is disabled */ |
| 350 | assert(s->cr & CR_EN); |
| 351 | |
| 352 | trace_imx_epit_cmp(s->sr); |
| 353 | /* Set interrupt status bit SR.OCIF and update the interrupt state */ |
| 354 | s->sr |= SR_OCIF; |
| 355 | imx_epit_update_int(s); |
| 356 | } |
| 357 | |
| 358 | static void imx_epit_reload(void *opaque) |
| 359 | { |
| 360 | /* No action required on rollover of timer_reload */ |
| 361 | } |
| 362 | |
| 363 | static const MemoryRegionOps imx_epit_ops = { |
| 364 | .read = imx_epit_read, |
| 365 | .write = imx_epit_write, |
| 366 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 367 | }; |
| 368 | |
| 369 | static const VMStateDescription vmstate_imx_timer_epit = { |
| 370 | .name = TYPE_IMX_EPIT, |
| 371 | .version_id = 3, |
| 372 | .minimum_version_id = 3, |
| 373 | .fields = (const VMStateField[]) { |
| 374 | VMSTATE_UINT32(cr, IMXEPITState), |
| 375 | VMSTATE_UINT32(sr, IMXEPITState), |
| 376 | VMSTATE_UINT32(lr, IMXEPITState), |
| 377 | VMSTATE_UINT32(cmp, IMXEPITState), |
| 378 | VMSTATE_PTIMER(timer_reload, IMXEPITState), |
| 379 | VMSTATE_PTIMER(timer_cmp, IMXEPITState), |
| 380 | VMSTATE_END_OF_LIST() |
| 381 | } |
| 382 | }; |
| 383 | |
| 384 | static void imx_epit_realize(DeviceState *dev, Error **errp) |
| 385 | { |
| 386 | IMXEPITState *s = IMX_EPIT(dev); |
| 387 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
| 388 | |
| 389 | sysbus_init_irq(sbd, &s->irq); |
| 390 | memory_region_init_io(&s->iomem, OBJECT(s), &imx_epit_ops, s, TYPE_IMX_EPIT, |
| 391 | 0x00001000); |
| 392 | sysbus_init_mmio(sbd, &s->iomem); |
| 393 | |
| 394 | /* |
| 395 | * The reload timer keeps running when the peripheral is enabled. It is a |
| 396 | * kind of wall clock that does not generate any interrupts. The callback |
| 397 | * needs to be provided, but it does nothing as the ptimer already supports |
| 398 | * all necessary reloading functionality. |
| 399 | */ |
| 400 | s->timer_reload = ptimer_init(imx_epit_reload, s, PTIMER_POLICY_LEGACY); |
| 401 | |
| 402 | /* |
| 403 | * The compare timer is running only when the peripheral configuration is |
| 404 | * in a state that will generate compare interrupts. |
| 405 | */ |
| 406 | s->timer_cmp = ptimer_init(imx_epit_cmp, s, PTIMER_POLICY_LEGACY); |
| 407 | } |
| 408 | |
| 409 | static void imx_epit_dev_reset(DeviceState *dev) |
| 410 | { |
| 411 | IMXEPITState *s = IMX_EPIT(dev); |
| 412 | imx_epit_reset(s, true); |
| 413 | } |
| 414 | |
| 415 | static void imx_epit_class_init(ObjectClass *klass, const void *data) |
| 416 | { |
| 417 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 418 | |
| 419 | dc->realize = imx_epit_realize; |
| 420 | device_class_set_legacy_reset(dc, imx_epit_dev_reset); |
| 421 | dc->vmsd = &vmstate_imx_timer_epit; |
| 422 | dc->desc = "i.MX periodic timer"; |
| 423 | } |
| 424 | |
| 425 | static const TypeInfo imx_epit_info = { |
| 426 | .name = TYPE_IMX_EPIT, |
| 427 | .parent = TYPE_SYS_BUS_DEVICE, |
| 428 | .instance_size = sizeof(IMXEPITState), |
| 429 | .class_init = imx_epit_class_init, |
| 430 | }; |
| 431 | |
| 432 | static void imx_epit_register_types(void) |
| 433 | { |
| 434 | type_register_static(&imx_epit_info); |
| 435 | } |
| 436 | |
| 437 | type_init(imx_epit_register_types) |