| 1 | /* |
| 2 | * IMX GPT Timer |
| 3 | * |
| 4 | * Copyright (c) 2008 OK Labs |
| 5 | * Copyright (c) 2011 NICTA Pty Ltd |
| 6 | * Originally written by Hans Jiang |
| 7 | * Updated by Peter Chubb |
| 8 | * Updated by Jean-Christophe Dubois <jcd@tribudubois.net> |
| 9 | * Updated by Gaurav Sharma <gaurav.sharma_7@nxp.com> |
| 10 | * |
| 11 | * This code is licensed under GPL version 2 or later. See |
| 12 | * the COPYING file in the top-level directory. |
| 13 | * |
| 14 | */ |
| 15 | |
| 16 | #include "qemu/osdep.h" |
| 17 | #include "hw/core/irq.h" |
| 18 | #include "hw/timer/imx_gpt.h" |
| 19 | #include "migration/vmstate.h" |
| 20 | #include "qemu/module.h" |
| 21 | #include "qemu/log.h" |
| 22 | #include "trace.h" |
| 23 | |
| 24 | static const char *imx_gpt_reg_name(uint32_t reg) |
| 25 | { |
| 26 | switch (reg) { |
| 27 | case 0: |
| 28 | return "CR"; |
| 29 | case 1: |
| 30 | return "PR"; |
| 31 | case 2: |
| 32 | return "SR"; |
| 33 | case 3: |
| 34 | return "IR"; |
| 35 | case 4: |
| 36 | return "OCR1"; |
| 37 | case 5: |
| 38 | return "OCR2"; |
| 39 | case 6: |
| 40 | return "OCR3"; |
| 41 | case 7: |
| 42 | return "ICR1"; |
| 43 | case 8: |
| 44 | return "ICR2"; |
| 45 | case 9: |
| 46 | return "CNT"; |
| 47 | default: |
| 48 | return "[?]"; |
| 49 | } |
| 50 | } |
| 51 | |
| 52 | static const VMStateDescription vmstate_imx_timer_gpt = { |
| 53 | .name = TYPE_IMX_GPT, |
| 54 | .version_id = 3, |
| 55 | .minimum_version_id = 3, |
| 56 | .fields = (const VMStateField[]) { |
| 57 | VMSTATE_UINT32(cr, IMXGPTState), |
| 58 | VMSTATE_UINT32(pr, IMXGPTState), |
| 59 | VMSTATE_UINT32(sr, IMXGPTState), |
| 60 | VMSTATE_UINT32(ir, IMXGPTState), |
| 61 | VMSTATE_UINT32(ocr1, IMXGPTState), |
| 62 | VMSTATE_UINT32(ocr2, IMXGPTState), |
| 63 | VMSTATE_UINT32(ocr3, IMXGPTState), |
| 64 | VMSTATE_UINT32(icr1, IMXGPTState), |
| 65 | VMSTATE_UINT32(icr2, IMXGPTState), |
| 66 | VMSTATE_UINT32(cnt, IMXGPTState), |
| 67 | VMSTATE_UINT32(next_timeout, IMXGPTState), |
| 68 | VMSTATE_UINT32(next_int, IMXGPTState), |
| 69 | VMSTATE_UINT32(freq, IMXGPTState), |
| 70 | VMSTATE_PTIMER(timer, IMXGPTState), |
| 71 | VMSTATE_END_OF_LIST() |
| 72 | } |
| 73 | }; |
| 74 | |
| 75 | static const IMXClk imx25_gpt_clocks[] = { |
| 76 | CLK_NONE, /* 000 No clock source */ |
| 77 | CLK_IPG, /* 001 ipg_clk, 532MHz*/ |
| 78 | CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */ |
| 79 | CLK_NONE, /* 011 not defined */ |
| 80 | CLK_32k, /* 100 ipg_clk_32k */ |
| 81 | CLK_32k, /* 101 ipg_clk_32k */ |
| 82 | CLK_32k, /* 110 ipg_clk_32k */ |
| 83 | CLK_32k, /* 111 ipg_clk_32k */ |
| 84 | }; |
| 85 | |
| 86 | static const IMXClk imx31_gpt_clocks[] = { |
| 87 | CLK_NONE, /* 000 No clock source */ |
| 88 | CLK_IPG, /* 001 ipg_clk, 532MHz*/ |
| 89 | CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */ |
| 90 | CLK_NONE, /* 011 not defined */ |
| 91 | CLK_32k, /* 100 ipg_clk_32k */ |
| 92 | CLK_NONE, /* 101 not defined */ |
| 93 | CLK_NONE, /* 110 not defined */ |
| 94 | CLK_NONE, /* 111 not defined */ |
| 95 | }; |
| 96 | |
| 97 | static const IMXClk imx6_gpt_clocks[] = { |
| 98 | CLK_NONE, /* 000 No clock source */ |
| 99 | CLK_IPG, /* 001 ipg_clk, 532MHz*/ |
| 100 | CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */ |
| 101 | CLK_EXT, /* 011 External clock */ |
| 102 | CLK_32k, /* 100 ipg_clk_32k */ |
| 103 | CLK_HIGH_DIV, /* 101 reference clock / 8 */ |
| 104 | CLK_NONE, /* 110 not defined */ |
| 105 | CLK_HIGH, /* 111 reference clock */ |
| 106 | }; |
| 107 | |
| 108 | static const IMXClk imx6ul_gpt_clocks[] = { |
| 109 | CLK_NONE, /* 000 No clock source */ |
| 110 | CLK_IPG, /* 001 ipg_clk, 532MHz*/ |
| 111 | CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */ |
| 112 | CLK_EXT, /* 011 External clock */ |
| 113 | CLK_32k, /* 100 ipg_clk_32k */ |
| 114 | CLK_NONE, /* 101 not defined */ |
| 115 | CLK_NONE, /* 110 not defined */ |
| 116 | CLK_NONE, /* 111 not defined */ |
| 117 | }; |
| 118 | |
| 119 | static const IMXClk imx7_gpt_clocks[] = { |
| 120 | CLK_NONE, /* 000 No clock source */ |
| 121 | CLK_IPG, /* 001 ipg_clk, 532MHz*/ |
| 122 | CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */ |
| 123 | CLK_EXT, /* 011 External clock */ |
| 124 | CLK_32k, /* 100 ipg_clk_32k */ |
| 125 | CLK_HIGH, /* 101 reference clock */ |
| 126 | CLK_NONE, /* 110 not defined */ |
| 127 | CLK_NONE, /* 111 not defined */ |
| 128 | }; |
| 129 | |
| 130 | static const IMXClk imx8mp_gpt_clocks[] = { |
| 131 | CLK_NONE, /* 000 No clock source */ |
| 132 | CLK_IPG, /* 001 ipg_clk, 532MHz */ |
| 133 | CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */ |
| 134 | CLK_EXT, /* 011 External clock */ |
| 135 | CLK_32k, /* 100 ipg_clk_32k */ |
| 136 | CLK_HIGH, /* 101 ipg_clk_16M */ |
| 137 | CLK_NONE, /* 110 not defined */ |
| 138 | CLK_NONE, /* 111 not defined */ |
| 139 | }; |
| 140 | |
| 141 | static const IMXClk imx8mm_gpt_clocks[] = { |
| 142 | CLK_NONE, /* 000 No clock source */ |
| 143 | CLK_IPG, /* 001 ipg_clk, 532MHz */ |
| 144 | CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */ |
| 145 | CLK_EXT, /* 011 External clock */ |
| 146 | CLK_32k, /* 100 ipg_clk_32k */ |
| 147 | CLK_HIGH, /* 101 ipg_clk_16M */ |
| 148 | CLK_NONE, /* 110 not defined */ |
| 149 | CLK_NONE, /* 111 not defined */ |
| 150 | }; |
| 151 | |
| 152 | /* Must be called from within ptimer_transaction_begin/commit block */ |
| 153 | static void imx_gpt_set_freq(IMXGPTState *s) |
| 154 | { |
| 155 | uint32_t clksrc = extract32(s->cr, GPT_CR_CLKSRC_SHIFT, 3); |
| 156 | |
| 157 | s->freq = imx_ccm_get_clock_frequency(s->ccm, |
| 158 | s->clocks[clksrc]) / (1 + s->pr); |
| 159 | |
| 160 | trace_imx_gpt_set_freq(clksrc, s->freq); |
| 161 | |
| 162 | if (s->freq) { |
| 163 | ptimer_set_freq(s->timer, s->freq); |
| 164 | } |
| 165 | } |
| 166 | |
| 167 | static void imx_gpt_update_int(IMXGPTState *s) |
| 168 | { |
| 169 | if ((s->sr & s->ir) && (s->cr & GPT_CR_EN)) { |
| 170 | qemu_irq_raise(s->irq); |
| 171 | } else { |
| 172 | qemu_irq_lower(s->irq); |
| 173 | } |
| 174 | } |
| 175 | |
| 176 | static uint32_t imx_gpt_update_count(IMXGPTState *s) |
| 177 | { |
| 178 | s->cnt = s->next_timeout - (uint32_t)ptimer_get_count(s->timer); |
| 179 | |
| 180 | return s->cnt; |
| 181 | } |
| 182 | |
| 183 | static inline uint32_t imx_gpt_find_limit(uint32_t count, uint32_t reg, |
| 184 | uint32_t timeout) |
| 185 | { |
| 186 | if ((count < reg) && (timeout > reg)) { |
| 187 | timeout = reg; |
| 188 | } |
| 189 | |
| 190 | return timeout; |
| 191 | } |
| 192 | |
| 193 | /* Must be called from within ptimer_transaction_begin/commit block */ |
| 194 | static void imx_gpt_compute_next_timeout(IMXGPTState *s, bool event) |
| 195 | { |
| 196 | uint32_t timeout = GPT_TIMER_MAX; |
| 197 | uint32_t count; |
| 198 | long long limit; |
| 199 | |
| 200 | if (!(s->cr & GPT_CR_EN)) { |
| 201 | /* if not enabled just return */ |
| 202 | return; |
| 203 | } |
| 204 | |
| 205 | /* update the count */ |
| 206 | count = imx_gpt_update_count(s); |
| 207 | |
| 208 | if (event) { |
| 209 | /* |
| 210 | * This is an event (the ptimer reached 0 and stopped), and the |
| 211 | * timer counter is now equal to s->next_timeout. |
| 212 | */ |
| 213 | if (!(s->cr & GPT_CR_FRR) && (count == s->ocr1)) { |
| 214 | /* We are in restart mode and we crossed the compare channel 1 |
| 215 | * value. We need to reset the counter to 0. |
| 216 | */ |
| 217 | count = s->cnt = s->next_timeout = 0; |
| 218 | } else if (count == GPT_TIMER_MAX) { |
| 219 | /* We reached GPT_TIMER_MAX so we need to rollover */ |
| 220 | count = s->cnt = s->next_timeout = 0; |
| 221 | } |
| 222 | } |
| 223 | |
| 224 | /* now, find the next timeout related to count */ |
| 225 | |
| 226 | if (s->ir & GPT_IR_OF1IE) { |
| 227 | timeout = imx_gpt_find_limit(count, s->ocr1, timeout); |
| 228 | } |
| 229 | if (s->ir & GPT_IR_OF2IE) { |
| 230 | timeout = imx_gpt_find_limit(count, s->ocr2, timeout); |
| 231 | } |
| 232 | if (s->ir & GPT_IR_OF3IE) { |
| 233 | timeout = imx_gpt_find_limit(count, s->ocr3, timeout); |
| 234 | } |
| 235 | |
| 236 | /* find the next set of interrupts to raise for next timer event */ |
| 237 | |
| 238 | s->next_int = 0; |
| 239 | if ((s->ir & GPT_IR_OF1IE) && (timeout == s->ocr1)) { |
| 240 | s->next_int |= GPT_SR_OF1; |
| 241 | } |
| 242 | if ((s->ir & GPT_IR_OF2IE) && (timeout == s->ocr2)) { |
| 243 | s->next_int |= GPT_SR_OF2; |
| 244 | } |
| 245 | if ((s->ir & GPT_IR_OF3IE) && (timeout == s->ocr3)) { |
| 246 | s->next_int |= GPT_SR_OF3; |
| 247 | } |
| 248 | if ((s->ir & GPT_IR_ROVIE) && (timeout == GPT_TIMER_MAX)) { |
| 249 | s->next_int |= GPT_SR_ROV; |
| 250 | } |
| 251 | |
| 252 | /* the new range to count down from */ |
| 253 | limit = timeout - imx_gpt_update_count(s); |
| 254 | |
| 255 | if (limit < 0) { |
| 256 | /* |
| 257 | * if we reach here, then QEMU is running too slow and we pass the |
| 258 | * timeout limit while computing it. Let's deliver the interrupt |
| 259 | * and compute a new limit. |
| 260 | */ |
| 261 | s->sr |= s->next_int; |
| 262 | |
| 263 | imx_gpt_compute_next_timeout(s, event); |
| 264 | |
| 265 | imx_gpt_update_int(s); |
| 266 | } else { |
| 267 | /* New timeout value */ |
| 268 | s->next_timeout = timeout; |
| 269 | |
| 270 | /* reset the limit to the computed range */ |
| 271 | ptimer_set_limit(s->timer, limit, 1); |
| 272 | } |
| 273 | } |
| 274 | |
| 275 | static uint64_t imx_gpt_read(void *opaque, hwaddr offset, unsigned size) |
| 276 | { |
| 277 | IMXGPTState *s = IMX_GPT(opaque); |
| 278 | uint32_t reg_value = 0; |
| 279 | |
| 280 | switch (offset >> 2) { |
| 281 | case 0: /* Control Register */ |
| 282 | reg_value = s->cr; |
| 283 | break; |
| 284 | |
| 285 | case 1: /* prescaler */ |
| 286 | reg_value = s->pr; |
| 287 | break; |
| 288 | |
| 289 | case 2: /* Status Register */ |
| 290 | reg_value = s->sr; |
| 291 | break; |
| 292 | |
| 293 | case 3: /* Interrupt Register */ |
| 294 | reg_value = s->ir; |
| 295 | break; |
| 296 | |
| 297 | case 4: /* Output Compare Register 1 */ |
| 298 | reg_value = s->ocr1; |
| 299 | break; |
| 300 | |
| 301 | case 5: /* Output Compare Register 2 */ |
| 302 | reg_value = s->ocr2; |
| 303 | break; |
| 304 | |
| 305 | case 6: /* Output Compare Register 3 */ |
| 306 | reg_value = s->ocr3; |
| 307 | break; |
| 308 | |
| 309 | case 7: /* input Capture Register 1 */ |
| 310 | qemu_log_mask(LOG_UNIMP, "[%s]%s: icr1 feature is not implemented\n", |
| 311 | TYPE_IMX_GPT, __func__); |
| 312 | reg_value = s->icr1; |
| 313 | break; |
| 314 | |
| 315 | case 8: /* input Capture Register 2 */ |
| 316 | qemu_log_mask(LOG_UNIMP, "[%s]%s: icr2 feature is not implemented\n", |
| 317 | TYPE_IMX_GPT, __func__); |
| 318 | reg_value = s->icr2; |
| 319 | break; |
| 320 | |
| 321 | case 9: /* cnt */ |
| 322 | imx_gpt_update_count(s); |
| 323 | reg_value = s->cnt; |
| 324 | break; |
| 325 | |
| 326 | default: |
| 327 | qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" |
| 328 | HWADDR_PRIx "\n", TYPE_IMX_GPT, __func__, offset); |
| 329 | break; |
| 330 | } |
| 331 | |
| 332 | trace_imx_gpt_read(imx_gpt_reg_name(offset >> 2), reg_value); |
| 333 | |
| 334 | return reg_value; |
| 335 | } |
| 336 | |
| 337 | |
| 338 | static void imx_gpt_reset_common(IMXGPTState *s, bool is_soft_reset) |
| 339 | { |
| 340 | ptimer_transaction_begin(s->timer); |
| 341 | /* stop timer */ |
| 342 | ptimer_stop(s->timer); |
| 343 | |
| 344 | /* Soft reset and hard reset differ only in their handling of the CR |
| 345 | * register -- soft reset preserves the values of some bits there. |
| 346 | */ |
| 347 | if (is_soft_reset) { |
| 348 | /* Clear all CR bits except those that are preserved by soft reset. */ |
| 349 | s->cr &= GPT_CR_EN | GPT_CR_ENMOD | GPT_CR_STOPEN | GPT_CR_DOZEN | |
| 350 | GPT_CR_WAITEN | GPT_CR_DBGEN | |
| 351 | (GPT_CR_CLKSRC_MASK << GPT_CR_CLKSRC_SHIFT); |
| 352 | } else { |
| 353 | s->cr = 0; |
| 354 | } |
| 355 | s->sr = 0; |
| 356 | s->pr = 0; |
| 357 | s->ir = 0; |
| 358 | s->cnt = 0; |
| 359 | s->ocr1 = GPT_TIMER_MAX; |
| 360 | s->ocr2 = GPT_TIMER_MAX; |
| 361 | s->ocr3 = GPT_TIMER_MAX; |
| 362 | s->icr1 = 0; |
| 363 | s->icr2 = 0; |
| 364 | |
| 365 | s->next_timeout = GPT_TIMER_MAX; |
| 366 | s->next_int = 0; |
| 367 | |
| 368 | /* compute new freq */ |
| 369 | imx_gpt_set_freq(s); |
| 370 | |
| 371 | /* reset the limit to GPT_TIMER_MAX */ |
| 372 | ptimer_set_limit(s->timer, GPT_TIMER_MAX, 1); |
| 373 | |
| 374 | /* if the timer is still enabled, restart it */ |
| 375 | if (s->freq && (s->cr & GPT_CR_EN)) { |
| 376 | ptimer_run(s->timer, 1); |
| 377 | } |
| 378 | ptimer_transaction_commit(s->timer); |
| 379 | } |
| 380 | |
| 381 | static void imx_gpt_soft_reset(DeviceState *dev) |
| 382 | { |
| 383 | IMXGPTState *s = IMX_GPT(dev); |
| 384 | imx_gpt_reset_common(s, true); |
| 385 | } |
| 386 | |
| 387 | static void imx_gpt_reset(DeviceState *dev) |
| 388 | { |
| 389 | IMXGPTState *s = IMX_GPT(dev); |
| 390 | imx_gpt_reset_common(s, false); |
| 391 | } |
| 392 | |
| 393 | static void imx_gpt_write(void *opaque, hwaddr offset, uint64_t value, |
| 394 | unsigned size) |
| 395 | { |
| 396 | IMXGPTState *s = IMX_GPT(opaque); |
| 397 | uint32_t oldreg; |
| 398 | |
| 399 | trace_imx_gpt_write(imx_gpt_reg_name(offset >> 2), (uint32_t)value); |
| 400 | |
| 401 | switch (offset >> 2) { |
| 402 | case 0: |
| 403 | oldreg = s->cr; |
| 404 | s->cr = value & ~0x7c14; |
| 405 | if (s->cr & GPT_CR_SWR) { /* force reset */ |
| 406 | /* handle the reset */ |
| 407 | imx_gpt_soft_reset(DEVICE(s)); |
| 408 | } else { |
| 409 | /* set our freq, as the source might have changed */ |
| 410 | ptimer_transaction_begin(s->timer); |
| 411 | imx_gpt_set_freq(s); |
| 412 | |
| 413 | if ((oldreg ^ s->cr) & GPT_CR_EN) { |
| 414 | if (s->cr & GPT_CR_EN) { |
| 415 | if (s->cr & GPT_CR_ENMOD) { |
| 416 | s->next_timeout = GPT_TIMER_MAX; |
| 417 | ptimer_set_count(s->timer, GPT_TIMER_MAX); |
| 418 | imx_gpt_compute_next_timeout(s, false); |
| 419 | } |
| 420 | ptimer_run(s->timer, 1); |
| 421 | } else { |
| 422 | /* stop timer */ |
| 423 | ptimer_stop(s->timer); |
| 424 | } |
| 425 | } |
| 426 | ptimer_transaction_commit(s->timer); |
| 427 | } |
| 428 | break; |
| 429 | |
| 430 | case 1: /* Prescaler */ |
| 431 | s->pr = value & 0xfff; |
| 432 | ptimer_transaction_begin(s->timer); |
| 433 | imx_gpt_set_freq(s); |
| 434 | ptimer_transaction_commit(s->timer); |
| 435 | break; |
| 436 | |
| 437 | case 2: /* SR */ |
| 438 | s->sr &= ~(value & 0x3f); |
| 439 | imx_gpt_update_int(s); |
| 440 | break; |
| 441 | |
| 442 | case 3: /* IR -- interrupt register */ |
| 443 | s->ir = value & 0x3f; |
| 444 | imx_gpt_update_int(s); |
| 445 | |
| 446 | ptimer_transaction_begin(s->timer); |
| 447 | imx_gpt_compute_next_timeout(s, false); |
| 448 | ptimer_transaction_commit(s->timer); |
| 449 | |
| 450 | break; |
| 451 | |
| 452 | case 4: /* OCR1 -- output compare register */ |
| 453 | s->ocr1 = value; |
| 454 | |
| 455 | ptimer_transaction_begin(s->timer); |
| 456 | /* In non-freerun mode, reset count when this register is written */ |
| 457 | if (!(s->cr & GPT_CR_FRR)) { |
| 458 | s->next_timeout = GPT_TIMER_MAX; |
| 459 | ptimer_set_limit(s->timer, GPT_TIMER_MAX, 1); |
| 460 | } |
| 461 | |
| 462 | /* compute the new timeout */ |
| 463 | imx_gpt_compute_next_timeout(s, false); |
| 464 | ptimer_transaction_commit(s->timer); |
| 465 | |
| 466 | break; |
| 467 | |
| 468 | case 5: /* OCR2 -- output compare register */ |
| 469 | s->ocr2 = value; |
| 470 | |
| 471 | /* compute the new timeout */ |
| 472 | ptimer_transaction_begin(s->timer); |
| 473 | imx_gpt_compute_next_timeout(s, false); |
| 474 | ptimer_transaction_commit(s->timer); |
| 475 | |
| 476 | break; |
| 477 | |
| 478 | case 6: /* OCR3 -- output compare register */ |
| 479 | s->ocr3 = value; |
| 480 | |
| 481 | /* compute the new timeout */ |
| 482 | ptimer_transaction_begin(s->timer); |
| 483 | imx_gpt_compute_next_timeout(s, false); |
| 484 | ptimer_transaction_commit(s->timer); |
| 485 | |
| 486 | break; |
| 487 | |
| 488 | default: |
| 489 | qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" |
| 490 | HWADDR_PRIx "\n", TYPE_IMX_GPT, __func__, offset); |
| 491 | break; |
| 492 | } |
| 493 | } |
| 494 | |
| 495 | static void imx_gpt_timeout(void *opaque) |
| 496 | { |
| 497 | IMXGPTState *s = IMX_GPT(opaque); |
| 498 | |
| 499 | trace_imx_gpt_timeout(); |
| 500 | |
| 501 | s->sr |= s->next_int; |
| 502 | s->next_int = 0; |
| 503 | |
| 504 | imx_gpt_compute_next_timeout(s, true); |
| 505 | |
| 506 | imx_gpt_update_int(s); |
| 507 | |
| 508 | if (s->freq && (s->cr & GPT_CR_EN)) { |
| 509 | ptimer_run(s->timer, 1); |
| 510 | } |
| 511 | } |
| 512 | |
| 513 | static const MemoryRegionOps imx_gpt_ops = { |
| 514 | .read = imx_gpt_read, |
| 515 | .write = imx_gpt_write, |
| 516 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 517 | }; |
| 518 | |
| 519 | |
| 520 | static void imx_gpt_realize(DeviceState *dev, Error **errp) |
| 521 | { |
| 522 | IMXGPTState *s = IMX_GPT(dev); |
| 523 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
| 524 | |
| 525 | sysbus_init_irq(sbd, &s->irq); |
| 526 | memory_region_init_io(&s->iomem, OBJECT(s), &imx_gpt_ops, s, TYPE_IMX_GPT, |
| 527 | 0x00001000); |
| 528 | sysbus_init_mmio(sbd, &s->iomem); |
| 529 | |
| 530 | s->timer = ptimer_init(imx_gpt_timeout, s, PTIMER_POLICY_LEGACY); |
| 531 | } |
| 532 | |
| 533 | static void imx_gpt_class_init(ObjectClass *klass, const void *data) |
| 534 | { |
| 535 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 536 | |
| 537 | dc->realize = imx_gpt_realize; |
| 538 | device_class_set_legacy_reset(dc, imx_gpt_reset); |
| 539 | dc->vmsd = &vmstate_imx_timer_gpt; |
| 540 | dc->desc = "i.MX general timer"; |
| 541 | } |
| 542 | |
| 543 | static void imx25_gpt_init(Object *obj) |
| 544 | { |
| 545 | IMXGPTState *s = IMX_GPT(obj); |
| 546 | |
| 547 | s->clocks = imx25_gpt_clocks; |
| 548 | } |
| 549 | |
| 550 | static void imx31_gpt_init(Object *obj) |
| 551 | { |
| 552 | IMXGPTState *s = IMX_GPT(obj); |
| 553 | |
| 554 | s->clocks = imx31_gpt_clocks; |
| 555 | } |
| 556 | |
| 557 | static void imx6_gpt_init(Object *obj) |
| 558 | { |
| 559 | IMXGPTState *s = IMX_GPT(obj); |
| 560 | |
| 561 | s->clocks = imx6_gpt_clocks; |
| 562 | } |
| 563 | |
| 564 | static void imx6ul_gpt_init(Object *obj) |
| 565 | { |
| 566 | IMXGPTState *s = IMX_GPT(obj); |
| 567 | |
| 568 | s->clocks = imx6ul_gpt_clocks; |
| 569 | } |
| 570 | |
| 571 | static void imx7_gpt_init(Object *obj) |
| 572 | { |
| 573 | IMXGPTState *s = IMX_GPT(obj); |
| 574 | |
| 575 | s->clocks = imx7_gpt_clocks; |
| 576 | } |
| 577 | |
| 578 | static void imx8mp_gpt_init(Object *obj) |
| 579 | { |
| 580 | IMXGPTState *s = IMX_GPT(obj); |
| 581 | |
| 582 | s->clocks = imx8mp_gpt_clocks; |
| 583 | } |
| 584 | |
| 585 | static void imx8mm_gpt_init(Object *obj) |
| 586 | { |
| 587 | IMXGPTState *s = IMX_GPT(obj); |
| 588 | |
| 589 | s->clocks = imx8mm_gpt_clocks; |
| 590 | } |
| 591 | |
| 592 | static const TypeInfo imx25_gpt_info = { |
| 593 | .name = TYPE_IMX25_GPT, |
| 594 | .parent = TYPE_SYS_BUS_DEVICE, |
| 595 | .instance_size = sizeof(IMXGPTState), |
| 596 | .instance_init = imx25_gpt_init, |
| 597 | .class_init = imx_gpt_class_init, |
| 598 | }; |
| 599 | |
| 600 | static const TypeInfo imx31_gpt_info = { |
| 601 | .name = TYPE_IMX31_GPT, |
| 602 | .parent = TYPE_IMX25_GPT, |
| 603 | .instance_init = imx31_gpt_init, |
| 604 | }; |
| 605 | |
| 606 | static const TypeInfo imx6_gpt_info = { |
| 607 | .name = TYPE_IMX6_GPT, |
| 608 | .parent = TYPE_IMX25_GPT, |
| 609 | .instance_init = imx6_gpt_init, |
| 610 | }; |
| 611 | |
| 612 | static const TypeInfo imx6ul_gpt_info = { |
| 613 | .name = TYPE_IMX6UL_GPT, |
| 614 | .parent = TYPE_IMX25_GPT, |
| 615 | .instance_init = imx6ul_gpt_init, |
| 616 | }; |
| 617 | |
| 618 | static const TypeInfo imx7_gpt_info = { |
| 619 | .name = TYPE_IMX7_GPT, |
| 620 | .parent = TYPE_IMX25_GPT, |
| 621 | .instance_init = imx7_gpt_init, |
| 622 | }; |
| 623 | |
| 624 | static const TypeInfo imx8mp_gpt_info = { |
| 625 | .name = TYPE_IMX8MP_GPT, |
| 626 | .parent = TYPE_IMX25_GPT, |
| 627 | .instance_init = imx8mp_gpt_init, |
| 628 | }; |
| 629 | |
| 630 | static const TypeInfo imx8mm_gpt_info = { |
| 631 | .name = TYPE_IMX8MM_GPT, |
| 632 | .parent = TYPE_IMX25_GPT, |
| 633 | .instance_init = imx8mm_gpt_init, |
| 634 | }; |
| 635 | |
| 636 | static void imx_gpt_register_types(void) |
| 637 | { |
| 638 | type_register_static(&imx25_gpt_info); |
| 639 | type_register_static(&imx31_gpt_info); |
| 640 | type_register_static(&imx6_gpt_info); |
| 641 | type_register_static(&imx6ul_gpt_info); |
| 642 | type_register_static(&imx7_gpt_info); |
| 643 | type_register_static(&imx8mp_gpt_info); |
| 644 | type_register_static(&imx8mm_gpt_info); |
| 645 | } |
| 646 | |
| 647 | type_init(imx_gpt_register_types) |