| 1 | /* |
| 2 | * QEMU Sparc SLAVIO timer controller emulation |
| 3 | * |
| 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 7 | * of this software and associated documentation files (the "Software"), to deal |
| 8 | * in the Software without restriction, including without limitation the rights |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 10 | * copies of the Software, and to permit persons to whom the Software is |
| 11 | * furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 22 | * THE SOFTWARE. |
| 23 | */ |
| 24 | |
| 25 | #include "qemu/osdep.h" |
| 26 | #include "qemu/timer.h" |
| 27 | #include "hw/core/irq.h" |
| 28 | #include "hw/core/ptimer.h" |
| 29 | #include "hw/core/qdev-properties.h" |
| 30 | #include "hw/core/sysbus.h" |
| 31 | #include "migration/vmstate.h" |
| 32 | #include "trace.h" |
| 33 | #include "qemu/module.h" |
| 34 | #include "qom/object.h" |
| 35 | |
| 36 | /* |
| 37 | * Registers of hardware timer in sun4m. |
| 38 | * |
| 39 | * This is the timer/counter part of chip STP2001 (Slave I/O), also |
| 40 | * produced as NCR89C105. See |
| 41 | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt |
| 42 | * |
| 43 | * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0 |
| 44 | * are zero. Bit 31 is 1 when count has been reached. |
| 45 | * |
| 46 | * Per-CPU timers interrupt local CPU, system timer uses normal |
| 47 | * interrupt routing. |
| 48 | * |
| 49 | */ |
| 50 | |
| 51 | #define MAX_CPUS 16 |
| 52 | |
| 53 | typedef struct CPUTimerState { |
| 54 | qemu_irq irq; |
| 55 | ptimer_state *timer; |
| 56 | uint32_t count, counthigh, reached; |
| 57 | /* processor only */ |
| 58 | uint32_t run; |
| 59 | uint64_t limit; |
| 60 | } CPUTimerState; |
| 61 | |
| 62 | #define TYPE_SLAVIO_TIMER "slavio_timer" |
| 63 | OBJECT_DECLARE_SIMPLE_TYPE(SLAVIO_TIMERState, SLAVIO_TIMER) |
| 64 | |
| 65 | typedef struct TimerContext { |
| 66 | MemoryRegion iomem; |
| 67 | SLAVIO_TIMERState *s; |
| 68 | unsigned int timer_index; /* 0 for system, 1 ... MAX_CPUS for CPU timers */ |
| 69 | } TimerContext; |
| 70 | |
| 71 | struct SLAVIO_TIMERState { |
| 72 | SysBusDevice parent_obj; |
| 73 | |
| 74 | uint32_t num_cpus; |
| 75 | uint32_t cputimer_mode; |
| 76 | CPUTimerState cputimer[MAX_CPUS + 1]; |
| 77 | TimerContext timer_context[MAX_CPUS + 1]; |
| 78 | }; |
| 79 | |
| 80 | #define SYS_TIMER_SIZE 0x14 |
| 81 | #define CPU_TIMER_SIZE 0x10 |
| 82 | |
| 83 | #define TIMER_LIMIT 0 |
| 84 | #define TIMER_COUNTER 1 |
| 85 | #define TIMER_COUNTER_NORST 2 |
| 86 | #define TIMER_STATUS 3 |
| 87 | #define TIMER_MODE 4 |
| 88 | |
| 89 | #define TIMER_COUNT_MASK32 0xfffffe00 |
| 90 | #define TIMER_LIMIT_MASK32 0x7fffffff |
| 91 | #define TIMER_MAX_COUNT64 0x7ffffffffffffe00ULL |
| 92 | #define TIMER_MAX_COUNT32 0x7ffffe00ULL |
| 93 | #define TIMER_REACHED 0x80000000 |
| 94 | #define TIMER_PERIOD 500ULL // 500ns |
| 95 | #define LIMIT_TO_PERIODS(l) (((l) >> 9) - 1) |
| 96 | #define PERIODS_TO_LIMIT(l) (((l) + 1) << 9) |
| 97 | |
| 98 | static int slavio_timer_is_user(TimerContext *tc) |
| 99 | { |
| 100 | SLAVIO_TIMERState *s = tc->s; |
| 101 | unsigned int timer_index = tc->timer_index; |
| 102 | |
| 103 | return timer_index != 0 && (s->cputimer_mode & (1 << (timer_index - 1))); |
| 104 | } |
| 105 | |
| 106 | // Update count, set irq, update expire_time |
| 107 | // Convert from ptimer countdown units |
| 108 | static void slavio_timer_get_out(CPUTimerState *t) |
| 109 | { |
| 110 | uint64_t count, limit; |
| 111 | |
| 112 | if (t->limit == 0) { /* free-run system or processor counter */ |
| 113 | limit = TIMER_MAX_COUNT32; |
| 114 | } else { |
| 115 | limit = t->limit; |
| 116 | } |
| 117 | count = limit - PERIODS_TO_LIMIT(ptimer_get_count(t->timer)); |
| 118 | |
| 119 | trace_slavio_timer_get_out(t->limit, t->counthigh, t->count); |
| 120 | t->count = count & TIMER_COUNT_MASK32; |
| 121 | t->counthigh = count >> 32; |
| 122 | } |
| 123 | |
| 124 | // timer callback |
| 125 | static void slavio_timer_irq(void *opaque) |
| 126 | { |
| 127 | TimerContext *tc = opaque; |
| 128 | SLAVIO_TIMERState *s = tc->s; |
| 129 | CPUTimerState *t = &s->cputimer[tc->timer_index]; |
| 130 | |
| 131 | slavio_timer_get_out(t); |
| 132 | trace_slavio_timer_irq(t->counthigh, t->count); |
| 133 | /* if limit is 0 (free-run), there will be no match */ |
| 134 | if (t->limit != 0) { |
| 135 | t->reached = TIMER_REACHED; |
| 136 | } |
| 137 | /* there is no interrupt if user timer or free-run */ |
| 138 | if (!slavio_timer_is_user(tc) && t->limit != 0) { |
| 139 | qemu_irq_raise(t->irq); |
| 140 | } |
| 141 | } |
| 142 | |
| 143 | static uint64_t slavio_timer_mem_readl(void *opaque, hwaddr addr, |
| 144 | unsigned size) |
| 145 | { |
| 146 | TimerContext *tc = opaque; |
| 147 | SLAVIO_TIMERState *s = tc->s; |
| 148 | uint32_t saddr, ret; |
| 149 | unsigned int timer_index = tc->timer_index; |
| 150 | CPUTimerState *t = &s->cputimer[timer_index]; |
| 151 | |
| 152 | saddr = addr >> 2; |
| 153 | switch (saddr) { |
| 154 | case TIMER_LIMIT: |
| 155 | // read limit (system counter mode) or read most signifying |
| 156 | // part of counter (user mode) |
| 157 | if (slavio_timer_is_user(tc)) { |
| 158 | // read user timer MSW |
| 159 | slavio_timer_get_out(t); |
| 160 | ret = t->counthigh | t->reached; |
| 161 | } else { |
| 162 | // read limit |
| 163 | // clear irq |
| 164 | qemu_irq_lower(t->irq); |
| 165 | t->reached = 0; |
| 166 | ret = t->limit & TIMER_LIMIT_MASK32; |
| 167 | } |
| 168 | break; |
| 169 | case TIMER_COUNTER: |
| 170 | // read counter and reached bit (system mode) or read lsbits |
| 171 | // of counter (user mode) |
| 172 | slavio_timer_get_out(t); |
| 173 | if (slavio_timer_is_user(tc)) { // read user timer LSW |
| 174 | ret = t->count & TIMER_MAX_COUNT64; |
| 175 | } else { // read limit |
| 176 | ret = (t->count & TIMER_MAX_COUNT32) | |
| 177 | t->reached; |
| 178 | } |
| 179 | break; |
| 180 | case TIMER_STATUS: |
| 181 | // only available in processor counter/timer |
| 182 | // read start/stop status |
| 183 | if (timer_index > 0) { |
| 184 | ret = t->run; |
| 185 | } else { |
| 186 | ret = 0; |
| 187 | } |
| 188 | break; |
| 189 | case TIMER_MODE: |
| 190 | // only available in system counter |
| 191 | // read user/system mode |
| 192 | ret = s->cputimer_mode; |
| 193 | break; |
| 194 | default: |
| 195 | trace_slavio_timer_mem_readl_invalid(addr); |
| 196 | ret = 0; |
| 197 | break; |
| 198 | } |
| 199 | trace_slavio_timer_mem_readl(addr, ret); |
| 200 | return ret; |
| 201 | } |
| 202 | |
| 203 | static void slavio_timer_mem_writel(void *opaque, hwaddr addr, |
| 204 | uint64_t val, unsigned size) |
| 205 | { |
| 206 | TimerContext *tc = opaque; |
| 207 | SLAVIO_TIMERState *s = tc->s; |
| 208 | uint32_t saddr; |
| 209 | unsigned int timer_index = tc->timer_index; |
| 210 | CPUTimerState *t = &s->cputimer[timer_index]; |
| 211 | |
| 212 | trace_slavio_timer_mem_writel(addr, val); |
| 213 | saddr = addr >> 2; |
| 214 | switch (saddr) { |
| 215 | case TIMER_LIMIT: |
| 216 | ptimer_transaction_begin(t->timer); |
| 217 | if (slavio_timer_is_user(tc)) { |
| 218 | uint64_t count; |
| 219 | |
| 220 | // set user counter MSW, reset counter |
| 221 | t->limit = TIMER_MAX_COUNT64; |
| 222 | t->counthigh = val & (TIMER_MAX_COUNT64 >> 32); |
| 223 | t->reached = 0; |
| 224 | count = ((uint64_t)t->counthigh << 32) | t->count; |
| 225 | trace_slavio_timer_mem_writel_limit(timer_index, count); |
| 226 | ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count)); |
| 227 | } else { |
| 228 | // set limit, reset counter |
| 229 | qemu_irq_lower(t->irq); |
| 230 | t->limit = val & TIMER_MAX_COUNT32; |
| 231 | if (t->limit == 0) { /* free-run */ |
| 232 | ptimer_set_limit(t->timer, |
| 233 | LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1); |
| 234 | } else { |
| 235 | ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 1); |
| 236 | } |
| 237 | } |
| 238 | ptimer_transaction_commit(t->timer); |
| 239 | break; |
| 240 | case TIMER_COUNTER: |
| 241 | if (slavio_timer_is_user(tc)) { |
| 242 | uint64_t count; |
| 243 | |
| 244 | // set user counter LSW, reset counter |
| 245 | t->limit = TIMER_MAX_COUNT64; |
| 246 | t->count = val & TIMER_MAX_COUNT64; |
| 247 | t->reached = 0; |
| 248 | count = ((uint64_t)t->counthigh) << 32 | t->count; |
| 249 | trace_slavio_timer_mem_writel_limit(timer_index, count); |
| 250 | ptimer_transaction_begin(t->timer); |
| 251 | ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count)); |
| 252 | ptimer_transaction_commit(t->timer); |
| 253 | } else { |
| 254 | trace_slavio_timer_mem_writel_counter_invalid(); |
| 255 | } |
| 256 | break; |
| 257 | case TIMER_COUNTER_NORST: |
| 258 | // set limit without resetting counter |
| 259 | t->limit = val & TIMER_MAX_COUNT32; |
| 260 | ptimer_transaction_begin(t->timer); |
| 261 | if (t->limit == 0) { /* free-run */ |
| 262 | ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 0); |
| 263 | } else { |
| 264 | ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 0); |
| 265 | } |
| 266 | ptimer_transaction_commit(t->timer); |
| 267 | break; |
| 268 | case TIMER_STATUS: |
| 269 | ptimer_transaction_begin(t->timer); |
| 270 | if (slavio_timer_is_user(tc)) { |
| 271 | // start/stop user counter |
| 272 | if (val & 1) { |
| 273 | trace_slavio_timer_mem_writel_status_start(timer_index); |
| 274 | ptimer_run(t->timer, 0); |
| 275 | } else { |
| 276 | trace_slavio_timer_mem_writel_status_stop(timer_index); |
| 277 | ptimer_stop(t->timer); |
| 278 | } |
| 279 | } |
| 280 | t->run = val & 1; |
| 281 | ptimer_transaction_commit(t->timer); |
| 282 | break; |
| 283 | case TIMER_MODE: |
| 284 | if (timer_index == 0) { |
| 285 | unsigned int i; |
| 286 | |
| 287 | for (i = 0; i < s->num_cpus; i++) { |
| 288 | unsigned int processor = 1 << i; |
| 289 | CPUTimerState *curr_timer = &s->cputimer[i + 1]; |
| 290 | |
| 291 | ptimer_transaction_begin(curr_timer->timer); |
| 292 | // check for a change in timer mode for this processor |
| 293 | if ((val & processor) != (s->cputimer_mode & processor)) { |
| 294 | if (val & processor) { // counter -> user timer |
| 295 | qemu_irq_lower(curr_timer->irq); |
| 296 | // counters are always running |
| 297 | if (!curr_timer->run) { |
| 298 | ptimer_stop(curr_timer->timer); |
| 299 | } |
| 300 | // user timer limit is always the same |
| 301 | curr_timer->limit = TIMER_MAX_COUNT64; |
| 302 | ptimer_set_limit(curr_timer->timer, |
| 303 | LIMIT_TO_PERIODS(curr_timer->limit), |
| 304 | 1); |
| 305 | // set this processors user timer bit in config |
| 306 | // register |
| 307 | s->cputimer_mode |= processor; |
| 308 | trace_slavio_timer_mem_writel_mode_user(timer_index); |
| 309 | } else { // user timer -> counter |
| 310 | // start the counter |
| 311 | ptimer_run(curr_timer->timer, 0); |
| 312 | // clear this processors user timer bit in config |
| 313 | // register |
| 314 | s->cputimer_mode &= ~processor; |
| 315 | trace_slavio_timer_mem_writel_mode_counter(timer_index); |
| 316 | } |
| 317 | } |
| 318 | ptimer_transaction_commit(curr_timer->timer); |
| 319 | } |
| 320 | } else { |
| 321 | trace_slavio_timer_mem_writel_mode_invalid(); |
| 322 | } |
| 323 | break; |
| 324 | default: |
| 325 | trace_slavio_timer_mem_writel_invalid(addr); |
| 326 | break; |
| 327 | } |
| 328 | } |
| 329 | |
| 330 | static const MemoryRegionOps slavio_timer_mem_ops = { |
| 331 | .read = slavio_timer_mem_readl, |
| 332 | .write = slavio_timer_mem_writel, |
| 333 | .endianness = DEVICE_BIG_ENDIAN, |
| 334 | .valid = { |
| 335 | .min_access_size = 4, |
| 336 | .max_access_size = 8, |
| 337 | }, |
| 338 | .impl = { |
| 339 | .min_access_size = 4, |
| 340 | .max_access_size = 4, |
| 341 | }, |
| 342 | }; |
| 343 | |
| 344 | static const VMStateDescription vmstate_timer = { |
| 345 | .name ="timer", |
| 346 | .version_id = 3, |
| 347 | .minimum_version_id = 3, |
| 348 | .fields = (const VMStateField[]) { |
| 349 | VMSTATE_UINT64(limit, CPUTimerState), |
| 350 | VMSTATE_UINT32(count, CPUTimerState), |
| 351 | VMSTATE_UINT32(counthigh, CPUTimerState), |
| 352 | VMSTATE_UINT32(reached, CPUTimerState), |
| 353 | VMSTATE_UINT32(run , CPUTimerState), |
| 354 | VMSTATE_PTIMER(timer, CPUTimerState), |
| 355 | VMSTATE_END_OF_LIST() |
| 356 | } |
| 357 | }; |
| 358 | |
| 359 | static const VMStateDescription vmstate_slavio_timer = { |
| 360 | .name ="slavio_timer", |
| 361 | .version_id = 3, |
| 362 | .minimum_version_id = 3, |
| 363 | .fields = (const VMStateField[]) { |
| 364 | VMSTATE_STRUCT_ARRAY(cputimer, SLAVIO_TIMERState, MAX_CPUS + 1, 3, |
| 365 | vmstate_timer, CPUTimerState), |
| 366 | VMSTATE_END_OF_LIST() |
| 367 | } |
| 368 | }; |
| 369 | |
| 370 | static void slavio_timer_reset(DeviceState *d) |
| 371 | { |
| 372 | SLAVIO_TIMERState *s = SLAVIO_TIMER(d); |
| 373 | unsigned int i; |
| 374 | CPUTimerState *curr_timer; |
| 375 | |
| 376 | for (i = 0; i <= MAX_CPUS; i++) { |
| 377 | curr_timer = &s->cputimer[i]; |
| 378 | curr_timer->limit = 0; |
| 379 | curr_timer->count = 0; |
| 380 | curr_timer->reached = 0; |
| 381 | if (i <= s->num_cpus) { |
| 382 | ptimer_transaction_begin(curr_timer->timer); |
| 383 | ptimer_set_limit(curr_timer->timer, |
| 384 | LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1); |
| 385 | ptimer_run(curr_timer->timer, 0); |
| 386 | curr_timer->run = 1; |
| 387 | ptimer_transaction_commit(curr_timer->timer); |
| 388 | } |
| 389 | } |
| 390 | s->cputimer_mode = 0; |
| 391 | } |
| 392 | |
| 393 | static void slavio_timer_init(Object *obj) |
| 394 | { |
| 395 | SLAVIO_TIMERState *s = SLAVIO_TIMER(obj); |
| 396 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); |
| 397 | unsigned int i; |
| 398 | TimerContext *tc; |
| 399 | |
| 400 | for (i = 0; i <= MAX_CPUS; i++) { |
| 401 | uint64_t size; |
| 402 | char timer_name[20]; |
| 403 | |
| 404 | tc = &s->timer_context[i]; |
| 405 | tc->s = s; |
| 406 | tc->timer_index = i; |
| 407 | |
| 408 | s->cputimer[i].timer = ptimer_init(slavio_timer_irq, tc, |
| 409 | PTIMER_POLICY_LEGACY); |
| 410 | ptimer_transaction_begin(s->cputimer[i].timer); |
| 411 | ptimer_set_period(s->cputimer[i].timer, TIMER_PERIOD); |
| 412 | ptimer_transaction_commit(s->cputimer[i].timer); |
| 413 | |
| 414 | size = i == 0 ? SYS_TIMER_SIZE : CPU_TIMER_SIZE; |
| 415 | snprintf(timer_name, sizeof(timer_name), "timer-%i", i); |
| 416 | memory_region_init_io(&tc->iomem, obj, &slavio_timer_mem_ops, tc, |
| 417 | timer_name, size); |
| 418 | sysbus_init_mmio(dev, &tc->iomem); |
| 419 | |
| 420 | sysbus_init_irq(dev, &s->cputimer[i].irq); |
| 421 | } |
| 422 | } |
| 423 | |
| 424 | static void slavio_timer_finalize(Object *obj) |
| 425 | { |
| 426 | SLAVIO_TIMERState *s = SLAVIO_TIMER(obj); |
| 427 | |
| 428 | for (int i = 0; i <= MAX_CPUS; i++) { |
| 429 | ptimer_free(s->cputimer[i].timer); |
| 430 | } |
| 431 | } |
| 432 | |
| 433 | static const Property slavio_timer_properties[] = { |
| 434 | DEFINE_PROP_UINT32("num_cpus", SLAVIO_TIMERState, num_cpus, 0), |
| 435 | }; |
| 436 | |
| 437 | static void slavio_timer_class_init(ObjectClass *klass, const void *data) |
| 438 | { |
| 439 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 440 | |
| 441 | device_class_set_legacy_reset(dc, slavio_timer_reset); |
| 442 | dc->vmsd = &vmstate_slavio_timer; |
| 443 | device_class_set_props(dc, slavio_timer_properties); |
| 444 | } |
| 445 | |
| 446 | static const TypeInfo slavio_timer_info = { |
| 447 | .name = TYPE_SLAVIO_TIMER, |
| 448 | .parent = TYPE_SYS_BUS_DEVICE, |
| 449 | .instance_size = sizeof(SLAVIO_TIMERState), |
| 450 | .instance_init = slavio_timer_init, |
| 451 | .instance_finalize = slavio_timer_finalize, |
| 452 | .class_init = slavio_timer_class_init, |
| 453 | }; |
| 454 | |
| 455 | static void slavio_timer_register_types(void) |
| 456 | { |
| 457 | type_register_static(&slavio_timer_info); |
| 458 | } |
| 459 | |
| 460 | type_init(slavio_timer_register_types) |