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1 /*
2 * QEMU Universal Flash Storage (UFS) Controller
3 *
4 * Copyright (c) 2023 Samsung Electronics Co., Ltd. All rights reserved.
5 *
6 * Written by Jeuk Kim <jeuk20.kim@samsung.com>
7 *
8 * SPDX-License-Identifier: GPL-2.0-or-later
9 */
10
11 /**
12 * Reference Specs: https://www.jedec.org/, 4.1
13 *
14 */
15
16 #include "qemu/osdep.h"
17 #include "qapi/error.h"
18 #include "scsi/constants.h"
19 #include "hw/core/irq.h"
20 #include "trace.h"
21 #include "ufs.h"
22
23 /* The QEMU-UFS device follows spec version 4.1 */
24 #define UFS_SPEC_VER 0x0410
25 #define UFS_MAX_NUTRS 32
26 #define UFS_MAX_NUTMRS 8
27 #define UFS_MCQ_QCFGPTR 2
28
29 /* Each value represents the temperature in celsius as (value - 80) */
30 #define UFS_TEMPERATURE 120
31 #define UFS_TOO_HIGH_TEMP_BOUNDARY 160
32 #define UFS_TOO_LOW_TEMP_BOUNDARY 60
33
34 #define UFS_HID_DEFRAG_BATCH_DIV 10 /* ~10% of remaining per tick */
35 #define UFS_HID_PROGRESS_COMPLETE 100
36
37 static void ufs_exec_req(UfsRequest *req);
38 static void ufs_clear_req(UfsRequest *req);
39
40 static inline uint64_t ufs_mcq_reg_addr(UfsHc *u, int qid)
41 {
42 /* Submission Queue MCQ Registers offset (400h) */
43 return (UFS_MCQ_QCFGPTR * 0x200) + qid * 0x40;
44 }
45
46 static inline uint64_t ufs_mcq_op_reg_addr(UfsHc *u, int qid)
47 {
48 /* MCQ Operation & Runtime Registers offset (1000h) */
49 return UFS_MCQ_OPR_START + qid * 48;
50 }
51
52 static inline uint64_t ufs_reg_size(UfsHc *u)
53 {
54 /* Total UFS HCI Register size in bytes */
55 return ufs_mcq_op_reg_addr(u, 0) + sizeof(u->mcq_op_reg);
56 }
57
58 static inline bool ufs_is_mcq_reg(UfsHc *u, uint64_t addr, unsigned size)
59 {
60 uint64_t mcq_reg_addr;
61
62 if (!u->params.mcq) {
63 return false;
64 }
65
66 mcq_reg_addr = ufs_mcq_reg_addr(u, 0);
67 return (addr >= mcq_reg_addr &&
68 addr + size <= mcq_reg_addr + sizeof(u->mcq_reg));
69 }
70
71 static inline bool ufs_is_mcq_op_reg(UfsHc *u, uint64_t addr, unsigned size)
72 {
73 uint64_t mcq_op_reg_addr;
74
75 if (!u->params.mcq) {
76 return false;
77 }
78
79 mcq_op_reg_addr = ufs_mcq_op_reg_addr(u, 0);
80 return (addr >= mcq_op_reg_addr &&
81 addr + size <= mcq_op_reg_addr + sizeof(u->mcq_op_reg));
82 }
83
84 static MemTxResult ufs_addr_read(UfsHc *u, hwaddr addr, void *buf, int size)
85 {
86 hwaddr hi = addr + size - 1;
87
88 if (hi < addr) {
89 return MEMTX_DECODE_ERROR;
90 }
91
92 if (!FIELD_EX32(u->reg.cap, CAP, 64AS) && (hi >> 32)) {
93 return MEMTX_DECODE_ERROR;
94 }
95
96 return dma_memory_read(u->dma_as, addr, buf, size, MEMTXATTRS_UNSPECIFIED);
97 }
98
99 static MemTxResult ufs_addr_write(UfsHc *u, hwaddr addr, const void *buf,
100 int size)
101 {
102 hwaddr hi = addr + size - 1;
103 if (hi < addr) {
104 return MEMTX_DECODE_ERROR;
105 }
106
107 if (!FIELD_EX32(u->reg.cap, CAP, 64AS) && (hi >> 32)) {
108 return MEMTX_DECODE_ERROR;
109 }
110
111 return dma_memory_write(u->dma_as, addr, buf, size, MEMTXATTRS_UNSPECIFIED);
112 }
113
114 static inline hwaddr ufs_get_utrd_addr(UfsHc *u, uint32_t slot)
115 {
116 hwaddr utrl_base_addr = (((hwaddr)u->reg.utrlbau) << 32) + u->reg.utrlba;
117 hwaddr utrd_addr = utrl_base_addr + slot * sizeof(UtpTransferReqDesc);
118
119 return utrd_addr;
120 }
121
122 static inline hwaddr ufs_get_req_upiu_base_addr(const UtpTransferReqDesc *utrd)
123 {
124 uint32_t cmd_desc_base_addr_lo =
125 le32_to_cpu(utrd->command_desc_base_addr_lo);
126 uint32_t cmd_desc_base_addr_hi =
127 le32_to_cpu(utrd->command_desc_base_addr_hi);
128
129 return (((hwaddr)cmd_desc_base_addr_hi) << 32) + cmd_desc_base_addr_lo;
130 }
131
132 static inline hwaddr ufs_get_rsp_upiu_base_addr(const UtpTransferReqDesc *utrd)
133 {
134 hwaddr req_upiu_base_addr = ufs_get_req_upiu_base_addr(utrd);
135 uint32_t rsp_upiu_byte_off =
136 le16_to_cpu(utrd->response_upiu_offset) * sizeof(uint32_t);
137 return req_upiu_base_addr + rsp_upiu_byte_off;
138 }
139
140 static MemTxResult ufs_dma_read_utrd(UfsRequest *req)
141 {
142 UfsHc *u = req->hc;
143 hwaddr utrd_addr = ufs_get_utrd_addr(u, req->slot);
144 MemTxResult ret;
145
146 ret = ufs_addr_read(u, utrd_addr, &req->utrd, sizeof(req->utrd));
147 if (ret) {
148 trace_ufs_err_dma_read_utrd(req->slot, utrd_addr);
149 }
150 return ret;
151 }
152
153 static MemTxResult ufs_dma_read_req_upiu(UfsRequest *req)
154 {
155 UfsHc *u = req->hc;
156 hwaddr req_upiu_base_addr = ufs_get_req_upiu_base_addr(&req->utrd);
157 UtpUpiuReq *req_upiu = &req->req_upiu;
158 uint32_t copy_size;
159 uint16_t data_segment_length;
160 MemTxResult ret;
161
162 /*
163 * To know the size of the req_upiu, we need to read the
164 * data_segment_length in the header first.
165 */
166 ret = ufs_addr_read(u, req_upiu_base_addr, &req_upiu->header,
167 sizeof(UtpUpiuHeader));
168 if (ret) {
169 trace_ufs_err_dma_read_req_upiu(req->slot, req_upiu_base_addr);
170 return ret;
171 }
172 data_segment_length = be16_to_cpu(req_upiu->header.data_segment_length);
173
174 copy_size = sizeof(UtpUpiuHeader) + UFS_TRANSACTION_SPECIFIC_FIELD_SIZE +
175 data_segment_length;
176
177 if (copy_size > sizeof(req->req_upiu)) {
178 copy_size = sizeof(req->req_upiu);
179 }
180
181 ret = ufs_addr_read(u, req_upiu_base_addr, &req->req_upiu, copy_size);
182 if (ret) {
183 trace_ufs_err_dma_read_req_upiu(req->slot, req_upiu_base_addr);
184 }
185 return ret;
186 }
187
188 static MemTxResult ufs_dma_read_prdt(UfsRequest *req)
189 {
190 UfsHc *u = req->hc;
191 uint16_t prdt_len = le16_to_cpu(req->utrd.prd_table_length);
192 uint16_t prdt_byte_off =
193 le16_to_cpu(req->utrd.prd_table_offset) * sizeof(uint32_t);
194 uint32_t prdt_size = prdt_len * sizeof(UfshcdSgEntry);
195 g_autofree UfshcdSgEntry *prd_entries = NULL;
196 hwaddr req_upiu_base_addr, prdt_base_addr;
197 int err;
198
199 assert(!req->sg);
200
201 if (prdt_size == 0) {
202 return MEMTX_OK;
203 }
204 prd_entries = g_new(UfshcdSgEntry, prdt_size);
205
206 req_upiu_base_addr = ufs_get_req_upiu_base_addr(&req->utrd);
207 prdt_base_addr = req_upiu_base_addr + prdt_byte_off;
208
209 err = ufs_addr_read(u, prdt_base_addr, prd_entries, prdt_size);
210 if (err) {
211 trace_ufs_err_dma_read_prdt(req->slot, prdt_base_addr);
212 return err;
213 }
214
215 req->sg = g_malloc0(sizeof(QEMUSGList));
216 qemu_sglist_init(req->sg, u->dev, prdt_len, u->dma_as);
217 req->data_len = 0;
218
219 for (uint16_t i = 0; i < prdt_len; ++i) {
220 hwaddr data_dma_addr = le64_to_cpu(prd_entries[i].addr);
221 uint32_t data_byte_count =
222 (le32_to_cpu(prd_entries[i].size) & 0x3ffff) + 1;
223 qemu_sglist_add(req->sg, data_dma_addr, data_byte_count);
224 req->data_len += data_byte_count;
225 }
226 return MEMTX_OK;
227 }
228
229 static MemTxResult ufs_dma_read_upiu(UfsRequest *req)
230 {
231 MemTxResult ret;
232
233 /*
234 * In case of MCQ, UTRD has already been read from a SQ, so skip it.
235 */
236 if (!ufs_mcq_req(req)) {
237 ret = ufs_dma_read_utrd(req);
238 if (ret) {
239 return ret;
240 }
241 }
242
243 ret = ufs_dma_read_req_upiu(req);
244 if (ret) {
245 return ret;
246 }
247
248 ret = ufs_dma_read_prdt(req);
249 if (ret) {
250 return ret;
251 }
252
253 return 0;
254 }
255
256 static MemTxResult ufs_dma_write_utrd(UfsRequest *req)
257 {
258 UfsHc *u = req->hc;
259 hwaddr utrd_addr = ufs_get_utrd_addr(u, req->slot);
260 MemTxResult ret;
261
262 ret = ufs_addr_write(u, utrd_addr, &req->utrd, sizeof(req->utrd));
263 if (ret) {
264 trace_ufs_err_dma_write_utrd(req->slot, utrd_addr);
265 }
266 return ret;
267 }
268
269 static MemTxResult ufs_dma_write_rsp_upiu(UfsRequest *req)
270 {
271 UfsHc *u = req->hc;
272 hwaddr rsp_upiu_base_addr = ufs_get_rsp_upiu_base_addr(&req->utrd);
273 uint32_t rsp_upiu_byte_len =
274 le16_to_cpu(req->utrd.response_upiu_length) * sizeof(uint32_t);
275 uint16_t data_segment_length =
276 be16_to_cpu(req->rsp_upiu.header.data_segment_length);
277 uint32_t copy_size = sizeof(UtpUpiuHeader) +
278 UFS_TRANSACTION_SPECIFIC_FIELD_SIZE +
279 data_segment_length;
280 MemTxResult ret;
281
282 if (copy_size > rsp_upiu_byte_len) {
283 copy_size = rsp_upiu_byte_len;
284 }
285
286 if (copy_size > sizeof(req->rsp_upiu)) {
287 copy_size = sizeof(req->rsp_upiu);
288 }
289
290 ret = ufs_addr_write(u, rsp_upiu_base_addr, &req->rsp_upiu, copy_size);
291 if (ret) {
292 trace_ufs_err_dma_write_rsp_upiu(req->slot, rsp_upiu_base_addr);
293 }
294 return ret;
295 }
296
297 static MemTxResult ufs_dma_write_upiu(UfsRequest *req)
298 {
299 MemTxResult ret;
300
301 ret = ufs_dma_write_rsp_upiu(req);
302 if (ret) {
303 return ret;
304 }
305
306 return ufs_dma_write_utrd(req);
307 }
308
309 static void ufs_irq_check(UfsHc *u)
310 {
311 if ((u->reg.is & UFS_INTR_MASK) & u->reg.ie) {
312 trace_ufs_irq_raise();
313 qemu_irq_raise(u->irq);
314 } else {
315 trace_ufs_irq_lower();
316 qemu_irq_lower(u->irq);
317 }
318 }
319
320 static void ufs_process_db(UfsHc *u, uint32_t val)
321 {
322 DECLARE_BITMAP(doorbell, UFS_MAX_NUTRS);
323 uint32_t slot;
324 uint32_t nutrs = u->params.nutrs;
325 UfsRequest *req;
326
327 val &= ~u->reg.utrldbr;
328 if (!val) {
329 return;
330 }
331
332 doorbell[0] = val;
333 slot = find_first_bit(doorbell, nutrs);
334
335 while (slot < nutrs) {
336 req = &u->req_list[slot];
337 if (req->state == UFS_REQUEST_ERROR) {
338 trace_ufs_err_utrl_slot_error(req->slot);
339 return;
340 }
341
342 if (req->state != UFS_REQUEST_IDLE) {
343 trace_ufs_err_utrl_slot_busy(req->slot);
344 return;
345 }
346
347 trace_ufs_process_db(slot);
348 req->state = UFS_REQUEST_READY;
349 slot = find_next_bit(doorbell, nutrs, slot + 1);
350 }
351
352 qemu_bh_schedule(u->doorbell_bh);
353 }
354
355 /*
356 * Return canned PA layer attribute values. The emulated link has no PHY,
357 * so these are purely declarative: a single lane in HS-Gear 4, FAST_MODE.
358 */
359 static uint32_t ufs_uic_dme_get_value(uint16_t attr_id)
360 {
361 switch (attr_id) {
362 case UFS_ATTR_PA_AVAILTXDATALANES:
363 case UFS_ATTR_PA_AVAILRXDATALANES:
364 case UFS_ATTR_PA_CONNECTEDTXDATALANES:
365 case UFS_ATTR_PA_CONNECTEDRXDATALANES:
366 return 1;
367 case UFS_ATTR_PA_MAXRXHSGEAR:
368 case UFS_ATTR_PA_MAXRXPWMGEAR:
369 return 4;
370 case UFS_ATTR_PA_PWRMODE:
371 return (1 << 4) | 1;
372 default:
373 return 0;
374 }
375 }
376
377 static void ufs_process_uiccmd(UfsHc *u, uint32_t val)
378 {
379 uint16_t attr_id;
380
381 trace_ufs_process_uiccmd(val, u->reg.ucmdarg1, u->reg.ucmdarg2,
382 u->reg.ucmdarg3);
383 /*
384 * Only the essential uic commands for running drivers on Linux and Windows
385 * are implemented.
386 */
387 switch (val) {
388 case UFS_UIC_CMD_DME_LINK_STARTUP:
389 u->reg.hcs = FIELD_DP32(u->reg.hcs, HCS, DP, 1);
390 u->reg.hcs = FIELD_DP32(u->reg.hcs, HCS, UTRLRDY, 1);
391 u->reg.hcs = FIELD_DP32(u->reg.hcs, HCS, UTMRLRDY, 1);
392 u->reg.ucmdarg2 = UFS_UIC_CMD_RESULT_SUCCESS;
393 break;
394 case UFS_UIC_CMD_DME_GET:
395 case UFS_UIC_CMD_DME_PEER_GET:
396 attr_id = (u->reg.ucmdarg1 >> 16) & 0xFFFF;
397 u->reg.ucmdarg3 = ufs_uic_dme_get_value(attr_id);
398 u->reg.ucmdarg2 = UFS_UIC_CMD_RESULT_SUCCESS;
399 break;
400 case UFS_UIC_CMD_DME_SET:
401 case UFS_UIC_CMD_DME_PEER_SET:
402 attr_id = (u->reg.ucmdarg1 >> 16) & 0xFFFF;
403 u->reg.ucmdarg2 = UFS_UIC_CMD_RESULT_SUCCESS;
404 /* DME_SET(PA_PWRMODE) is a power-mode-change trigger. */
405 if (val == UFS_UIC_CMD_DME_SET && attr_id == UFS_ATTR_PA_PWRMODE) {
406 u->reg.is = FIELD_DP32(u->reg.is, IS, UPMS, 1);
407 u->reg.hcs = FIELD_DP32(u->reg.hcs, HCS, UPMCRS, UFS_PWR_LOCAL);
408 }
409 break;
410 /*
411 * TODO: Revisit after PM implementation
412 * Power Management is not supported in current QEMU-UFS,
413 * So Write Booster's Flush during Hibern8 operation is also remained
414 * as not considered.
415 */
416 case UFS_UIC_CMD_DME_HIBER_ENTER:
417 u->reg.is = FIELD_DP32(u->reg.is, IS, UHES, 1);
418 u->reg.hcs = FIELD_DP32(u->reg.hcs, HCS, UPMCRS, UFS_PWR_LOCAL);
419 u->reg.ucmdarg2 = UFS_UIC_CMD_RESULT_SUCCESS;
420 break;
421 case UFS_UIC_CMD_DME_HIBER_EXIT:
422 u->reg.is = FIELD_DP32(u->reg.is, IS, UHXS, 1);
423 u->reg.hcs = FIELD_DP32(u->reg.hcs, HCS, UPMCRS, UFS_PWR_LOCAL);
424 u->reg.ucmdarg2 = UFS_UIC_CMD_RESULT_SUCCESS;
425 break;
426 default:
427 u->reg.ucmdarg2 = UFS_UIC_CMD_RESULT_FAILURE;
428 }
429
430 u->reg.is = FIELD_DP32(u->reg.is, IS, UCCS, 1);
431
432 ufs_irq_check(u);
433 }
434
435 static void ufs_mcq_init_req(UfsHc *u, UfsRequest *req, UfsSq *sq)
436 {
437 memset(req, 0, sizeof(*req));
438
439 req->hc = u;
440 req->state = UFS_REQUEST_IDLE;
441 req->slot = UFS_INVALID_SLOT;
442 req->sq = sq;
443 }
444
445 static void ufs_mcq_process_sq(void *opaque)
446 {
447 UfsSq *sq = opaque;
448 UfsHc *u = sq->u;
449 UfsSqEntry sqe;
450 UfsRequest *req;
451 hwaddr addr;
452 uint16_t head = ufs_mcq_sq_head(u, sq->sqid);
453 int err;
454
455 while (!(ufs_mcq_sq_empty(u, sq->sqid) || QTAILQ_EMPTY(&sq->req_list))) {
456 addr = sq->addr + head;
457 err = ufs_addr_read(sq->u, addr, (void *)&sqe, sizeof(sqe));
458 if (err) {
459 trace_ufs_err_dma_read_sq(sq->sqid, addr);
460 return;
461 }
462
463 head = (head + sizeof(sqe)) % (sq->size * sizeof(sqe));
464 ufs_mcq_update_sq_head(u, sq->sqid, head);
465
466 req = QTAILQ_FIRST(&sq->req_list);
467 QTAILQ_REMOVE(&sq->req_list, req, entry);
468
469 ufs_mcq_init_req(sq->u, req, sq);
470 memcpy(&req->utrd, &sqe, sizeof(req->utrd));
471
472 req->state = UFS_REQUEST_RUNNING;
473 ufs_exec_req(req);
474 }
475 }
476
477 static void ufs_mcq_process_cq(void *opaque)
478 {
479 UfsCq *cq = opaque;
480 UfsHc *u = cq->u;
481 UfsRequest *req, *next;
482 MemTxResult ret;
483 uint32_t tail = ufs_mcq_cq_tail(u, cq->cqid);
484
485 QTAILQ_FOREACH_SAFE(req, &cq->req_list, entry, next)
486 {
487 if (ufs_mcq_cq_full(u, cq->cqid)) {
488 break;
489 }
490
491 ufs_dma_write_rsp_upiu(req);
492
493 /* UTRD/CQE are LE; round-trip through host to keep BE correct. */
494 uint64_t ucdba =
495 ((uint64_t)le32_to_cpu(req->utrd.command_desc_base_addr_hi)
496 << 32ULL) |
497 le32_to_cpu(req->utrd.command_desc_base_addr_lo);
498 uint16_t resp_len = le16_to_cpu(req->utrd.response_upiu_length);
499 uint16_t resp_off = le16_to_cpu(req->utrd.response_upiu_offset);
500 uint16_t prdt_len = le16_to_cpu(req->utrd.prd_table_length);
501 uint16_t prdt_off = le16_to_cpu(req->utrd.prd_table_offset);
502 uint8_t status = le32_to_cpu(req->utrd.header.dword_2) & UFS_MASK_OCS;
503
504 ucdba |= req->sq->sqid;
505 req->cqe.utp_addr = cpu_to_le64(ucdba);
506 req->cqe.resp_len = cpu_to_le16(resp_len);
507 req->cqe.resp_off = cpu_to_le16(resp_off);
508 req->cqe.prdt_len = cpu_to_le16(prdt_len);
509 req->cqe.prdt_off = cpu_to_le16(prdt_off);
510 req->cqe.status = status;
511 req->cqe.error = 0;
512 /*
513 * From UFSHCI 4.1 the host derives the request tag from cqe.task_tag
514 * rather than decoding it from utp_addr.
515 */
516 req->cqe.task_tag = req->req_upiu.header.task_tag;
517 req->cqe.lun = req->req_upiu.header.lun;
518
519 ret = ufs_addr_write(u, cq->addr + tail, &req->cqe, sizeof(req->cqe));
520 if (ret) {
521 trace_ufs_err_dma_write_cq(cq->cqid, cq->addr + tail);
522 }
523 QTAILQ_REMOVE(&cq->req_list, req, entry);
524
525 tail = (tail + sizeof(req->cqe)) % (cq->size * sizeof(req->cqe));
526 ufs_mcq_update_cq_tail(u, cq->cqid, tail);
527
528 if (QTAILQ_EMPTY(&req->sq->req_list) &&
529 !ufs_mcq_sq_empty(u, req->sq->sqid)) {
530 /* Dequeueing from SQ was blocked due to lack of free requests */
531 qemu_bh_schedule(req->sq->bh);
532 }
533
534 ufs_clear_req(req);
535 QTAILQ_INSERT_TAIL(&req->sq->req_list, req, entry);
536 }
537
538 if (!ufs_mcq_cq_empty(u, cq->cqid)) {
539 u->mcq_op_reg[cq->cqid].cq_int.is =
540 FIELD_DP32(u->mcq_op_reg[cq->cqid].cq_int.is, CQIS, TEPS, 1);
541
542 u->reg.is = FIELD_DP32(u->reg.is, IS, CQES, 1);
543 ufs_irq_check(u);
544 }
545 }
546
547 static bool ufs_mcq_create_sq(UfsHc *u, uint8_t qid, uint32_t attr)
548 {
549 UfsMcqReg *reg = &u->mcq_reg[qid];
550 UfsSq *sq;
551 uint8_t cqid = FIELD_EX32(attr, SQATTR, CQID);
552 uint16_t qsize =
553 ((FIELD_EX32(attr, SQATTR, SIZE) + 1) << 2) / sizeof(UfsSqEntry);
554
555 if (qid >= u->params.mcq_maxq) {
556 trace_ufs_err_mcq_create_sq_invalid_sqid(qid);
557 return false;
558 }
559
560 if (u->sq[qid]) {
561 trace_ufs_err_mcq_create_sq_already_exists(qid);
562 return false;
563 }
564
565 if (cqid >= u->params.mcq_maxq) {
566 trace_ufs_err_mcq_create_sq_invalid_cqid(cqid);
567 return false;
568 }
569
570 if (!u->cq[cqid]) {
571 trace_ufs_err_mcq_create_sq_invalid_cqid(cqid);
572 return false;
573 }
574
575 if (!qsize) {
576 trace_ufs_err_mcq_create_sq_invalid_size(qid);
577 return false;
578 }
579
580 sq = g_malloc0(sizeof(*sq));
581 sq->u = u;
582 sq->sqid = qid;
583 sq->cq = u->cq[cqid];
584 sq->addr = ((uint64_t)reg->squba << 32) | reg->sqlba;
585 sq->size = qsize;
586
587 sq->bh = qemu_bh_new_guarded(ufs_mcq_process_sq, sq,
588 &u->dev->mem_reentrancy_guard);
589 sq->req = g_new0(UfsRequest, sq->size);
590 QTAILQ_INIT(&sq->req_list);
591 for (int i = 0; i < sq->size; i++) {
592 ufs_mcq_init_req(u, &sq->req[i], sq);
593 QTAILQ_INSERT_TAIL(&sq->req_list, &sq->req[i], entry);
594 }
595
596 u->sq[qid] = sq;
597
598 trace_ufs_mcq_create_sq(sq->sqid, sq->cq->cqid, sq->addr, sq->size);
599 return true;
600 }
601
602 static bool ufs_mcq_sq_has_outstanding_req(UfsSq *sq)
603 {
604 UfsRequest *req;
605 uint16_t free_reqs = 0;
606
607 QTAILQ_FOREACH(req, &sq->req_list, entry)
608 {
609 free_reqs++;
610 }
611
612 return free_reqs != sq->size;
613 }
614
615 static void ufs_mcq_free_sq(UfsSq *sq)
616 {
617 qemu_bh_delete(sq->bh);
618
619 for (int i = 0; i < sq->size; i++) {
620 ufs_clear_req(&sq->req[i]);
621 }
622
623 g_free(sq->req);
624 g_free(sq);
625 }
626
627 static bool ufs_mcq_delete_sq(UfsHc *u, uint8_t qid)
628 {
629 UfsSq *sq;
630
631 if (qid >= u->params.mcq_maxq) {
632 trace_ufs_err_mcq_delete_sq_invalid_sqid(qid);
633 return false;
634 }
635
636 if (!u->sq[qid]) {
637 trace_ufs_err_mcq_delete_sq_not_exists(qid);
638 return false;
639 }
640
641 sq = u->sq[qid];
642
643 if (ufs_mcq_sq_has_outstanding_req(sq)) {
644 trace_ufs_err_mcq_delete_sq_busy(qid);
645 return false;
646 }
647
648 ufs_mcq_free_sq(sq);
649 u->sq[qid] = NULL;
650 return true;
651 }
652
653 static bool ufs_mcq_create_cq(UfsHc *u, uint8_t qid, uint32_t attr)
654 {
655 UfsMcqReg *reg = &u->mcq_reg[qid];
656 UfsCq *cq;
657 uint16_t qsize =
658 ((FIELD_EX32(attr, CQATTR, SIZE) + 1) << 2) / sizeof(UfsCqEntry);
659
660 if (qid >= u->params.mcq_maxq) {
661 trace_ufs_err_mcq_create_cq_invalid_cqid(qid);
662 return false;
663 }
664
665 if (u->cq[qid]) {
666 trace_ufs_err_mcq_create_cq_already_exists(qid);
667 return false;
668 }
669
670 if (!qsize) {
671 trace_ufs_err_mcq_create_cq_invalid_size(qid);
672 return false;
673 }
674
675 cq = g_malloc0(sizeof(*cq));
676 cq->u = u;
677 cq->cqid = qid;
678 cq->addr = ((uint64_t)reg->cquba << 32) | reg->cqlba;
679 cq->size = qsize;
680
681 cq->bh = qemu_bh_new_guarded(ufs_mcq_process_cq, cq,
682 &u->dev->mem_reentrancy_guard);
683 QTAILQ_INIT(&cq->req_list);
684
685 u->cq[qid] = cq;
686
687 trace_ufs_mcq_create_cq(cq->cqid, cq->addr, cq->size);
688 return true;
689 }
690
691 static void ufs_mcq_free_cq(UfsCq *cq)
692 {
693 qemu_bh_delete(cq->bh);
694 g_free(cq);
695 }
696
697 static bool ufs_mcq_delete_cq(UfsHc *u, uint8_t qid)
698 {
699 UfsCq *cq;
700
701 if (qid >= u->params.mcq_maxq) {
702 trace_ufs_err_mcq_delete_cq_invalid_cqid(qid);
703 return false;
704 }
705
706 if (!u->cq[qid]) {
707 trace_ufs_err_mcq_delete_cq_not_exists(qid);
708 return false;
709 }
710
711 for (int i = 0; i < ARRAY_SIZE(u->sq); i++) {
712 if (u->sq[i] && u->sq[i]->cq->cqid == qid) {
713 trace_ufs_err_mcq_delete_cq_sq_not_deleted(i, qid);
714 return false;
715 }
716 }
717
718 cq = u->cq[qid];
719
720 ufs_mcq_free_cq(cq);
721 u->cq[qid] = NULL;
722 return true;
723 }
724
725 static void ufs_write_reg(UfsHc *u, hwaddr offset, uint32_t data, unsigned size)
726 {
727 switch (offset) {
728 case A_IS:
729 u->reg.is &= ~data;
730 ufs_irq_check(u);
731 break;
732 case A_IE:
733 u->reg.ie = data;
734 ufs_irq_check(u);
735 break;
736 case A_HCE:
737 if (!FIELD_EX32(u->reg.hce, HCE, HCE) && FIELD_EX32(data, HCE, HCE)) {
738 u->reg.hcs = FIELD_DP32(u->reg.hcs, HCS, UCRDY, 1);
739 u->reg.hce = FIELD_DP32(u->reg.hce, HCE, HCE, 1);
740 } else if (FIELD_EX32(u->reg.hce, HCE, HCE) &&
741 !FIELD_EX32(data, HCE, HCE)) {
742 u->reg.hcs = 0;
743 u->reg.hce = FIELD_DP32(u->reg.hce, HCE, HCE, 0);
744 }
745 break;
746 case A_UTRLBA:
747 u->reg.utrlba = data & R_UTRLBA_UTRLBA_MASK;
748 break;
749 case A_UTRLBAU:
750 u->reg.utrlbau = data;
751 break;
752 case A_UTRLDBR:
753 ufs_process_db(u, data);
754 u->reg.utrldbr |= data;
755 break;
756 case A_UTRLRSR:
757 u->reg.utrlrsr = data;
758 break;
759 case A_UTRLCNR:
760 u->reg.utrlcnr &= ~data;
761 break;
762 case A_UTMRLBA:
763 u->reg.utmrlba = data & R_UTMRLBA_UTMRLBA_MASK;
764 break;
765 case A_UTMRLBAU:
766 u->reg.utmrlbau = data;
767 break;
768 case A_UICCMD:
769 ufs_process_uiccmd(u, data);
770 break;
771 case A_UCMDARG1:
772 u->reg.ucmdarg1 = data;
773 break;
774 case A_UCMDARG2:
775 u->reg.ucmdarg2 = data;
776 break;
777 case A_UCMDARG3:
778 u->reg.ucmdarg3 = data;
779 break;
780 case A_CONFIG:
781 u->reg.config = data;
782 break;
783 case A_MCQCONFIG:
784 u->reg.mcqconfig = data;
785 break;
786 case A_UTRLCLR:
787 case A_UTMRLDBR:
788 case A_UTMRLCLR:
789 case A_UTMRLRSR:
790 trace_ufs_err_unsupport_register_offset(offset);
791 break;
792 default:
793 trace_ufs_err_invalid_register_offset(offset);
794 break;
795 }
796 }
797
798 static void ufs_write_mcq_reg(UfsHc *u, hwaddr offset, uint32_t data,
799 unsigned size)
800 {
801 int qid = offset / sizeof(UfsMcqReg);
802 UfsMcqReg *reg = &u->mcq_reg[qid];
803
804 switch (offset % sizeof(UfsMcqReg)) {
805 case A_SQATTR:
806 if (!FIELD_EX32(reg->sqattr, SQATTR, SQEN) &&
807 FIELD_EX32(data, SQATTR, SQEN)) {
808 if (!ufs_mcq_create_sq(u, qid, data)) {
809 break;
810 }
811 } else if (FIELD_EX32(reg->sqattr, SQATTR, SQEN) &&
812 !FIELD_EX32(data, SQATTR, SQEN)) {
813 if (!ufs_mcq_delete_sq(u, qid)) {
814 break;
815 }
816 }
817 reg->sqattr = data;
818 break;
819 case A_SQLBA:
820 reg->sqlba = data;
821 break;
822 case A_SQUBA:
823 reg->squba = data;
824 break;
825 case A_SQCFG:
826 reg->sqcfg = data;
827 break;
828 case A_CQATTR:
829 if (!FIELD_EX32(reg->cqattr, CQATTR, CQEN) &&
830 FIELD_EX32(data, CQATTR, CQEN)) {
831 if (!ufs_mcq_create_cq(u, qid, data)) {
832 break;
833 }
834 } else if (FIELD_EX32(reg->cqattr, CQATTR, CQEN) &&
835 !FIELD_EX32(data, CQATTR, CQEN)) {
836 if (!ufs_mcq_delete_cq(u, qid)) {
837 break;
838 }
839 }
840 reg->cqattr = data;
841 break;
842 case A_CQLBA:
843 reg->cqlba = data;
844 break;
845 case A_CQUBA:
846 reg->cquba = data;
847 break;
848 case A_CQCFG:
849 reg->cqcfg = data;
850 break;
851 case A_SQDAO:
852 case A_SQISAO:
853 case A_CQDAO:
854 case A_CQISAO:
855 trace_ufs_err_unsupport_register_offset(offset);
856 break;
857 default:
858 trace_ufs_err_invalid_register_offset(offset);
859 break;
860 }
861 }
862
863 static void ufs_mcq_process_db(UfsHc *u, uint8_t qid, uint32_t db)
864 {
865 UfsSq *sq;
866
867 if (qid >= u->params.mcq_maxq) {
868 trace_ufs_err_mcq_db_wr_invalid_sqid(qid);
869 return;
870 }
871
872 sq = u->sq[qid];
873 if (!sq) {
874 trace_ufs_err_mcq_db_wr_invalid_sqid(qid);
875 return;
876 }
877
878 if (sq->size * sizeof(UfsSqEntry) <= db) {
879 trace_ufs_err_mcq_db_wr_invalid_db(qid, db);
880 return;
881 }
882
883 ufs_mcq_update_sq_tail(u, sq->sqid, db);
884 qemu_bh_schedule(sq->bh);
885 }
886
887 static void ufs_write_mcq_op_reg(UfsHc *u, hwaddr offset, uint32_t data,
888 unsigned size)
889 {
890 int qid = offset / sizeof(UfsMcqOpReg);
891 UfsMcqOpReg *opr;
892
893 if (qid >= u->params.mcq_maxq) {
894 trace_ufs_err_invalid_register_offset(offset);
895 return;
896 }
897
898 opr = &u->mcq_op_reg[qid];
899
900 switch (offset % sizeof(UfsMcqOpReg)) {
901 case offsetof(UfsMcqOpReg, sq.tp):
902 if (opr->sq.tp != data) {
903 ufs_mcq_process_db(u, qid, data);
904 }
905 opr->sq.tp = data;
906 break;
907 case offsetof(UfsMcqOpReg, cq.hp): {
908 UfsCq *cq = u->cq[qid];
909
910 if (!cq) {
911 break;
912 }
913
914 if (ufs_mcq_cq_full(u, qid) && !QTAILQ_EMPTY(&cq->req_list)) {
915 /* Enqueueing to CQ was blocked because it was full */
916 qemu_bh_schedule(cq->bh);
917 }
918
919 opr->cq.hp = data;
920 ufs_mcq_update_cq_head(u, qid, data);
921 break;
922 }
923 case offsetof(UfsMcqOpReg, cq_int.is):
924 opr->cq_int.is &= ~data;
925 break;
926 default:
927 trace_ufs_err_invalid_register_offset(offset);
928 break;
929 }
930 }
931
932 static uint64_t ufs_mmio_read(void *opaque, hwaddr addr, unsigned size)
933 {
934 UfsHc *u = (UfsHc *)opaque;
935 uint32_t *ptr;
936 uint64_t value;
937 uint64_t offset;
938
939 if (addr + size <= sizeof(u->reg)) {
940 offset = addr;
941 ptr = (uint32_t *)&u->reg;
942 } else if (ufs_is_mcq_reg(u, addr, size)) {
943 offset = addr - ufs_mcq_reg_addr(u, 0);
944 ptr = (uint32_t *)&u->mcq_reg;
945 } else if (ufs_is_mcq_op_reg(u, addr, size)) {
946 offset = addr - ufs_mcq_op_reg_addr(u, 0);
947 ptr = (uint32_t *)&u->mcq_op_reg;
948 } else {
949 trace_ufs_err_invalid_register_offset(addr);
950 return 0;
951 }
952
953 value = ptr[offset >> 2];
954 trace_ufs_mmio_read(addr, value, size);
955 return value;
956 }
957
958 static void ufs_mmio_write(void *opaque, hwaddr addr, uint64_t data,
959 unsigned size)
960 {
961 UfsHc *u = (UfsHc *)opaque;
962
963 trace_ufs_mmio_write(addr, data, size);
964
965 if (addr + size <= sizeof(u->reg)) {
966 ufs_write_reg(u, addr, data, size);
967 } else if (ufs_is_mcq_reg(u, addr, size)) {
968 ufs_write_mcq_reg(u, addr - ufs_mcq_reg_addr(u, 0), data, size);
969 } else if (ufs_is_mcq_op_reg(u, addr, size)) {
970 ufs_write_mcq_op_reg(u, addr - ufs_mcq_op_reg_addr(u, 0), data, size);
971 } else {
972 trace_ufs_err_invalid_register_offset(addr);
973 }
974 }
975
976 static const MemoryRegionOps ufs_mmio_ops = {
977 .read = ufs_mmio_read,
978 .write = ufs_mmio_write,
979 .endianness = DEVICE_LITTLE_ENDIAN,
980 .impl = {
981 .min_access_size = 4,
982 .max_access_size = 4,
983 },
984 };
985
986 static void ufs_wb_update_ee_status(UfsHc *u, uint16_t *ee_status)
987 {
988 UfsWb *wb = &u->wb;
989 uint64_t curr_bytes = wb->curr_bytes - wb->pinned_curr_bytes;
990 uint64_t used_bytes = wb->used_bytes - wb->pinned_used_bytes;
991
992 if (curr_bytes != 0 && used_bytes >= curr_bytes) {
993 *ee_status |= MASK_EE_WB_FLUSH_NEEDED;
994 } else {
995 *ee_status &= ~MASK_EE_WB_FLUSH_NEEDED;
996 }
997
998 if (u->attributes.wb_buffer_resize_hint != UFS_WB_HINT_KEEP) {
999 *ee_status |= MASK_EE_WB_RESIZE_HINT;
1000 } else {
1001 *ee_status &= ~MASK_EE_WB_RESIZE_HINT;
1002 }
1003
1004 if (wb->pinned_used_bytes != 0 &&
1005 wb->pinned_used_bytes >= wb->pinned_curr_bytes) {
1006 *ee_status |= MASK_EE_PINNED_WB_FULL;
1007 } else {
1008 *ee_status &= ~MASK_EE_PINNED_WB_FULL;
1009 }
1010 }
1011
1012 static void ufs_update_ee_status(UfsHc *u)
1013 {
1014 uint16_t ee_status = be16_to_cpu(u->attributes.exception_event_status);
1015 uint8_t high_temp_thresh = u->attributes.device_too_high_temp_boundary;
1016 uint8_t low_temp_thresh = u->attributes.device_too_low_temp_boundary;
1017
1018 if (u->temperature >= high_temp_thresh) {
1019 ee_status |= MASK_EE_TOO_HIGH_TEMP;
1020 } else {
1021 ee_status &= ~MASK_EE_TOO_HIGH_TEMP;
1022 }
1023
1024 if (u->temperature <= low_temp_thresh) {
1025 ee_status |= MASK_EE_TOO_LOW_TEMP;
1026 } else {
1027 ee_status &= ~MASK_EE_TOO_LOW_TEMP;
1028 }
1029
1030 ufs_wb_update_ee_status(u, &ee_status);
1031
1032 u->attributes.exception_event_status = cpu_to_be16(ee_status);
1033 }
1034
1035 static bool ufs_check_exception_event_alert(UfsHc *u, uint8_t trans_type)
1036 {
1037 uint16_t ee_control = be16_to_cpu(u->attributes.exception_event_control);
1038 uint16_t ee_status;
1039
1040 if (trans_type != UFS_UPIU_TRANSACTION_RESPONSE) {
1041 return false;
1042 }
1043
1044 ufs_update_ee_status(u);
1045
1046 ee_status = be16_to_cpu(u->attributes.exception_event_status);
1047
1048 return ee_control & ee_status;
1049 }
1050
1051 void ufs_build_upiu_header(UfsRequest *req, uint8_t trans_type, uint8_t flags,
1052 uint8_t response, uint8_t scsi_status,
1053 uint16_t data_segment_length)
1054 {
1055 memcpy(&req->rsp_upiu.header, &req->req_upiu.header, sizeof(UtpUpiuHeader));
1056 req->rsp_upiu.header.trans_type = trans_type;
1057 req->rsp_upiu.header.flags = flags;
1058 req->rsp_upiu.header.response = response;
1059 req->rsp_upiu.header.scsi_status = scsi_status;
1060 req->rsp_upiu.header.device_inf =
1061 ufs_check_exception_event_alert(req->hc, trans_type);
1062 req->rsp_upiu.header.data_segment_length = cpu_to_be16(data_segment_length);
1063 }
1064
1065 void ufs_build_query_response(UfsRequest *req)
1066 {
1067 req->rsp_upiu.qr.opcode = req->req_upiu.qr.opcode;
1068 req->rsp_upiu.qr.idn = req->req_upiu.qr.idn;
1069 req->rsp_upiu.qr.index = req->req_upiu.qr.index;
1070 req->rsp_upiu.qr.selector = req->req_upiu.qr.selector;
1071 }
1072
1073 static UfsReqResult ufs_exec_scsi_cmd(UfsRequest *req)
1074 {
1075 UfsHc *u = req->hc;
1076 uint8_t lun = req->req_upiu.header.lun;
1077
1078 UfsLu *lu = NULL;
1079
1080 trace_ufs_exec_scsi_cmd(req->slot, lun, req->req_upiu.sc.cdb[0]);
1081
1082 if (!is_wlun(lun) && (lun >= UFS_MAX_LUS || u->lus[lun] == NULL)) {
1083 trace_ufs_err_scsi_cmd_invalid_lun(lun);
1084 return UFS_REQUEST_FAIL;
1085 }
1086
1087 switch (lun) {
1088 case UFS_UPIU_REPORT_LUNS_WLUN:
1089 lu = &u->report_wlu;
1090 break;
1091 case UFS_UPIU_UFS_DEVICE_WLUN:
1092 lu = &u->dev_wlu;
1093 break;
1094 case UFS_UPIU_BOOT_WLUN:
1095 lu = &u->boot_wlu;
1096 break;
1097 case UFS_UPIU_RPMB_WLUN:
1098 lu = &u->rpmb_wlu;
1099 break;
1100 default:
1101 lu = u->lus[lun];
1102 }
1103
1104 return lu->scsi_op(lu, req);
1105 }
1106
1107 static UfsReqResult ufs_exec_nop_cmd(UfsRequest *req)
1108 {
1109 trace_ufs_exec_nop_cmd(req->slot);
1110 ufs_build_upiu_header(req, UFS_UPIU_TRANSACTION_NOP_IN, 0, 0, 0, 0);
1111 return UFS_REQUEST_SUCCESS;
1112 }
1113
1114 /*
1115 * This defines the permission of flags based on their IDN. There are some
1116 * things that are declared read-only, which is inconsistent with the ufs spec,
1117 * because we want to return an error for features that are not yet supported.
1118 */
1119 static const int flag_permission[UFS_QUERY_FLAG_IDN_COUNT] = {
1120 [UFS_QUERY_FLAG_IDN_FDEVICEINIT] = UFS_QUERY_FLAG_READ | UFS_QUERY_FLAG_SET,
1121 /* Write protection is not supported */
1122 [UFS_QUERY_FLAG_IDN_PERMANENT_WPE] = UFS_QUERY_FLAG_READ,
1123 [UFS_QUERY_FLAG_IDN_PWR_ON_WPE] = UFS_QUERY_FLAG_READ,
1124 [UFS_QUERY_FLAG_IDN_BKOPS_EN] = UFS_QUERY_FLAG_READ | UFS_QUERY_FLAG_SET |
1125 UFS_QUERY_FLAG_CLEAR |
1126 UFS_QUERY_FLAG_TOGGLE,
1127 [UFS_QUERY_FLAG_IDN_LIFE_SPAN_MODE_ENABLE] =
1128 UFS_QUERY_FLAG_READ | UFS_QUERY_FLAG_SET | UFS_QUERY_FLAG_CLEAR |
1129 UFS_QUERY_FLAG_TOGGLE,
1130 /* Purge Operation is not supported */
1131 [UFS_QUERY_FLAG_IDN_PURGE_ENABLE] = UFS_QUERY_FLAG_NONE,
1132 /* Refresh Operation is not supported */
1133 [UFS_QUERY_FLAG_IDN_REFRESH_ENABLE] = UFS_QUERY_FLAG_NONE,
1134 /* Physical Resource Removal is not supported */
1135 [UFS_QUERY_FLAG_IDN_FPHYRESOURCEREMOVAL] = UFS_QUERY_FLAG_READ,
1136 [UFS_QUERY_FLAG_IDN_BUSY_RTC] = UFS_QUERY_FLAG_READ,
1137 [UFS_QUERY_FLAG_IDN_PERMANENTLY_DISABLE_FW_UPDATE] = UFS_QUERY_FLAG_READ,
1138 [UFS_QUERY_FLAG_IDN_WB_EN] = UFS_QUERY_FLAG_READ | UFS_QUERY_FLAG_SET |
1139 UFS_QUERY_FLAG_CLEAR | UFS_QUERY_FLAG_TOGGLE,
1140 [UFS_QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN] =
1141 UFS_QUERY_FLAG_READ | UFS_QUERY_FLAG_SET | UFS_QUERY_FLAG_CLEAR |
1142 UFS_QUERY_FLAG_TOGGLE,
1143 /* TODO: Revisit after PM implementation */
1144 [UFS_QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8] = UFS_QUERY_FLAG_READ,
1145 [UFS_QUERY_FLAG_IDN_UNPIN_EN] = UFS_QUERY_FLAG_READ | UFS_QUERY_FLAG_SET |
1146 UFS_QUERY_FLAG_CLEAR |
1147 UFS_QUERY_FLAG_TOGGLE,
1148 };
1149
1150 static inline QueryRespCode ufs_flag_check_idn_valid(uint8_t idn, int op)
1151 {
1152 if (idn >= UFS_QUERY_FLAG_IDN_COUNT) {
1153 return UFS_QUERY_RESULT_INVALID_IDN;
1154 }
1155
1156 if (!(flag_permission[idn] & op)) {
1157 if (op == UFS_QUERY_FLAG_READ) {
1158 trace_ufs_err_query_flag_not_readable(idn);
1159 return UFS_QUERY_RESULT_NOT_READABLE;
1160 }
1161 trace_ufs_err_query_flag_not_writable(idn);
1162 return UFS_QUERY_RESULT_NOT_WRITEABLE;
1163 }
1164
1165 return UFS_QUERY_RESULT_SUCCESS;
1166 }
1167
1168 static uint32_t ufs_read_flag_value(UfsHc *u, uint8_t idn)
1169 {
1170 switch (idn) {
1171 case UFS_QUERY_FLAG_IDN_FDEVICEINIT:
1172 return u->flags.device_init;
1173 case UFS_QUERY_FLAG_IDN_PERMANENT_WPE:
1174 return u->flags.permanent_wp_en;
1175 case UFS_QUERY_FLAG_IDN_PWR_ON_WPE:
1176 return u->flags.power_on_wp_en;
1177 case UFS_QUERY_FLAG_IDN_BKOPS_EN:
1178 return u->flags.background_ops_en;
1179 case UFS_QUERY_FLAG_IDN_LIFE_SPAN_MODE_ENABLE:
1180 return u->flags.device_life_span_mode_en;
1181 case UFS_QUERY_FLAG_IDN_PURGE_ENABLE:
1182 return u->flags.purge_enable;
1183 case UFS_QUERY_FLAG_IDN_REFRESH_ENABLE:
1184 return u->flags.refresh_enable;
1185 case UFS_QUERY_FLAG_IDN_FPHYRESOURCEREMOVAL:
1186 return u->flags.phy_resource_removal;
1187 case UFS_QUERY_FLAG_IDN_BUSY_RTC:
1188 return u->flags.busy_rtc;
1189 case UFS_QUERY_FLAG_IDN_PERMANENTLY_DISABLE_FW_UPDATE:
1190 return u->flags.permanently_disable_fw_update;
1191 case UFS_QUERY_FLAG_IDN_WB_EN:
1192 return u->flags.wb_en;
1193 case UFS_QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN:
1194 return u->flags.wb_buffer_flush_en;
1195 case UFS_QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8:
1196 return u->flags.wb_buffer_flush_during_hibernate;
1197 case UFS_QUERY_FLAG_IDN_UNPIN_EN:
1198 return u->flags.unpin_en;
1199 default:
1200 g_assert_not_reached();
1201 return 0;
1202 }
1203 }
1204
1205 static QueryRespCode ufs_write_flag_value(UfsHc *u, uint8_t idn, uint8_t value)
1206 {
1207 switch (idn) {
1208 case UFS_QUERY_FLAG_IDN_FDEVICEINIT:
1209 u->flags.device_init = 0;
1210 break;
1211 case UFS_QUERY_FLAG_IDN_PERMANENT_WPE:
1212 u->flags.permanent_wp_en = value;
1213 break;
1214 case UFS_QUERY_FLAG_IDN_PWR_ON_WPE:
1215 u->flags.power_on_wp_en = value;
1216 break;
1217 case UFS_QUERY_FLAG_IDN_BKOPS_EN:
1218 u->flags.background_ops_en = value;
1219 break;
1220 case UFS_QUERY_FLAG_IDN_LIFE_SPAN_MODE_ENABLE:
1221 u->flags.device_life_span_mode_en = value;
1222 break;
1223 case UFS_QUERY_FLAG_IDN_PURGE_ENABLE:
1224 u->flags.purge_enable = value;
1225 break;
1226 case UFS_QUERY_FLAG_IDN_REFRESH_ENABLE:
1227 u->flags.refresh_enable = value;
1228 break;
1229 case UFS_QUERY_FLAG_IDN_FPHYRESOURCEREMOVAL:
1230 u->flags.phy_resource_removal = value;
1231 break;
1232 case UFS_QUERY_FLAG_IDN_PERMANENTLY_DISABLE_FW_UPDATE:
1233 u->flags.permanently_disable_fw_update = value;
1234 break;
1235 case UFS_QUERY_FLAG_IDN_WB_EN:
1236 u->flags.wb_en = value;
1237 break;
1238 case UFS_QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN:
1239 u->flags.wb_buffer_flush_en = value;
1240 break;
1241 case UFS_QUERY_FLAG_IDN_UNPIN_EN:
1242 u->flags.unpin_en = value;
1243 break;
1244 default:
1245 return UFS_QUERY_RESULT_INVALID_VALUE;
1246 }
1247
1248 return UFS_QUERY_RESULT_SUCCESS;
1249 }
1250
1251 static QueryRespCode ufs_exec_query_flag(UfsRequest *req, int op)
1252 {
1253 UfsHc *u = req->hc;
1254 uint8_t idn = req->req_upiu.qr.idn;
1255 uint8_t value;
1256 QueryRespCode ret;
1257
1258 ret = ufs_flag_check_idn_valid(idn, op);
1259 if (ret) {
1260 return ret;
1261 }
1262
1263 if (op == UFS_QUERY_FLAG_READ) {
1264 value = ufs_read_flag_value(u, idn);
1265 ret = UFS_QUERY_RESULT_SUCCESS;
1266 } else if (op == UFS_QUERY_FLAG_SET) {
1267 value = 1;
1268 ret = ufs_write_flag_value(u, idn, value);
1269 } else if (op == UFS_QUERY_FLAG_CLEAR) {
1270 value = 0;
1271 ret = ufs_write_flag_value(u, idn, value);
1272 } else if (op == UFS_QUERY_FLAG_TOGGLE) {
1273 value = !(ufs_read_flag_value(u, idn));
1274 ret = ufs_write_flag_value(u, idn, value);
1275 } else {
1276 trace_ufs_err_query_invalid_opcode(op);
1277 return UFS_QUERY_RESULT_INVALID_OPCODE;
1278 }
1279
1280 req->rsp_upiu.qr.value = cpu_to_be32(value);
1281 return ret;
1282 }
1283
1284 static const int attr_permission[UFS_QUERY_ATTR_IDN_COUNT] = {
1285 /* booting is not supported */
1286 [UFS_QUERY_ATTR_IDN_BOOT_LU_EN] = UFS_QUERY_ATTR_READ,
1287 [UFS_QUERY_ATTR_IDN_POWER_MODE] = UFS_QUERY_ATTR_READ,
1288 [UFS_QUERY_ATTR_IDN_ACTIVE_ICC_LVL] =
1289 UFS_QUERY_ATTR_READ | UFS_QUERY_ATTR_WRITE,
1290 [UFS_QUERY_ATTR_IDN_OOO_DATA_EN] = UFS_QUERY_ATTR_READ,
1291 [UFS_QUERY_ATTR_IDN_BKOPS_STATUS] = UFS_QUERY_ATTR_READ,
1292 [UFS_QUERY_ATTR_IDN_PURGE_STATUS] = UFS_QUERY_ATTR_READ,
1293 [UFS_QUERY_ATTR_IDN_MAX_DATA_IN] =
1294 UFS_QUERY_ATTR_READ | UFS_QUERY_ATTR_WRITE,
1295 [UFS_QUERY_ATTR_IDN_MAX_DATA_OUT] =
1296 UFS_QUERY_ATTR_READ | UFS_QUERY_ATTR_WRITE,
1297 [UFS_QUERY_ATTR_IDN_DYN_CAP_NEEDED] = UFS_QUERY_ATTR_READ,
1298 [UFS_QUERY_ATTR_IDN_REF_CLK_FREQ] =
1299 UFS_QUERY_ATTR_READ | UFS_QUERY_ATTR_WRITE,
1300 [UFS_QUERY_ATTR_IDN_CONF_DESC_LOCK] = UFS_QUERY_ATTR_READ,
1301 [UFS_QUERY_ATTR_IDN_MAX_NUM_OF_RTT] =
1302 UFS_QUERY_ATTR_READ | UFS_QUERY_ATTR_WRITE,
1303 [UFS_QUERY_ATTR_IDN_EE_CONTROL] =
1304 UFS_QUERY_ATTR_READ | UFS_QUERY_ATTR_WRITE,
1305 [UFS_QUERY_ATTR_IDN_EE_STATUS] = UFS_QUERY_ATTR_READ,
1306 [UFS_QUERY_ATTR_IDN_SECONDS_PASSED] = UFS_QUERY_ATTR_WRITE,
1307 [UFS_QUERY_ATTR_IDN_CNTX_CONF] = UFS_QUERY_ATTR_READ,
1308 [UFS_QUERY_ATTR_IDN_FFU_STATUS] = UFS_QUERY_ATTR_READ,
1309 [UFS_QUERY_ATTR_IDN_PSA_STATE] = UFS_QUERY_ATTR_READ | UFS_QUERY_ATTR_WRITE,
1310 [UFS_QUERY_ATTR_IDN_PSA_DATA_SIZE] =
1311 UFS_QUERY_ATTR_READ | UFS_QUERY_ATTR_WRITE,
1312 [UFS_QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME] = UFS_QUERY_ATTR_READ,
1313 [UFS_QUERY_ATTR_IDN_CASE_ROUGH_TEMP] = UFS_QUERY_ATTR_READ,
1314 [UFS_QUERY_ATTR_IDN_HIGH_TEMP_BOUND] = UFS_QUERY_ATTR_READ,
1315 [UFS_QUERY_ATTR_IDN_LOW_TEMP_BOUND] = UFS_QUERY_ATTR_READ,
1316 [UFS_QUERY_ATTR_IDN_THROTTLING_STATUS] = UFS_QUERY_ATTR_READ,
1317 [UFS_QUERY_ATTR_IDN_WB_FLUSH_STATUS] = UFS_QUERY_ATTR_READ,
1318 [UFS_QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE] = UFS_QUERY_ATTR_READ,
1319 [UFS_QUERY_ATTR_IDN_WB_BUFF_LIFE_TIME_EST] = UFS_QUERY_ATTR_READ,
1320 [UFS_QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE] = UFS_QUERY_ATTR_READ,
1321 [UFS_QUERY_ATTR_IDN_EXT_IID_EN] = UFS_QUERY_ATTR_READ,
1322 [UFS_QUERY_ATTR_IDN_HOST_HINT_CACHE_SIZE] = UFS_QUERY_ATTR_READ,
1323 /* refresh operation is not supported */
1324 [UFS_QUERY_ATTR_IDN_REFRESH_STATUS] = UFS_QUERY_ATTR_READ,
1325 [UFS_QUERY_ATTR_IDN_REFRESH_FREQ] = UFS_QUERY_ATTR_READ,
1326 [UFS_QUERY_ATTR_IDN_REFRESH_UNIT] = UFS_QUERY_ATTR_READ,
1327 [UFS_QUERY_ATTR_IDN_TIMESTAMP] = UFS_QUERY_ATTR_WRITE,
1328 [UFS_QUERY_ATTR_IDN_DEVICE_LEVEL_EXCEPTION_ID] = UFS_QUERY_ATTR_READ,
1329 [UFS_QUERY_ATTR_IDN_DEFRAG_OP] = UFS_QUERY_ATTR_READ | UFS_QUERY_ATTR_WRITE,
1330 [UFS_QUERY_ATTR_IDN_HID_AVAIL_SIZE] = UFS_QUERY_ATTR_READ,
1331 [UFS_QUERY_ATTR_IDN_HID_SIZE] = UFS_QUERY_ATTR_READ | UFS_QUERY_ATTR_WRITE,
1332 [UFS_QUERY_ATTR_IDN_HID_PROG_RATIO] = UFS_QUERY_ATTR_READ,
1333 [UFS_QUERY_ATTR_IDN_HID_STATE] = UFS_QUERY_ATTR_READ,
1334 [UFS_QUERY_ATTR_IDN_WB_BUFF_RESIZE_HINT] = UFS_QUERY_ATTR_READ,
1335 [UFS_QUERY_ATTR_IDN_WB_BUFF_RESIZE_EN] = UFS_QUERY_ATTR_WRITE,
1336 [UFS_QUERY_ATTR_IDN_WB_BUFF_RESIZE_STATUS] = UFS_QUERY_ATTR_READ,
1337 [UFS_QUERY_ATTR_IDN_WB_BUFF_PARTIAL_FLUSH_MODE] =
1338 UFS_QUERY_ATTR_READ | UFS_QUERY_ATTR_WRITE,
1339 [UFS_QUERY_ATTR_IDN_MAX_FIFO_WB_PARTIAL_FLUSH_MODE] =
1340 UFS_QUERY_ATTR_READ | UFS_QUERY_ATTR_WRITE,
1341 [UFS_QUERY_ATTR_IDN_CURR_FIFO_WB_PARTIAL_FLUSH_MODE] = UFS_QUERY_ATTR_READ,
1342 [UFS_QUERY_ATTR_IDN_PINNED_WB_BUFF_CURR_ALLOC_UNITS] = UFS_QUERY_ATTR_READ,
1343 [UFS_QUERY_ATTR_IDN_PINNED_WB_BUFF_AVAIL_PERCENT] = UFS_QUERY_ATTR_READ,
1344 [UFS_QUERY_ATTR_IDN_PINNED_WB_CUMM_WRITTEN_SIZE] = UFS_QUERY_ATTR_READ,
1345 [UFS_QUERY_ATTR_IDN_PINNED_WB_NUM_ALLOC_UNITS] =
1346 UFS_QUERY_ATTR_READ | UFS_QUERY_ATTR_WRITE,
1347 [UFS_QUERY_ATTR_IDN_NON_PINNED_WB_MIN_NUM_ALLOC_UNITS] =
1348 UFS_QUERY_ATTR_READ | UFS_QUERY_ATTR_WRITE,
1349 };
1350
1351 static inline QueryRespCode ufs_attr_check_idn_valid(uint8_t idn, int op)
1352 {
1353 if (idn >= UFS_QUERY_ATTR_IDN_COUNT) {
1354 return UFS_QUERY_RESULT_INVALID_IDN;
1355 }
1356
1357 if (!(attr_permission[idn] & op)) {
1358 if (op == UFS_QUERY_ATTR_READ) {
1359 trace_ufs_err_query_attr_not_readable(idn);
1360 return UFS_QUERY_RESULT_NOT_READABLE;
1361 }
1362 trace_ufs_err_query_attr_not_writable(idn);
1363 return UFS_QUERY_RESULT_NOT_WRITEABLE;
1364 }
1365
1366 return UFS_QUERY_RESULT_SUCCESS;
1367 }
1368
1369 static inline uint8_t ufs_read_device_temp(UfsHc *u)
1370 {
1371 uint8_t feat_sup = u->device_desc.ufs_features_support;
1372 bool high_temp_sup, low_temp_sup, high_temp_en, low_temp_en;
1373 uint16_t ee_control = be16_to_cpu(u->attributes.exception_event_control);
1374
1375 high_temp_sup = feat_sup & UFS_DEV_HIGH_TEMP_NOTIF;
1376 low_temp_sup = feat_sup & UFS_DEV_LOW_TEMP_NOTIF;
1377 high_temp_en = ee_control & MASK_EE_TOO_HIGH_TEMP;
1378 low_temp_en = ee_control & MASK_EE_TOO_LOW_TEMP;
1379
1380 if ((high_temp_sup && high_temp_en) ||
1381 (low_temp_sup && low_temp_en)) {
1382 return u->temperature;
1383 }
1384
1385 return 0;
1386 }
1387
1388 static inline uint32_t ufs_wb_read_flush_status(UfsHc *u)
1389 {
1390 uint32_t value = u->attributes.wb_buffer_flush_status;
1391
1392 if (value == UFS_WB_FLUSH_SUSPENDED || value == UFS_WB_FLUSH_COMPLETED ||
1393 value == UFS_WB_FLUSH_FAILED) {
1394 u->attributes.wb_buffer_flush_status = UFS_WB_FLUSH_IDLE;
1395 }
1396
1397 return value;
1398 }
1399
1400 static inline uint32_t ufs_wb_read_resize_status(UfsHc *u)
1401 {
1402 uint32_t value = u->attributes.wb_buffer_resize_status;
1403
1404 if (value == UFS_WB_RESIZE_COMPLETED || value == UFS_WB_RESIZE_FAILED) {
1405 u->attributes.wb_buffer_resize_status = UFS_WB_RESIZE_IDLE;
1406 }
1407
1408 return value;
1409 }
1410
1411 static void ufs_hid_reset(UfsHc *u)
1412 {
1413 u->attributes.defrag_op = UFS_HID_OP_DISABLE;
1414 u->attributes.hid_state = UFS_HID_STATE_IDLE;
1415 u->attributes.hid_prog_ratio = 0;
1416 u->attributes.hid_avail_size = cpu_to_be32(0xFFFFFFFF);
1417 u->hid_defrag_total = 0;
1418 u->hid_defrag_remaining = 0;
1419 }
1420
1421 static uint32_t ufs_hid_read_progress_ratio(UfsHc *u)
1422 {
1423 uint32_t value = u->attributes.hid_prog_ratio;
1424
1425 if (value == UFS_HID_PROGRESS_COMPLETE) {
1426 ufs_hid_reset(u);
1427 }
1428
1429 return value;
1430 }
1431
1432 static uint32_t ufs_read_attr_value(UfsHc *u, uint8_t idn)
1433 {
1434 uint8_t state;
1435
1436 switch (idn) {
1437 case UFS_QUERY_ATTR_IDN_BOOT_LU_EN:
1438 return u->attributes.boot_lun_en;
1439 case UFS_QUERY_ATTR_IDN_POWER_MODE:
1440 return u->attributes.current_power_mode;
1441 case UFS_QUERY_ATTR_IDN_ACTIVE_ICC_LVL:
1442 return u->attributes.active_icc_level;
1443 case UFS_QUERY_ATTR_IDN_OOO_DATA_EN:
1444 return u->attributes.out_of_order_data_en;
1445 case UFS_QUERY_ATTR_IDN_BKOPS_STATUS:
1446 return u->attributes.background_op_status;
1447 case UFS_QUERY_ATTR_IDN_PURGE_STATUS:
1448 return u->attributes.purge_status;
1449 case UFS_QUERY_ATTR_IDN_MAX_DATA_IN:
1450 return u->attributes.max_data_in_size;
1451 case UFS_QUERY_ATTR_IDN_MAX_DATA_OUT:
1452 return u->attributes.max_data_out_size;
1453 case UFS_QUERY_ATTR_IDN_DYN_CAP_NEEDED:
1454 return be32_to_cpu(u->attributes.dyn_cap_needed);
1455 case UFS_QUERY_ATTR_IDN_REF_CLK_FREQ:
1456 return u->attributes.ref_clk_freq;
1457 case UFS_QUERY_ATTR_IDN_CONF_DESC_LOCK:
1458 return u->attributes.config_descr_lock;
1459 case UFS_QUERY_ATTR_IDN_MAX_NUM_OF_RTT:
1460 return u->attributes.max_num_of_rtt;
1461 case UFS_QUERY_ATTR_IDN_EE_CONTROL:
1462 return be16_to_cpu(u->attributes.exception_event_control);
1463 case UFS_QUERY_ATTR_IDN_EE_STATUS:
1464 ufs_update_ee_status(u);
1465 return be16_to_cpu(u->attributes.exception_event_status);
1466 case UFS_QUERY_ATTR_IDN_SECONDS_PASSED:
1467 return be32_to_cpu(u->attributes.seconds_passed);
1468 case UFS_QUERY_ATTR_IDN_CNTX_CONF:
1469 return be16_to_cpu(u->attributes.context_conf);
1470 case UFS_QUERY_ATTR_IDN_FFU_STATUS:
1471 return u->attributes.device_ffu_status;
1472 case UFS_QUERY_ATTR_IDN_PSA_STATE:
1473 return be32_to_cpu(u->attributes.psa_state);
1474 case UFS_QUERY_ATTR_IDN_PSA_DATA_SIZE:
1475 return be32_to_cpu(u->attributes.psa_data_size);
1476 case UFS_QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME:
1477 return u->attributes.ref_clk_gating_wait_time;
1478 case UFS_QUERY_ATTR_IDN_CASE_ROUGH_TEMP:
1479 u->attributes.device_case_rough_temperature = ufs_read_device_temp(u);
1480 return u->attributes.device_case_rough_temperature;
1481 case UFS_QUERY_ATTR_IDN_HIGH_TEMP_BOUND:
1482 return u->attributes.device_too_high_temp_boundary;
1483 case UFS_QUERY_ATTR_IDN_LOW_TEMP_BOUND:
1484 return u->attributes.device_too_low_temp_boundary;
1485 case UFS_QUERY_ATTR_IDN_THROTTLING_STATUS:
1486 return u->attributes.throttling_status;
1487 case UFS_QUERY_ATTR_IDN_WB_FLUSH_STATUS:
1488 return ufs_wb_read_flush_status(u);
1489 case UFS_QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE:
1490 return u->attributes.available_wb_buffer_size;
1491 case UFS_QUERY_ATTR_IDN_WB_BUFF_LIFE_TIME_EST:
1492 return u->attributes.wb_buffer_life_time_est;
1493 case UFS_QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE:
1494 return be32_to_cpu(u->attributes.current_wb_buffer_size);
1495 case UFS_QUERY_ATTR_IDN_EXT_IID_EN:
1496 return u->attributes.ext_iid_en;
1497 case UFS_QUERY_ATTR_IDN_HOST_HINT_CACHE_SIZE:
1498 return be16_to_cpu(u->attributes.host_hint_cache_size);
1499 case UFS_QUERY_ATTR_IDN_REFRESH_STATUS:
1500 return u->attributes.refresh_status;
1501 case UFS_QUERY_ATTR_IDN_REFRESH_FREQ:
1502 return u->attributes.refresh_freq;
1503 case UFS_QUERY_ATTR_IDN_REFRESH_UNIT:
1504 return u->attributes.refresh_unit;
1505 case UFS_QUERY_ATTR_IDN_DEVICE_LEVEL_EXCEPTION_ID:
1506 return be64_to_cpu(u->attributes.device_level_exception_id);
1507 case UFS_QUERY_ATTR_IDN_DEFRAG_OP:
1508 return u->attributes.defrag_op;
1509 case UFS_QUERY_ATTR_IDN_HID_AVAIL_SIZE:
1510 return be32_to_cpu(u->attributes.hid_avail_size);
1511 case UFS_QUERY_ATTR_IDN_HID_SIZE:
1512 return be32_to_cpu(u->attributes.hid_size);
1513 case UFS_QUERY_ATTR_IDN_HID_PROG_RATIO:
1514 return ufs_hid_read_progress_ratio(u);
1515 case UFS_QUERY_ATTR_IDN_HID_STATE:
1516 state = u->attributes.hid_state;
1517
1518 if (state == UFS_HID_STATE_DEFRAG_COMPLETED ||
1519 state == UFS_HID_STATE_DEFRAG_NOT_REQUIRED) {
1520 ufs_hid_reset(u);
1521 }
1522
1523 return state;
1524 case UFS_QUERY_ATTR_IDN_WB_BUFF_RESIZE_HINT:
1525 return u->attributes.wb_buffer_resize_hint;
1526 case UFS_QUERY_ATTR_IDN_WB_BUFF_RESIZE_STATUS:
1527 return ufs_wb_read_resize_status(u);
1528 case UFS_QUERY_ATTR_IDN_WB_BUFF_PARTIAL_FLUSH_MODE:
1529 return u->attributes.wb_buffer_partial_flush_mode;
1530 case UFS_QUERY_ATTR_IDN_MAX_FIFO_WB_PARTIAL_FLUSH_MODE:
1531 return be32_to_cpu(u->attributes.max_fifo_wb_partial_flush_mode);
1532 case UFS_QUERY_ATTR_IDN_CURR_FIFO_WB_PARTIAL_FLUSH_MODE:
1533 return be32_to_cpu(u->attributes.curr_fifo_wb_partial_flush_mode);
1534 case UFS_QUERY_ATTR_IDN_PINNED_WB_BUFF_CURR_ALLOC_UNITS:
1535 return be32_to_cpu(u->attributes.pinned_wb_buffer_curr_alloc_units);
1536 case UFS_QUERY_ATTR_IDN_PINNED_WB_BUFF_AVAIL_PERCENT:
1537 return u->attributes.pinned_wb_buffer_avail_percent;
1538 case UFS_QUERY_ATTR_IDN_PINNED_WB_CUMM_WRITTEN_SIZE:
1539 return be32_to_cpu(u->attributes.pinned_wb_cumm_written_size);
1540 case UFS_QUERY_ATTR_IDN_PINNED_WB_NUM_ALLOC_UNITS:
1541 return be32_to_cpu(u->attributes.pinned_wb_num_alloc_units);
1542 case UFS_QUERY_ATTR_IDN_NON_PINNED_WB_MIN_NUM_ALLOC_UNITS:
1543 return be32_to_cpu(u->attributes.non_pinned_wb_min_num_alloc_units);
1544 }
1545 return 0;
1546 }
1547
1548 static void ufs_wb_resize_op(UfsHc *u, uint32_t value)
1549 {
1550 if (u->attributes.wb_buffer_resize_status == UFS_WB_RESIZE_IN_PROGRESS) {
1551 return;
1552 }
1553
1554 if (value == UFS_WB_IDLE) {
1555 return;
1556 }
1557
1558 u->attributes.wb_buffer_resize_en = value;
1559 u->attributes.wb_buffer_resize_status = UFS_WB_RESIZE_IN_PROGRESS;
1560 u->attributes.wb_buffer_resize_hint = UFS_WB_HINT_KEEP;
1561 }
1562
1563 void ufs_wb_update_avail_buffer(UfsHc *u)
1564 {
1565 UfsWb *wb = &u->wb;
1566 uint64_t non_pinned_curr_bytes, non_pinned_used_bytes;
1567 uint32_t units;
1568
1569 units = ufs_byte_to_unit(u, wb->fifo_curr_bytes);
1570 u->attributes.curr_fifo_wb_partial_flush_mode = cpu_to_be32(units);
1571
1572 units = ufs_byte_to_unit(u, wb->pinned_curr_bytes);
1573 u->attributes.pinned_wb_buffer_curr_alloc_units = cpu_to_be32(units);
1574
1575 if (wb->pinned_curr_bytes <= wb->pinned_used_bytes)
1576 u->attributes.pinned_wb_buffer_avail_percent = 0;
1577 else
1578 u->attributes.pinned_wb_buffer_avail_percent =
1579 (wb->pinned_curr_bytes - wb->pinned_used_bytes) * 10 /
1580 wb->pinned_curr_bytes;
1581
1582 non_pinned_curr_bytes = wb->curr_bytes - wb->pinned_curr_bytes;
1583 non_pinned_used_bytes = wb->used_bytes - wb->pinned_used_bytes;
1584
1585 units = ufs_byte_to_unit(u, non_pinned_curr_bytes);
1586 u->attributes.current_wb_buffer_size = cpu_to_be32(units);
1587
1588 if (!non_pinned_curr_bytes)
1589 u->attributes.available_wb_buffer_size = 0;
1590 else
1591 u->attributes.available_wb_buffer_size =
1592 (non_pinned_curr_bytes - non_pinned_used_bytes) * 10 /
1593 non_pinned_curr_bytes;
1594
1595 assert(wb->curr_bytes >= wb->pinned_curr_bytes);
1596 assert(wb->used_bytes >= wb->pinned_used_bytes);
1597 }
1598
1599 static void ufs_wb_sync_buffer_size(UfsHc *u)
1600 {
1601 UfsWb *wb = &u->wb;
1602 uint64_t avail_bytes;
1603
1604 wb->fifo_curr_bytes = MIN(wb->curr_bytes, wb->fifo_max_bytes);
1605 avail_bytes = wb->curr_bytes - wb->used_bytes + wb->pinned_used_bytes;
1606
1607 if ((u->attributes.wb_buffer_partial_flush_mode != UFS_WB_FLUSH_PINNED) ||
1608 (wb->curr_bytes <= wb->non_pinned_min_bytes)) {
1609 wb->pinned_curr_bytes = 0;
1610 wb->pinned_used_bytes = 0;
1611
1612 } else if (avail_bytes <= wb->pinned_max_bytes) {
1613 wb->pinned_curr_bytes = avail_bytes;
1614 wb->pinned_used_bytes =
1615 MIN(wb->pinned_curr_bytes, wb->pinned_used_bytes);
1616
1617 } else {
1618 wb->pinned_curr_bytes = wb->pinned_max_bytes;
1619 wb->pinned_used_bytes =
1620 MIN(wb->pinned_curr_bytes, wb->pinned_used_bytes);
1621 }
1622
1623 ufs_wb_update_avail_buffer(u);
1624 }
1625
1626 static bool ufs_wb_max_fifo(UfsHc *u, uint32_t value)
1627 {
1628 UfsWb *wb = &u->wb;
1629 uint64_t fifo_max_bytes = ufs_unit_to_byte(u, value);
1630
1631 if (fifo_max_bytes > wb->max_bytes) {
1632 return false;
1633 }
1634
1635 u->attributes.max_fifo_wb_partial_flush_mode = cpu_to_be32(value);
1636 wb->fifo_max_bytes = fifo_max_bytes;
1637 ufs_wb_sync_buffer_size(u);
1638
1639 return true;
1640 }
1641
1642 static bool ufs_wb_pinned_max_size(UfsHc *u, uint32_t value)
1643 {
1644 UfsWb *wb = &u->wb;
1645 uint64_t pinned_max_bytes = ufs_unit_to_byte(u, value);
1646
1647 if (wb->max_bytes < wb->non_pinned_min_bytes + pinned_max_bytes) {
1648 return false;
1649 }
1650
1651 u->attributes.pinned_wb_num_alloc_units = cpu_to_be32(value);
1652 wb->pinned_max_bytes = pinned_max_bytes;
1653 ufs_wb_sync_buffer_size(u);
1654
1655 return true;
1656 }
1657
1658 static bool ufs_wb_pinned_min_size(UfsHc *u, uint32_t value)
1659 {
1660 UfsWb *wb = &u->wb;
1661 uint64_t non_pinned_min_bytes = ufs_unit_to_byte(u, value);
1662
1663 if (wb->max_bytes < non_pinned_min_bytes + wb->pinned_max_bytes) {
1664 return false;
1665 }
1666
1667 u->attributes.non_pinned_wb_min_num_alloc_units = cpu_to_be32(value);
1668 wb->non_pinned_min_bytes = non_pinned_min_bytes;
1669 ufs_wb_sync_buffer_size(u);
1670
1671 return true;
1672 }
1673
1674 static QueryRespCode ufs_hid_write_defrag_operation(UfsHc *u, uint32_t value)
1675 {
1676 switch (value) {
1677 case UFS_HID_OP_DISABLE:
1678 ufs_hid_reset(u);
1679 break;
1680 case UFS_HID_OP_ANALYSIS:
1681 case UFS_HID_OP_DEFRAG:
1682 u->attributes.defrag_op = value;
1683 u->attributes.hid_state = UFS_HID_STATE_ANALYSIS_IN_PROGRESS;
1684 u->attributes.hid_prog_ratio = 0;
1685 break;
1686 default:
1687 return UFS_QUERY_RESULT_INVALID_VALUE;
1688 }
1689
1690 trace_ufs_hid_defrag_operation(value, u->attributes.hid_state);
1691 return UFS_QUERY_RESULT_SUCCESS;
1692 }
1693
1694 static QueryRespCode ufs_write_attr_value(UfsHc *u, uint8_t idn, uint32_t value)
1695 {
1696 switch (idn) {
1697 case UFS_QUERY_ATTR_IDN_ACTIVE_ICC_LVL:
1698 if (value > UFS_QUERY_ATTR_ACTIVE_ICC_MAXVALUE) {
1699 return UFS_QUERY_RESULT_INVALID_VALUE;
1700 }
1701 u->attributes.active_icc_level = value;
1702 break;
1703 case UFS_QUERY_ATTR_IDN_MAX_DATA_IN:
1704 u->attributes.max_data_in_size = value;
1705 break;
1706 case UFS_QUERY_ATTR_IDN_MAX_DATA_OUT:
1707 u->attributes.max_data_out_size = value;
1708 break;
1709 case UFS_QUERY_ATTR_IDN_REF_CLK_FREQ:
1710 u->attributes.ref_clk_freq = value;
1711 break;
1712 case UFS_QUERY_ATTR_IDN_MAX_NUM_OF_RTT:
1713 u->attributes.max_num_of_rtt = value;
1714 break;
1715 case UFS_QUERY_ATTR_IDN_EE_CONTROL:
1716 u->attributes.exception_event_control = cpu_to_be16(value);
1717 break;
1718 case UFS_QUERY_ATTR_IDN_SECONDS_PASSED:
1719 u->attributes.seconds_passed = cpu_to_be32(value);
1720 break;
1721 case UFS_QUERY_ATTR_IDN_PSA_STATE:
1722 u->attributes.psa_state = value;
1723 break;
1724 case UFS_QUERY_ATTR_IDN_PSA_DATA_SIZE:
1725 u->attributes.psa_data_size = cpu_to_be32(value);
1726 break;
1727 case UFS_QUERY_ATTR_IDN_TIMESTAMP:
1728 u->attributes.timestamp = cpu_to_be64(value);
1729 break;
1730 case UFS_QUERY_ATTR_IDN_WB_BUFF_RESIZE_EN:
1731 if (value >= UFS_WB_RESIZE_OP_MAX) {
1732 return UFS_QUERY_RESULT_INVALID_VALUE;
1733 }
1734 ufs_wb_resize_op(u, value);
1735 break;
1736 case UFS_QUERY_ATTR_IDN_WB_BUFF_PARTIAL_FLUSH_MODE:
1737 if (value >= UFS_WB_FLUSH_MODE_MAX) {
1738 return UFS_QUERY_RESULT_INVALID_VALUE;
1739 }
1740 u->attributes.wb_buffer_partial_flush_mode = value;
1741 ufs_wb_sync_buffer_size(u);
1742 break;
1743 case UFS_QUERY_ATTR_IDN_MAX_FIFO_WB_PARTIAL_FLUSH_MODE:
1744 if (!ufs_wb_max_fifo(u, value)) {
1745 return UFS_QUERY_RESULT_INVALID_VALUE;
1746 }
1747 break;
1748 case UFS_QUERY_ATTR_IDN_PINNED_WB_NUM_ALLOC_UNITS:
1749 if (!ufs_wb_pinned_max_size(u, value)) {
1750 return UFS_QUERY_RESULT_INVALID_VALUE;
1751 }
1752 break;
1753 case UFS_QUERY_ATTR_IDN_NON_PINNED_WB_MIN_NUM_ALLOC_UNITS:
1754 if (!ufs_wb_pinned_min_size(u, value)) {
1755 return UFS_QUERY_RESULT_INVALID_VALUE;
1756 }
1757 break;
1758 case UFS_QUERY_ATTR_IDN_DEFRAG_OP:
1759 return ufs_hid_write_defrag_operation(u, value);
1760 case UFS_QUERY_ATTR_IDN_HID_SIZE:
1761 u->attributes.hid_size = cpu_to_be32(value);
1762 break;
1763 default:
1764 g_assert_not_reached();
1765 return 0;
1766 }
1767 return UFS_QUERY_RESULT_SUCCESS;
1768 }
1769
1770 static QueryRespCode ufs_exec_query_attr(UfsRequest *req, int op)
1771 {
1772 UfsHc *u = req->hc;
1773 uint8_t idn = req->req_upiu.qr.idn;
1774 uint32_t value;
1775 QueryRespCode ret;
1776
1777 ret = ufs_attr_check_idn_valid(idn, op);
1778 if (ret) {
1779 return ret;
1780 }
1781
1782 if (op == UFS_QUERY_ATTR_READ) {
1783 value = ufs_read_attr_value(u, idn);
1784 ret = UFS_QUERY_RESULT_SUCCESS;
1785 } else {
1786 value = be32_to_cpu(req->req_upiu.qr.value);
1787 ret = ufs_write_attr_value(u, idn, value);
1788 }
1789 req->rsp_upiu.qr.value = cpu_to_be32(value);
1790 return ret;
1791 }
1792
1793 static const RpmbUnitDescriptor rpmb_unit_desc = {
1794 .length = sizeof(RpmbUnitDescriptor),
1795 .descriptor_idn = 2,
1796 .unit_index = UFS_UPIU_RPMB_WLUN,
1797 .lu_enable = 0,
1798 };
1799
1800 static QueryRespCode ufs_read_unit_desc(UfsRequest *req)
1801 {
1802 UfsHc *u = req->hc;
1803 uint8_t lun = req->req_upiu.qr.index;
1804
1805 if (lun != UFS_UPIU_RPMB_WLUN &&
1806 (lun >= UFS_MAX_LUS || u->lus[lun] == NULL)) {
1807 trace_ufs_err_query_invalid_index(req->req_upiu.qr.opcode, lun);
1808 return UFS_QUERY_RESULT_INVALID_INDEX;
1809 }
1810
1811 if (lun == UFS_UPIU_RPMB_WLUN) {
1812 memcpy(&req->rsp_upiu.qr.data, &rpmb_unit_desc, rpmb_unit_desc.length);
1813 } else {
1814 memcpy(&req->rsp_upiu.qr.data, &u->lus[lun]->unit_desc,
1815 sizeof(u->lus[lun]->unit_desc));
1816 }
1817
1818 return UFS_QUERY_RESULT_SUCCESS;
1819 }
1820
1821 static inline StringDescriptor manufacturer_str_desc(void)
1822 {
1823 StringDescriptor desc = {
1824 .length = 0x12,
1825 .descriptor_idn = UFS_QUERY_DESC_IDN_STRING,
1826 };
1827 desc.UC[0] = cpu_to_be16('R');
1828 desc.UC[1] = cpu_to_be16('E');
1829 desc.UC[2] = cpu_to_be16('D');
1830 desc.UC[3] = cpu_to_be16('H');
1831 desc.UC[4] = cpu_to_be16('A');
1832 desc.UC[5] = cpu_to_be16('T');
1833 return desc;
1834 }
1835
1836 static inline StringDescriptor product_name_str_desc(void)
1837 {
1838 StringDescriptor desc = {
1839 .length = 0x22,
1840 .descriptor_idn = UFS_QUERY_DESC_IDN_STRING,
1841 };
1842 desc.UC[0] = cpu_to_be16('Q');
1843 desc.UC[1] = cpu_to_be16('E');
1844 desc.UC[2] = cpu_to_be16('M');
1845 desc.UC[3] = cpu_to_be16('U');
1846 desc.UC[4] = cpu_to_be16(' ');
1847 desc.UC[5] = cpu_to_be16('U');
1848 desc.UC[6] = cpu_to_be16('F');
1849 desc.UC[7] = cpu_to_be16('S');
1850 return desc;
1851 }
1852
1853 static inline StringDescriptor product_rev_level_str_desc(void)
1854 {
1855 StringDescriptor desc = {
1856 .length = 0x0a,
1857 .descriptor_idn = UFS_QUERY_DESC_IDN_STRING,
1858 };
1859 desc.UC[0] = cpu_to_be16('0');
1860 desc.UC[1] = cpu_to_be16('0');
1861 desc.UC[2] = cpu_to_be16('0');
1862 desc.UC[3] = cpu_to_be16('1');
1863 return desc;
1864 }
1865
1866 static const StringDescriptor null_str_desc = {
1867 .length = 0x02,
1868 .descriptor_idn = UFS_QUERY_DESC_IDN_STRING,
1869 };
1870
1871 static QueryRespCode ufs_read_string_desc(UfsRequest *req)
1872 {
1873 UfsHc *u = req->hc;
1874 uint8_t index = req->req_upiu.qr.index;
1875 StringDescriptor desc;
1876
1877 if (index == u->device_desc.manufacturer_name) {
1878 desc = manufacturer_str_desc();
1879 memcpy(&req->rsp_upiu.qr.data, &desc, desc.length);
1880 } else if (index == u->device_desc.product_name) {
1881 desc = product_name_str_desc();
1882 memcpy(&req->rsp_upiu.qr.data, &desc, desc.length);
1883 } else if (index == u->device_desc.serial_number) {
1884 memcpy(&req->rsp_upiu.qr.data, &null_str_desc, null_str_desc.length);
1885 } else if (index == u->device_desc.oem_id) {
1886 memcpy(&req->rsp_upiu.qr.data, &null_str_desc, null_str_desc.length);
1887 } else if (index == u->device_desc.product_revision_level) {
1888 desc = product_rev_level_str_desc();
1889 memcpy(&req->rsp_upiu.qr.data, &desc, desc.length);
1890 } else {
1891 trace_ufs_err_query_invalid_index(req->req_upiu.qr.opcode, index);
1892 return UFS_QUERY_RESULT_INVALID_INDEX;
1893 }
1894 return UFS_QUERY_RESULT_SUCCESS;
1895 }
1896
1897 static inline InterconnectDescriptor interconnect_desc(void)
1898 {
1899 InterconnectDescriptor desc = {
1900 .length = sizeof(InterconnectDescriptor),
1901 .descriptor_idn = UFS_QUERY_DESC_IDN_INTERCONNECT,
1902 };
1903 desc.bcd_unipro_version = cpu_to_be16(0x180);
1904 desc.bcd_mphy_version = cpu_to_be16(0x410);
1905 return desc;
1906 }
1907
1908 static QueryRespCode ufs_read_desc(UfsRequest *req)
1909 {
1910 UfsHc *u = req->hc;
1911 QueryRespCode status;
1912 uint8_t idn = req->req_upiu.qr.idn;
1913 uint8_t selector = req->req_upiu.qr.selector;
1914 uint16_t length = be16_to_cpu(req->req_upiu.qr.length);
1915 InterconnectDescriptor desc;
1916 if (selector != 0) {
1917 return UFS_QUERY_RESULT_INVALID_SELECTOR;
1918 }
1919 switch (idn) {
1920 case UFS_QUERY_DESC_IDN_DEVICE:
1921 memcpy(&req->rsp_upiu.qr.data, &u->device_desc, sizeof(u->device_desc));
1922 status = UFS_QUERY_RESULT_SUCCESS;
1923 break;
1924 case UFS_QUERY_DESC_IDN_UNIT:
1925 status = ufs_read_unit_desc(req);
1926 break;
1927 case UFS_QUERY_DESC_IDN_GEOMETRY:
1928 memcpy(&req->rsp_upiu.qr.data, &u->geometry_desc,
1929 sizeof(u->geometry_desc));
1930 status = UFS_QUERY_RESULT_SUCCESS;
1931 break;
1932 case UFS_QUERY_DESC_IDN_INTERCONNECT: {
1933 desc = interconnect_desc();
1934 memcpy(&req->rsp_upiu.qr.data, &desc, sizeof(InterconnectDescriptor));
1935 status = UFS_QUERY_RESULT_SUCCESS;
1936 break;
1937 }
1938 case UFS_QUERY_DESC_IDN_STRING:
1939 status = ufs_read_string_desc(req);
1940 break;
1941 case UFS_QUERY_DESC_IDN_POWER:
1942 /* mocking of power descriptor is not supported */
1943 memset(&req->rsp_upiu.qr.data, 0, sizeof(PowerParametersDescriptor));
1944 req->rsp_upiu.qr.data[0] = sizeof(PowerParametersDescriptor);
1945 req->rsp_upiu.qr.data[1] = UFS_QUERY_DESC_IDN_POWER;
1946 status = UFS_QUERY_RESULT_SUCCESS;
1947 break;
1948 case UFS_QUERY_DESC_IDN_HEALTH:
1949 /* mocking of health descriptor is not supported */
1950 memset(&req->rsp_upiu.qr.data, 0, sizeof(DeviceHealthDescriptor));
1951 req->rsp_upiu.qr.data[0] = sizeof(DeviceHealthDescriptor);
1952 req->rsp_upiu.qr.data[1] = UFS_QUERY_DESC_IDN_HEALTH;
1953 status = UFS_QUERY_RESULT_SUCCESS;
1954 break;
1955 default:
1956 length = 0;
1957 trace_ufs_err_query_invalid_idn(req->req_upiu.qr.opcode, idn);
1958 status = UFS_QUERY_RESULT_INVALID_IDN;
1959 }
1960
1961 if (length > req->rsp_upiu.qr.data[0]) {
1962 length = req->rsp_upiu.qr.data[0];
1963 }
1964 req->rsp_upiu.qr.length = cpu_to_be16(length);
1965
1966 return status;
1967 }
1968
1969 static QueryRespCode ufs_exec_query_read(UfsRequest *req)
1970 {
1971 QueryRespCode status;
1972 switch (req->req_upiu.qr.opcode) {
1973 case UFS_UPIU_QUERY_OPCODE_NOP:
1974 status = UFS_QUERY_RESULT_SUCCESS;
1975 break;
1976 case UFS_UPIU_QUERY_OPCODE_READ_DESC:
1977 status = ufs_read_desc(req);
1978 break;
1979 case UFS_UPIU_QUERY_OPCODE_READ_ATTR:
1980 status = ufs_exec_query_attr(req, UFS_QUERY_ATTR_READ);
1981 break;
1982 case UFS_UPIU_QUERY_OPCODE_READ_FLAG:
1983 status = ufs_exec_query_flag(req, UFS_QUERY_FLAG_READ);
1984 break;
1985 default:
1986 trace_ufs_err_query_invalid_opcode(req->req_upiu.qr.opcode);
1987 status = UFS_QUERY_RESULT_INVALID_OPCODE;
1988 break;
1989 }
1990
1991 return status;
1992 }
1993
1994 static QueryRespCode ufs_exec_query_write(UfsRequest *req)
1995 {
1996 QueryRespCode status;
1997 switch (req->req_upiu.qr.opcode) {
1998 case UFS_UPIU_QUERY_OPCODE_NOP:
1999 status = UFS_QUERY_RESULT_SUCCESS;
2000 break;
2001 case UFS_UPIU_QUERY_OPCODE_WRITE_DESC:
2002 /* write descriptor is not supported */
2003 status = UFS_QUERY_RESULT_NOT_WRITEABLE;
2004 break;
2005 case UFS_UPIU_QUERY_OPCODE_WRITE_ATTR:
2006 status = ufs_exec_query_attr(req, UFS_QUERY_ATTR_WRITE);
2007 break;
2008 case UFS_UPIU_QUERY_OPCODE_SET_FLAG:
2009 status = ufs_exec_query_flag(req, UFS_QUERY_FLAG_SET);
2010 break;
2011 case UFS_UPIU_QUERY_OPCODE_CLEAR_FLAG:
2012 status = ufs_exec_query_flag(req, UFS_QUERY_FLAG_CLEAR);
2013 break;
2014 case UFS_UPIU_QUERY_OPCODE_TOGGLE_FLAG:
2015 status = ufs_exec_query_flag(req, UFS_QUERY_FLAG_TOGGLE);
2016 break;
2017 default:
2018 trace_ufs_err_query_invalid_opcode(req->req_upiu.qr.opcode);
2019 status = UFS_QUERY_RESULT_INVALID_OPCODE;
2020 break;
2021 }
2022
2023 return status;
2024 }
2025
2026 static UfsReqResult ufs_exec_query_cmd(UfsRequest *req)
2027 {
2028 uint8_t query_func = req->req_upiu.header.query_func;
2029 uint16_t data_segment_length;
2030 QueryRespCode status;
2031
2032 trace_ufs_exec_query_cmd(req->slot, req->req_upiu.qr.opcode);
2033 if (query_func == UFS_UPIU_QUERY_FUNC_STANDARD_READ_REQUEST) {
2034 status = ufs_exec_query_read(req);
2035 } else if (query_func == UFS_UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST) {
2036 status = ufs_exec_query_write(req);
2037 } else {
2038 status = UFS_QUERY_RESULT_GENERAL_FAILURE;
2039 }
2040
2041 data_segment_length = be16_to_cpu(req->rsp_upiu.qr.length);
2042 ufs_build_upiu_header(req, UFS_UPIU_TRANSACTION_QUERY_RSP, 0, status, 0,
2043 data_segment_length);
2044 ufs_build_query_response(req);
2045
2046 if (status != UFS_QUERY_RESULT_SUCCESS) {
2047 return UFS_REQUEST_FAIL;
2048 }
2049 return UFS_REQUEST_SUCCESS;
2050 }
2051
2052 static void ufs_exec_req(UfsRequest *req)
2053 {
2054 UfsReqResult req_result;
2055
2056 if (ufs_dma_read_upiu(req)) {
2057 return;
2058 }
2059
2060 switch (req->req_upiu.header.trans_type) {
2061 case UFS_UPIU_TRANSACTION_NOP_OUT:
2062 req_result = ufs_exec_nop_cmd(req);
2063 break;
2064 case UFS_UPIU_TRANSACTION_COMMAND:
2065 req_result = ufs_exec_scsi_cmd(req);
2066 break;
2067 case UFS_UPIU_TRANSACTION_QUERY_REQ:
2068 req_result = ufs_exec_query_cmd(req);
2069 break;
2070 default:
2071 trace_ufs_err_invalid_trans_code(req->slot,
2072 req->req_upiu.header.trans_type);
2073 req_result = UFS_REQUEST_FAIL;
2074 }
2075
2076 /*
2077 * The ufs_complete_req for scsi commands is handled by the
2078 * ufs_scsi_command_complete() callback function. Therefore, to avoid
2079 * duplicate processing, ufs_complete_req() is not called for scsi commands.
2080 */
2081 if (req_result != UFS_REQUEST_NO_COMPLETE) {
2082 ufs_complete_req(req, req_result);
2083 }
2084 }
2085
2086 static void ufs_process_req(void *opaque)
2087 {
2088 UfsHc *u = opaque;
2089 UfsRequest *req;
2090 int slot;
2091
2092 for (slot = 0; slot < u->params.nutrs; slot++) {
2093 req = &u->req_list[slot];
2094
2095 if (req->state != UFS_REQUEST_READY) {
2096 continue;
2097 }
2098 trace_ufs_process_req(slot);
2099 req->state = UFS_REQUEST_RUNNING;
2100
2101 ufs_exec_req(req);
2102 }
2103 }
2104
2105 void ufs_complete_req(UfsRequest *req, UfsReqResult req_result)
2106 {
2107 UfsHc *u = req->hc;
2108 assert(req->state == UFS_REQUEST_RUNNING);
2109
2110 if (req_result == UFS_REQUEST_SUCCESS) {
2111 req->utrd.header.dword_2 = cpu_to_le32(UFS_OCS_SUCCESS);
2112 } else {
2113 req->utrd.header.dword_2 = cpu_to_le32(UFS_OCS_INVALID_CMD_TABLE_ATTR);
2114 }
2115
2116 req->state = UFS_REQUEST_COMPLETE;
2117
2118 if (ufs_mcq_req(req)) {
2119 trace_ufs_mcq_complete_req(req->sq->sqid);
2120 QTAILQ_INSERT_TAIL(&req->sq->cq->req_list, req, entry);
2121 qemu_bh_schedule(req->sq->cq->bh);
2122 } else {
2123 trace_ufs_complete_req(req->slot);
2124 qemu_bh_schedule(u->complete_bh);
2125 }
2126 }
2127
2128 static void ufs_clear_req(UfsRequest *req)
2129 {
2130 if (req->sg != NULL) {
2131 qemu_sglist_destroy(req->sg);
2132 g_free(req->sg);
2133 req->sg = NULL;
2134 req->data_len = 0;
2135 }
2136
2137 memset(&req->utrd, 0, sizeof(req->utrd));
2138 memset(&req->req_upiu, 0, sizeof(req->req_upiu));
2139 memset(&req->rsp_upiu, 0, sizeof(req->rsp_upiu));
2140 }
2141
2142 static void ufs_sendback_req(void *opaque)
2143 {
2144 UfsHc *u = opaque;
2145 UfsRequest *req;
2146 int slot;
2147
2148 for (slot = 0; slot < u->params.nutrs; slot++) {
2149 req = &u->req_list[slot];
2150
2151 if (req->state != UFS_REQUEST_COMPLETE) {
2152 continue;
2153 }
2154
2155 if (ufs_dma_write_upiu(req)) {
2156 req->state = UFS_REQUEST_ERROR;
2157 continue;
2158 }
2159
2160 /*
2161 * TODO: UTP Transfer Request Interrupt Aggregation Control is not yet
2162 * supported
2163 */
2164 if (le32_to_cpu(req->utrd.header.dword_2) != UFS_OCS_SUCCESS ||
2165 le32_to_cpu(req->utrd.header.dword_0) & UFS_UTP_REQ_DESC_INT_CMD) {
2166 u->reg.is = FIELD_DP32(u->reg.is, IS, UTRCS, 1);
2167 }
2168
2169 u->reg.utrldbr &= ~(1 << slot);
2170 u->reg.utrlcnr |= (1 << slot);
2171
2172 trace_ufs_sendback_req(req->slot);
2173
2174 ufs_clear_req(req);
2175 req->state = UFS_REQUEST_IDLE;
2176 }
2177
2178 ufs_irq_check(u);
2179 }
2180
2181 static inline uint64_t ufs_wb_total_flush_bytes(UfsHc *u)
2182 {
2183 UfsWb *wb = &u->wb;
2184 uint64_t no_flush_bytes;
2185
2186 switch (u->attributes.wb_buffer_partial_flush_mode) {
2187 case UFS_WB_FLUSH_NONE:
2188 no_flush_bytes = 0;
2189 break;
2190 case UFS_WB_FLUSH_FIFO:
2191 no_flush_bytes = wb->fifo_curr_bytes;
2192 break;
2193 case UFS_WB_FLUSH_PINNED:
2194 no_flush_bytes = (u->flags.unpin_en) ? 0 : wb->pinned_used_bytes;
2195 break;
2196 default:
2197 g_assert_not_reached();
2198 break;
2199 }
2200
2201 if (wb->used_bytes < no_flush_bytes) {
2202 return 0;
2203 }
2204
2205 return wb->used_bytes - no_flush_bytes;
2206 }
2207
2208 #define UFS_WB_FLUSH_BYTES (4096 * 1024)
2209 static void ufs_wb_process_flush(UfsHc *u)
2210 {
2211 UfsWb *wb = &u->wb;
2212 uint64_t flush_bytes, total_flush_bytes;
2213
2214 switch (u->attributes.wb_buffer_flush_status) {
2215 case UFS_WB_FLUSH_IDLE:
2216 case UFS_WB_FLUSH_SUSPENDED:
2217 if (!u->flags.wb_buffer_flush_en || !ufs_wb_total_flush_bytes(u)) {
2218 break;
2219 }
2220
2221 u->attributes.wb_buffer_flush_status = UFS_WB_FLUSH_IN_PROGRESS;
2222 /* fallthrough */
2223 case UFS_WB_FLUSH_IN_PROGRESS:
2224 if (!u->flags.wb_buffer_flush_en) {
2225 u->attributes.wb_buffer_flush_status = UFS_WB_FLUSH_SUSPENDED;
2226 break;
2227 }
2228
2229 total_flush_bytes = ufs_wb_total_flush_bytes(u);
2230 if (!total_flush_bytes) {
2231 u->attributes.wb_buffer_flush_status = UFS_WB_FLUSH_COMPLETED;
2232 break;
2233 }
2234
2235 /* Flush Pinned first */
2236 if (wb->pinned_used_bytes && u->flags.unpin_en) {
2237 flush_bytes = MIN(wb->pinned_used_bytes, UFS_WB_FLUSH_BYTES);
2238 wb->pinned_used_bytes -= flush_bytes;
2239 wb->used_bytes -= flush_bytes;
2240 } else {
2241 flush_bytes = MIN(total_flush_bytes, UFS_WB_FLUSH_BYTES);
2242 wb->used_bytes -= flush_bytes;
2243 }
2244
2245 u->attributes.wb_buffer_flush_status = UFS_WB_FLUSH_COMPLETED;
2246 /* fallthrough */
2247 case UFS_WB_FLUSH_COMPLETED:
2248 if (ufs_wb_total_flush_bytes(u)) {
2249 u->attributes.wb_buffer_flush_status =
2250 (u->flags.wb_buffer_flush_en) ? UFS_WB_FLUSH_IN_PROGRESS :
2251 UFS_WB_FLUSH_IDLE;
2252 }
2253 }
2254 }
2255
2256 static void ufs_wb_process_resize(UfsHc *u)
2257 {
2258 UfsWb *wb = &u->wb;
2259
2260 if (u->attributes.wb_buffer_resize_status != UFS_WB_RESIZE_IN_PROGRESS) {
2261 return;
2262 }
2263
2264 switch (u->attributes.wb_buffer_resize_en) {
2265 case UFS_WB_IDLE:
2266 /* Do nothing. Complete resize directly. */
2267 break;
2268 case UFS_WB_DECREASE:
2269 if (wb->curr_bytes <= wb->min_bytes ||
2270 wb->curr_bytes <= wb->used_bytes) {
2271 u->attributes.wb_buffer_resize_status = UFS_WB_RESIZE_FAILED;
2272 return;
2273 }
2274
2275 if (wb->curr_bytes - wb->used_bytes >= wb->resize_bytes) {
2276 wb->curr_bytes -= wb->resize_bytes;
2277 } else {
2278 wb->curr_bytes = wb->used_bytes;
2279 }
2280
2281 if (wb->curr_bytes < wb->min_bytes) {
2282 wb->curr_bytes = wb->min_bytes;
2283 }
2284
2285 break;
2286 case UFS_WB_INCREASE:
2287 if (wb->curr_bytes >= wb->max_bytes) {
2288 u->attributes.wb_buffer_resize_status = UFS_WB_RESIZE_FAILED;
2289 return;
2290 }
2291
2292 wb->curr_bytes += wb->resize_bytes;
2293 if (wb->curr_bytes >= wb->max_bytes) {
2294 wb->curr_bytes = wb->max_bytes;
2295 }
2296
2297 break;
2298 default:
2299 g_assert_not_reached();
2300 break;
2301 }
2302
2303 u->attributes.wb_buffer_resize_status = UFS_WB_RESIZE_COMPLETED;
2304 }
2305
2306 static void ufs_hid_process(UfsHc *u)
2307 {
2308 uint32_t requested, batch, done;
2309
2310 switch (u->attributes.hid_state) {
2311 case UFS_HID_STATE_ANALYSIS_IN_PROGRESS:
2312 u->attributes.hid_avail_size = cpu_to_be32(u->hid_fragment_count);
2313 if (u->hid_fragment_count > 0) {
2314 u->attributes.hid_state = UFS_HID_STATE_DEFRAG_REQUIRED;
2315 } else {
2316 u->attributes.hid_state = UFS_HID_STATE_DEFRAG_NOT_REQUIRED;
2317 }
2318
2319 if (u->attributes.defrag_op == UFS_HID_OP_ANALYSIS ||
2320 u->attributes.hid_state == UFS_HID_STATE_DEFRAG_NOT_REQUIRED) {
2321 u->attributes.defrag_op = UFS_HID_OP_DISABLE;
2322 }
2323
2324 trace_ufs_hid_defrag_operation(u->attributes.defrag_op,
2325 u->attributes.hid_state);
2326 break;
2327
2328 case UFS_HID_STATE_DEFRAG_REQUIRED:
2329 if (u->attributes.defrag_op != UFS_HID_OP_DEFRAG) {
2330 break;
2331 }
2332
2333 requested = MIN(be32_to_cpu(u->attributes.hid_size),
2334 be32_to_cpu(u->attributes.hid_avail_size));
2335 if (!requested) {
2336 u->attributes.hid_state = UFS_HID_STATE_DEFRAG_COMPLETED;
2337 u->attributes.defrag_op = UFS_HID_OP_DISABLE;
2338 u->attributes.hid_prog_ratio = UFS_HID_PROGRESS_COMPLETE;
2339
2340 trace_ufs_hid_defrag_operation(u->attributes.defrag_op,
2341 u->attributes.hid_state);
2342 break;
2343 }
2344
2345 u->attributes.hid_state = UFS_HID_STATE_DEFRAG_IN_PROGRESS;
2346 u->hid_defrag_total = requested;
2347 u->hid_defrag_remaining = requested;
2348 u->attributes.hid_prog_ratio = 0;
2349 break;
2350
2351 case UFS_HID_STATE_DEFRAG_IN_PROGRESS:
2352 if (u->hid_defrag_remaining > 0) {
2353 batch = u->hid_defrag_remaining / UFS_HID_DEFRAG_BATCH_DIV;
2354 if (batch == 0) {
2355 batch = 1;
2356 }
2357
2358 u->hid_defrag_remaining -= batch;
2359 u->hid_fragment_count -= batch;
2360
2361 done = u->hid_defrag_total - u->hid_defrag_remaining;
2362 u->attributes.hid_prog_ratio =
2363 ((uint64_t)done * UFS_HID_PROGRESS_COMPLETE) /
2364 u->hid_defrag_total;
2365
2366 trace_ufs_hid_defrag_progress(u->hid_defrag_remaining,
2367 u->attributes.hid_prog_ratio);
2368 }
2369
2370 if (!u->hid_defrag_remaining) {
2371 u->attributes.hid_state = UFS_HID_STATE_DEFRAG_COMPLETED;
2372 u->attributes.defrag_op = UFS_HID_OP_DISABLE;
2373 u->attributes.hid_prog_ratio = UFS_HID_PROGRESS_COMPLETE;
2374
2375 trace_ufs_hid_defrag_operation(u->attributes.defrag_op,
2376 u->attributes.hid_state);
2377 }
2378
2379 break;
2380
2381 default:
2382 break;
2383 }
2384 }
2385
2386 static void ufs_process_idle(UfsHc *u)
2387 {
2388 ufs_wb_process_flush(u);
2389 ufs_wb_process_resize(u);
2390 ufs_wb_sync_buffer_size(u);
2391 ufs_hid_process(u);
2392 }
2393
2394 static inline bool ufs_check_idle(UfsHc *u)
2395 {
2396 return !u->reg.utrldbr;
2397 }
2398
2399 static inline bool ufs_mcq_check_idle(UfsHc *u)
2400 {
2401 if (!u->params.mcq) {
2402 return true;
2403 }
2404
2405 for (int qid = 0; qid < ARRAY_SIZE(u->sq); qid++) {
2406 if (!u->sq[qid]) {
2407 continue;
2408 }
2409
2410 if (!ufs_mcq_sq_empty(u, qid)) {
2411 return false;
2412 }
2413
2414 /* internal ongoing MCQ request check */
2415 UfsSq *sq = u->sq[qid];
2416 for (int i = 0; i < sq->size; i++) {
2417 if (sq->req[i].state != UFS_REQUEST_IDLE) {
2418 return false;
2419 }
2420 }
2421 }
2422
2423 for (int qid = 0; qid < ARRAY_SIZE(u->cq); qid++) {
2424 if (!u->cq[qid]) {
2425 continue;
2426 }
2427
2428 if (!ufs_mcq_cq_empty(u, qid)) {
2429 return false;
2430 }
2431
2432 if (!QTAILQ_EMPTY(&u->cq[qid]->req_list)) {
2433 return false;
2434 }
2435 }
2436
2437 return true;
2438 }
2439
2440 #define UFS_IDLE_TIMER_TICK 100 /* 0.1s */
2441 static void ufs_idle_timer_cb(void *opaque)
2442 {
2443 UfsHc *u = opaque;
2444 int64_t now = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL_RT);
2445
2446 if (ufs_check_idle(u) && ufs_mcq_check_idle(u)) {
2447 ufs_process_idle(u);
2448 }
2449
2450 timer_mod(&u->idle_timer, now + UFS_IDLE_TIMER_TICK);
2451 }
2452
2453 static bool ufs_check_constraints(UfsHc *u, Error **errp)
2454 {
2455 if (u->params.nutrs > UFS_MAX_NUTRS) {
2456 error_setg(errp, "nutrs must be less than or equal to %d",
2457 UFS_MAX_NUTRS);
2458 return false;
2459 }
2460
2461 if (u->params.nutmrs > UFS_MAX_NUTMRS) {
2462 error_setg(errp, "nutmrs must be less than or equal to %d",
2463 UFS_MAX_NUTMRS);
2464 return false;
2465 }
2466
2467 if (u->params.mcq_maxq >= UFS_MAX_MCQ_QNUM) {
2468 error_setg(errp, "mcq-maxq must be less than %d", UFS_MAX_MCQ_QNUM);
2469 return false;
2470 }
2471
2472 if (u->params.wb_min_size > u->params.wb_max_size) {
2473 error_setg(errp, "wb-min-size must be less than or equal wb-max-size");
2474 return false;
2475 }
2476
2477 return true;
2478 }
2479
2480 static void ufs_init_state(UfsHc *u)
2481 {
2482 u->req_list = g_new0(UfsRequest, u->params.nutrs);
2483
2484 for (int i = 0; i < u->params.nutrs; i++) {
2485 u->req_list[i].hc = u;
2486 u->req_list[i].slot = i;
2487 u->req_list[i].sg = NULL;
2488 u->req_list[i].state = UFS_REQUEST_IDLE;
2489 }
2490
2491 u->doorbell_bh =
2492 qemu_bh_new_guarded(ufs_process_req, u, &u->dev->mem_reentrancy_guard);
2493 u->complete_bh =
2494 qemu_bh_new_guarded(ufs_sendback_req, u, &u->dev->mem_reentrancy_guard);
2495
2496 if (u->params.mcq) {
2497 memset(u->sq, 0, sizeof(u->sq));
2498 memset(u->cq, 0, sizeof(u->cq));
2499 }
2500 }
2501
2502 static void ufs_wb_init(UfsHc *u)
2503 {
2504 UfsWb *wb = &u->wb;
2505 uint32_t max_units = u->params.wb_max_size;
2506 uint32_t min_units = u->params.wb_min_size;
2507
2508 wb->max_bytes = ufs_unit_to_byte(u, max_units);
2509 wb->min_bytes = ufs_unit_to_byte(u, min_units);
2510
2511 wb->curr_bytes = wb->max_bytes;
2512 wb->used_bytes = 0;
2513 wb->resize_bytes = (wb->max_bytes - wb->min_bytes) / 10;
2514
2515 u->attributes.wb_buffer_flush_status = UFS_WB_FLUSH_IDLE;
2516 u->attributes.available_wb_buffer_size = 0xA;
2517 u->attributes.wb_buffer_life_time_est = 0x1;
2518 u->attributes.current_wb_buffer_size = cpu_to_be32(max_units);
2519
2520 u->attributes.wb_buffer_resize_hint = UFS_WB_HINT_KEEP;
2521 u->attributes.wb_buffer_resize_status = UFS_WB_RESIZE_IDLE;
2522
2523 u->attributes.wb_buffer_partial_flush_mode = UFS_WB_FLUSH_NONE;
2524
2525 u->attributes.max_fifo_wb_partial_flush_mode = cpu_to_be32(max_units);
2526 u->attributes.curr_fifo_wb_partial_flush_mode = cpu_to_be32(max_units);
2527
2528 wb->fifo_max_bytes = ufs_unit_to_byte(u, max_units);
2529 wb->fifo_curr_bytes = ufs_unit_to_byte(u, max_units);
2530
2531 u->attributes.pinned_wb_num_alloc_units = cpu_to_be32(max_units);
2532 u->attributes.non_pinned_wb_min_num_alloc_units = 0;
2533
2534 wb->pinned_curr_bytes = 0;
2535 wb->pinned_used_bytes = 0;
2536 wb->pinned_max_bytes = ufs_unit_to_byte(u, max_units);
2537 wb->non_pinned_min_bytes = 0;
2538 wb->pinned_total_written_bytes = 0;
2539 }
2540
2541 static void ufs_init_hc(UfsHc *u)
2542 {
2543 uint32_t cap = 0;
2544 uint32_t mcqconfig = 0;
2545 uint32_t mcqcap = 0;
2546 uint32_t ext_wb_sup = WB_RESIZE | WB_FIFO | WB_PINNED;
2547 uint32_t ext_ufs_feat_sup = UFS_DEV_WB_SUPPORT | UFS_DEV_HIGH_TEMP_NOTIF |
2548 UFS_DEV_LOW_TEMP_NOTIF | UFS_DEV_HID_SUPPORT;
2549 int64_t now = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL_RT);
2550
2551 u->reg_size = pow2ceil(ufs_reg_size(u));
2552
2553 memset(&u->reg, 0, sizeof(u->reg));
2554 memset(&u->mcq_reg, 0, sizeof(u->mcq_reg));
2555 memset(&u->mcq_op_reg, 0, sizeof(u->mcq_op_reg));
2556 cap = FIELD_DP32(cap, CAP, NUTRS, (u->params.nutrs - 1));
2557 cap = FIELD_DP32(cap, CAP, RTT, 2);
2558 cap = FIELD_DP32(cap, CAP, NUTMRS, (u->params.nutmrs - 1));
2559 cap = FIELD_DP32(cap, CAP, AUTOH8, 0);
2560 cap = FIELD_DP32(cap, CAP, 64AS, 1);
2561 cap = FIELD_DP32(cap, CAP, OODDS, 0);
2562 cap = FIELD_DP32(cap, CAP, UICDMETMS, 0);
2563 cap = FIELD_DP32(cap, CAP, CS, 0);
2564 cap = FIELD_DP32(cap, CAP, LSDBS, 0);
2565 cap = FIELD_DP32(cap, CAP, MCQS, u->params.mcq);
2566 u->reg.cap = cap;
2567
2568 if (u->params.mcq) {
2569 mcqconfig = FIELD_DP32(mcqconfig, MCQCONFIG, MAC, 0x1f);
2570 u->reg.mcqconfig = mcqconfig;
2571
2572 mcqcap = FIELD_DP32(mcqcap, MCQCAP, MAXQ, u->params.mcq_maxq - 1);
2573 mcqcap = FIELD_DP32(mcqcap, MCQCAP, RRP, 1);
2574 mcqcap = FIELD_DP32(mcqcap, MCQCAP, QCFGPTR, UFS_MCQ_QCFGPTR);
2575 u->reg.mcqcap = mcqcap;
2576
2577 for (int i = 0; i < ARRAY_SIZE(u->mcq_reg); i++) {
2578 uint64_t addr = ufs_mcq_op_reg_addr(u, i);
2579 u->mcq_reg[i].sqdao = addr;
2580 u->mcq_reg[i].sqisao = addr + sizeof(UfsMcqSqReg);
2581 addr += sizeof(UfsMcqSqReg);
2582 u->mcq_reg[i].cqdao = addr + sizeof(UfsMcqSqIntReg);
2583 addr += sizeof(UfsMcqSqIntReg);
2584 u->mcq_reg[i].cqisao = addr + sizeof(UfsMcqCqReg);
2585 }
2586 }
2587 u->reg.ver = UFS_SPEC_VER;
2588
2589 memset(&u->device_desc, 0, sizeof(DeviceDescriptor));
2590 u->device_desc.length = sizeof(DeviceDescriptor);
2591 u->device_desc.descriptor_idn = UFS_QUERY_DESC_IDN_DEVICE;
2592 u->device_desc.device_sub_class = 0x01;
2593 u->device_desc.number_lu = 0x00;
2594 u->device_desc.number_wlu = 0x04;
2595 /* TODO: Revisit it when Power Management is implemented */
2596 u->device_desc.init_power_mode = 0x01; /* Active Mode */
2597 u->device_desc.high_priority_lun = 0x7F; /* Same Priority */
2598 u->device_desc.spec_version = cpu_to_be16(UFS_SPEC_VER);
2599 u->device_desc.manufacturer_name = 0x00;
2600 u->device_desc.product_name = 0x01;
2601 u->device_desc.serial_number = 0x02;
2602 u->device_desc.oem_id = 0x03;
2603 u->device_desc.ud_0_base_offset = 0x16;
2604 u->device_desc.ud_config_p_length = 0x1A;
2605 u->device_desc.device_rtt_cap = 0x02;
2606 u->device_desc.ufs_features_support = UFS_DEV_HIGH_TEMP_NOTIF |
2607 UFS_DEV_LOW_TEMP_NOTIF;
2608 u->device_desc.queue_depth = u->params.nutrs;
2609 u->device_desc.product_revision_level = 0x04;
2610 u->device_desc.extended_wb_support |= cpu_to_be16(ext_wb_sup);
2611 u->device_desc.extended_ufs_features_support =
2612 cpu_to_be32((ext_ufs_feat_sup));
2613 u->device_desc.write_booster_buffer_preserve_user_space_en = 0x01;
2614 u->device_desc.write_booster_buffer_type = 0x01;
2615 u->device_desc.num_shared_write_booster_buffer_alloc_units =
2616 cpu_to_be32(u->params.wb_max_size);
2617
2618 memset(&u->geometry_desc, 0, sizeof(GeometryDescriptor));
2619 u->geometry_desc.length = sizeof(GeometryDescriptor);
2620 u->geometry_desc.descriptor_idn = UFS_QUERY_DESC_IDN_GEOMETRY;
2621 u->geometry_desc.max_number_lu = (UFS_MAX_LUS == 32) ? 0x1 : 0x0;
2622 u->geometry_desc.segment_size = cpu_to_be32(0x2000); /* 4MB: 8192 * 512B */
2623 u->geometry_desc.allocation_unit_size = 0x1; /* 4MB: 1 segment */
2624 u->geometry_desc.min_addr_block_size = 0x8; /* 4KB */
2625 u->geometry_desc.max_in_buffer_size = 0x8;
2626 u->geometry_desc.max_out_buffer_size = 0x8;
2627 u->geometry_desc.rpmb_read_write_size = 0x40;
2628 u->geometry_desc.data_ordering =
2629 0x0; /* out-of-order data transfer is not supported */
2630 u->geometry_desc.max_context_id_number = 0x5;
2631 u->geometry_desc.supported_memory_types = cpu_to_be16(0x8001);
2632 u->geometry_desc.write_booster_buffer_max_n_alloc_units =
2633 cpu_to_be32(u->params.wb_max_size);
2634 u->geometry_desc.device_max_write_booster_l_us = 0x1;
2635 u->geometry_desc.write_booster_buffer_cap_adj_fac = 0x3;
2636 u->geometry_desc.supported_write_booster_buffer_user_space_reduction_types =
2637 0x1;
2638 u->geometry_desc.supported_write_booster_buffer_types =
2639 0x1; /* lu-dedicated buffer type is not supported */
2640
2641 memset(&u->attributes, 0, sizeof(u->attributes));
2642 u->attributes.max_data_in_size = 0x08;
2643 u->attributes.max_data_out_size = 0x08;
2644 u->attributes.ref_clk_freq = 0x01; /* 26 MHz */
2645 /* configure descriptor is not supported */
2646 u->attributes.config_descr_lock = 0x01;
2647 u->attributes.max_num_of_rtt = 0x02;
2648 u->attributes.device_too_high_temp_boundary = UFS_TOO_HIGH_TEMP_BOUNDARY;
2649 u->attributes.device_too_low_temp_boundary = UFS_TOO_LOW_TEMP_BOUNDARY;
2650 u->attributes.hid_avail_size = cpu_to_be32(0xFFFFFFFF);
2651 u->attributes.hid_size = cpu_to_be32(0xFFFFFFFF);
2652
2653 memset(&u->flags, 0, sizeof(u->flags));
2654 u->flags.permanently_disable_fw_update = 1;
2655
2656 ufs_wb_init(u);
2657
2658 /*
2659 * The temperature value is fixed to UFS_TEMPERATURE and does not change
2660 * dynamically
2661 */
2662 u->temperature = UFS_TEMPERATURE;
2663
2664 timer_init_ms(&u->idle_timer, QEMU_CLOCK_VIRTUAL_RT, ufs_idle_timer_cb, u);
2665 timer_mod(&u->idle_timer, now + UFS_IDLE_TIMER_TICK);
2666 }
2667
2668 bool ufs_realize(UfsHc *u, DeviceState *dev, AddressSpace *dma_as, Error **errp)
2669 {
2670 u->dev = dev;
2671 u->dma_as = dma_as;
2672
2673 if (!ufs_check_constraints(u, errp)) {
2674 return false;
2675 }
2676
2677 qbus_init(&u->bus, sizeof(UfsBus), TYPE_UFS_BUS, dev, dev->id);
2678 u->bus.hc = u;
2679
2680 ufs_init_state(u);
2681 ufs_init_hc(u);
2682 memory_region_init_io(&u->iomem, OBJECT(dev), &ufs_mmio_ops, u, "ufs",
2683 u->reg_size);
2684
2685 ufs_init_wlu(&u->report_wlu, UFS_UPIU_REPORT_LUNS_WLUN);
2686 ufs_init_wlu(&u->dev_wlu, UFS_UPIU_UFS_DEVICE_WLUN);
2687 ufs_init_wlu(&u->boot_wlu, UFS_UPIU_BOOT_WLUN);
2688 ufs_init_wlu(&u->rpmb_wlu, UFS_UPIU_RPMB_WLUN);
2689
2690 return true;
2691 }
2692
2693 void ufs_unrealize(UfsHc *u)
2694 {
2695 timer_del(&u->idle_timer);
2696
2697 qemu_bh_delete(u->doorbell_bh);
2698 qemu_bh_delete(u->complete_bh);
2699
2700 for (int i = 0; i < u->params.nutrs; i++) {
2701 ufs_clear_req(&u->req_list[i]);
2702 }
2703 g_free(u->req_list);
2704
2705 for (int i = 0; i < ARRAY_SIZE(u->sq); i++) {
2706 if (u->sq[i]) {
2707 ufs_mcq_free_sq(u->sq[i]);
2708 u->sq[i] = NULL;
2709 }
2710 }
2711 for (int i = 0; i < ARRAY_SIZE(u->cq); i++) {
2712 if (u->cq[i]) {
2713 ufs_mcq_free_cq(u->cq[i]);
2714 u->cq[i] = NULL;
2715 }
2716 }
2717 }
2718
2719 static bool ufs_bus_check_address(BusState *qbus, DeviceState *qdev,
2720 Error **errp)
2721 {
2722 if (strcmp(object_get_typename(OBJECT(qdev)), TYPE_UFS_LU) != 0) {
2723 error_setg(errp, "%s cannot be connected to ufs-bus",
2724 object_get_typename(OBJECT(qdev)));
2725 return false;
2726 }
2727
2728 return true;
2729 }
2730
2731 static char *ufs_bus_get_dev_path(DeviceState *dev)
2732 {
2733 BusState *bus = qdev_get_parent_bus(dev);
2734
2735 return qdev_get_dev_path(bus->parent);
2736 }
2737
2738 static void ufs_bus_class_init(ObjectClass *class, const void *data)
2739 {
2740 BusClass *bc = BUS_CLASS(class);
2741 bc->get_dev_path = ufs_bus_get_dev_path;
2742 bc->check_address = ufs_bus_check_address;
2743 }
2744
2745 static const TypeInfo ufs_bus_info = {
2746 .name = TYPE_UFS_BUS,
2747 .parent = TYPE_BUS,
2748 .class_init = ufs_bus_class_init,
2749 .class_size = sizeof(UfsBusClass),
2750 .instance_size = sizeof(UfsBus),
2751 };
2752
2753 static void ufs_register_types(void)
2754 {
2755 type_register_static(&ufs_bus_info);
2756 }
2757
2758 type_init(ufs_register_types)