| 1 | /* |
| 2 | * QEMU USB EHCI Emulation |
| 3 | * |
| 4 | * This library is free software; you can redistribute it and/or |
| 5 | * modify it under the terms of the GNU Lesser General Public |
| 6 | * License as published by the Free Software Foundation; either |
| 7 | * version 2.1 of the License, or (at your option) any later version. |
| 8 | * |
| 9 | * This library is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 12 | * Lesser General Public License for more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU Lesser General Public License |
| 15 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
| 16 | */ |
| 17 | |
| 18 | #ifndef HW_USB_HCD_EHCI_H |
| 19 | #define HW_USB_HCD_EHCI_H |
| 20 | |
| 21 | #include "qemu/timer.h" |
| 22 | #include "hw/usb/usb.h" |
| 23 | #include "system/dma.h" |
| 24 | #include "hw/pci/pci_device.h" |
| 25 | #include "hw/core/sysbus.h" |
| 26 | |
| 27 | #define MMIO_SIZE 0x1000 |
| 28 | #define CAPA_SIZE 0x10 |
| 29 | |
| 30 | #define EHCI_PORTS 6 /* Max. Number of downstream ports */ |
| 31 | |
| 32 | typedef struct EHCIPacket EHCIPacket; |
| 33 | typedef struct EHCIQueue EHCIQueue; |
| 34 | typedef struct EHCIState EHCIState; |
| 35 | |
| 36 | /* |
| 37 | * EHCI spec version 1.0 Section 3.3 |
| 38 | */ |
| 39 | typedef struct EHCIitd { |
| 40 | uint32_t next; |
| 41 | |
| 42 | uint32_t transact[8]; |
| 43 | #define ITD_XACT_ACTIVE (1 << 31) |
| 44 | #define ITD_XACT_DBERROR (1 << 30) |
| 45 | #define ITD_XACT_BABBLE (1 << 29) |
| 46 | #define ITD_XACT_XACTERR (1 << 28) |
| 47 | #define ITD_XACT_LENGTH_MASK 0x0fff0000 |
| 48 | #define ITD_XACT_LENGTH_SH 16 |
| 49 | #define ITD_XACT_IOC (1 << 15) |
| 50 | #define ITD_XACT_PGSEL_MASK 0x00007000 |
| 51 | #define ITD_XACT_PGSEL_SH 12 |
| 52 | #define ITD_XACT_OFFSET_MASK 0x00000fff |
| 53 | |
| 54 | uint32_t bufptr[7]; |
| 55 | #define ITD_BUFPTR_MASK 0xfffff000 |
| 56 | #define ITD_BUFPTR_SH 12 |
| 57 | #define ITD_BUFPTR_EP_MASK 0x00000f00 |
| 58 | #define ITD_BUFPTR_EP_SH 8 |
| 59 | #define ITD_BUFPTR_DEVADDR_MASK 0x0000007f |
| 60 | #define ITD_BUFPTR_DEVADDR_SH 0 |
| 61 | #define ITD_BUFPTR_DIRECTION (1 << 11) |
| 62 | #define ITD_BUFPTR_MAXPKT_MASK 0x000007ff |
| 63 | #define ITD_BUFPTR_MAXPKT_SH 0 |
| 64 | #define ITD_BUFPTR_MULT_MASK 0x00000003 |
| 65 | #define ITD_BUFPTR_MULT_SH 0 |
| 66 | uint32_t bufptr_hi[7]; |
| 67 | } EHCIitd; |
| 68 | |
| 69 | /* |
| 70 | * EHCI spec version 1.0 Section 3.4 |
| 71 | */ |
| 72 | typedef struct EHCIsitd { |
| 73 | uint32_t next; /* Standard next link pointer */ |
| 74 | uint32_t epchar; |
| 75 | #define SITD_EPCHAR_IO (1 << 31) |
| 76 | #define SITD_EPCHAR_PORTNUM_MASK 0x7f000000 |
| 77 | #define SITD_EPCHAR_PORTNUM_SH 24 |
| 78 | #define SITD_EPCHAR_HUBADD_MASK 0x007f0000 |
| 79 | #define SITD_EPCHAR_HUBADDR_SH 16 |
| 80 | #define SITD_EPCHAR_EPNUM_MASK 0x00000f00 |
| 81 | #define SITD_EPCHAR_EPNUM_SH 8 |
| 82 | #define SITD_EPCHAR_DEVADDR_MASK 0x0000007f |
| 83 | |
| 84 | uint32_t uframe; |
| 85 | #define SITD_UFRAME_CMASK_MASK 0x0000ff00 |
| 86 | #define SITD_UFRAME_CMASK_SH 8 |
| 87 | #define SITD_UFRAME_SMASK_MASK 0x000000ff |
| 88 | |
| 89 | uint32_t results; |
| 90 | #define SITD_RESULTS_IOC (1 << 31) |
| 91 | #define SITD_RESULTS_PGSEL (1 << 30) |
| 92 | #define SITD_RESULTS_TBYTES_MASK 0x03ff0000 |
| 93 | #define SITD_RESULTS_TYBYTES_SH 16 |
| 94 | #define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00 |
| 95 | #define SITD_RESULTS_CPROGMASK_SH 8 |
| 96 | #define SITD_RESULTS_ACTIVE (1 << 7) |
| 97 | #define SITD_RESULTS_ERR (1 << 6) |
| 98 | #define SITD_RESULTS_DBERR (1 << 5) |
| 99 | #define SITD_RESULTS_BABBLE (1 << 4) |
| 100 | #define SITD_RESULTS_XACTERR (1 << 3) |
| 101 | #define SITD_RESULTS_MISSEDUF (1 << 2) |
| 102 | #define SITD_RESULTS_SPLITXSTATE (1 << 1) |
| 103 | |
| 104 | uint32_t bufptr[2]; |
| 105 | #define SITD_BUFPTR_MASK 0xfffff000 |
| 106 | #define SITD_BUFPTR_CURROFF_MASK 0x00000fff |
| 107 | #define SITD_BUFPTR_TPOS_MASK 0x00000018 |
| 108 | #define SITD_BUFPTR_TPOS_SH 3 |
| 109 | #define SITD_BUFPTR_TCNT_MASK 0x00000007 |
| 110 | |
| 111 | uint32_t backptr; /* Standard next link pointer */ |
| 112 | } EHCIsitd; |
| 113 | |
| 114 | /* |
| 115 | * EHCI spec version 1.0 Section 3.5 |
| 116 | */ |
| 117 | typedef struct EHCIqtd { |
| 118 | uint32_t next; /* Standard next link pointer */ |
| 119 | uint32_t altnext; /* Standard next link pointer */ |
| 120 | uint32_t token; |
| 121 | #define QTD_TOKEN_DTOGGLE (1 << 31) |
| 122 | #define QTD_TOKEN_TBYTES_MASK 0x7fff0000 |
| 123 | #define QTD_TOKEN_TBYTES_SH 16 |
| 124 | #define QTD_TOKEN_IOC (1 << 15) |
| 125 | #define QTD_TOKEN_CPAGE_MASK 0x00007000 |
| 126 | #define QTD_TOKEN_CPAGE_SH 12 |
| 127 | #define QTD_TOKEN_CERR_MASK 0x00000c00 |
| 128 | #define QTD_TOKEN_CERR_SH 10 |
| 129 | #define QTD_TOKEN_PID_MASK 0x00000300 |
| 130 | #define QTD_TOKEN_PID_SH 8 |
| 131 | #define QTD_TOKEN_ACTIVE (1 << 7) |
| 132 | #define QTD_TOKEN_HALT (1 << 6) |
| 133 | #define QTD_TOKEN_DBERR (1 << 5) |
| 134 | #define QTD_TOKEN_BABBLE (1 << 4) |
| 135 | #define QTD_TOKEN_XACTERR (1 << 3) |
| 136 | #define QTD_TOKEN_MISSEDUF (1 << 2) |
| 137 | #define QTD_TOKEN_SPLITXSTATE (1 << 1) |
| 138 | #define QTD_TOKEN_PING (1 << 0) |
| 139 | |
| 140 | uint32_t bufptr[5]; /* Standard buffer pointer */ |
| 141 | #define QTD_BUFPTR_MASK 0xfffff000 |
| 142 | #define QTD_BUFPTR_SH 12 |
| 143 | uint32_t bufptr_hi[5]; |
| 144 | } EHCIqtd; |
| 145 | |
| 146 | /* QH overlay: altnext_qtd, token, bufptr[5], bufptr_hi[5] */ |
| 147 | #define EHCI_QH_OVERLAY_COUNT 12 |
| 148 | |
| 149 | /* |
| 150 | * EHCI spec version 1.0 Section 3.6 |
| 151 | */ |
| 152 | typedef struct EHCIqh { |
| 153 | uint32_t next; /* Standard next link pointer */ |
| 154 | |
| 155 | /* endpoint characteristics */ |
| 156 | uint32_t epchar; |
| 157 | #define QH_EPCHAR_RL_MASK 0xf0000000 |
| 158 | #define QH_EPCHAR_RL_SH 28 |
| 159 | #define QH_EPCHAR_C (1 << 27) |
| 160 | #define QH_EPCHAR_MPLEN_MASK 0x07FF0000 |
| 161 | #define QH_EPCHAR_MPLEN_SH 16 |
| 162 | #define QH_EPCHAR_H (1 << 15) |
| 163 | #define QH_EPCHAR_DTC (1 << 14) |
| 164 | #define QH_EPCHAR_EPS_MASK 0x00003000 |
| 165 | #define QH_EPCHAR_EPS_SH 12 |
| 166 | #define EHCI_QH_EPS_FULL 0 |
| 167 | #define EHCI_QH_EPS_LOW 1 |
| 168 | #define EHCI_QH_EPS_HIGH 2 |
| 169 | #define EHCI_QH_EPS_RESERVED 3 |
| 170 | |
| 171 | #define QH_EPCHAR_EP_MASK 0x00000f00 |
| 172 | #define QH_EPCHAR_EP_SH 8 |
| 173 | #define QH_EPCHAR_I (1 << 7) |
| 174 | #define QH_EPCHAR_DEVADDR_MASK 0x0000007f |
| 175 | #define QH_EPCHAR_DEVADDR_SH 0 |
| 176 | |
| 177 | /* endpoint capabilities */ |
| 178 | uint32_t epcap; |
| 179 | #define QH_EPCAP_MULT_MASK 0xc0000000 |
| 180 | #define QH_EPCAP_MULT_SH 30 |
| 181 | #define QH_EPCAP_PORTNUM_MASK 0x3f800000 |
| 182 | #define QH_EPCAP_PORTNUM_SH 23 |
| 183 | #define QH_EPCAP_HUBADDR_MASK 0x007f0000 |
| 184 | #define QH_EPCAP_HUBADDR_SH 16 |
| 185 | #define QH_EPCAP_CMASK_MASK 0x0000ff00 |
| 186 | #define QH_EPCAP_CMASK_SH 8 |
| 187 | #define QH_EPCAP_SMASK_MASK 0x000000ff |
| 188 | #define QH_EPCAP_SMASK_SH 0 |
| 189 | |
| 190 | uint32_t current_qtd; /* Standard next link pointer */ |
| 191 | uint32_t next_qtd; /* Standard next link pointer */ |
| 192 | uint32_t altnext_qtd; |
| 193 | #define QH_ALTNEXT_NAKCNT_MASK 0x0000001e |
| 194 | #define QH_ALTNEXT_NAKCNT_SH 1 |
| 195 | |
| 196 | uint32_t token; /* Same as QTD token */ |
| 197 | uint32_t bufptr[5]; /* Standard buffer pointer */ |
| 198 | #define BUFPTR_CPROGMASK_MASK 0x000000ff |
| 199 | #define BUFPTR_FRAMETAG_MASK 0x0000001f |
| 200 | #define BUFPTR_SBYTES_MASK 0x00000fe0 |
| 201 | #define BUFPTR_SBYTES_SH 5 |
| 202 | uint32_t bufptr_hi[5]; |
| 203 | } EHCIqh; |
| 204 | |
| 205 | enum async_state { |
| 206 | EHCI_ASYNC_NONE = 0, |
| 207 | EHCI_ASYNC_INITIALIZED, |
| 208 | EHCI_ASYNC_INFLIGHT, |
| 209 | EHCI_ASYNC_FINISHED, |
| 210 | }; |
| 211 | |
| 212 | struct EHCIPacket { |
| 213 | EHCIQueue *queue; |
| 214 | QTAILQ_ENTRY(EHCIPacket) next; |
| 215 | |
| 216 | EHCIqtd qtd; /* copy of current QTD (being worked on) */ |
| 217 | uint64_t qtdaddr; /* address QTD read from */ |
| 218 | |
| 219 | USBPacket packet; |
| 220 | QEMUSGList sgl; |
| 221 | int pid; |
| 222 | enum async_state async; |
| 223 | }; |
| 224 | |
| 225 | struct EHCIQueue { |
| 226 | EHCIState *ehci; |
| 227 | QTAILQ_ENTRY(EHCIQueue) next; |
| 228 | uint32_t seen; |
| 229 | uint64_t ts; |
| 230 | int async; |
| 231 | int transact_ctr; |
| 232 | |
| 233 | /* |
| 234 | * cached data from guest - needs to be flushed |
| 235 | * when guest removes an entry (doorbell, handshake sequence) |
| 236 | */ |
| 237 | EHCIqh qh; /* copy of current QH (being worked on) */ |
| 238 | uint64_t qhaddr; /* address QH read from */ |
| 239 | uint64_t qtdaddr; /* address QTD read from */ |
| 240 | int last_pid; /* pid of last packet executed */ |
| 241 | USBDevice *dev; |
| 242 | QTAILQ_HEAD(, EHCIPacket) packets; |
| 243 | }; |
| 244 | |
| 245 | typedef QTAILQ_HEAD(EHCIQueueHead, EHCIQueue) EHCIQueueHead; |
| 246 | |
| 247 | struct EHCIState { |
| 248 | USBBus bus; |
| 249 | DeviceState *device; |
| 250 | qemu_irq irq; |
| 251 | MemoryRegion mem; |
| 252 | AddressSpace *as; |
| 253 | MemoryRegion mem_caps; |
| 254 | MemoryRegion mem_opreg; |
| 255 | MemoryRegion mem_ports; |
| 256 | int companion_count; |
| 257 | bool companion_enable; |
| 258 | uint16_t capsbase; |
| 259 | uint16_t opregbase; |
| 260 | uint16_t portscbase; |
| 261 | uint16_t portnr; |
| 262 | |
| 263 | /* properties */ |
| 264 | uint32_t maxframes; |
| 265 | /* |
| 266 | * Controls migration stream compatibility for old machine types. |
| 267 | * Old machine types only transfer 32-bit fetch addresses. |
| 268 | */ |
| 269 | bool migrate_fetch_addr_64bit; |
| 270 | bool caps_64bit_addr; |
| 271 | uint32_t ctrldssegment_default; |
| 272 | |
| 273 | /* |
| 274 | * EHCI spec version 1.0 Section 2.3 |
| 275 | * Host Controller Operational Registers |
| 276 | */ |
| 277 | uint8_t caps[CAPA_SIZE]; |
| 278 | union { |
| 279 | uint32_t opreg[0x44 / sizeof(uint32_t)]; |
| 280 | struct { |
| 281 | uint32_t usbcmd; |
| 282 | uint32_t usbsts; |
| 283 | uint32_t usbintr; |
| 284 | uint32_t frindex; |
| 285 | uint32_t ctrldssegment; |
| 286 | uint32_t periodiclistbase; |
| 287 | uint32_t asynclistaddr; |
| 288 | uint32_t notused[9]; |
| 289 | uint32_t configflag; |
| 290 | }; |
| 291 | }; |
| 292 | uint32_t portsc[EHCI_PORTS]; |
| 293 | |
| 294 | /* |
| 295 | * Internal states, shadow registers, etc |
| 296 | */ |
| 297 | QEMUTimer *frame_timer; |
| 298 | QEMUBH *async_bh; |
| 299 | bool working; |
| 300 | uint32_t astate; /* Current state in asynchronous schedule */ |
| 301 | uint32_t pstate; /* Current state in periodic schedule */ |
| 302 | USBPort ports[EHCI_PORTS]; |
| 303 | USBPort *companion_ports[EHCI_PORTS]; |
| 304 | uint32_t usbsts_pending; |
| 305 | uint32_t usbsts_frindex; |
| 306 | EHCIQueueHead aqueues; |
| 307 | EHCIQueueHead pqueues; |
| 308 | |
| 309 | /* |
| 310 | * which address to look at next |
| 311 | * |
| 312 | * Migration compatibility fields for old machine types that only |
| 313 | * support 32-bit fetch addresses in the migration stream. |
| 314 | * |
| 315 | * New machine types migrate the full 64-bit runtime fetch address. |
| 316 | */ |
| 317 | uint32_t migrate_a_fetch_addr; |
| 318 | uint32_t migrate_p_fetch_addr; |
| 319 | uint64_t a_fetch_addr; |
| 320 | uint64_t p_fetch_addr; |
| 321 | |
| 322 | USBPacket ipacket; |
| 323 | QEMUSGList isgl; |
| 324 | |
| 325 | uint64_t last_run_ns; |
| 326 | uint32_t async_stepdown; |
| 327 | uint32_t periodic_sched_active; |
| 328 | bool int_req_by_async; |
| 329 | VMChangeStateEntry *vmstate; |
| 330 | }; |
| 331 | |
| 332 | #define DEFINE_EHCI_COMMON_PROPERTIES(_state) \ |
| 333 | DEFINE_PROP_UINT32("maxframes", _state, ehci.maxframes, 128), \ |
| 334 | DEFINE_PROP_BOOL("x-migrate-fetch-addr-64bit", _state, \ |
| 335 | ehci.migrate_fetch_addr_64bit, true), \ |
| 336 | DEFINE_PROP_BOOL("caps-64bit-addr", _state, \ |
| 337 | ehci.caps_64bit_addr, false), \ |
| 338 | DEFINE_PROP_UINT32("ctrldssegment-default", _state, \ |
| 339 | ehci.ctrldssegment_default, 0) |
| 340 | |
| 341 | extern const VMStateDescription vmstate_ehci; |
| 342 | |
| 343 | void usb_ehci_init(EHCIState *s, DeviceState *dev); |
| 344 | void usb_ehci_finalize(EHCIState *s); |
| 345 | void usb_ehci_realize(EHCIState *s, DeviceState *dev, Error **errp); |
| 346 | void usb_ehci_unrealize(EHCIState *s, DeviceState *dev); |
| 347 | void ehci_reset(void *opaque); |
| 348 | |
| 349 | #define TYPE_PCI_EHCI "pci-ehci-usb" |
| 350 | OBJECT_DECLARE_SIMPLE_TYPE(EHCIPCIState, PCI_EHCI) |
| 351 | |
| 352 | struct EHCIPCIState { |
| 353 | /*< private >*/ |
| 354 | PCIDevice pcidev; |
| 355 | /*< public >*/ |
| 356 | |
| 357 | EHCIState ehci; |
| 358 | }; |
| 359 | |
| 360 | |
| 361 | #define TYPE_SYS_BUS_EHCI "sysbus-ehci-usb" |
| 362 | #define TYPE_PLATFORM_EHCI "platform-ehci-usb" |
| 363 | #define TYPE_EXYNOS4210_EHCI "exynos4210-ehci-usb" |
| 364 | #define TYPE_AW_H3_EHCI "aw-h3-ehci-usb" |
| 365 | #define TYPE_NPCM7XX_EHCI "npcm7xx-ehci-usb" |
| 366 | #define TYPE_TEGRA2_EHCI "tegra2-ehci-usb" |
| 367 | #define TYPE_PPC4xx_EHCI "ppc4xx-ehci-usb" |
| 368 | #define TYPE_FUSBH200_EHCI "fusbh200-ehci-usb" |
| 369 | |
| 370 | OBJECT_DECLARE_TYPE(EHCISysBusState, SysBusEHCIClass, SYS_BUS_EHCI) |
| 371 | |
| 372 | struct EHCISysBusState { |
| 373 | /*< private >*/ |
| 374 | SysBusDevice parent_obj; |
| 375 | /*< public >*/ |
| 376 | |
| 377 | EHCIState ehci; |
| 378 | }; |
| 379 | |
| 380 | struct SysBusEHCIClass { |
| 381 | /*< private >*/ |
| 382 | SysBusDeviceClass parent_class; |
| 383 | /*< public >*/ |
| 384 | |
| 385 | uint16_t capsbase; |
| 386 | uint16_t opregbase; |
| 387 | uint16_t portscbase; |
| 388 | uint16_t portnr; |
| 389 | }; |
| 390 | |
| 391 | OBJECT_DECLARE_SIMPLE_TYPE(FUSBH200EHCIState, FUSBH200_EHCI) |
| 392 | |
| 393 | struct FUSBH200EHCIState { |
| 394 | /*< private >*/ |
| 395 | EHCISysBusState parent_obj; |
| 396 | /*< public >*/ |
| 397 | |
| 398 | MemoryRegion mem_vendor; |
| 399 | }; |
| 400 | |
| 401 | #endif |