| 1 | /* |
| 2 | * QEMU USB OHCI Emulation |
| 3 | * Copyright (c) 2006 Openedhand Ltd. |
| 4 | * Copyright (c) 2010 CodeSourcery |
| 5 | * Copyright (c) 2024 Red Hat, Inc. |
| 6 | * |
| 7 | * This library is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU Lesser General Public |
| 9 | * License as published by the Free Software Foundation; either |
| 10 | * version 2.1 of the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This library is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 15 | * Lesser General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU Lesser General Public |
| 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 19 | */ |
| 20 | |
| 21 | #include "qemu/osdep.h" |
| 22 | #include "hw/core/irq.h" |
| 23 | #include "qapi/error.h" |
| 24 | #include "qemu/module.h" |
| 25 | #include "qemu/timer.h" |
| 26 | #include "hw/usb/usb.h" |
| 27 | #include "migration/vmstate.h" |
| 28 | #include "hw/core/sysbus.h" |
| 29 | #include "hw/core/qdev-properties.h" |
| 30 | #include "trace.h" |
| 31 | #include "hcd-ohci.h" |
| 32 | |
| 33 | |
| 34 | static void ohci_sysbus_realize(DeviceState *dev, Error **errp) |
| 35 | { |
| 36 | OHCISysBusState *s = SYSBUS_OHCI(dev); |
| 37 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
| 38 | Error *err = NULL; |
| 39 | |
| 40 | usb_ohci_init(&s->ohci, dev, s->num_ports, s->dma_offset, |
| 41 | s->masterbus, s->firstport, |
| 42 | &address_space_memory, ohci_sysbus_die, &err); |
| 43 | if (err) { |
| 44 | error_propagate(errp, err); |
| 45 | return; |
| 46 | } |
| 47 | sysbus_init_irq(sbd, &s->ohci.irq); |
| 48 | sysbus_init_mmio(sbd, &s->ohci.mem); |
| 49 | } |
| 50 | |
| 51 | static void ohci_sysbus_reset(DeviceState *dev) |
| 52 | { |
| 53 | OHCISysBusState *s = SYSBUS_OHCI(dev); |
| 54 | OHCIState *ohci = &s->ohci; |
| 55 | |
| 56 | ohci_hard_reset(ohci); |
| 57 | } |
| 58 | |
| 59 | static const Property ohci_sysbus_properties[] = { |
| 60 | DEFINE_PROP_STRING("masterbus", OHCISysBusState, masterbus), |
| 61 | DEFINE_PROP_UINT32("num-ports", OHCISysBusState, num_ports, 3), |
| 62 | DEFINE_PROP_UINT32("firstport", OHCISysBusState, firstport, 0), |
| 63 | DEFINE_PROP_UINT64("dma-offset", OHCISysBusState, dma_offset, 0), |
| 64 | }; |
| 65 | |
| 66 | static void ohci_sysbus_class_init(ObjectClass *klass, const void *data) |
| 67 | { |
| 68 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 69 | |
| 70 | dc->realize = ohci_sysbus_realize; |
| 71 | set_bit(DEVICE_CATEGORY_USB, dc->categories); |
| 72 | dc->desc = "OHCI USB Controller"; |
| 73 | device_class_set_props(dc, ohci_sysbus_properties); |
| 74 | device_class_set_legacy_reset(dc, ohci_sysbus_reset); |
| 75 | } |
| 76 | |
| 77 | static const TypeInfo ohci_sysbus_types[] = { |
| 78 | { |
| 79 | .name = TYPE_SYSBUS_OHCI, |
| 80 | .parent = TYPE_SYS_BUS_DEVICE, |
| 81 | .instance_size = sizeof(OHCISysBusState), |
| 82 | .class_init = ohci_sysbus_class_init, |
| 83 | }, |
| 84 | }; |
| 85 | |
| 86 | DEFINE_TYPES(ohci_sysbus_types); |