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1 /*
2 * USB xHCI controller emulation
3 *
4 * Copyright (c) 2011 Securiforest
5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com>
6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2.1 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #include "qemu/osdep.h"
23 #include "qemu/timer.h"
24 #include "qemu/log.h"
25 #include "qemu/module.h"
26 #include "qemu/queue.h"
27 #include "migration/vmstate.h"
28 #include "hw/core/qdev-properties.h"
29 #include "trace.h"
30 #include "qapi/error.h"
31
32 #include "hcd-xhci.h"
33
34 //#define DEBUG_XHCI
35 //#define DEBUG_DATA
36
37 #ifdef DEBUG_XHCI
38 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__)
39 #else
40 #define DPRINTF(...) do {} while (0)
41 #endif
42
43 #define TRB_LINK_LIMIT 32
44 #define COMMAND_LIMIT 256
45 #define TRANSFER_LIMIT 256
46
47 #define LEN_CAP 0x40
48 #define LEN_OPER (0x400 + 0x10 * XHCI_MAXPORTS)
49 #define LEN_RUNTIME ((XHCI_MAXINTRS + 1) * 0x20)
50 #define LEN_DOORBELL ((XHCI_MAXSLOTS + 1) * 0x20)
51
52 #define OFF_OPER LEN_CAP
53 #define OFF_RUNTIME 0x1000
54 #define OFF_DOORBELL 0x2000
55
56 #if (OFF_OPER + LEN_OPER) > OFF_RUNTIME
57 #error Increase OFF_RUNTIME
58 #endif
59 #if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL
60 #error Increase OFF_DOORBELL
61 #endif
62 #if (OFF_DOORBELL + LEN_DOORBELL) > XHCI_LEN_REGS
63 # error Increase XHCI_LEN_REGS
64 #endif
65
66 /* bit definitions */
67 #define USBCMD_RS (1<<0)
68 #define USBCMD_HCRST (1<<1)
69 #define USBCMD_INTE (1<<2)
70 #define USBCMD_HSEE (1<<3)
71 #define USBCMD_LHCRST (1<<7)
72 #define USBCMD_CSS (1<<8)
73 #define USBCMD_CRS (1<<9)
74 #define USBCMD_EWE (1<<10)
75 #define USBCMD_EU3S (1<<11)
76
77 #define USBSTS_HCH (1<<0)
78 #define USBSTS_HSE (1<<2)
79 #define USBSTS_EINT (1<<3)
80 #define USBSTS_PCD (1<<4)
81 #define USBSTS_SSS (1<<8)
82 #define USBSTS_RSS (1<<9)
83 #define USBSTS_SRE (1<<10)
84 #define USBSTS_CNR (1<<11)
85 #define USBSTS_HCE (1<<12)
86
87
88 #define PORTSC_CCS (1<<0)
89 #define PORTSC_PED (1<<1)
90 #define PORTSC_OCA (1<<3)
91 #define PORTSC_PR (1<<4)
92 #define PORTSC_PLS_SHIFT 5
93 #define PORTSC_PLS_MASK 0xf
94 #define PORTSC_PP (1<<9)
95 #define PORTSC_SPEED_SHIFT 10
96 #define PORTSC_SPEED_MASK 0xf
97 #define PORTSC_SPEED_FULL (1<<10)
98 #define PORTSC_SPEED_LOW (2<<10)
99 #define PORTSC_SPEED_HIGH (3<<10)
100 #define PORTSC_SPEED_SUPER (4<<10)
101 #define PORTSC_PIC_SHIFT 14
102 #define PORTSC_PIC_MASK 0x3
103 #define PORTSC_LWS (1<<16)
104 #define PORTSC_CSC (1<<17)
105 #define PORTSC_PEC (1<<18)
106 #define PORTSC_WRC (1<<19)
107 #define PORTSC_OCC (1<<20)
108 #define PORTSC_PRC (1<<21)
109 #define PORTSC_PLC (1<<22)
110 #define PORTSC_CEC (1<<23)
111 #define PORTSC_CAS (1<<24)
112 #define PORTSC_WCE (1<<25)
113 #define PORTSC_WDE (1<<26)
114 #define PORTSC_WOE (1<<27)
115 #define PORTSC_DR (1<<30)
116 #define PORTSC_WPR (1<<31)
117
118 #define CRCR_RCS (1<<0)
119 #define CRCR_CS (1<<1)
120 #define CRCR_CA (1<<2)
121 #define CRCR_CRR (1<<3)
122
123 #define IMAN_IP (1<<0)
124 #define IMAN_IE (1<<1)
125
126 #define ERDP_EHB (1<<3)
127
128 #define TRB_SIZE 16
129 typedef struct XHCITRB {
130 uint64_t parameter;
131 uint32_t status;
132 uint32_t control;
133 dma_addr_t addr;
134 bool ccs;
135 } XHCITRB;
136
137 enum {
138 PLS_U0 = 0,
139 PLS_U1 = 1,
140 PLS_U2 = 2,
141 PLS_U3 = 3,
142 PLS_DISABLED = 4,
143 PLS_RX_DETECT = 5,
144 PLS_INACTIVE = 6,
145 PLS_POLLING = 7,
146 PLS_RECOVERY = 8,
147 PLS_HOT_RESET = 9,
148 PLS_COMPILANCE_MODE = 10,
149 PLS_TEST_MODE = 11,
150 PLS_RESUME = 15,
151 };
152
153 #define CR_LINK TR_LINK
154
155 #define TRB_C (1<<0)
156 #define TRB_TYPE_SHIFT 10
157 #define TRB_TYPE_MASK 0x3f
158 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK)
159
160 #define TRB_EV_ED (1<<2)
161
162 #define TRB_TR_ENT (1<<1)
163 #define TRB_TR_ISP (1<<2)
164 #define TRB_TR_NS (1<<3)
165 #define TRB_TR_CH (1<<4)
166 #define TRB_TR_IOC (1<<5)
167 #define TRB_TR_IDT (1<<6)
168 #define TRB_TR_TBC_SHIFT 7
169 #define TRB_TR_TBC_MASK 0x3
170 #define TRB_TR_BEI (1<<9)
171 #define TRB_TR_TLBPC_SHIFT 16
172 #define TRB_TR_TLBPC_MASK 0xf
173 #define TRB_TR_FRAMEID_SHIFT 20
174 #define TRB_TR_FRAMEID_MASK 0x7ff
175 #define TRB_TR_SIA (1<<31)
176
177 #define TRB_TR_DIR (1<<16)
178
179 #define TRB_CR_SLOTID_SHIFT 24
180 #define TRB_CR_SLOTID_MASK 0xff
181 #define TRB_CR_EPID_SHIFT 16
182 #define TRB_CR_EPID_MASK 0x1f
183
184 #define TRB_CR_BSR (1<<9)
185 #define TRB_CR_DC (1<<9)
186
187 #define TRB_LK_TC (1<<1)
188
189 #define TRB_INTR_SHIFT 22
190 #define TRB_INTR_MASK 0x3ff
191 #define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK)
192
193 #define EP_TYPE_MASK 0x7
194 #define EP_TYPE_SHIFT 3
195
196 #define EP_STATE_MASK 0x7
197 #define EP_DISABLED (0<<0)
198 #define EP_RUNNING (1<<0)
199 #define EP_HALTED (2<<0)
200 #define EP_STOPPED (3<<0)
201 #define EP_ERROR (4<<0)
202
203 #define SLOT_STATE_MASK 0x1f
204 #define SLOT_STATE_SHIFT 27
205 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK)
206 #define SLOT_ENABLED 0
207 #define SLOT_DEFAULT 1
208 #define SLOT_ADDRESSED 2
209 #define SLOT_CONFIGURED 3
210
211 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f
212 #define SLOT_CONTEXT_ENTRIES_SHIFT 27
213
214 #define get_field(data, field) \
215 (((data) >> field##_SHIFT) & field##_MASK)
216
217 #define set_field(data, newval, field) do { \
218 uint32_t val_ = *data; \
219 val_ &= ~(field##_MASK << field##_SHIFT); \
220 val_ |= ((newval) & field##_MASK) << field##_SHIFT; \
221 *data = val_; \
222 } while (0)
223
224 typedef enum EPType {
225 ET_INVALID = 0,
226 ET_ISO_OUT,
227 ET_BULK_OUT,
228 ET_INTR_OUT,
229 ET_CONTROL,
230 ET_ISO_IN,
231 ET_BULK_IN,
232 ET_INTR_IN,
233 } EPType;
234
235 typedef struct XHCITransfer {
236 XHCIEPContext *epctx;
237 USBPacket packet;
238 QEMUSGList sgl;
239 bool running_async;
240 bool running_retry;
241 bool complete;
242 bool int_req;
243 unsigned int iso_pkts;
244 unsigned int streamid;
245 bool in_xfer;
246 bool iso_xfer;
247 bool timed_xfer;
248
249 unsigned int trb_count;
250 XHCITRB *trbs;
251
252 TRBCCode status;
253
254 unsigned int pkts;
255 unsigned int pktsize;
256 unsigned int cur_pkt;
257
258 uint64_t mfindex_kick;
259
260 QTAILQ_ENTRY(XHCITransfer) next;
261 } XHCITransfer;
262
263 struct XHCIStreamContext {
264 dma_addr_t pctx;
265 unsigned int sct;
266 XHCIRing ring;
267 };
268
269 struct XHCIEPContext {
270 XHCIState *xhci;
271 unsigned int slotid;
272 unsigned int epid;
273
274 XHCIRing ring;
275 uint32_t xfer_count;
276 QTAILQ_HEAD(, XHCITransfer) transfers;
277 XHCITransfer *retry;
278 EPType type;
279 dma_addr_t pctx;
280 unsigned int max_psize;
281 uint32_t state;
282 uint32_t kick_active;
283
284 /* streams */
285 unsigned int max_pstreams;
286 bool lsa;
287 unsigned int nr_pstreams;
288 XHCIStreamContext *pstreams;
289
290 /* iso xfer scheduling */
291 unsigned int interval;
292 int64_t mfindex_last;
293 QEMUTimer *kick_timer;
294 };
295
296 typedef struct XHCIEvRingSeg {
297 uint32_t addr_low;
298 uint32_t addr_high;
299 uint32_t size;
300 uint32_t rsvd;
301 } XHCIEvRingSeg;
302
303 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid,
304 unsigned int epid, unsigned int streamid);
305 static void xhci_kick_epctx(XHCIEPContext *epctx, unsigned int streamid);
306 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid,
307 unsigned int epid);
308 static void xhci_xfer_report(XHCITransfer *xfer);
309 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v);
310 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v);
311 static USBEndpoint *xhci_epid_to_usbep(XHCIEPContext *epctx);
312
313 static const char *TRBType_names[] = {
314 [TRB_RESERVED] = "TRB_RESERVED",
315 [TR_NORMAL] = "TR_NORMAL",
316 [TR_SETUP] = "TR_SETUP",
317 [TR_DATA] = "TR_DATA",
318 [TR_STATUS] = "TR_STATUS",
319 [TR_ISOCH] = "TR_ISOCH",
320 [TR_LINK] = "TR_LINK",
321 [TR_EVDATA] = "TR_EVDATA",
322 [TR_NOOP] = "TR_NOOP",
323 [CR_ENABLE_SLOT] = "CR_ENABLE_SLOT",
324 [CR_DISABLE_SLOT] = "CR_DISABLE_SLOT",
325 [CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE",
326 [CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT",
327 [CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT",
328 [CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT",
329 [CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT",
330 [CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE",
331 [CR_RESET_DEVICE] = "CR_RESET_DEVICE",
332 [CR_FORCE_EVENT] = "CR_FORCE_EVENT",
333 [CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW",
334 [CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE",
335 [CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH",
336 [CR_FORCE_HEADER] = "CR_FORCE_HEADER",
337 [CR_NOOP] = "CR_NOOP",
338 [ER_TRANSFER] = "ER_TRANSFER",
339 [ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE",
340 [ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE",
341 [ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST",
342 [ER_DOORBELL] = "ER_DOORBELL",
343 [ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER",
344 [ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION",
345 [ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP",
346 [CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION",
347 [CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE",
348 };
349
350 static const char *TRBCCode_names[] = {
351 [CC_INVALID] = "CC_INVALID",
352 [CC_SUCCESS] = "CC_SUCCESS",
353 [CC_DATA_BUFFER_ERROR] = "CC_DATA_BUFFER_ERROR",
354 [CC_BABBLE_DETECTED] = "CC_BABBLE_DETECTED",
355 [CC_USB_TRANSACTION_ERROR] = "CC_USB_TRANSACTION_ERROR",
356 [CC_TRB_ERROR] = "CC_TRB_ERROR",
357 [CC_STALL_ERROR] = "CC_STALL_ERROR",
358 [CC_RESOURCE_ERROR] = "CC_RESOURCE_ERROR",
359 [CC_BANDWIDTH_ERROR] = "CC_BANDWIDTH_ERROR",
360 [CC_NO_SLOTS_ERROR] = "CC_NO_SLOTS_ERROR",
361 [CC_INVALID_STREAM_TYPE_ERROR] = "CC_INVALID_STREAM_TYPE_ERROR",
362 [CC_SLOT_NOT_ENABLED_ERROR] = "CC_SLOT_NOT_ENABLED_ERROR",
363 [CC_EP_NOT_ENABLED_ERROR] = "CC_EP_NOT_ENABLED_ERROR",
364 [CC_SHORT_PACKET] = "CC_SHORT_PACKET",
365 [CC_RING_UNDERRUN] = "CC_RING_UNDERRUN",
366 [CC_RING_OVERRUN] = "CC_RING_OVERRUN",
367 [CC_VF_ER_FULL] = "CC_VF_ER_FULL",
368 [CC_PARAMETER_ERROR] = "CC_PARAMETER_ERROR",
369 [CC_BANDWIDTH_OVERRUN] = "CC_BANDWIDTH_OVERRUN",
370 [CC_CONTEXT_STATE_ERROR] = "CC_CONTEXT_STATE_ERROR",
371 [CC_NO_PING_RESPONSE_ERROR] = "CC_NO_PING_RESPONSE_ERROR",
372 [CC_EVENT_RING_FULL_ERROR] = "CC_EVENT_RING_FULL_ERROR",
373 [CC_INCOMPATIBLE_DEVICE_ERROR] = "CC_INCOMPATIBLE_DEVICE_ERROR",
374 [CC_MISSED_SERVICE_ERROR] = "CC_MISSED_SERVICE_ERROR",
375 [CC_COMMAND_RING_STOPPED] = "CC_COMMAND_RING_STOPPED",
376 [CC_COMMAND_ABORTED] = "CC_COMMAND_ABORTED",
377 [CC_STOPPED] = "CC_STOPPED",
378 [CC_STOPPED_LENGTH_INVALID] = "CC_STOPPED_LENGTH_INVALID",
379 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR]
380 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR",
381 [CC_ISOCH_BUFFER_OVERRUN] = "CC_ISOCH_BUFFER_OVERRUN",
382 [CC_EVENT_LOST_ERROR] = "CC_EVENT_LOST_ERROR",
383 [CC_UNDEFINED_ERROR] = "CC_UNDEFINED_ERROR",
384 [CC_INVALID_STREAM_ID_ERROR] = "CC_INVALID_STREAM_ID_ERROR",
385 [CC_SECONDARY_BANDWIDTH_ERROR] = "CC_SECONDARY_BANDWIDTH_ERROR",
386 [CC_SPLIT_TRANSACTION_ERROR] = "CC_SPLIT_TRANSACTION_ERROR",
387 };
388
389 static const char *ep_state_names[] = {
390 [EP_DISABLED] = "disabled",
391 [EP_RUNNING] = "running",
392 [EP_HALTED] = "halted",
393 [EP_STOPPED] = "stopped",
394 [EP_ERROR] = "error",
395 };
396
397 static const char *lookup_name(uint32_t index, const char **list, uint32_t llen)
398 {
399 if (index >= llen || list[index] == NULL) {
400 return "???";
401 }
402 return list[index];
403 }
404
405 static const char *trb_name(XHCITRB *trb)
406 {
407 return lookup_name(TRB_TYPE(*trb), TRBType_names,
408 ARRAY_SIZE(TRBType_names));
409 }
410
411 static const char *event_name(XHCIEvent *event)
412 {
413 return lookup_name(event->ccode, TRBCCode_names,
414 ARRAY_SIZE(TRBCCode_names));
415 }
416
417 static const char *ep_state_name(uint32_t state)
418 {
419 return lookup_name(state, ep_state_names,
420 ARRAY_SIZE(ep_state_names));
421 }
422
423 bool xhci_get_flag(XHCIState *xhci, enum xhci_flags bit)
424 {
425 return xhci->flags & (1 << bit);
426 }
427
428 void xhci_set_flag(XHCIState *xhci, enum xhci_flags bit)
429 {
430 xhci->flags |= (1 << bit);
431 }
432
433 static uint64_t xhci_mfindex_get(XHCIState *xhci)
434 {
435 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
436 return (now - xhci->mfindex_start) / 125000;
437 }
438
439 static void xhci_mfwrap_update(XHCIState *xhci)
440 {
441 const uint32_t bits = USBCMD_RS | USBCMD_EWE;
442 uint32_t mfindex, left;
443 int64_t now;
444
445 if ((xhci->usbcmd & bits) == bits) {
446 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
447 mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff;
448 left = 0x4000 - mfindex;
449 timer_mod(xhci->mfwrap_timer, now + left * 125000);
450 } else {
451 timer_del(xhci->mfwrap_timer);
452 }
453 }
454
455 static void xhci_mfwrap_timer(void *opaque)
456 {
457 XHCIState *xhci = opaque;
458 XHCIEvent wrap = { ER_MFINDEX_WRAP, CC_SUCCESS };
459
460 xhci_event(xhci, &wrap, 0);
461 xhci_mfwrap_update(xhci);
462 }
463
464 static void xhci_die(XHCIState *xhci)
465 {
466 xhci->usbsts |= USBSTS_HCE;
467 DPRINTF("xhci: asserted controller error\n");
468 }
469
470 static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high)
471 {
472 if (sizeof(dma_addr_t) == 4) {
473 return low;
474 } else {
475 return low | (((dma_addr_t)high << 16) << 16);
476 }
477 }
478
479 static inline dma_addr_t xhci_mask64(uint64_t addr)
480 {
481 if (sizeof(dma_addr_t) == 4) {
482 return addr & 0xffffffff;
483 } else {
484 return addr;
485 }
486 }
487
488 static inline void xhci_dma_read_u32s(XHCIState *xhci, dma_addr_t addr,
489 uint32_t *buf, size_t len)
490 {
491 int i;
492
493 assert((len % sizeof(uint32_t)) == 0);
494
495 if (dma_memory_read(xhci->as, addr, buf, len,
496 MEMTXATTRS_UNSPECIFIED) != MEMTX_OK) {
497 qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA memory access failed!\n",
498 __func__);
499 memset(buf, 0xff, len);
500 xhci_die(xhci);
501 return;
502 }
503
504 for (i = 0; i < (len / sizeof(uint32_t)); i++) {
505 buf[i] = le32_to_cpu(buf[i]);
506 }
507 }
508
509 static inline void xhci_dma_write_u32s(XHCIState *xhci, dma_addr_t addr,
510 const uint32_t *buf, size_t len)
511 {
512 int i;
513 uint32_t tmp[5];
514 uint32_t n = len / sizeof(uint32_t);
515
516 assert((len % sizeof(uint32_t)) == 0);
517 assert(n <= ARRAY_SIZE(tmp));
518
519 for (i = 0; i < n; i++) {
520 tmp[i] = cpu_to_le32(buf[i]);
521 }
522 if (dma_memory_write(xhci->as, addr, tmp, len,
523 MEMTXATTRS_UNSPECIFIED) != MEMTX_OK) {
524 qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA memory access failed!\n",
525 __func__);
526 xhci_die(xhci);
527 return;
528 }
529 }
530
531 static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport)
532 {
533 int index;
534
535 if (!uport->dev) {
536 return NULL;
537 }
538 switch (uport->dev->speed) {
539 case USB_SPEED_LOW:
540 case USB_SPEED_FULL:
541 case USB_SPEED_HIGH:
542 index = uport->index + xhci->numports_3;
543 break;
544 case USB_SPEED_SUPER:
545 index = uport->index;
546 break;
547 default:
548 return NULL;
549 }
550 return &xhci->ports[index];
551 }
552
553 static void xhci_intr_update(XHCIState *xhci, int v)
554 {
555 int level = 0;
556
557 if (v == 0) {
558 if (xhci->intr[0].iman & IMAN_IP &&
559 xhci->intr[0].iman & IMAN_IE &&
560 xhci->usbcmd & USBCMD_INTE) {
561 level = 1;
562 }
563 if (xhci->intr_raise) {
564 if (xhci->intr_raise(xhci, 0, level)) {
565 xhci->intr[0].iman &= ~IMAN_IP;
566 }
567 }
568 }
569 if (xhci->intr_update) {
570 xhci->intr_update(xhci, v,
571 xhci->intr[v].iman & IMAN_IE);
572 }
573 }
574
575 static void xhci_intr_raise(XHCIState *xhci, int v)
576 {
577 bool pending = (xhci->intr[v].erdp_low & ERDP_EHB);
578
579 xhci->intr[v].erdp_low |= ERDP_EHB;
580 xhci->intr[v].iman |= IMAN_IP;
581 xhci->usbsts |= USBSTS_EINT;
582
583 if (pending) {
584 return;
585 }
586 if (!(xhci->intr[v].iman & IMAN_IE)) {
587 return;
588 }
589
590 if (!(xhci->usbcmd & USBCMD_INTE)) {
591 return;
592 }
593 if (xhci->intr_raise) {
594 if (xhci->intr_raise(xhci, v, true)) {
595 xhci->intr[v].iman &= ~IMAN_IP;
596 }
597 }
598 }
599
600 static inline int xhci_running(XHCIState *xhci)
601 {
602 return !(xhci->usbsts & USBSTS_HCH);
603 }
604
605 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v)
606 {
607 XHCIInterrupter *intr = &xhci->intr[v];
608 XHCITRB ev_trb;
609 dma_addr_t addr;
610
611 ev_trb.parameter = cpu_to_le64(event->ptr);
612 ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24));
613 ev_trb.control = (event->slotid << 24) | (event->epid << 16) |
614 event->flags | (event->type << TRB_TYPE_SHIFT);
615 if (intr->er_pcs) {
616 ev_trb.control |= TRB_C;
617 }
618 ev_trb.control = cpu_to_le32(ev_trb.control);
619
620 trace_usb_xhci_queue_event(v, intr->er_ep_idx, trb_name(&ev_trb),
621 event_name(event), ev_trb.parameter,
622 ev_trb.status, ev_trb.control);
623
624 addr = intr->er_start + TRB_SIZE*intr->er_ep_idx;
625 if (dma_memory_write(xhci->as, addr, &ev_trb, TRB_SIZE,
626 MEMTXATTRS_UNSPECIFIED) != MEMTX_OK) {
627 qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA memory access failed!\n",
628 __func__);
629 xhci_die(xhci);
630 }
631
632 intr->er_ep_idx++;
633 if (intr->er_ep_idx >= intr->er_size) {
634 intr->er_ep_idx = 0;
635 intr->er_pcs = !intr->er_pcs;
636 }
637 }
638
639 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v)
640 {
641 XHCIInterrupter *intr;
642 dma_addr_t erdp;
643 unsigned int dp_idx;
644
645 if (xhci->numintrs == 1 ||
646 (xhci->intr_mapping_supported && !xhci->intr_mapping_supported(xhci))) {
647 v = 0;
648 }
649
650 if (v >= xhci->numintrs) {
651 DPRINTF("intr nr out of range (%d >= %d)\n", v, xhci->numintrs);
652 return;
653 }
654 intr = &xhci->intr[v];
655
656 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high);
657 if (erdp < intr->er_start ||
658 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) {
659 DPRINTF("xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp);
660 DPRINTF("xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n",
661 v, intr->er_start, intr->er_size);
662 xhci_die(xhci);
663 return;
664 }
665
666 dp_idx = (erdp - intr->er_start) / TRB_SIZE;
667 assert(dp_idx < intr->er_size);
668
669 if ((intr->er_ep_idx + 2) % intr->er_size == dp_idx) {
670 DPRINTF("xhci: ER %d full, send ring full error\n", v);
671 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR};
672 xhci_write_event(xhci, &full, v);
673 } else if ((intr->er_ep_idx + 1) % intr->er_size == dp_idx) {
674 DPRINTF("xhci: ER %d full, drop event\n", v);
675 } else {
676 xhci_write_event(xhci, event, v);
677 }
678
679 xhci_intr_raise(xhci, v);
680 }
681
682 static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring,
683 dma_addr_t base)
684 {
685 ring->dequeue = base;
686 ring->ccs = 1;
687 }
688
689 static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb,
690 dma_addr_t *addr)
691 {
692 uint32_t link_cnt = 0;
693
694 while (1) {
695 TRBType type;
696 if (dma_memory_read(xhci->as, ring->dequeue, trb, TRB_SIZE,
697 MEMTXATTRS_UNSPECIFIED) != MEMTX_OK) {
698 qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA memory access failed!\n",
699 __func__);
700 return 0;
701 }
702 trb->addr = ring->dequeue;
703 trb->ccs = ring->ccs;
704 le64_to_cpus(&trb->parameter);
705 le32_to_cpus(&trb->status);
706 le32_to_cpus(&trb->control);
707
708 trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb),
709 trb->parameter, trb->status, trb->control);
710
711 if ((trb->control & TRB_C) != ring->ccs) {
712 return 0;
713 }
714
715 type = TRB_TYPE(*trb);
716
717 if (type != TR_LINK) {
718 if (addr) {
719 *addr = ring->dequeue;
720 }
721 ring->dequeue += TRB_SIZE;
722 return type;
723 } else {
724 if (++link_cnt > TRB_LINK_LIMIT) {
725 trace_usb_xhci_enforced_limit("trb-link");
726 return 0;
727 }
728 ring->dequeue = xhci_mask64(trb->parameter);
729 if (trb->control & TRB_LK_TC) {
730 ring->ccs = !ring->ccs;
731 }
732 }
733 }
734 }
735
736 static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring)
737 {
738 XHCITRB trb;
739 int length = 0;
740 dma_addr_t dequeue = ring->dequeue;
741 bool ccs = ring->ccs;
742 /* hack to bundle together the two/three TDs that make a setup transfer */
743 bool control_td_set = 0;
744 uint32_t link_cnt = 0;
745
746 do {
747 TRBType type;
748 if (dma_memory_read(xhci->as, dequeue, &trb, TRB_SIZE,
749 MEMTXATTRS_UNSPECIFIED) != MEMTX_OK) {
750 qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA memory access failed!\n",
751 __func__);
752 return -1;
753 }
754 le64_to_cpus(&trb.parameter);
755 le32_to_cpus(&trb.status);
756 le32_to_cpus(&trb.control);
757
758 if ((trb.control & TRB_C) != ccs) {
759 return -length;
760 }
761
762 type = TRB_TYPE(trb);
763
764 if (type == TR_LINK) {
765 if (++link_cnt > TRB_LINK_LIMIT) {
766 return -length;
767 }
768 dequeue = xhci_mask64(trb.parameter);
769 if (trb.control & TRB_LK_TC) {
770 ccs = !ccs;
771 }
772 continue;
773 }
774
775 length += 1;
776 dequeue += TRB_SIZE;
777
778 if (type == TR_SETUP) {
779 control_td_set = 1;
780 } else if (type == TR_STATUS) {
781 control_td_set = 0;
782 }
783
784 if (!control_td_set && !(trb.control & TRB_TR_CH)) {
785 return length;
786 }
787
788 /*
789 * According to the xHCI spec, Transfer Ring segments should have
790 * a maximum size of 64 kB (see chapter "6 Data Structures")
791 */
792 } while (length < TRB_LINK_LIMIT * 65536 / TRB_SIZE);
793
794 qemu_log_mask(LOG_GUEST_ERROR, "%s: exceeded maximum transfer ring size!\n",
795 __func__);
796
797 return -1;
798 }
799
800 static void xhci_er_reset(XHCIState *xhci, int v)
801 {
802 XHCIInterrupter *intr = &xhci->intr[v];
803 XHCIEvRingSeg seg;
804 dma_addr_t erstba = xhci_addr64(intr->erstba_low, intr->erstba_high);
805
806 if (intr->erstsz == 0 || erstba == 0) {
807 /* disabled */
808 intr->er_start = 0;
809 intr->er_size = 0;
810 return;
811 }
812 /* cache the (sole) event ring segment location */
813 if (intr->erstsz != 1) {
814 DPRINTF("xhci: invalid value for ERSTSZ: %d\n", intr->erstsz);
815 xhci_die(xhci);
816 return;
817 }
818 if (dma_memory_read(xhci->as, erstba, &seg, sizeof(seg),
819 MEMTXATTRS_UNSPECIFIED) != MEMTX_OK) {
820 qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA memory access failed!\n",
821 __func__);
822 xhci_die(xhci);
823 return;
824 }
825
826 le32_to_cpus(&seg.addr_low);
827 le32_to_cpus(&seg.addr_high);
828 le32_to_cpus(&seg.size);
829 if (seg.size < 16 || seg.size > 4096) {
830 DPRINTF("xhci: invalid value for segment size: %d\n", seg.size);
831 xhci_die(xhci);
832 return;
833 }
834 intr->er_start = xhci_addr64(seg.addr_low, seg.addr_high);
835 intr->er_size = seg.size;
836
837 intr->er_ep_idx = 0;
838 intr->er_pcs = 1;
839
840 DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT " [%d]\n",
841 v, intr->er_start, intr->er_size);
842 }
843
844 static void xhci_run(XHCIState *xhci)
845 {
846 trace_usb_xhci_run();
847 xhci->usbsts &= ~USBSTS_HCH;
848 xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
849 }
850
851 static void xhci_stop(XHCIState *xhci)
852 {
853 trace_usb_xhci_stop();
854 xhci->usbsts |= USBSTS_HCH;
855 xhci->crcr_low &= ~CRCR_CRR;
856 }
857
858 static XHCIStreamContext *xhci_alloc_stream_contexts(unsigned count,
859 dma_addr_t base)
860 {
861 XHCIStreamContext *stctx;
862 unsigned int i;
863
864 stctx = g_new0(XHCIStreamContext, count);
865 for (i = 0; i < count; i++) {
866 stctx[i].pctx = base + i * 16;
867 stctx[i].sct = -1;
868 }
869 return stctx;
870 }
871
872 static void xhci_reset_streams(XHCIEPContext *epctx)
873 {
874 unsigned int i;
875
876 for (i = 0; i < epctx->nr_pstreams; i++) {
877 epctx->pstreams[i].sct = -1;
878 }
879 }
880
881 static void xhci_alloc_streams(XHCIEPContext *epctx, dma_addr_t base)
882 {
883 assert(epctx->pstreams == NULL);
884 epctx->nr_pstreams = 2 << epctx->max_pstreams;
885 epctx->pstreams = xhci_alloc_stream_contexts(epctx->nr_pstreams, base);
886 }
887
888 static void xhci_free_streams(XHCIEPContext *epctx)
889 {
890 assert(epctx->pstreams != NULL);
891
892 g_free(epctx->pstreams);
893 epctx->pstreams = NULL;
894 epctx->nr_pstreams = 0;
895 }
896
897 static int xhci_epmask_to_eps_with_streams(XHCIState *xhci,
898 unsigned int slotid,
899 uint32_t epmask,
900 XHCIEPContext **epctxs,
901 USBEndpoint **eps)
902 {
903 XHCISlot *slot;
904 XHCIEPContext *epctx;
905 USBEndpoint *ep;
906 int i, j;
907
908 assert(slotid >= 1 && slotid <= xhci->numslots);
909
910 slot = &xhci->slots[slotid - 1];
911
912 for (i = 2, j = 0; i <= 31; i++) {
913 if (!(epmask & (1u << i))) {
914 continue;
915 }
916
917 epctx = slot->eps[i - 1];
918 ep = xhci_epid_to_usbep(epctx);
919 if (!epctx || !epctx->nr_pstreams || !ep) {
920 continue;
921 }
922
923 if (epctxs) {
924 epctxs[j] = epctx;
925 }
926 eps[j++] = ep;
927 }
928 return j;
929 }
930
931 static void xhci_free_device_streams(XHCIState *xhci, unsigned int slotid,
932 uint32_t epmask)
933 {
934 USBEndpoint *eps[30];
935 int nr_eps;
936
937 nr_eps = xhci_epmask_to_eps_with_streams(xhci, slotid, epmask, NULL, eps);
938 if (nr_eps) {
939 usb_device_free_streams(eps[0]->dev, eps, nr_eps);
940 }
941 }
942
943 static TRBCCode xhci_alloc_device_streams(XHCIState *xhci, unsigned int slotid,
944 uint32_t epmask)
945 {
946 XHCIEPContext *epctxs[30];
947 USBEndpoint *eps[30];
948 int i, r, nr_eps, req_nr_streams, dev_max_streams;
949
950 nr_eps = xhci_epmask_to_eps_with_streams(xhci, slotid, epmask, epctxs,
951 eps);
952 if (nr_eps == 0) {
953 return CC_SUCCESS;
954 }
955
956 req_nr_streams = epctxs[0]->nr_pstreams;
957 dev_max_streams = eps[0]->max_streams;
958
959 for (i = 1; i < nr_eps; i++) {
960 /*
961 * HdG: I don't expect these to ever trigger, but if they do we need
962 * to come up with another solution, ie group identical endpoints
963 * together and make an usb_device_alloc_streams call per group.
964 */
965 if (epctxs[i]->nr_pstreams != req_nr_streams) {
966 qemu_log_mask(LOG_UNIMP,
967 "guest streams config not identical for all eps\n");
968 return CC_RESOURCE_ERROR;
969 }
970 if (eps[i]->max_streams != dev_max_streams) {
971 qemu_log_mask(LOG_UNIMP,
972 "device streams config not identical for all eps\n");
973 return CC_RESOURCE_ERROR;
974 }
975 }
976
977 /*
978 * max-streams in both the device descriptor and in the controller is a
979 * power of 2. But stream id 0 is reserved, so if a device can do up to 4
980 * streams the guest will ask for 5 rounded up to the next power of 2 which
981 * becomes 8. For emulated devices usb_device_alloc_streams is a nop.
982 *
983 * For redirected devices however this is an issue, as there we must ask
984 * the real xhci controller to alloc streams, and the host driver for the
985 * real xhci controller will likely disallow allocating more streams then
986 * the device can handle.
987 *
988 * So we limit the requested nr_streams to the maximum number the device
989 * can handle.
990 */
991 if (req_nr_streams > dev_max_streams) {
992 req_nr_streams = dev_max_streams;
993 }
994
995 r = usb_device_alloc_streams(eps[0]->dev, eps, nr_eps, req_nr_streams);
996 if (r != 0) {
997 DPRINTF("xhci: alloc streams failed\n");
998 return CC_RESOURCE_ERROR;
999 }
1000
1001 return CC_SUCCESS;
1002 }
1003
1004 static XHCIStreamContext *xhci_find_stream(XHCIEPContext *epctx,
1005 unsigned int streamid,
1006 uint32_t *cc_error)
1007 {
1008 XHCIStreamContext *sctx;
1009 dma_addr_t base;
1010 uint32_t ctx[2], sct;
1011
1012 if (!streamid) {
1013 qemu_log_mask(LOG_GUEST_ERROR, "xhci: stream ID is zero\n");
1014 *cc_error = CC_INVALID_STREAM_ID_ERROR;
1015 return NULL;
1016 }
1017
1018 if (epctx->lsa) {
1019 if (streamid >= epctx->nr_pstreams) {
1020 *cc_error = CC_INVALID_STREAM_ID_ERROR;
1021 return NULL;
1022 }
1023 sctx = epctx->pstreams + streamid;
1024 } else {
1025 qemu_log_mask(LOG_UNIMP,
1026 "xhci: secondary streams not implemented yet\n");
1027 *cc_error = CC_INVALID_STREAM_TYPE_ERROR;
1028 return NULL;
1029 }
1030
1031 if (sctx->sct == -1) {
1032 xhci_dma_read_u32s(epctx->xhci, sctx->pctx, ctx, sizeof(ctx));
1033 sct = (ctx[0] >> 1) & 0x07;
1034 if (epctx->lsa && sct != 1) {
1035 *cc_error = CC_INVALID_STREAM_TYPE_ERROR;
1036 return NULL;
1037 }
1038 sctx->sct = sct;
1039 base = xhci_addr64(ctx[0] & ~0xf, ctx[1]);
1040 xhci_ring_init(epctx->xhci, &sctx->ring, base);
1041 }
1042 return sctx;
1043 }
1044
1045 static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx,
1046 XHCIStreamContext *sctx, uint32_t state)
1047 {
1048 XHCIRing *ring = NULL;
1049 uint32_t ctx[5];
1050 uint32_t ctx2[2];
1051
1052 xhci_dma_read_u32s(xhci, epctx->pctx, ctx, sizeof(ctx));
1053 ctx[0] &= ~EP_STATE_MASK;
1054 ctx[0] |= state;
1055
1056 /* update ring dequeue ptr */
1057 if (epctx->nr_pstreams) {
1058 if (sctx != NULL) {
1059 ring = &sctx->ring;
1060 xhci_dma_read_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2));
1061 ctx2[0] &= 0xe;
1062 ctx2[0] |= sctx->ring.dequeue | sctx->ring.ccs;
1063 ctx2[1] = (sctx->ring.dequeue >> 16) >> 16;
1064 xhci_dma_write_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2));
1065 }
1066 } else {
1067 ring = &epctx->ring;
1068 }
1069 if (ring) {
1070 ctx[2] = ring->dequeue | ring->ccs;
1071 ctx[3] = (ring->dequeue >> 16) >> 16;
1072
1073 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n",
1074 epctx->pctx, state, ctx[3], ctx[2]);
1075 }
1076
1077 xhci_dma_write_u32s(xhci, epctx->pctx, ctx, sizeof(ctx));
1078 if (epctx->state != state) {
1079 trace_usb_xhci_ep_state(epctx->slotid, epctx->epid,
1080 ep_state_name(epctx->state),
1081 ep_state_name(state));
1082 }
1083 epctx->state = state;
1084 }
1085
1086 static void xhci_ep_kick_timer(void *opaque)
1087 {
1088 XHCIEPContext *epctx = opaque;
1089 xhci_kick_epctx(epctx, 0);
1090 }
1091
1092 static XHCIEPContext *xhci_alloc_epctx(XHCIState *xhci,
1093 unsigned int slotid,
1094 unsigned int epid)
1095 {
1096 XHCIEPContext *epctx;
1097
1098 epctx = g_new0(XHCIEPContext, 1);
1099 epctx->xhci = xhci;
1100 epctx->slotid = slotid;
1101 epctx->epid = epid;
1102
1103 QTAILQ_INIT(&epctx->transfers);
1104 epctx->kick_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_ep_kick_timer, epctx);
1105
1106 return epctx;
1107 }
1108
1109 static void xhci_init_epctx(XHCIEPContext *epctx,
1110 dma_addr_t pctx, uint32_t *ctx)
1111 {
1112 dma_addr_t dequeue;
1113
1114 dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]);
1115
1116 epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK;
1117 epctx->pctx = pctx;
1118 epctx->max_psize = ctx[1]>>16;
1119 epctx->max_psize *= 1+((ctx[1]>>8)&0xff);
1120 epctx->max_pstreams = (ctx[0] >> 10) & epctx->xhci->max_pstreams_mask;
1121 epctx->lsa = (ctx[0] >> 15) & 1;
1122 if (epctx->max_pstreams) {
1123 xhci_alloc_streams(epctx, dequeue);
1124 } else {
1125 xhci_ring_init(epctx->xhci, &epctx->ring, dequeue);
1126 epctx->ring.ccs = ctx[2] & 1;
1127 }
1128
1129 epctx->interval = 1u << MIN((ctx[0] >> 16) & 0xffu, 18u);
1130 }
1131
1132 static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid,
1133 unsigned int epid, dma_addr_t pctx,
1134 uint32_t *ctx)
1135 {
1136 XHCISlot *slot;
1137 XHCIEPContext *epctx;
1138
1139 trace_usb_xhci_ep_enable(slotid, epid);
1140 assert(slotid >= 1 && slotid <= xhci->numslots);
1141 assert(epid >= 1 && epid <= 31);
1142
1143 slot = &xhci->slots[slotid-1];
1144 if (slot->eps[epid-1]) {
1145 xhci_disable_ep(xhci, slotid, epid);
1146 }
1147
1148 epctx = xhci_alloc_epctx(xhci, slotid, epid);
1149 slot->eps[epid-1] = epctx;
1150 xhci_init_epctx(epctx, pctx, ctx);
1151
1152 DPRINTF("xhci: endpoint %d.%d type is %d, max transaction (burst) "
1153 "size is %d\n", epid/2, epid%2, epctx->type, epctx->max_psize);
1154
1155 epctx->mfindex_last = 0;
1156
1157 epctx->state = EP_RUNNING;
1158 ctx[0] &= ~EP_STATE_MASK;
1159 ctx[0] |= EP_RUNNING;
1160
1161 return CC_SUCCESS;
1162 }
1163
1164 static XHCITransfer *xhci_ep_alloc_xfer(XHCIEPContext *epctx,
1165 uint32_t length)
1166 {
1167 uint32_t limit = epctx->nr_pstreams + 16;
1168 XHCITransfer *xfer;
1169
1170 if (epctx->xfer_count >= limit) {
1171 return NULL;
1172 }
1173
1174 xfer = g_new0(XHCITransfer, 1);
1175 xfer->epctx = epctx;
1176 xfer->trbs = g_new(XHCITRB, length);
1177 xfer->trb_count = length;
1178 usb_packet_init(&xfer->packet);
1179
1180 QTAILQ_INSERT_TAIL(&epctx->transfers, xfer, next);
1181 epctx->xfer_count++;
1182
1183 return xfer;
1184 }
1185
1186 static void xhci_ep_free_xfer(XHCITransfer *xfer)
1187 {
1188 QTAILQ_REMOVE(&xfer->epctx->transfers, xfer, next);
1189 xfer->epctx->xfer_count--;
1190
1191 usb_packet_cleanup(&xfer->packet);
1192 g_free(xfer->trbs);
1193 g_free(xfer);
1194 }
1195
1196 static void xhci_xfer_unmap(XHCITransfer *xfer)
1197 {
1198 usb_packet_unmap(&xfer->packet, &xfer->sgl);
1199 qemu_sglist_destroy(&xfer->sgl);
1200 }
1201
1202 static int xhci_ep_nuke_one_xfer(XHCITransfer *t, TRBCCode report)
1203 {
1204 int killed = 0;
1205
1206 if (report && (t->running_async || t->running_retry)) {
1207 t->status = report;
1208 xhci_xfer_report(t);
1209 }
1210
1211 if (t->running_async) {
1212 usb_cancel_packet(&t->packet);
1213 xhci_xfer_unmap(t);
1214 t->running_async = 0;
1215 killed = 1;
1216 }
1217 if (t->running_retry) {
1218 if (t->epctx) {
1219 t->epctx->retry = NULL;
1220 timer_del(t->epctx->kick_timer);
1221 }
1222 t->running_retry = 0;
1223 killed = 1;
1224 }
1225 g_free(t->trbs);
1226
1227 t->trbs = NULL;
1228 t->trb_count = 0;
1229
1230 return killed;
1231 }
1232
1233 static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid,
1234 unsigned int epid, TRBCCode report)
1235 {
1236 XHCISlot *slot;
1237 XHCIEPContext *epctx;
1238 XHCITransfer *xfer;
1239 int killed = 0;
1240 USBEndpoint *ep = NULL;
1241 assert(slotid >= 1 && slotid <= xhci->numslots);
1242 assert(epid >= 1 && epid <= 31);
1243
1244 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid);
1245
1246 slot = &xhci->slots[slotid-1];
1247
1248 if (!slot->eps[epid-1]) {
1249 return 0;
1250 }
1251
1252 epctx = slot->eps[epid-1];
1253
1254 for (;;) {
1255 xfer = QTAILQ_FIRST(&epctx->transfers);
1256 if (xfer == NULL) {
1257 break;
1258 }
1259 killed += xhci_ep_nuke_one_xfer(xfer, report);
1260 if (killed) {
1261 report = 0; /* Only report once */
1262 }
1263 xhci_ep_free_xfer(xfer);
1264 }
1265
1266 ep = xhci_epid_to_usbep(epctx);
1267 if (ep) {
1268 usb_device_ep_stopped(ep->dev, ep);
1269 }
1270 return killed;
1271 }
1272
1273 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid,
1274 unsigned int epid)
1275 {
1276 XHCISlot *slot;
1277 XHCIEPContext *epctx;
1278
1279 trace_usb_xhci_ep_disable(slotid, epid);
1280 assert(slotid >= 1 && slotid <= xhci->numslots);
1281 assert(epid >= 1 && epid <= 31);
1282
1283 slot = &xhci->slots[slotid-1];
1284
1285 if (!slot->eps[epid-1]) {
1286 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid);
1287 return CC_SUCCESS;
1288 }
1289
1290 xhci_ep_nuke_xfers(xhci, slotid, epid, 0);
1291
1292 epctx = slot->eps[epid-1];
1293
1294 if (epctx->nr_pstreams) {
1295 xhci_free_streams(epctx);
1296 }
1297
1298 /* only touch guest RAM if we're not resetting the HC */
1299 if (xhci->dcbaap_low || xhci->dcbaap_high) {
1300 xhci_set_ep_state(xhci, epctx, NULL, EP_DISABLED);
1301 }
1302
1303 timer_free(epctx->kick_timer);
1304 g_free(epctx);
1305 slot->eps[epid-1] = NULL;
1306
1307 return CC_SUCCESS;
1308 }
1309
1310 static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid,
1311 unsigned int epid)
1312 {
1313 XHCISlot *slot;
1314 XHCIEPContext *epctx;
1315
1316 trace_usb_xhci_ep_stop(slotid, epid);
1317 assert(slotid >= 1 && slotid <= xhci->numslots);
1318
1319 if (epid < 1 || epid > 31) {
1320 DPRINTF("xhci: bad ep %d\n", epid);
1321 return CC_TRB_ERROR;
1322 }
1323
1324 slot = &xhci->slots[slotid-1];
1325
1326 if (!slot->eps[epid-1]) {
1327 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1328 return CC_EP_NOT_ENABLED_ERROR;
1329 }
1330
1331 if (xhci_ep_nuke_xfers(xhci, slotid, epid, CC_STOPPED) > 0) {
1332 DPRINTF("xhci: FIXME: endpoint stopped w/ xfers running, "
1333 "data might be lost\n");
1334 }
1335
1336 epctx = slot->eps[epid-1];
1337
1338 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED);
1339
1340 if (epctx->nr_pstreams) {
1341 xhci_reset_streams(epctx);
1342 }
1343
1344 return CC_SUCCESS;
1345 }
1346
1347 static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid,
1348 unsigned int epid)
1349 {
1350 XHCISlot *slot;
1351 XHCIEPContext *epctx;
1352
1353 trace_usb_xhci_ep_reset(slotid, epid);
1354 assert(slotid >= 1 && slotid <= xhci->numslots);
1355
1356 if (epid < 1 || epid > 31) {
1357 DPRINTF("xhci: bad ep %d\n", epid);
1358 return CC_TRB_ERROR;
1359 }
1360
1361 slot = &xhci->slots[slotid-1];
1362
1363 if (!slot->eps[epid-1]) {
1364 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1365 return CC_EP_NOT_ENABLED_ERROR;
1366 }
1367
1368 epctx = slot->eps[epid-1];
1369
1370 if (epctx->state != EP_HALTED) {
1371 DPRINTF("xhci: reset EP while EP %d not halted (%d)\n",
1372 epid, epctx->state);
1373 return CC_CONTEXT_STATE_ERROR;
1374 }
1375
1376 if (xhci_ep_nuke_xfers(xhci, slotid, epid, 0) > 0) {
1377 DPRINTF("xhci: FIXME: endpoint reset w/ xfers running, "
1378 "data might be lost\n");
1379 }
1380
1381 if (!xhci->slots[slotid-1].uport ||
1382 !xhci->slots[slotid-1].uport->dev ||
1383 !xhci->slots[slotid-1].uport->dev->attached) {
1384 return CC_USB_TRANSACTION_ERROR;
1385 }
1386
1387 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED);
1388
1389 if (epctx->nr_pstreams) {
1390 xhci_reset_streams(epctx);
1391 }
1392
1393 return CC_SUCCESS;
1394 }
1395
1396 static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid,
1397 unsigned int epid, unsigned int streamid,
1398 uint64_t pdequeue)
1399 {
1400 XHCISlot *slot;
1401 XHCIEPContext *epctx;
1402 XHCIStreamContext *sctx;
1403 dma_addr_t dequeue;
1404
1405 assert(slotid >= 1 && slotid <= xhci->numslots);
1406
1407 if (epid < 1 || epid > 31) {
1408 DPRINTF("xhci: bad ep %d\n", epid);
1409 return CC_TRB_ERROR;
1410 }
1411
1412 trace_usb_xhci_ep_set_dequeue(slotid, epid, streamid, pdequeue);
1413 dequeue = xhci_mask64(pdequeue);
1414
1415 slot = &xhci->slots[slotid-1];
1416
1417 if (!slot->eps[epid-1]) {
1418 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1419 return CC_EP_NOT_ENABLED_ERROR;
1420 }
1421
1422 epctx = slot->eps[epid-1];
1423
1424 if (epctx->state != EP_STOPPED) {
1425 DPRINTF("xhci: set EP dequeue pointer while EP %d not stopped\n", epid);
1426 return CC_CONTEXT_STATE_ERROR;
1427 }
1428
1429 if (epctx->nr_pstreams) {
1430 uint32_t err;
1431 sctx = xhci_find_stream(epctx, streamid, &err);
1432 if (sctx == NULL) {
1433 return err;
1434 }
1435 xhci_ring_init(xhci, &sctx->ring, dequeue & ~0xf);
1436 sctx->ring.ccs = dequeue & 1;
1437 } else {
1438 sctx = NULL;
1439 xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF);
1440 epctx->ring.ccs = dequeue & 1;
1441 }
1442
1443 xhci_set_ep_state(xhci, epctx, sctx, EP_STOPPED);
1444
1445 return CC_SUCCESS;
1446 }
1447
1448 static int xhci_xfer_create_sgl(XHCITransfer *xfer, int in_xfer)
1449 {
1450 XHCIState *xhci = xfer->epctx->xhci;
1451 int i;
1452
1453 xfer->int_req = false;
1454 qemu_sglist_init(&xfer->sgl, DEVICE(xhci), xfer->trb_count, xhci->as);
1455 for (i = 0; i < xfer->trb_count; i++) {
1456 XHCITRB *trb = &xfer->trbs[i];
1457 dma_addr_t addr;
1458 unsigned int chunk = 0;
1459
1460 if (trb->control & TRB_TR_IOC) {
1461 xfer->int_req = true;
1462 }
1463
1464 switch (TRB_TYPE(*trb)) {
1465 case TR_DATA:
1466 if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) {
1467 qemu_log_mask(LOG_GUEST_ERROR,
1468 "xhci: data direction mismatch for TR_DATA\n");
1469 goto err;
1470 }
1471 /* fallthrough */
1472 case TR_NORMAL:
1473 case TR_ISOCH:
1474 addr = xhci_mask64(trb->parameter);
1475 chunk = trb->status & 0x1ffff;
1476 if (trb->control & TRB_TR_IDT) {
1477 if (chunk > 8 || in_xfer) {
1478 qemu_log_mask(LOG_GUEST_ERROR,
1479 "xhci: invalid immediate data TRB\n");
1480 goto err;
1481 }
1482 qemu_sglist_add(&xfer->sgl, trb->addr, chunk);
1483 } else {
1484 qemu_sglist_add(&xfer->sgl, addr, chunk);
1485 }
1486 break;
1487 }
1488 }
1489
1490 return 0;
1491
1492 err:
1493 qemu_sglist_destroy(&xfer->sgl);
1494 xhci_die(xhci);
1495 return -1;
1496 }
1497
1498 static void xhci_xfer_report(XHCITransfer *xfer)
1499 {
1500 uint32_t edtla = 0;
1501 unsigned int left;
1502 bool reported = 0;
1503 bool shortpkt = 0;
1504 XHCIEvent event = {ER_TRANSFER, CC_SUCCESS};
1505 XHCIState *xhci = xfer->epctx->xhci;
1506 int i;
1507
1508 left = xfer->packet.actual_length;
1509
1510 for (i = 0; i < xfer->trb_count; i++) {
1511 XHCITRB *trb = &xfer->trbs[i];
1512 unsigned int chunk = 0;
1513
1514 switch (TRB_TYPE(*trb)) {
1515 case TR_SETUP:
1516 chunk = trb->status & 0x1ffff;
1517 if (chunk > 8) {
1518 chunk = 8;
1519 }
1520 break;
1521 case TR_DATA:
1522 case TR_NORMAL:
1523 case TR_ISOCH:
1524 chunk = trb->status & 0x1ffff;
1525 if (chunk > left) {
1526 chunk = left;
1527 if (xfer->status == CC_SUCCESS) {
1528 shortpkt = 1;
1529 }
1530 }
1531 left -= chunk;
1532 edtla += chunk;
1533 break;
1534 case TR_STATUS:
1535 reported = 0;
1536 shortpkt = 0;
1537 break;
1538 }
1539
1540 if (!reported && ((trb->control & TRB_TR_IOC) ||
1541 (shortpkt && (trb->control & TRB_TR_ISP)) ||
1542 (xfer->status != CC_SUCCESS && left == 0))) {
1543 event.slotid = xfer->epctx->slotid;
1544 event.epid = xfer->epctx->epid;
1545 event.length = (trb->status & 0x1ffff) - chunk;
1546 event.flags = 0;
1547 event.ptr = trb->addr;
1548 if (xfer->status == CC_SUCCESS) {
1549 event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS;
1550 } else {
1551 event.ccode = xfer->status;
1552 }
1553 if (TRB_TYPE(*trb) == TR_EVDATA) {
1554 event.ptr = trb->parameter;
1555 event.flags |= TRB_EV_ED;
1556 event.length = edtla & 0xffffff;
1557 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length);
1558 edtla = 0;
1559 }
1560 xhci_event(xhci, &event, TRB_INTR(*trb));
1561 reported = 1;
1562 if (xfer->status != CC_SUCCESS) {
1563 return;
1564 }
1565 }
1566
1567 switch (TRB_TYPE(*trb)) {
1568 case TR_SETUP:
1569 reported = 0;
1570 shortpkt = 0;
1571 break;
1572 }
1573
1574 }
1575 }
1576
1577 static void xhci_stall_ep(XHCITransfer *xfer)
1578 {
1579 XHCIEPContext *epctx = xfer->epctx;
1580 XHCIState *xhci = epctx->xhci;
1581 uint32_t err;
1582 XHCIStreamContext *sctx;
1583
1584 if (epctx->type == ET_ISO_IN || epctx->type == ET_ISO_OUT) {
1585 /* never halt isoch endpoints, 4.10.2 */
1586 return;
1587 }
1588
1589 if (epctx->nr_pstreams) {
1590 sctx = xhci_find_stream(epctx, xfer->streamid, &err);
1591 if (sctx == NULL) {
1592 return;
1593 }
1594 sctx->ring.dequeue = xfer->trbs[0].addr;
1595 sctx->ring.ccs = xfer->trbs[0].ccs;
1596 xhci_set_ep_state(xhci, epctx, sctx, EP_HALTED);
1597 } else {
1598 epctx->ring.dequeue = xfer->trbs[0].addr;
1599 epctx->ring.ccs = xfer->trbs[0].ccs;
1600 xhci_set_ep_state(xhci, epctx, NULL, EP_HALTED);
1601 }
1602 }
1603
1604 static int xhci_setup_packet(XHCITransfer *xfer)
1605 {
1606 USBEndpoint *ep;
1607 int dir;
1608
1609 dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT;
1610
1611 if (xfer->packet.ep) {
1612 ep = xfer->packet.ep;
1613 } else {
1614 ep = xhci_epid_to_usbep(xfer->epctx);
1615 if (!ep) {
1616 DPRINTF("xhci: slot %d has no device\n",
1617 xfer->epctx->slotid);
1618 return -1;
1619 }
1620 }
1621
1622 if (xhci_xfer_create_sgl(xfer, dir == USB_TOKEN_IN) < 0) { /* Also sets int_req */
1623 return -1;
1624 }
1625 usb_packet_setup(&xfer->packet, dir, ep, xfer->streamid,
1626 xfer->trbs[0].addr, false, xfer->int_req);
1627 if (usb_packet_map(&xfer->packet, &xfer->sgl)) {
1628 qemu_sglist_destroy(&xfer->sgl);
1629 return -1;
1630 }
1631 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n",
1632 xfer->packet.pid, ep->dev->addr, ep->nr);
1633 return 0;
1634 }
1635
1636 static int xhci_try_complete_packet(XHCITransfer *xfer)
1637 {
1638 if (xfer->packet.status == USB_RET_ASYNC) {
1639 trace_usb_xhci_xfer_async(xfer);
1640 xfer->running_async = 1;
1641 xfer->running_retry = 0;
1642 xfer->complete = 0;
1643 return 0;
1644 } else if (xfer->packet.status == USB_RET_NAK) {
1645 trace_usb_xhci_xfer_nak(xfer);
1646 xfer->running_async = 0;
1647 xfer->running_retry = 1;
1648 xfer->complete = 0;
1649 return 0;
1650 } else {
1651 xfer->running_async = 0;
1652 xfer->running_retry = 0;
1653 xfer->complete = 1;
1654 xhci_xfer_unmap(xfer);
1655 }
1656
1657 if (xfer->packet.status == USB_RET_SUCCESS) {
1658 trace_usb_xhci_xfer_success(xfer, xfer->packet.actual_length);
1659 xfer->status = CC_SUCCESS;
1660 xhci_xfer_report(xfer);
1661 return 0;
1662 }
1663
1664 /* error */
1665 trace_usb_xhci_xfer_error(xfer, xfer->packet.status);
1666 switch (xfer->packet.status) {
1667 case USB_RET_NODEV:
1668 case USB_RET_IOERROR:
1669 xfer->status = CC_USB_TRANSACTION_ERROR;
1670 xhci_xfer_report(xfer);
1671 xhci_stall_ep(xfer);
1672 break;
1673 case USB_RET_STALL:
1674 xfer->status = CC_STALL_ERROR;
1675 xhci_xfer_report(xfer);
1676 xhci_stall_ep(xfer);
1677 break;
1678 case USB_RET_BABBLE:
1679 xfer->status = CC_BABBLE_DETECTED;
1680 xhci_xfer_report(xfer);
1681 xhci_stall_ep(xfer);
1682 break;
1683 default:
1684 g_assert_not_reached();
1685 }
1686 return 0;
1687 }
1688
1689 static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer)
1690 {
1691 XHCITRB *trb_setup, *trb_status;
1692 uint8_t bmRequestType;
1693
1694 trb_setup = &xfer->trbs[0];
1695 trb_status = &xfer->trbs[xfer->trb_count-1];
1696
1697 trace_usb_xhci_xfer_start(xfer, xfer->epctx->slotid,
1698 xfer->epctx->epid, xfer->streamid);
1699
1700 /* at most one Event Data TRB allowed after STATUS */
1701 if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) {
1702 trb_status--;
1703 }
1704
1705 /* do some sanity checks */
1706 if (TRB_TYPE(*trb_setup) != TR_SETUP) {
1707 DPRINTF("xhci: ep0 first TD not SETUP: %d\n",
1708 TRB_TYPE(*trb_setup));
1709 return -1;
1710 }
1711 if (TRB_TYPE(*trb_status) != TR_STATUS) {
1712 DPRINTF("xhci: ep0 last TD not STATUS: %d\n",
1713 TRB_TYPE(*trb_status));
1714 return -1;
1715 }
1716 if (!(trb_setup->control & TRB_TR_IDT)) {
1717 DPRINTF("xhci: Setup TRB doesn't have IDT set\n");
1718 return -1;
1719 }
1720 if ((trb_setup->status & 0x1ffff) != 8) {
1721 DPRINTF("xhci: Setup TRB has bad length (%d)\n",
1722 (trb_setup->status & 0x1ffff));
1723 return -1;
1724 }
1725
1726 bmRequestType = trb_setup->parameter;
1727
1728 xfer->in_xfer = bmRequestType & USB_DIR_IN;
1729 xfer->iso_xfer = false;
1730 xfer->timed_xfer = false;
1731
1732 if (xhci_setup_packet(xfer) < 0) {
1733 return -1;
1734 }
1735 xfer->packet.parameter = trb_setup->parameter;
1736
1737 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1738 xhci_try_complete_packet(xfer);
1739 return 0;
1740 }
1741
1742 static void xhci_calc_intr_kick(XHCIState *xhci, XHCITransfer *xfer,
1743 XHCIEPContext *epctx, uint64_t mfindex)
1744 {
1745 uint64_t asap = ((mfindex + epctx->interval - 1) &
1746 ~(epctx->interval-1));
1747 uint64_t kick = epctx->mfindex_last + epctx->interval;
1748
1749 assert(epctx->interval != 0);
1750 xfer->mfindex_kick = MAX(asap, kick);
1751 }
1752
1753 static void xhci_calc_iso_kick(XHCIState *xhci, XHCITransfer *xfer,
1754 XHCIEPContext *epctx, uint64_t mfindex)
1755 {
1756 if (xfer->trbs[0].control & TRB_TR_SIA) {
1757 uint64_t asap = ((mfindex + epctx->interval - 1) &
1758 ~(epctx->interval-1));
1759 if (asap >= epctx->mfindex_last &&
1760 asap <= epctx->mfindex_last + epctx->interval * 4) {
1761 xfer->mfindex_kick = epctx->mfindex_last + epctx->interval;
1762 } else {
1763 xfer->mfindex_kick = asap;
1764 }
1765 } else {
1766 xfer->mfindex_kick = ((xfer->trbs[0].control >> TRB_TR_FRAMEID_SHIFT)
1767 & TRB_TR_FRAMEID_MASK) << 3;
1768 xfer->mfindex_kick |= mfindex & ~0x3fff;
1769 if (xfer->mfindex_kick + 0x100 < mfindex) {
1770 xfer->mfindex_kick += 0x4000;
1771 }
1772 }
1773 }
1774
1775 static void xhci_check_intr_iso_kick(XHCIState *xhci, XHCITransfer *xfer,
1776 XHCIEPContext *epctx, uint64_t mfindex)
1777 {
1778 if (xfer->mfindex_kick > mfindex) {
1779 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
1780 (xfer->mfindex_kick - mfindex) * 125000);
1781 xfer->running_retry = 1;
1782 } else {
1783 epctx->mfindex_last = xfer->mfindex_kick;
1784 timer_del(epctx->kick_timer);
1785 xfer->running_retry = 0;
1786 }
1787 }
1788
1789
1790 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
1791 {
1792 uint64_t mfindex;
1793
1794 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", epctx->slotid, epctx->epid);
1795
1796 xfer->in_xfer = epctx->type>>2;
1797
1798 switch(epctx->type) {
1799 case ET_INTR_OUT:
1800 case ET_INTR_IN:
1801 xfer->pkts = 0;
1802 xfer->iso_xfer = false;
1803 xfer->timed_xfer = true;
1804 mfindex = xhci_mfindex_get(xhci);
1805 xhci_calc_intr_kick(xhci, xfer, epctx, mfindex);
1806 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex);
1807 if (xfer->running_retry) {
1808 return -1;
1809 }
1810 break;
1811 case ET_BULK_OUT:
1812 case ET_BULK_IN:
1813 xfer->pkts = 0;
1814 xfer->iso_xfer = false;
1815 xfer->timed_xfer = false;
1816 break;
1817 case ET_ISO_OUT:
1818 case ET_ISO_IN:
1819 xfer->pkts = 1;
1820 xfer->iso_xfer = true;
1821 xfer->timed_xfer = true;
1822 mfindex = xhci_mfindex_get(xhci);
1823 xhci_calc_iso_kick(xhci, xfer, epctx, mfindex);
1824 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex);
1825 if (xfer->running_retry) {
1826 return -1;
1827 }
1828 break;
1829 default:
1830 trace_usb_xhci_unimplemented("endpoint type", epctx->type);
1831 return -1;
1832 }
1833
1834 if (xhci_setup_packet(xfer) < 0) {
1835 return -1;
1836 }
1837 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1838 xhci_try_complete_packet(xfer);
1839 return 0;
1840 }
1841
1842 static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
1843 {
1844 trace_usb_xhci_xfer_start(xfer, xfer->epctx->slotid,
1845 xfer->epctx->epid, xfer->streamid);
1846 return xhci_submit(xhci, xfer, epctx);
1847 }
1848
1849 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid,
1850 unsigned int epid, unsigned int streamid)
1851 {
1852 XHCIEPContext *epctx;
1853
1854 assert(slotid >= 1 && slotid <= xhci->numslots);
1855 assert(epid >= 1 && epid <= 31);
1856
1857 if (!xhci->slots[slotid-1].enabled) {
1858 DPRINTF("xhci: xhci_kick_ep for disabled slot %d\n", slotid);
1859 return;
1860 }
1861 epctx = xhci->slots[slotid-1].eps[epid-1];
1862 if (!epctx) {
1863 DPRINTF("xhci: xhci_kick_ep for disabled endpoint %d,%d\n",
1864 epid, slotid);
1865 return;
1866 }
1867
1868 if (epctx->kick_active) {
1869 return;
1870 }
1871 xhci_kick_epctx(epctx, streamid);
1872 }
1873
1874 static bool xhci_slot_ok(XHCIState *xhci, int slotid)
1875 {
1876 return (xhci->slots[slotid - 1].uport &&
1877 xhci->slots[slotid - 1].uport->dev &&
1878 xhci->slots[slotid - 1].uport->dev->attached);
1879 }
1880
1881 static void xhci_kick_epctx(XHCIEPContext *epctx, unsigned int streamid)
1882 {
1883 XHCIState *xhci = epctx->xhci;
1884 XHCIStreamContext *stctx = NULL;
1885 XHCITransfer *xfer;
1886 XHCIRing *ring;
1887 USBEndpoint *ep = NULL;
1888 uint64_t mfindex;
1889 unsigned int count = 0;
1890 int length;
1891 int i;
1892
1893 trace_usb_xhci_ep_kick(epctx->slotid, epctx->epid, streamid);
1894 assert(!epctx->kick_active);
1895
1896 /* If the device has been detached, but the guest has not noticed this
1897 yet the 2 above checks will succeed, but we must NOT continue */
1898 if (!xhci_slot_ok(xhci, epctx->slotid)) {
1899 return;
1900 }
1901
1902 if (epctx->retry) {
1903 xfer = epctx->retry;
1904
1905 trace_usb_xhci_xfer_retry(xfer);
1906 assert(xfer->running_retry);
1907 if (xfer->timed_xfer) {
1908 /* time to kick the transfer? */
1909 mfindex = xhci_mfindex_get(xhci);
1910 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex);
1911 if (xfer->running_retry) {
1912 return;
1913 }
1914 xfer->timed_xfer = 0;
1915 xfer->running_retry = 1;
1916 }
1917 if (xfer->iso_xfer) {
1918 /* retry iso transfer */
1919 if (xhci_setup_packet(xfer) < 0) {
1920 return;
1921 }
1922 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1923 assert(xfer->packet.status != USB_RET_NAK);
1924 xhci_try_complete_packet(xfer);
1925 } else {
1926 /* retry nak'ed transfer */
1927 if (xhci_setup_packet(xfer) < 0) {
1928 return;
1929 }
1930 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1931 if (xfer->packet.status == USB_RET_NAK) {
1932 xhci_xfer_unmap(xfer);
1933 return;
1934 }
1935 xhci_try_complete_packet(xfer);
1936 }
1937 assert(!xfer->running_retry);
1938 if (xfer->complete) {
1939 /* update ring dequeue ptr */
1940 xhci_set_ep_state(xhci, epctx, stctx, epctx->state);
1941 xhci_ep_free_xfer(epctx->retry);
1942 }
1943 epctx->retry = NULL;
1944 }
1945
1946 if (epctx->state == EP_HALTED) {
1947 DPRINTF("xhci: ep halted, not running schedule\n");
1948 return;
1949 }
1950
1951
1952 if (epctx->nr_pstreams) {
1953 uint32_t err;
1954 stctx = xhci_find_stream(epctx, streamid, &err);
1955 if (stctx == NULL) {
1956 return;
1957 }
1958 ring = &stctx->ring;
1959 xhci_set_ep_state(xhci, epctx, stctx, EP_RUNNING);
1960 } else {
1961 ring = &epctx->ring;
1962 streamid = 0;
1963 xhci_set_ep_state(xhci, epctx, NULL, EP_RUNNING);
1964 }
1965 if (!ring->dequeue) {
1966 return;
1967 }
1968
1969 epctx->kick_active++;
1970 while (1) {
1971 length = xhci_ring_chain_length(xhci, ring);
1972 if (length <= 0) {
1973 if (epctx->type == ET_ISO_OUT || epctx->type == ET_ISO_IN) {
1974 /* 4.10.3.1 */
1975 XHCIEvent ev = { ER_TRANSFER };
1976 ev.ccode = epctx->type == ET_ISO_IN ?
1977 CC_RING_OVERRUN : CC_RING_UNDERRUN;
1978 ev.slotid = epctx->slotid;
1979 ev.epid = epctx->epid;
1980 ev.ptr = epctx->ring.dequeue;
1981 xhci_event(xhci, &ev, xhci->slots[epctx->slotid-1].intr);
1982 }
1983 break;
1984 }
1985 xfer = xhci_ep_alloc_xfer(epctx, length);
1986 if (xfer == NULL) {
1987 break;
1988 }
1989
1990 for (i = 0; i < length; i++) {
1991 TRBType type;
1992 type = xhci_ring_fetch(xhci, ring, &xfer->trbs[i], NULL);
1993 if (!type) {
1994 xhci_die(xhci);
1995 xhci_ep_free_xfer(xfer);
1996 epctx->kick_active--;
1997 return;
1998 }
1999 }
2000 xfer->streamid = streamid;
2001
2002 if (epctx->epid == 1) {
2003 xhci_fire_ctl_transfer(xhci, xfer);
2004 } else {
2005 xhci_fire_transfer(xhci, xfer, epctx);
2006 }
2007 if (!xhci_slot_ok(xhci, epctx->slotid)) {
2008 /* surprise removal -> stop processing */
2009 break;
2010 }
2011 if (xfer->complete) {
2012 /* update ring dequeue ptr */
2013 xhci_set_ep_state(xhci, epctx, stctx, epctx->state);
2014 xhci_ep_free_xfer(xfer);
2015 xfer = NULL;
2016 }
2017
2018 if (epctx->state == EP_HALTED) {
2019 break;
2020 }
2021 if (xfer != NULL && xfer->running_retry) {
2022 DPRINTF("xhci: xfer nacked, stopping schedule\n");
2023 epctx->retry = xfer;
2024 xhci_xfer_unmap(xfer);
2025 break;
2026 }
2027 if (count++ > TRANSFER_LIMIT) {
2028 trace_usb_xhci_enforced_limit("transfers");
2029 break;
2030 }
2031 }
2032 epctx->kick_active--;
2033
2034 ep = xhci_epid_to_usbep(epctx);
2035 if (ep) {
2036 usb_device_flush_ep_queue(ep->dev, ep);
2037 }
2038 }
2039
2040 static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid)
2041 {
2042 trace_usb_xhci_slot_enable(slotid);
2043 assert(slotid >= 1 && slotid <= xhci->numslots);
2044 xhci->slots[slotid-1].enabled = 1;
2045 xhci->slots[slotid-1].uport = NULL;
2046 memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31);
2047
2048 return CC_SUCCESS;
2049 }
2050
2051 static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid)
2052 {
2053 int i;
2054
2055 trace_usb_xhci_slot_disable(slotid);
2056 assert(slotid >= 1 && slotid <= xhci->numslots);
2057
2058 for (i = 1; i <= 31; i++) {
2059 if (xhci->slots[slotid-1].eps[i-1]) {
2060 xhci_disable_ep(xhci, slotid, i);
2061 }
2062 }
2063
2064 xhci->slots[slotid-1].enabled = 0;
2065 xhci->slots[slotid-1].addressed = 0;
2066 xhci->slots[slotid-1].uport = NULL;
2067 xhci->slots[slotid-1].intr = 0;
2068 return CC_SUCCESS;
2069 }
2070
2071 static USBPort *xhci_lookup_uport(XHCIState *xhci, uint32_t *slot_ctx)
2072 {
2073 USBPort *uport;
2074 char path[32];
2075 int i, pos, port;
2076
2077 port = (slot_ctx[1]>>16) & 0xFF;
2078 if (port < 1 || port > xhci->numports) {
2079 return NULL;
2080 }
2081 port = xhci->ports[port-1].uport->index+1;
2082 pos = snprintf(path, sizeof(path), "%d", port);
2083 for (i = 0; i < 5; i++) {
2084 port = (slot_ctx[0] >> 4*i) & 0x0f;
2085 if (!port) {
2086 break;
2087 }
2088 pos += snprintf(path + pos, sizeof(path) - pos, ".%d", port);
2089 }
2090
2091 QTAILQ_FOREACH(uport, &xhci->bus.used, next) {
2092 if (strcmp(uport->path, path) == 0) {
2093 return uport;
2094 }
2095 }
2096 return NULL;
2097 }
2098
2099 static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid,
2100 uint64_t pictx, bool bsr)
2101 {
2102 XHCISlot *slot;
2103 USBPort *uport;
2104 USBDevice *dev;
2105 dma_addr_t ictx, octx, dcbaap;
2106 uint64_t poctx;
2107 uint32_t ictl_ctx[2];
2108 uint32_t slot_ctx[4];
2109 uint32_t ep0_ctx[5];
2110 int i;
2111 TRBCCode res;
2112
2113 assert(slotid >= 1 && slotid <= xhci->numslots);
2114
2115 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high);
2116 ldq_le_dma(xhci->as, dcbaap + 8 * slotid, &poctx, MEMTXATTRS_UNSPECIFIED);
2117 ictx = xhci_mask64(pictx);
2118 octx = xhci_mask64(poctx);
2119
2120 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
2121 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
2122
2123 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx));
2124
2125 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) {
2126 DPRINTF("xhci: invalid input context control %08x %08x\n",
2127 ictl_ctx[0], ictl_ctx[1]);
2128 return CC_TRB_ERROR;
2129 }
2130
2131 xhci_dma_read_u32s(xhci, ictx+32, slot_ctx, sizeof(slot_ctx));
2132 xhci_dma_read_u32s(xhci, ictx+64, ep0_ctx, sizeof(ep0_ctx));
2133
2134 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2135 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2136
2137 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2138 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
2139
2140 uport = xhci_lookup_uport(xhci, slot_ctx);
2141 if (uport == NULL) {
2142 DPRINTF("xhci: port not found\n");
2143 return CC_TRB_ERROR;
2144 }
2145 trace_usb_xhci_slot_address(slotid, uport->path);
2146
2147 dev = uport->dev;
2148 if (!dev || !dev->attached) {
2149 DPRINTF("xhci: port %s not connected\n", uport->path);
2150 return CC_USB_TRANSACTION_ERROR;
2151 }
2152
2153 for (i = 0; i < xhci->numslots; i++) {
2154 if (i == slotid-1) {
2155 continue;
2156 }
2157 if (xhci->slots[i].uport == uport) {
2158 DPRINTF("xhci: port %s already assigned to slot %d\n",
2159 uport->path, i+1);
2160 return CC_TRB_ERROR;
2161 }
2162 }
2163
2164 slot = &xhci->slots[slotid-1];
2165 slot->uport = uport;
2166 slot->ctx = octx;
2167 slot->intr = get_field(slot_ctx[2], TRB_INTR);
2168
2169 /* Make sure device is in USB_STATE_DEFAULT state */
2170 usb_device_reset(dev);
2171 if (bsr) {
2172 slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT;
2173 } else {
2174 USBPacket p;
2175 uint8_t buf[1];
2176
2177 slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slotid;
2178 memset(&p, 0, sizeof(p));
2179 usb_packet_addbuf(&p, buf, sizeof(buf));
2180 usb_packet_setup(&p, USB_TOKEN_OUT,
2181 usb_ep_get(dev, USB_TOKEN_OUT, 0), 0,
2182 0, false, false);
2183 usb_device_handle_control(dev, &p,
2184 DeviceOutRequest | USB_REQ_SET_ADDRESS,
2185 slotid, 0, 0, NULL);
2186 assert(p.status != USB_RET_ASYNC);
2187 usb_packet_cleanup(&p);
2188 }
2189
2190 res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx);
2191
2192 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2193 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2194 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2195 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
2196
2197 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2198 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx));
2199
2200 xhci->slots[slotid-1].addressed = 1;
2201 return res;
2202 }
2203
2204
2205 static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid,
2206 uint64_t pictx, bool dc)
2207 {
2208 dma_addr_t ictx, octx;
2209 uint32_t ictl_ctx[2];
2210 uint32_t slot_ctx[4];
2211 uint32_t islot_ctx[4];
2212 uint32_t ep_ctx[5];
2213 int i;
2214 TRBCCode res;
2215
2216 trace_usb_xhci_slot_configure(slotid);
2217 assert(slotid >= 1 && slotid <= xhci->numslots);
2218
2219 ictx = xhci_mask64(pictx);
2220 octx = xhci->slots[slotid-1].ctx;
2221
2222 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
2223 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
2224
2225 if (dc) {
2226 for (i = 2; i <= 31; i++) {
2227 if (xhci->slots[slotid-1].eps[i-1]) {
2228 xhci_disable_ep(xhci, slotid, i);
2229 }
2230 }
2231
2232 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2233 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
2234 slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT;
2235 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2236 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2237 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2238
2239 return CC_SUCCESS;
2240 }
2241
2242 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx));
2243
2244 if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) {
2245 DPRINTF("xhci: invalid input context control %08x %08x\n",
2246 ictl_ctx[0], ictl_ctx[1]);
2247 return CC_TRB_ERROR;
2248 }
2249
2250 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx));
2251 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2252
2253 if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) {
2254 DPRINTF("xhci: invalid slot state %08x\n", slot_ctx[3]);
2255 return CC_CONTEXT_STATE_ERROR;
2256 }
2257
2258 xhci_free_device_streams(xhci, slotid, ictl_ctx[0] | ictl_ctx[1]);
2259
2260 for (i = 2; i <= 31; i++) {
2261 if (ictl_ctx[0] & (1<<i)) {
2262 xhci_disable_ep(xhci, slotid, i);
2263 }
2264 if (ictl_ctx[1] & (1<<i)) {
2265 xhci_dma_read_u32s(xhci, ictx+32+(32*i), ep_ctx, sizeof(ep_ctx));
2266 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n",
2267 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],
2268 ep_ctx[3], ep_ctx[4]);
2269 xhci_disable_ep(xhci, slotid, i);
2270 res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx);
2271 if (res != CC_SUCCESS) {
2272 return res;
2273 }
2274 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n",
2275 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],
2276 ep_ctx[3], ep_ctx[4]);
2277 xhci_dma_write_u32s(xhci, octx+(32*i), ep_ctx, sizeof(ep_ctx));
2278 }
2279 }
2280
2281 res = xhci_alloc_device_streams(xhci, slotid, ictl_ctx[1]);
2282 if (res != CC_SUCCESS) {
2283 for (i = 2; i <= 31; i++) {
2284 if (ictl_ctx[1] & (1u << i)) {
2285 xhci_disable_ep(xhci, slotid, i);
2286 }
2287 }
2288 return res;
2289 }
2290
2291 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
2292 slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT;
2293 slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT);
2294 slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK <<
2295 SLOT_CONTEXT_ENTRIES_SHIFT);
2296 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2297 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2298
2299 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2300
2301 return CC_SUCCESS;
2302 }
2303
2304
2305 static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid,
2306 uint64_t pictx)
2307 {
2308 dma_addr_t ictx, octx;
2309 uint32_t ictl_ctx[2];
2310 uint32_t iep0_ctx[5];
2311 uint32_t ep0_ctx[5];
2312 uint32_t islot_ctx[4];
2313 uint32_t slot_ctx[4];
2314
2315 trace_usb_xhci_slot_evaluate(slotid);
2316 assert(slotid >= 1 && slotid <= xhci->numslots);
2317
2318 ictx = xhci_mask64(pictx);
2319 octx = xhci->slots[slotid-1].ctx;
2320
2321 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
2322 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
2323
2324 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx));
2325
2326 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) {
2327 DPRINTF("xhci: invalid input context control %08x %08x\n",
2328 ictl_ctx[0], ictl_ctx[1]);
2329 return CC_TRB_ERROR;
2330 }
2331
2332 if (ictl_ctx[1] & 0x1) {
2333 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx));
2334
2335 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2336 islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]);
2337
2338 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2339
2340 slot_ctx[1] &= ~0xFFFF; /* max exit latency */
2341 slot_ctx[1] |= islot_ctx[1] & 0xFFFF;
2342 /* update interrupter target field */
2343 xhci->slots[slotid-1].intr = get_field(islot_ctx[2], TRB_INTR);
2344 set_field(&slot_ctx[2], xhci->slots[slotid-1].intr, TRB_INTR);
2345
2346 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2347 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2348
2349 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2350 }
2351
2352 if (ictl_ctx[1] & 0x2) {
2353 xhci_dma_read_u32s(xhci, ictx+64, iep0_ctx, sizeof(iep0_ctx));
2354
2355 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2356 iep0_ctx[0], iep0_ctx[1], iep0_ctx[2],
2357 iep0_ctx[3], iep0_ctx[4]);
2358
2359 xhci_dma_read_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx));
2360
2361 ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/
2362 ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000;
2363
2364 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2365 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
2366
2367 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx));
2368 }
2369
2370 return CC_SUCCESS;
2371 }
2372
2373 static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid)
2374 {
2375 uint32_t slot_ctx[4];
2376 dma_addr_t octx;
2377 int i;
2378
2379 trace_usb_xhci_slot_reset(slotid);
2380 assert(slotid >= 1 && slotid <= xhci->numslots);
2381
2382 octx = xhci->slots[slotid-1].ctx;
2383
2384 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
2385
2386 for (i = 2; i <= 31; i++) {
2387 if (xhci->slots[slotid-1].eps[i-1]) {
2388 xhci_disable_ep(xhci, slotid, i);
2389 }
2390 }
2391
2392 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2393 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
2394 slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT;
2395 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2396 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2397 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2398
2399 return CC_SUCCESS;
2400 }
2401
2402 static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb)
2403 {
2404 unsigned int slotid;
2405 slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK;
2406 if (slotid < 1 || slotid > xhci->numslots) {
2407 DPRINTF("xhci: bad slot id %d\n", slotid);
2408 event->ccode = CC_TRB_ERROR;
2409 return 0;
2410 } else if (!xhci->slots[slotid-1].enabled) {
2411 DPRINTF("xhci: slot id %d not enabled\n", slotid);
2412 event->ccode = CC_SLOT_NOT_ENABLED_ERROR;
2413 return 0;
2414 }
2415 return slotid;
2416 }
2417
2418 /* cleanup slot state on usb device detach */
2419 static void xhci_detach_slot(XHCIState *xhci, USBPort *uport)
2420 {
2421 int slot, ep;
2422
2423 for (slot = 0; slot < xhci->numslots; slot++) {
2424 if (xhci->slots[slot].uport == uport) {
2425 break;
2426 }
2427 }
2428 if (slot == xhci->numslots) {
2429 return;
2430 }
2431
2432 for (ep = 0; ep < 31; ep++) {
2433 if (xhci->slots[slot].eps[ep]) {
2434 xhci_ep_nuke_xfers(xhci, slot + 1, ep + 1, 0);
2435 }
2436 }
2437 xhci->slots[slot].uport = NULL;
2438 }
2439
2440 static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx)
2441 {
2442 dma_addr_t ctx;
2443
2444 DPRINTF("xhci_get_port_bandwidth()\n");
2445
2446 ctx = xhci_mask64(pctx);
2447
2448 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx);
2449
2450 /* TODO: actually implement real values here. This is 80% for all ports. */
2451 if (stb_dma(xhci->as, ctx, 0, MEMTXATTRS_UNSPECIFIED) != MEMTX_OK ||
2452 dma_memory_set(xhci->as, ctx + 1, 80, xhci->numports,
2453 MEMTXATTRS_UNSPECIFIED) != MEMTX_OK) {
2454 qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA memory write failed!\n",
2455 __func__);
2456 return CC_TRB_ERROR;
2457 }
2458
2459 return CC_SUCCESS;
2460 }
2461
2462 static uint32_t rotl(uint32_t v, unsigned count)
2463 {
2464 count &= 31;
2465 return (v << count) | (v >> (32 - count));
2466 }
2467
2468
2469 static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo)
2470 {
2471 uint32_t val;
2472 val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F));
2473 val += rotl(lo + 0x49434878, hi & 0x1F);
2474 val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F);
2475 return ~val;
2476 }
2477
2478 static void xhci_process_commands(XHCIState *xhci)
2479 {
2480 XHCITRB trb;
2481 TRBType type;
2482 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS};
2483 dma_addr_t addr;
2484 unsigned int i, slotid = 0, count = 0;
2485
2486 DPRINTF("xhci_process_commands()\n");
2487 if (!xhci_running(xhci)) {
2488 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n");
2489 return;
2490 }
2491
2492 xhci->crcr_low |= CRCR_CRR;
2493
2494 while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) {
2495 event.ptr = addr;
2496 switch (type) {
2497 case CR_ENABLE_SLOT:
2498 for (i = 0; i < xhci->numslots; i++) {
2499 if (!xhci->slots[i].enabled) {
2500 break;
2501 }
2502 }
2503 if (i >= xhci->numslots) {
2504 DPRINTF("xhci: no device slots available\n");
2505 event.ccode = CC_NO_SLOTS_ERROR;
2506 } else {
2507 slotid = i+1;
2508 event.ccode = xhci_enable_slot(xhci, slotid);
2509 }
2510 break;
2511 case CR_DISABLE_SLOT:
2512 slotid = xhci_get_slot(xhci, &event, &trb);
2513 if (slotid) {
2514 event.ccode = xhci_disable_slot(xhci, slotid);
2515 }
2516 break;
2517 case CR_ADDRESS_DEVICE:
2518 slotid = xhci_get_slot(xhci, &event, &trb);
2519 if (slotid) {
2520 event.ccode = xhci_address_slot(xhci, slotid, trb.parameter,
2521 trb.control & TRB_CR_BSR);
2522 }
2523 break;
2524 case CR_CONFIGURE_ENDPOINT:
2525 slotid = xhci_get_slot(xhci, &event, &trb);
2526 if (slotid) {
2527 event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter,
2528 trb.control & TRB_CR_DC);
2529 }
2530 break;
2531 case CR_EVALUATE_CONTEXT:
2532 slotid = xhci_get_slot(xhci, &event, &trb);
2533 if (slotid) {
2534 event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter);
2535 }
2536 break;
2537 case CR_STOP_ENDPOINT:
2538 slotid = xhci_get_slot(xhci, &event, &trb);
2539 if (slotid) {
2540 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2541 & TRB_CR_EPID_MASK;
2542 event.ccode = xhci_stop_ep(xhci, slotid, epid);
2543 }
2544 break;
2545 case CR_RESET_ENDPOINT:
2546 slotid = xhci_get_slot(xhci, &event, &trb);
2547 if (slotid) {
2548 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2549 & TRB_CR_EPID_MASK;
2550 event.ccode = xhci_reset_ep(xhci, slotid, epid);
2551 }
2552 break;
2553 case CR_SET_TR_DEQUEUE:
2554 slotid = xhci_get_slot(xhci, &event, &trb);
2555 if (slotid) {
2556 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2557 & TRB_CR_EPID_MASK;
2558 unsigned int streamid = (trb.status >> 16) & 0xffff;
2559 event.ccode = xhci_set_ep_dequeue(xhci, slotid,
2560 epid, streamid,
2561 trb.parameter);
2562 }
2563 break;
2564 case CR_RESET_DEVICE:
2565 slotid = xhci_get_slot(xhci, &event, &trb);
2566 if (slotid) {
2567 event.ccode = xhci_reset_slot(xhci, slotid);
2568 }
2569 break;
2570 case CR_GET_PORT_BANDWIDTH:
2571 event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter);
2572 break;
2573 case CR_NOOP:
2574 event.ccode = CC_SUCCESS;
2575 break;
2576 case CR_VENDOR_NEC_FIRMWARE_REVISION:
2577 if (xhci->nec_quirks) {
2578 event.type = 48; /* NEC reply */
2579 event.length = 0x3034;
2580 } else {
2581 event.ccode = CC_TRB_ERROR;
2582 }
2583 break;
2584 case CR_VENDOR_NEC_CHALLENGE_RESPONSE:
2585 if (xhci->nec_quirks) {
2586 uint32_t chi = trb.parameter >> 32;
2587 uint32_t clo = trb.parameter;
2588 uint32_t val = xhci_nec_challenge(chi, clo);
2589 event.length = val & 0xFFFF;
2590 event.epid = val >> 16;
2591 slotid = val >> 24;
2592 event.type = 48; /* NEC reply */
2593 } else {
2594 event.ccode = CC_TRB_ERROR;
2595 }
2596 break;
2597 default:
2598 trace_usb_xhci_unimplemented("command", type);
2599 event.ccode = CC_TRB_ERROR;
2600 break;
2601 }
2602 event.slotid = slotid;
2603 xhci_event(xhci, &event, 0);
2604
2605 if (count++ > COMMAND_LIMIT) {
2606 trace_usb_xhci_enforced_limit("commands");
2607 return;
2608 }
2609 }
2610 }
2611
2612 static bool xhci_port_have_device(XHCIPort *port)
2613 {
2614 if (!port->uport->dev || !port->uport->dev->attached) {
2615 return false; /* no device present */
2616 }
2617 if (!((1 << port->uport->dev->speed) & port->speedmask)) {
2618 return false; /* speed mismatch */
2619 }
2620 return true;
2621 }
2622
2623 static void xhci_port_notify(XHCIPort *port, uint32_t bits)
2624 {
2625 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS,
2626 port->portnr << 24 };
2627
2628 if ((port->portsc & bits) == bits) {
2629 return;
2630 }
2631 trace_usb_xhci_port_notify(port->portnr, bits);
2632 port->portsc |= bits;
2633 if (!xhci_running(port->xhci)) {
2634 return;
2635 }
2636 xhci_event(port->xhci, &ev, 0);
2637 }
2638
2639 static void xhci_port_update(XHCIPort *port, int is_detach)
2640 {
2641 uint32_t pls = PLS_RX_DETECT;
2642
2643 assert(port);
2644 port->portsc = PORTSC_PP;
2645 if (!is_detach && xhci_port_have_device(port)) {
2646 port->portsc |= PORTSC_CCS;
2647 switch (port->uport->dev->speed) {
2648 case USB_SPEED_LOW:
2649 port->portsc |= PORTSC_SPEED_LOW;
2650 pls = PLS_POLLING;
2651 break;
2652 case USB_SPEED_FULL:
2653 port->portsc |= PORTSC_SPEED_FULL;
2654 pls = PLS_POLLING;
2655 break;
2656 case USB_SPEED_HIGH:
2657 port->portsc |= PORTSC_SPEED_HIGH;
2658 pls = PLS_POLLING;
2659 break;
2660 case USB_SPEED_SUPER:
2661 port->portsc |= PORTSC_SPEED_SUPER;
2662 port->portsc |= PORTSC_PED;
2663 pls = PLS_U0;
2664 break;
2665 }
2666 }
2667 set_field(&port->portsc, pls, PORTSC_PLS);
2668 trace_usb_xhci_port_link(port->portnr, pls);
2669 xhci_port_notify(port, PORTSC_CSC);
2670 }
2671
2672 static void xhci_port_reset(XHCIPort *port, bool warm_reset)
2673 {
2674 trace_usb_xhci_port_reset(port->portnr, warm_reset);
2675
2676 if (!xhci_port_have_device(port)) {
2677 return;
2678 }
2679
2680 usb_device_reset(port->uport->dev);
2681
2682 switch (port->uport->dev->speed) {
2683 case USB_SPEED_SUPER:
2684 if (warm_reset) {
2685 port->portsc |= PORTSC_WRC;
2686 }
2687 /* fall through */
2688 case USB_SPEED_LOW:
2689 case USB_SPEED_FULL:
2690 case USB_SPEED_HIGH:
2691 set_field(&port->portsc, PLS_U0, PORTSC_PLS);
2692 trace_usb_xhci_port_link(port->portnr, PLS_U0);
2693 port->portsc |= PORTSC_PED;
2694 break;
2695 }
2696
2697 port->portsc &= ~PORTSC_PR;
2698 xhci_port_notify(port, PORTSC_PRC);
2699 }
2700
2701 static void xhci_reset(DeviceState *dev)
2702 {
2703 XHCIState *xhci = XHCI(dev);
2704 int i;
2705
2706 trace_usb_xhci_reset();
2707 if (!(xhci->usbsts & USBSTS_HCH)) {
2708 DPRINTF("xhci: reset while running!\n");
2709 }
2710
2711 xhci->usbcmd = 0;
2712 xhci->usbsts = USBSTS_HCH;
2713 xhci->dnctrl = 0;
2714 xhci->crcr_low = 0;
2715 xhci->crcr_high = 0;
2716 xhci->dcbaap_low = 0;
2717 xhci->dcbaap_high = 0;
2718 xhci->config = 0;
2719
2720 for (i = 0; i < xhci->numslots; i++) {
2721 xhci_disable_slot(xhci, i+1);
2722 }
2723
2724 for (i = 0; i < xhci->numports; i++) {
2725 xhci_port_update(xhci->ports + i, 0);
2726 }
2727
2728 for (i = 0; i < xhci->numintrs; i++) {
2729 xhci->intr[i].iman = 0;
2730 xhci->intr[i].imod = 0;
2731 xhci->intr[i].erstsz = 0;
2732 xhci->intr[i].erstba_low = 0;
2733 xhci->intr[i].erstba_high = 0;
2734 xhci->intr[i].erdp_low = 0;
2735 xhci->intr[i].erdp_high = 0;
2736
2737 xhci->intr[i].er_ep_idx = 0;
2738 xhci->intr[i].er_pcs = 1;
2739 xhci->intr[i].ev_buffer_put = 0;
2740 xhci->intr[i].ev_buffer_get = 0;
2741 }
2742
2743 xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
2744 xhci_mfwrap_update(xhci);
2745 }
2746
2747 static uint64_t xhci_cap_read(void *ptr, hwaddr reg, unsigned size)
2748 {
2749 XHCIState *xhci = ptr;
2750 uint32_t ret;
2751
2752 switch (reg) {
2753 case 0x00: /* HCIVERSION, CAPLENGTH */
2754 ret = 0x01000000 | LEN_CAP;
2755 break;
2756 case 0x04: /* HCSPARAMS 1 */
2757 ret = ((xhci->numports_2+xhci->numports_3)<<24)
2758 | (xhci->numintrs<<8) | xhci->numslots;
2759 break;
2760 case 0x08: /* HCSPARAMS 2 */
2761 ret = 0x0000000f;
2762 break;
2763 case 0x0c: /* HCSPARAMS 3 */
2764 ret = 0x00000000;
2765 break;
2766 case 0x10: /* HCCPARAMS */
2767 if (sizeof(dma_addr_t) == 4) {
2768 ret = 0x00080000 | (xhci->max_pstreams_mask << 12);
2769 } else {
2770 ret = 0x00080001 | (xhci->max_pstreams_mask << 12);
2771 }
2772 break;
2773 case 0x14: /* DBOFF */
2774 ret = OFF_DOORBELL;
2775 break;
2776 case 0x18: /* RTSOFF */
2777 ret = OFF_RUNTIME;
2778 break;
2779
2780 /* extended capabilities */
2781 case 0x20: /* Supported Protocol:00 */
2782 ret = 0x02000402; /* USB 2.0 */
2783 break;
2784 case 0x24: /* Supported Protocol:04 */
2785 ret = 0x20425355; /* "USB " */
2786 break;
2787 case 0x28: /* Supported Protocol:08 */
2788 ret = (xhci->numports_2 << 8) | (xhci->numports_3 + 1);
2789 break;
2790 case 0x2c: /* Supported Protocol:0c */
2791 ret = 0x00000000; /* reserved */
2792 break;
2793 case 0x30: /* Supported Protocol:00 */
2794 ret = 0x03000002; /* USB 3.0 */
2795 break;
2796 case 0x34: /* Supported Protocol:04 */
2797 ret = 0x20425355; /* "USB " */
2798 break;
2799 case 0x38: /* Supported Protocol:08 */
2800 ret = (xhci->numports_3 << 8) | 1;
2801 break;
2802 case 0x3c: /* Supported Protocol:0c */
2803 ret = 0x00000000; /* reserved */
2804 break;
2805 default:
2806 trace_usb_xhci_unimplemented("cap read", reg);
2807 ret = 0;
2808 }
2809
2810 trace_usb_xhci_cap_read(reg, ret);
2811 return ret;
2812 }
2813
2814 static uint64_t xhci_port_read(void *ptr, hwaddr reg, unsigned size)
2815 {
2816 XHCIPort *port = ptr;
2817 uint32_t ret;
2818
2819 switch (reg) {
2820 case 0x00: /* PORTSC */
2821 ret = port->portsc;
2822 break;
2823 case 0x04: /* PORTPMSC */
2824 case 0x08: /* PORTLI */
2825 ret = 0;
2826 break;
2827 case 0x0c: /* PORTHLPMC */
2828 ret = 0;
2829 qemu_log_mask(LOG_UNIMP, "%s: read from port register PORTHLPMC",
2830 __func__);
2831 break;
2832 default:
2833 qemu_log_mask(LOG_GUEST_ERROR,
2834 "%s: read from port offset 0x%" HWADDR_PRIx,
2835 __func__, reg);
2836 ret = 0;
2837 }
2838
2839 trace_usb_xhci_port_read(port->portnr, reg, ret);
2840 return ret;
2841 }
2842
2843 static void xhci_port_write(void *ptr, hwaddr reg,
2844 uint64_t val, unsigned size)
2845 {
2846 XHCIPort *port = ptr;
2847 uint32_t portsc, notify;
2848
2849 trace_usb_xhci_port_write(port->portnr, reg, val);
2850
2851 switch (reg) {
2852 case 0x00: /* PORTSC */
2853 /* write-1-to-start bits */
2854 if (val & PORTSC_WPR) {
2855 xhci_port_reset(port, true);
2856 break;
2857 }
2858 if (val & PORTSC_PR) {
2859 xhci_port_reset(port, false);
2860 break;
2861 }
2862
2863 portsc = port->portsc;
2864 notify = 0;
2865 /* write-1-to-clear bits*/
2866 portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC|
2867 PORTSC_PRC|PORTSC_PLC|PORTSC_CEC));
2868 if (val & PORTSC_LWS) {
2869 /* overwrite PLS only when LWS=1 */
2870 uint32_t old_pls = get_field(port->portsc, PORTSC_PLS);
2871 uint32_t new_pls = get_field(val, PORTSC_PLS);
2872 switch (new_pls) {
2873 case PLS_U0:
2874 if (old_pls != PLS_U0) {
2875 set_field(&portsc, new_pls, PORTSC_PLS);
2876 trace_usb_xhci_port_link(port->portnr, new_pls);
2877 notify = PORTSC_PLC;
2878 }
2879 break;
2880 case PLS_U3:
2881 if (old_pls < PLS_U3) {
2882 set_field(&portsc, new_pls, PORTSC_PLS);
2883 trace_usb_xhci_port_link(port->portnr, new_pls);
2884 }
2885 break;
2886 case PLS_RESUME:
2887 /* windows does this for some reason, don't spam stderr */
2888 break;
2889 default:
2890 DPRINTF("%s: ignore pls write (old %d, new %d)\n",
2891 __func__, old_pls, new_pls);
2892 break;
2893 }
2894 }
2895 /* read/write bits */
2896 portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE);
2897 portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE));
2898 port->portsc = portsc;
2899 if (notify) {
2900 xhci_port_notify(port, notify);
2901 }
2902 break;
2903 case 0x04: /* PORTPMSC */
2904 case 0x0c: /* PORTHLPMC */
2905 qemu_log_mask(LOG_UNIMP,
2906 "%s: write 0x%" PRIx64
2907 " (%u bytes) to port register at offset 0x%" HWADDR_PRIx,
2908 __func__, val, size, reg);
2909 break;
2910 case 0x08: /* PORTLI */
2911 qemu_log_mask(LOG_GUEST_ERROR, "%s: Write to read-only PORTLI register",
2912 __func__);
2913 break;
2914 default:
2915 qemu_log_mask(LOG_GUEST_ERROR,
2916 "%s: write 0x%" PRIx64 " (%u bytes) to unknown port "
2917 "register at offset 0x%" HWADDR_PRIx,
2918 __func__, val, size, reg);
2919 break;
2920 }
2921 }
2922
2923 static uint64_t xhci_oper_read(void *ptr, hwaddr reg, unsigned size)
2924 {
2925 XHCIState *xhci = ptr;
2926 uint32_t ret;
2927
2928 switch (reg) {
2929 case 0x00: /* USBCMD */
2930 ret = xhci->usbcmd;
2931 break;
2932 case 0x04: /* USBSTS */
2933 ret = xhci->usbsts;
2934 break;
2935 case 0x08: /* PAGESIZE */
2936 ret = 1; /* 4KiB */
2937 break;
2938 case 0x14: /* DNCTRL */
2939 ret = xhci->dnctrl;
2940 break;
2941 case 0x18: /* CRCR low */
2942 ret = xhci->crcr_low & ~0xe;
2943 break;
2944 case 0x1c: /* CRCR high */
2945 ret = xhci->crcr_high;
2946 break;
2947 case 0x30: /* DCBAAP low */
2948 ret = xhci->dcbaap_low;
2949 break;
2950 case 0x34: /* DCBAAP high */
2951 ret = xhci->dcbaap_high;
2952 break;
2953 case 0x38: /* CONFIG */
2954 ret = xhci->config;
2955 break;
2956 default:
2957 trace_usb_xhci_unimplemented("oper read", reg);
2958 ret = 0;
2959 }
2960
2961 trace_usb_xhci_oper_read(reg, ret);
2962 return ret;
2963 }
2964
2965 static void xhci_oper_write(void *ptr, hwaddr reg,
2966 uint64_t val, unsigned size)
2967 {
2968 XHCIState *xhci = XHCI(ptr);
2969
2970 trace_usb_xhci_oper_write(reg, val);
2971
2972 switch (reg) {
2973 case 0x00: /* USBCMD */
2974 if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) {
2975 xhci_run(xhci);
2976 } else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) {
2977 xhci_stop(xhci);
2978 }
2979 if (val & USBCMD_CSS) {
2980 /* save state */
2981 xhci->usbsts &= ~USBSTS_SRE;
2982 }
2983 if (val & USBCMD_CRS) {
2984 /* restore state */
2985 xhci->usbsts |= USBSTS_SRE;
2986 }
2987 xhci->usbcmd = val & 0xc0f;
2988 xhci_mfwrap_update(xhci);
2989 if (val & USBCMD_HCRST) {
2990 xhci_reset(DEVICE(xhci));
2991 }
2992 xhci_intr_update(xhci, 0);
2993 break;
2994
2995 case 0x04: /* USBSTS */
2996 /* these bits are write-1-to-clear */
2997 xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE));
2998 xhci_intr_update(xhci, 0);
2999 break;
3000
3001 case 0x14: /* DNCTRL */
3002 xhci->dnctrl = val & 0xffff;
3003 break;
3004 case 0x18: /* CRCR low */
3005 xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR);
3006 break;
3007 case 0x1c: /* CRCR high */
3008 xhci->crcr_high = val;
3009 if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) {
3010 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED};
3011 xhci->crcr_low &= ~CRCR_CRR;
3012 xhci_event(xhci, &event, 0);
3013 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low);
3014 } else {
3015 dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val);
3016 xhci_ring_init(xhci, &xhci->cmd_ring, base);
3017 }
3018 xhci->crcr_low &= ~(CRCR_CA | CRCR_CS);
3019 break;
3020 case 0x30: /* DCBAAP low */
3021 xhci->dcbaap_low = val & 0xffffffc0;
3022 break;
3023 case 0x34: /* DCBAAP high */
3024 xhci->dcbaap_high = val;
3025 break;
3026 case 0x38: /* CONFIG */
3027 xhci->config = val & 0xff;
3028 break;
3029 default:
3030 trace_usb_xhci_unimplemented("oper write", reg);
3031 }
3032 }
3033
3034 static uint64_t xhci_runtime_read(void *ptr, hwaddr reg,
3035 unsigned size)
3036 {
3037 XHCIState *xhci = ptr;
3038 uint32_t ret = 0;
3039
3040 if (reg < 0x20) {
3041 switch (reg) {
3042 case 0x00: /* MFINDEX */
3043 ret = xhci_mfindex_get(xhci) & 0x3fff;
3044 break;
3045 default:
3046 trace_usb_xhci_unimplemented("runtime read", reg);
3047 break;
3048 }
3049 } else {
3050 int v = (reg - 0x20) / 0x20;
3051
3052 if (v >= xhci->numintrs) {
3053 qemu_log_mask(LOG_GUEST_ERROR,
3054 "xhci: read from nonexistent interrupter %i\n", v);
3055 goto out_trace;
3056 }
3057 XHCIInterrupter *intr = &xhci->intr[v];
3058 switch (reg & 0x1f) {
3059 case 0x00: /* IMAN */
3060 ret = intr->iman;
3061 break;
3062 case 0x04: /* IMOD */
3063 ret = intr->imod;
3064 break;
3065 case 0x08: /* ERSTSZ */
3066 ret = intr->erstsz;
3067 break;
3068 case 0x10: /* ERSTBA low */
3069 ret = intr->erstba_low;
3070 break;
3071 case 0x14: /* ERSTBA high */
3072 ret = intr->erstba_high;
3073 break;
3074 case 0x18: /* ERDP low */
3075 ret = intr->erdp_low;
3076 break;
3077 case 0x1c: /* ERDP high */
3078 ret = intr->erdp_high;
3079 break;
3080 }
3081 }
3082
3083 out_trace:
3084 trace_usb_xhci_runtime_read(reg, ret);
3085 return ret;
3086 }
3087
3088 static void xhci_runtime_write(void *ptr, hwaddr reg,
3089 uint64_t val, unsigned size)
3090 {
3091 XHCIState *xhci = ptr;
3092 XHCIInterrupter *intr;
3093 int v;
3094
3095 trace_usb_xhci_runtime_write(reg, val);
3096
3097 if (reg < 0x20) {
3098 trace_usb_xhci_unimplemented("runtime write", reg);
3099 return;
3100 }
3101
3102 v = (reg - 0x20) / 0x20;
3103 if (v >= xhci->numintrs) {
3104 qemu_log_mask(LOG_GUEST_ERROR,
3105 "xhci: write to nonexistent interrupter %i\n", v);
3106 return;
3107 }
3108 intr = &xhci->intr[v];
3109
3110 switch (reg & 0x1f) {
3111 case 0x00: /* IMAN */
3112 if (val & IMAN_IP) {
3113 intr->iman &= ~IMAN_IP;
3114 }
3115 intr->iman &= ~IMAN_IE;
3116 intr->iman |= val & IMAN_IE;
3117 xhci_intr_update(xhci, v);
3118 break;
3119 case 0x04: /* IMOD */
3120 intr->imod = val;
3121 break;
3122 case 0x08: /* ERSTSZ */
3123 intr->erstsz = val & 0xffff;
3124 break;
3125 case 0x10: /* ERSTBA low */
3126 if (xhci->nec_quirks) {
3127 /* NEC driver bug: it doesn't align this to 64 bytes */
3128 intr->erstba_low = val & 0xfffffff0;
3129 } else {
3130 intr->erstba_low = val & 0xffffffc0;
3131 }
3132 break;
3133 case 0x14: /* ERSTBA high */
3134 intr->erstba_high = val;
3135 xhci_er_reset(xhci, v);
3136 break;
3137 case 0x18: /* ERDP low */
3138 if (val & ERDP_EHB) {
3139 intr->erdp_low &= ~ERDP_EHB;
3140 }
3141 intr->erdp_low = (val & ~ERDP_EHB) | (intr->erdp_low & ERDP_EHB);
3142 if (val & ERDP_EHB) {
3143 dma_addr_t erdp = xhci_addr64(intr->erdp_low, intr->erdp_high);
3144 unsigned int dp_idx = (erdp - intr->er_start) / TRB_SIZE;
3145 if (erdp >= intr->er_start &&
3146 erdp < (intr->er_start + TRB_SIZE * intr->er_size) &&
3147 dp_idx != intr->er_ep_idx) {
3148 xhci_intr_raise(xhci, v);
3149 }
3150 }
3151 break;
3152 case 0x1c: /* ERDP high */
3153 intr->erdp_high = val;
3154 break;
3155 default:
3156 trace_usb_xhci_unimplemented("oper write", reg);
3157 }
3158 }
3159
3160 static uint64_t xhci_doorbell_read(void *ptr, hwaddr reg,
3161 unsigned size)
3162 {
3163 /* doorbells always read as 0 */
3164 trace_usb_xhci_doorbell_read(reg, 0);
3165 return 0;
3166 }
3167
3168 static void xhci_doorbell_write(void *ptr, hwaddr reg,
3169 uint64_t val, unsigned size)
3170 {
3171 XHCIState *xhci = ptr;
3172 unsigned int epid, streamid;
3173
3174 trace_usb_xhci_doorbell_write(reg, val);
3175
3176 if (!xhci_running(xhci)) {
3177 DPRINTF("xhci: wrote doorbell while xHC stopped or paused\n");
3178 return;
3179 }
3180
3181 reg >>= 2;
3182
3183 if (reg == 0) {
3184 if (val == 0) {
3185 xhci_process_commands(xhci);
3186 } else {
3187 DPRINTF("xhci: bad doorbell 0 write: 0x%x\n",
3188 (uint32_t)val);
3189 }
3190 } else {
3191 epid = val & 0xff;
3192 streamid = (val >> 16) & 0xffff;
3193 if (reg > xhci->numslots) {
3194 DPRINTF("xhci: bad doorbell %d\n", (int)reg);
3195 } else if (epid == 0 || epid > 31) {
3196 DPRINTF("xhci: bad doorbell %d write: 0x%x\n",
3197 (int)reg, (uint32_t)val);
3198 } else {
3199 xhci_kick_ep(xhci, reg, epid, streamid);
3200 }
3201 }
3202 }
3203
3204 static void xhci_cap_write(void *opaque, hwaddr addr, uint64_t val,
3205 unsigned width)
3206 {
3207 /* nothing */
3208 }
3209
3210 static const MemoryRegionOps xhci_cap_ops = {
3211 .read = xhci_cap_read,
3212 .write = xhci_cap_write,
3213 .valid.min_access_size = 1,
3214 .valid.max_access_size = 4,
3215 .impl.min_access_size = 4,
3216 .impl.max_access_size = 4,
3217 .endianness = DEVICE_LITTLE_ENDIAN,
3218 };
3219
3220 static const MemoryRegionOps xhci_oper_ops = {
3221 .read = xhci_oper_read,
3222 .write = xhci_oper_write,
3223 .valid.min_access_size = 4,
3224 .valid.max_access_size = sizeof(dma_addr_t),
3225 .endianness = DEVICE_LITTLE_ENDIAN,
3226 };
3227
3228 static const MemoryRegionOps xhci_port_ops = {
3229 .read = xhci_port_read,
3230 .write = xhci_port_write,
3231 .valid.min_access_size = 4,
3232 .valid.max_access_size = 4,
3233 .endianness = DEVICE_LITTLE_ENDIAN,
3234 };
3235
3236 static const MemoryRegionOps xhci_runtime_ops = {
3237 .read = xhci_runtime_read,
3238 .write = xhci_runtime_write,
3239 .valid.min_access_size = 4,
3240 .valid.max_access_size = sizeof(dma_addr_t),
3241 .endianness = DEVICE_LITTLE_ENDIAN,
3242 };
3243
3244 static const MemoryRegionOps xhci_doorbell_ops = {
3245 .read = xhci_doorbell_read,
3246 .write = xhci_doorbell_write,
3247 .valid.min_access_size = 4,
3248 .valid.max_access_size = 4,
3249 .endianness = DEVICE_LITTLE_ENDIAN,
3250 };
3251
3252 static void xhci_attach(USBPort *usbport)
3253 {
3254 XHCIState *xhci = usbport->opaque;
3255 XHCIPort *port = xhci_lookup_port(xhci, usbport);
3256
3257 xhci_port_update(port, 0);
3258 }
3259
3260 static void xhci_detach(USBPort *usbport)
3261 {
3262 XHCIState *xhci = usbport->opaque;
3263 XHCIPort *port = xhci_lookup_port(xhci, usbport);
3264
3265 xhci_detach_slot(xhci, usbport);
3266 xhci_port_update(port, 1);
3267 }
3268
3269 static void xhci_wakeup(USBPort *usbport)
3270 {
3271 XHCIState *xhci = usbport->opaque;
3272 XHCIPort *port = xhci_lookup_port(xhci, usbport);
3273
3274 assert(port);
3275 if (get_field(port->portsc, PORTSC_PLS) != PLS_U3) {
3276 return;
3277 }
3278 set_field(&port->portsc, PLS_RESUME, PORTSC_PLS);
3279 xhci_port_notify(port, PORTSC_PLC);
3280 }
3281
3282 static void xhci_complete(USBPort *port, USBPacket *packet)
3283 {
3284 XHCITransfer *xfer = container_of(packet, XHCITransfer, packet);
3285
3286 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) {
3287 xhci_ep_nuke_one_xfer(xfer, 0);
3288 return;
3289 }
3290 xhci_try_complete_packet(xfer);
3291 xhci_kick_epctx(xfer->epctx, xfer->streamid);
3292 if (xfer->complete) {
3293 xhci_ep_free_xfer(xfer);
3294 }
3295 }
3296
3297 static void xhci_child_detach(USBPort *uport, USBDevice *child)
3298 {
3299 USBBus *bus = usb_bus_from_device(child);
3300 XHCIState *xhci = container_of(bus, XHCIState, bus);
3301
3302 xhci_detach_slot(xhci, child->port);
3303 }
3304
3305 static USBPortOps xhci_uport_ops = {
3306 .attach = xhci_attach,
3307 .detach = xhci_detach,
3308 .wakeup = xhci_wakeup,
3309 .complete = xhci_complete,
3310 .child_detach = xhci_child_detach,
3311 };
3312
3313 static int xhci_find_epid(USBEndpoint *ep)
3314 {
3315 if (ep->nr == 0) {
3316 return 1;
3317 }
3318 if (ep->pid == USB_TOKEN_IN) {
3319 return ep->nr * 2 + 1;
3320 } else {
3321 return ep->nr * 2;
3322 }
3323 }
3324
3325 static USBEndpoint *xhci_epid_to_usbep(XHCIEPContext *epctx)
3326 {
3327 USBPort *uport;
3328 uint32_t token;
3329
3330 if (!epctx) {
3331 return NULL;
3332 }
3333 uport = epctx->xhci->slots[epctx->slotid - 1].uport;
3334 if (!uport || !uport->dev) {
3335 return NULL;
3336 }
3337 token = (epctx->epid & 1) ? USB_TOKEN_IN : USB_TOKEN_OUT;
3338 return usb_ep_get(uport->dev, token, epctx->epid >> 1);
3339 }
3340
3341 static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep,
3342 unsigned int stream)
3343 {
3344 XHCIState *xhci = container_of(bus, XHCIState, bus);
3345 int slotid;
3346
3347 DPRINTF("%s\n", __func__);
3348 slotid = ep->dev->addr;
3349 if (slotid == 0 || slotid > xhci->numslots ||
3350 !xhci->slots[slotid - 1].enabled) {
3351 DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr);
3352 return;
3353 }
3354 xhci_kick_ep(xhci, slotid, xhci_find_epid(ep), stream);
3355 }
3356
3357 static USBBusOps xhci_bus_ops = {
3358 .wakeup_endpoint = xhci_wakeup_endpoint,
3359 };
3360
3361 static void usb_xhci_init(XHCIState *xhci)
3362 {
3363 XHCIPort *port;
3364 unsigned int i, usbports, speedmask;
3365
3366 xhci->usbsts = USBSTS_HCH;
3367
3368 if (xhci->numports_2 > XHCI_MAXPORTS_2) {
3369 xhci->numports_2 = XHCI_MAXPORTS_2;
3370 }
3371 if (xhci->numports_3 > XHCI_MAXPORTS_3) {
3372 xhci->numports_3 = XHCI_MAXPORTS_3;
3373 }
3374 usbports = MAX(xhci->numports_2, xhci->numports_3);
3375 xhci->numports = xhci->numports_2 + xhci->numports_3;
3376
3377 usb_bus_new(&xhci->bus, sizeof(xhci->bus), &xhci_bus_ops, xhci->hostOpaque);
3378
3379 for (i = 0; i < usbports; i++) {
3380 speedmask = 0;
3381 if (i < xhci->numports_2) {
3382 port = &xhci->ports[i + xhci->numports_3];
3383 port->portnr = i + 1 + xhci->numports_3;
3384 port->uport = &xhci->uports[i];
3385 port->speedmask =
3386 USB_SPEED_MASK_LOW |
3387 USB_SPEED_MASK_FULL |
3388 USB_SPEED_MASK_HIGH;
3389 assert(i < XHCI_MAXPORTS);
3390 snprintf(port->name, sizeof(port->name), "usb2 port #%d", i+1);
3391 speedmask |= port->speedmask;
3392 }
3393 if (i < xhci->numports_3) {
3394 port = &xhci->ports[i];
3395 port->portnr = i + 1;
3396 port->uport = &xhci->uports[i];
3397 port->speedmask = USB_SPEED_MASK_SUPER;
3398 assert(i < XHCI_MAXPORTS);
3399 snprintf(port->name, sizeof(port->name), "usb3 port #%d", i+1);
3400 speedmask |= port->speedmask;
3401 }
3402 usb_register_port(&xhci->bus, &xhci->uports[i], xhci, i,
3403 &xhci_uport_ops, speedmask);
3404 }
3405 }
3406
3407 static void usb_xhci_realize(DeviceState *dev, Error **errp)
3408 {
3409 int i;
3410
3411 XHCIState *xhci = XHCI(dev);
3412
3413 if (xhci->numintrs > XHCI_MAXINTRS) {
3414 xhci->numintrs = XHCI_MAXINTRS;
3415 }
3416 while (xhci->numintrs & (xhci->numintrs - 1)) { /* ! power of 2 */
3417 xhci->numintrs++;
3418 }
3419 if (xhci->numintrs < 1) {
3420 xhci->numintrs = 1;
3421 }
3422 if (xhci->numslots > XHCI_MAXSLOTS) {
3423 xhci->numslots = XHCI_MAXSLOTS;
3424 }
3425 if (xhci->numslots < 1) {
3426 xhci->numslots = 1;
3427 }
3428 if (xhci_get_flag(xhci, XHCI_FLAG_ENABLE_STREAMS)) {
3429 xhci->max_pstreams_mask = 7; /* == 256 primary streams */
3430 } else {
3431 xhci->max_pstreams_mask = 0;
3432 }
3433
3434 usb_xhci_init(xhci);
3435 xhci->mfwrap_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_mfwrap_timer, xhci);
3436
3437 memory_region_init(&xhci->mem, OBJECT(dev), "xhci", XHCI_LEN_REGS);
3438 memory_region_init_io(&xhci->mem_cap, OBJECT(dev), &xhci_cap_ops, xhci,
3439 "capabilities", LEN_CAP);
3440 memory_region_init_io(&xhci->mem_oper, OBJECT(dev), &xhci_oper_ops, xhci,
3441 "operational", 0x400);
3442 memory_region_init_io(&xhci->mem_runtime, OBJECT(dev), &xhci_runtime_ops,
3443 xhci, "runtime", LEN_RUNTIME);
3444 memory_region_init_io(&xhci->mem_doorbell, OBJECT(dev), &xhci_doorbell_ops,
3445 xhci, "doorbell", LEN_DOORBELL);
3446
3447 memory_region_add_subregion(&xhci->mem, 0, &xhci->mem_cap);
3448 memory_region_add_subregion(&xhci->mem, OFF_OPER, &xhci->mem_oper);
3449 memory_region_add_subregion(&xhci->mem, OFF_RUNTIME, &xhci->mem_runtime);
3450 memory_region_add_subregion(&xhci->mem, OFF_DOORBELL, &xhci->mem_doorbell);
3451
3452 for (i = 0; i < xhci->numports; i++) {
3453 XHCIPort *port = &xhci->ports[i];
3454 uint32_t offset = OFF_OPER + 0x400 + 0x10 * i;
3455 port->xhci = xhci;
3456 memory_region_init_io(&port->mem, OBJECT(dev), &xhci_port_ops, port,
3457 port->name, 0x10);
3458 memory_region_add_subregion(&xhci->mem, offset, &port->mem);
3459 }
3460 }
3461
3462 static void usb_xhci_unrealize(DeviceState *dev)
3463 {
3464 int i;
3465 XHCIState *xhci = XHCI(dev);
3466
3467 trace_usb_xhci_exit();
3468
3469 for (i = 0; i < xhci->numslots; i++) {
3470 xhci_disable_slot(xhci, i + 1);
3471 }
3472
3473 if (xhci->mfwrap_timer) {
3474 timer_free(xhci->mfwrap_timer);
3475 xhci->mfwrap_timer = NULL;
3476 }
3477
3478 memory_region_del_subregion(&xhci->mem, &xhci->mem_cap);
3479 memory_region_del_subregion(&xhci->mem, &xhci->mem_oper);
3480 memory_region_del_subregion(&xhci->mem, &xhci->mem_runtime);
3481 memory_region_del_subregion(&xhci->mem, &xhci->mem_doorbell);
3482
3483 for (i = 0; i < xhci->numports; i++) {
3484 XHCIPort *port = &xhci->ports[i];
3485 memory_region_del_subregion(&xhci->mem, &port->mem);
3486 }
3487
3488 usb_bus_release(&xhci->bus);
3489 }
3490
3491 static int usb_xhci_post_load(void *opaque, int version_id)
3492 {
3493 XHCIState *xhci = opaque;
3494 XHCISlot *slot;
3495 XHCIEPContext *epctx;
3496 dma_addr_t dcbaap, pctx;
3497 uint32_t slot_ctx[4];
3498 uint32_t ep_ctx[5];
3499 int slotid, epid, state;
3500 uint64_t addr;
3501
3502 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high);
3503
3504 for (slotid = 1; slotid <= xhci->numslots; slotid++) {
3505 slot = &xhci->slots[slotid-1];
3506 if (!slot->addressed) {
3507 continue;
3508 }
3509 ldq_le_dma(xhci->as, dcbaap + 8 * slotid, &addr, MEMTXATTRS_UNSPECIFIED);
3510 slot->ctx = xhci_mask64(addr);
3511
3512 xhci_dma_read_u32s(xhci, slot->ctx, slot_ctx, sizeof(slot_ctx));
3513 slot->uport = xhci_lookup_uport(xhci, slot_ctx);
3514 if (!slot->uport) {
3515 /* should not happen, but may trigger on guest bugs */
3516 slot->enabled = 0;
3517 slot->addressed = 0;
3518 continue;
3519 }
3520 assert(slot->uport && slot->uport->dev);
3521
3522 for (epid = 1; epid <= 31; epid++) {
3523 pctx = slot->ctx + 32 * epid;
3524 xhci_dma_read_u32s(xhci, pctx, ep_ctx, sizeof(ep_ctx));
3525 state = ep_ctx[0] & EP_STATE_MASK;
3526 if (state == EP_DISABLED) {
3527 continue;
3528 }
3529 epctx = xhci_alloc_epctx(xhci, slotid, epid);
3530 slot->eps[epid-1] = epctx;
3531 xhci_init_epctx(epctx, pctx, ep_ctx);
3532 epctx->state = state;
3533 if (state == EP_RUNNING) {
3534 /* kick endpoint after vmload is finished */
3535 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
3536 }
3537 }
3538 }
3539 return 0;
3540 }
3541
3542 static const VMStateDescription vmstate_xhci_ring = {
3543 .name = "xhci-ring",
3544 .version_id = 1,
3545 .fields = (const VMStateField[]) {
3546 VMSTATE_UINT64(dequeue, XHCIRing),
3547 VMSTATE_BOOL(ccs, XHCIRing),
3548 VMSTATE_END_OF_LIST()
3549 }
3550 };
3551
3552 static const VMStateDescription vmstate_xhci_port = {
3553 .name = "xhci-port",
3554 .version_id = 1,
3555 .fields = (const VMStateField[]) {
3556 VMSTATE_UINT32(portsc, XHCIPort),
3557 VMSTATE_END_OF_LIST()
3558 }
3559 };
3560
3561 static const VMStateDescription vmstate_xhci_slot = {
3562 .name = "xhci-slot",
3563 .version_id = 1,
3564 .fields = (const VMStateField[]) {
3565 VMSTATE_BOOL(enabled, XHCISlot),
3566 VMSTATE_BOOL(addressed, XHCISlot),
3567 VMSTATE_END_OF_LIST()
3568 }
3569 };
3570
3571 static const VMStateDescription vmstate_xhci_event = {
3572 .name = "xhci-event",
3573 .version_id = 1,
3574 .fields = (const VMStateField[]) {
3575 VMSTATE_UINT32(type, XHCIEvent),
3576 VMSTATE_UINT32(ccode, XHCIEvent),
3577 VMSTATE_UINT64(ptr, XHCIEvent),
3578 VMSTATE_UINT32(length, XHCIEvent),
3579 VMSTATE_UINT32(flags, XHCIEvent),
3580 VMSTATE_UINT8(slotid, XHCIEvent),
3581 VMSTATE_UINT8(epid, XHCIEvent),
3582 VMSTATE_END_OF_LIST()
3583 }
3584 };
3585
3586 static bool xhci_er_full(void *opaque, int version_id)
3587 {
3588 return false;
3589 }
3590
3591 static const VMStateDescription vmstate_xhci_intr = {
3592 .name = "xhci-intr",
3593 .version_id = 1,
3594 .fields = (const VMStateField[]) {
3595 /* registers */
3596 VMSTATE_UINT32(iman, XHCIInterrupter),
3597 VMSTATE_UINT32(imod, XHCIInterrupter),
3598 VMSTATE_UINT32(erstsz, XHCIInterrupter),
3599 VMSTATE_UINT32(erstba_low, XHCIInterrupter),
3600 VMSTATE_UINT32(erstba_high, XHCIInterrupter),
3601 VMSTATE_UINT32(erdp_low, XHCIInterrupter),
3602 VMSTATE_UINT32(erdp_high, XHCIInterrupter),
3603
3604 /* state */
3605 VMSTATE_BOOL(msix_used, XHCIInterrupter),
3606 VMSTATE_BOOL(er_pcs, XHCIInterrupter),
3607 VMSTATE_UINT64(er_start, XHCIInterrupter),
3608 VMSTATE_UINT32(er_size, XHCIInterrupter),
3609 VMSTATE_UINT32(er_ep_idx, XHCIInterrupter),
3610
3611 /* event queue (used if ring is full) */
3612 VMSTATE_BOOL(er_full_unused, XHCIInterrupter),
3613 VMSTATE_UINT32_TEST(ev_buffer_put, XHCIInterrupter, xhci_er_full),
3614 VMSTATE_UINT32_TEST(ev_buffer_get, XHCIInterrupter, xhci_er_full),
3615 VMSTATE_STRUCT_ARRAY_TEST(ev_buffer, XHCIInterrupter, EV_QUEUE,
3616 xhci_er_full, 1,
3617 vmstate_xhci_event, XHCIEvent),
3618
3619 VMSTATE_END_OF_LIST()
3620 }
3621 };
3622
3623 const VMStateDescription vmstate_xhci = {
3624 .name = "xhci-core",
3625 .version_id = 1,
3626 .post_load = usb_xhci_post_load,
3627 .fields = (const VMStateField[]) {
3628 VMSTATE_STRUCT_VARRAY_UINT32(ports, XHCIState, numports, 1,
3629 vmstate_xhci_port, XHCIPort),
3630 VMSTATE_STRUCT_VARRAY_UINT32(slots, XHCIState, numslots, 1,
3631 vmstate_xhci_slot, XHCISlot),
3632 VMSTATE_STRUCT_VARRAY_UINT32(intr, XHCIState, numintrs, 1,
3633 vmstate_xhci_intr, XHCIInterrupter),
3634
3635 /* Operational Registers */
3636 VMSTATE_UINT32(usbcmd, XHCIState),
3637 VMSTATE_UINT32(usbsts, XHCIState),
3638 VMSTATE_UINT32(dnctrl, XHCIState),
3639 VMSTATE_UINT32(crcr_low, XHCIState),
3640 VMSTATE_UINT32(crcr_high, XHCIState),
3641 VMSTATE_UINT32(dcbaap_low, XHCIState),
3642 VMSTATE_UINT32(dcbaap_high, XHCIState),
3643 VMSTATE_UINT32(config, XHCIState),
3644
3645 /* Runtime Registers & state */
3646 VMSTATE_INT64(mfindex_start, XHCIState),
3647 VMSTATE_TIMER_PTR(mfwrap_timer, XHCIState),
3648 VMSTATE_STRUCT(cmd_ring, XHCIState, 1, vmstate_xhci_ring, XHCIRing),
3649
3650 VMSTATE_END_OF_LIST()
3651 }
3652 };
3653
3654 static const Property xhci_properties[] = {
3655 DEFINE_PROP_BIT("streams", XHCIState, flags,
3656 XHCI_FLAG_ENABLE_STREAMS, true),
3657 DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4),
3658 DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4),
3659 DEFINE_PROP_LINK("host", XHCIState, hostOpaque, TYPE_DEVICE,
3660 DeviceState *),
3661 };
3662
3663 static void xhci_class_init(ObjectClass *klass, const void *data)
3664 {
3665 DeviceClass *dc = DEVICE_CLASS(klass);
3666
3667 dc->realize = usb_xhci_realize;
3668 dc->unrealize = usb_xhci_unrealize;
3669 device_class_set_legacy_reset(dc, xhci_reset);
3670 device_class_set_props(dc, xhci_properties);
3671 dc->user_creatable = false;
3672 }
3673
3674 static const TypeInfo xhci_info = {
3675 .name = TYPE_XHCI,
3676 .parent = TYPE_DEVICE,
3677 .instance_size = sizeof(XHCIState),
3678 .class_init = xhci_class_init,
3679 };
3680
3681 static void xhci_register_types(void)
3682 {
3683 type_register_static(&xhci_info);
3684 }
3685
3686 type_init(xhci_register_types)