| 1 | /* |
| 2 | * VMApple machine emulation |
| 3 | * |
| 4 | * Copyright © 2023 Amazon.com, Inc. or its affiliates. All Rights Reserved. |
| 5 | * |
| 6 | * This work is licensed under the terms of the GNU GPL, version 2 or later. |
| 7 | * See the COPYING file in the top-level directory. |
| 8 | * |
| 9 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 10 | * |
| 11 | * VMApple is the device model that the macOS built-in hypervisor called |
| 12 | * "Virtualization.framework" exposes to Apple Silicon macOS guests. The |
| 13 | * machine model in this file implements the same device model in QEMU, but |
| 14 | * does not use any code from Virtualization.Framework. |
| 15 | */ |
| 16 | |
| 17 | #include "qemu/osdep.h" |
| 18 | #include "qemu/bitops.h" |
| 19 | #include "qemu/datadir.h" |
| 20 | #include "qemu/error-report.h" |
| 21 | #include "qemu/guest-random.h" |
| 22 | #include "qemu/help-texts.h" |
| 23 | #include "qemu/log.h" |
| 24 | #include "qemu/module.h" |
| 25 | #include "qemu/option.h" |
| 26 | #include "qemu/units.h" |
| 27 | #include "monitor/qdev.h" |
| 28 | #include "hw/core/boards.h" |
| 29 | #include "hw/core/irq.h" |
| 30 | #include "hw/core/loader.h" |
| 31 | #include "hw/core/qdev-properties.h" |
| 32 | #include "hw/core/sysbus.h" |
| 33 | #include "hw/usb/usb.h" |
| 34 | #include "hw/arm/boot.h" |
| 35 | #include "hw/char/pl011.h" |
| 36 | #include "hw/intc/arm_gic.h" |
| 37 | #include "hw/intc/arm_gicv3_common.h" |
| 38 | #include "hw/misc/pvpanic.h" |
| 39 | #include "hw/pci-host/gpex.h" |
| 40 | #include "hw/usb/hcd-xhci-pci.h" |
| 41 | #include "hw/virtio/virtio-pci.h" |
| 42 | #include "hw/vmapple/vmapple.h" |
| 43 | #include "net/net.h" |
| 44 | #include "qapi/error.h" |
| 45 | #include "qapi/visitor.h" |
| 46 | #include "qapi/qapi-visit-common.h" |
| 47 | #include "qobject/qlist.h" |
| 48 | #include "standard-headers/linux/input.h" |
| 49 | #include "system/hvf.h" |
| 50 | #include "system/reset.h" |
| 51 | #include "system/runstate.h" |
| 52 | #include "system/system.h" |
| 53 | #include "target/arm/gtimer.h" |
| 54 | #include "target/arm/cpu.h" |
| 55 | |
| 56 | struct VMAppleMachineState { |
| 57 | MachineState parent; |
| 58 | |
| 59 | Notifier machine_done; |
| 60 | struct arm_boot_info bootinfo; |
| 61 | const MemMapEntry *memmap; |
| 62 | const int *irqmap; |
| 63 | DeviceState *gic; |
| 64 | DeviceState *cfg; |
| 65 | DeviceState *pvpanic; |
| 66 | Notifier powerdown_notifier; |
| 67 | PCIBus *bus; |
| 68 | MemoryRegion fw_mr; |
| 69 | MemoryRegion ecam_alias; |
| 70 | uint64_t uuid; |
| 71 | }; |
| 72 | |
| 73 | #define TYPE_VMAPPLE_MACHINE MACHINE_TYPE_NAME("vmapple") |
| 74 | OBJECT_DECLARE_SIMPLE_TYPE(VMAppleMachineState, VMAPPLE_MACHINE) |
| 75 | |
| 76 | /* Number of external interrupt lines to configure the GIC with */ |
| 77 | #define NUM_IRQS 256 |
| 78 | |
| 79 | enum { |
| 80 | VMAPPLE_FIRMWARE, |
| 81 | VMAPPLE_CONFIG, |
| 82 | VMAPPLE_MEM, |
| 83 | VMAPPLE_GIC_DIST, |
| 84 | VMAPPLE_GIC_REDIST, |
| 85 | VMAPPLE_UART, |
| 86 | VMAPPLE_RTC, |
| 87 | VMAPPLE_PCIE, |
| 88 | VMAPPLE_PCIE_MMIO, |
| 89 | VMAPPLE_PCIE_ECAM, |
| 90 | VMAPPLE_GPIO, |
| 91 | VMAPPLE_PVPANIC, |
| 92 | VMAPPLE_APV_GFX, |
| 93 | VMAPPLE_APV_IOSFC, |
| 94 | VMAPPLE_AES_1, |
| 95 | VMAPPLE_AES_2, |
| 96 | VMAPPLE_BDOOR, |
| 97 | VMAPPLE_MEMMAP_LAST, |
| 98 | }; |
| 99 | |
| 100 | static const MemMapEntry memmap[] = { |
| 101 | [VMAPPLE_FIRMWARE] = { 0x00100000, 0x00100000 }, |
| 102 | [VMAPPLE_CONFIG] = { 0x00400000, 0x00010000 }, |
| 103 | |
| 104 | [VMAPPLE_GIC_DIST] = { 0x10000000, 0x00010000 }, |
| 105 | [VMAPPLE_GIC_REDIST] = { 0x10010000, 0x00400000 }, |
| 106 | |
| 107 | [VMAPPLE_UART] = { 0x20010000, 0x00010000 }, |
| 108 | [VMAPPLE_RTC] = { 0x20050000, 0x00001000 }, |
| 109 | [VMAPPLE_GPIO] = { 0x20060000, 0x00001000 }, |
| 110 | [VMAPPLE_PVPANIC] = { 0x20070000, 0x00000002 }, |
| 111 | [VMAPPLE_BDOOR] = { 0x30000000, 0x00200000 }, |
| 112 | [VMAPPLE_APV_GFX] = { 0x30200000, 0x00010000 }, |
| 113 | [VMAPPLE_APV_IOSFC] = { 0x30210000, 0x00010000 }, |
| 114 | [VMAPPLE_AES_1] = { 0x30220000, 0x00004000 }, |
| 115 | [VMAPPLE_AES_2] = { 0x30230000, 0x00004000 }, |
| 116 | [VMAPPLE_PCIE_ECAM] = { 0x40000000, 0x10000000 }, |
| 117 | [VMAPPLE_PCIE_MMIO] = { 0x50000000, 0x1fff0000 }, |
| 118 | |
| 119 | /* Actual RAM size depends on configuration */ |
| 120 | [VMAPPLE_MEM] = { 0x70000000ULL, GiB}, |
| 121 | }; |
| 122 | |
| 123 | static const int irqmap[] = { |
| 124 | [VMAPPLE_UART] = 1, |
| 125 | [VMAPPLE_RTC] = 2, |
| 126 | [VMAPPLE_GPIO] = 0x5, |
| 127 | [VMAPPLE_APV_IOSFC] = 0x10, |
| 128 | [VMAPPLE_APV_GFX] = 0x11, |
| 129 | [VMAPPLE_AES_1] = 0x12, |
| 130 | [VMAPPLE_PCIE] = 0x20, |
| 131 | }; |
| 132 | |
| 133 | #define GPEX_NUM_IRQS 16 |
| 134 | |
| 135 | static void create_bdif(VMAppleMachineState *vms, MemoryRegion *mem) |
| 136 | { |
| 137 | DeviceState *bdif; |
| 138 | SysBusDevice *bdif_sb; |
| 139 | DriveInfo *di_aux = drive_get(IF_PFLASH, 0, 0); |
| 140 | DriveInfo *di_root = drive_get(IF_PFLASH, 0, 1); |
| 141 | |
| 142 | if (!di_aux) { |
| 143 | error_report("No AUX device. Please specify one as pflash drive."); |
| 144 | exit(1); |
| 145 | } |
| 146 | |
| 147 | if (!di_root) { |
| 148 | /* Fall back to the first IF_VIRTIO device as root device */ |
| 149 | di_root = drive_get(IF_VIRTIO, 0, 0); |
| 150 | } |
| 151 | |
| 152 | if (!di_root) { |
| 153 | error_report("No root device. Please specify one as virtio drive."); |
| 154 | exit(1); |
| 155 | } |
| 156 | |
| 157 | /* PV backdoor device */ |
| 158 | bdif = qdev_new(TYPE_VMAPPLE_BDIF); |
| 159 | bdif_sb = SYS_BUS_DEVICE(bdif); |
| 160 | sysbus_mmio_map(bdif_sb, 0, vms->memmap[VMAPPLE_BDOOR].base); |
| 161 | |
| 162 | qdev_prop_set_drive(DEVICE(bdif), "aux", blk_by_legacy_dinfo(di_aux)); |
| 163 | qdev_prop_set_drive(DEVICE(bdif), "root", blk_by_legacy_dinfo(di_root)); |
| 164 | |
| 165 | sysbus_realize_and_unref(bdif_sb, &error_fatal); |
| 166 | } |
| 167 | |
| 168 | static void create_pvpanic(VMAppleMachineState *vms, MemoryRegion *mem) |
| 169 | { |
| 170 | SysBusDevice *pvpanic; |
| 171 | |
| 172 | vms->pvpanic = qdev_new(TYPE_PVPANIC_MMIO_DEVICE); |
| 173 | pvpanic = SYS_BUS_DEVICE(vms->pvpanic); |
| 174 | sysbus_mmio_map(pvpanic, 0, vms->memmap[VMAPPLE_PVPANIC].base); |
| 175 | |
| 176 | sysbus_realize_and_unref(pvpanic, &error_fatal); |
| 177 | } |
| 178 | |
| 179 | static bool create_cfg(VMAppleMachineState *vms, MemoryRegion *mem, |
| 180 | Error **errp) |
| 181 | { |
| 182 | ERRP_GUARD(); |
| 183 | SysBusDevice *cfg; |
| 184 | MachineState *machine = MACHINE(vms); |
| 185 | uint32_t rnd = 1; |
| 186 | |
| 187 | vms->cfg = qdev_new(TYPE_VMAPPLE_CFG); |
| 188 | cfg = SYS_BUS_DEVICE(vms->cfg); |
| 189 | sysbus_mmio_map(cfg, 0, vms->memmap[VMAPPLE_CONFIG].base); |
| 190 | |
| 191 | qemu_guest_getrandom_nofail(&rnd, sizeof(rnd)); |
| 192 | |
| 193 | qdev_prop_set_uint32(vms->cfg, "nr-cpus", machine->smp.cpus); |
| 194 | qdev_prop_set_uint64(vms->cfg, "ecid", vms->uuid); |
| 195 | qdev_prop_set_uint64(vms->cfg, "ram-size", machine->ram_size); |
| 196 | qdev_prop_set_uint32(vms->cfg, "rnd", rnd); |
| 197 | |
| 198 | if (!sysbus_realize_and_unref(cfg, errp)) { |
| 199 | error_prepend(errp, "Error creating vmapple cfg device: "); |
| 200 | return false; |
| 201 | } |
| 202 | |
| 203 | return true; |
| 204 | } |
| 205 | |
| 206 | static void create_gfx(VMAppleMachineState *vms, MemoryRegion *mem) |
| 207 | { |
| 208 | int irq_gfx = vms->irqmap[VMAPPLE_APV_GFX]; |
| 209 | int irq_iosfc = vms->irqmap[VMAPPLE_APV_IOSFC]; |
| 210 | SysBusDevice *gfx; |
| 211 | |
| 212 | gfx = SYS_BUS_DEVICE(qdev_new("apple-gfx-mmio")); |
| 213 | sysbus_mmio_map(gfx, 0, vms->memmap[VMAPPLE_APV_GFX].base); |
| 214 | sysbus_mmio_map(gfx, 1, vms->memmap[VMAPPLE_APV_IOSFC].base); |
| 215 | sysbus_connect_irq(gfx, 0, qdev_get_gpio_in(vms->gic, irq_gfx)); |
| 216 | sysbus_connect_irq(gfx, 1, qdev_get_gpio_in(vms->gic, irq_iosfc)); |
| 217 | sysbus_realize_and_unref(gfx, &error_fatal); |
| 218 | } |
| 219 | |
| 220 | static void create_aes(VMAppleMachineState *vms, MemoryRegion *mem) |
| 221 | { |
| 222 | int irq = vms->irqmap[VMAPPLE_AES_1]; |
| 223 | SysBusDevice *aes; |
| 224 | |
| 225 | aes = SYS_BUS_DEVICE(qdev_new(TYPE_APPLE_AES)); |
| 226 | sysbus_mmio_map(aes, 0, vms->memmap[VMAPPLE_AES_1].base); |
| 227 | sysbus_mmio_map(aes, 1, vms->memmap[VMAPPLE_AES_2].base); |
| 228 | sysbus_connect_irq(aes, 0, qdev_get_gpio_in(vms->gic, irq)); |
| 229 | sysbus_realize_and_unref(aes, &error_fatal); |
| 230 | } |
| 231 | |
| 232 | static int arm_gic_ppi_index(int cpu_nr, int ppi_index) |
| 233 | { |
| 234 | return NUM_IRQS + cpu_nr * GIC_INTERNAL + ppi_index; |
| 235 | } |
| 236 | |
| 237 | static void create_gic(VMAppleMachineState *vms, MemoryRegion *mem) |
| 238 | { |
| 239 | MachineState *ms = MACHINE(vms); |
| 240 | /* We create a standalone GIC */ |
| 241 | SysBusDevice *gicbusdev; |
| 242 | QList *redist_region_count; |
| 243 | int i; |
| 244 | unsigned int smp_cpus = ms->smp.cpus; |
| 245 | |
| 246 | vms->gic = qdev_new(gicv3_class_name()); |
| 247 | qdev_prop_set_uint32(vms->gic, "revision", 3); |
| 248 | qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus); |
| 249 | /* |
| 250 | * Note that the num-irq property counts both internal and external |
| 251 | * interrupts; there are always 32 of the former (mandated by GIC spec). |
| 252 | */ |
| 253 | qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32); |
| 254 | |
| 255 | uint32_t redist0_capacity = |
| 256 | vms->memmap[VMAPPLE_GIC_REDIST].size / GICV3_REDIST_SIZE; |
| 257 | uint32_t redist0_count = MIN(smp_cpus, redist0_capacity); |
| 258 | |
| 259 | redist_region_count = qlist_new(); |
| 260 | qlist_append_int(redist_region_count, redist0_count); |
| 261 | qdev_prop_set_array(vms->gic, "redist-region-count", redist_region_count); |
| 262 | |
| 263 | gicbusdev = SYS_BUS_DEVICE(vms->gic); |
| 264 | sysbus_realize_and_unref(gicbusdev, &error_fatal); |
| 265 | sysbus_mmio_map(gicbusdev, 0, vms->memmap[VMAPPLE_GIC_DIST].base); |
| 266 | sysbus_mmio_map(gicbusdev, 1, vms->memmap[VMAPPLE_GIC_REDIST].base); |
| 267 | |
| 268 | /* |
| 269 | * Wire the outputs from each CPU's generic timer and the GICv3 |
| 270 | * maintenance interrupt signal to the appropriate GIC PPI inputs, |
| 271 | * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. |
| 272 | */ |
| 273 | for (i = 0; i < smp_cpus; i++) { |
| 274 | DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); |
| 275 | |
| 276 | /* Map the virt timer to PPI 27 */ |
| 277 | qdev_connect_gpio_out(cpudev, GTIMER_VIRT, |
| 278 | qdev_get_gpio_in(vms->gic, |
| 279 | arm_gic_ppi_index(i, 27))); |
| 280 | |
| 281 | /* Map the GIC IRQ and FIQ lines to CPU */ |
| 282 | sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); |
| 283 | sysbus_connect_irq(gicbusdev, i + smp_cpus, |
| 284 | qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); |
| 285 | } |
| 286 | } |
| 287 | |
| 288 | static void create_uart(const VMAppleMachineState *vms, int uart, |
| 289 | MemoryRegion *mem, Chardev *chr) |
| 290 | { |
| 291 | hwaddr base = vms->memmap[uart].base; |
| 292 | int irq = vms->irqmap[uart]; |
| 293 | DeviceState *dev = qdev_new(TYPE_PL011); |
| 294 | SysBusDevice *s = SYS_BUS_DEVICE(dev); |
| 295 | |
| 296 | qdev_prop_set_chr(dev, "chardev", chr); |
| 297 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
| 298 | memory_region_add_subregion(mem, base, |
| 299 | sysbus_mmio_get_region(s, 0)); |
| 300 | sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); |
| 301 | } |
| 302 | |
| 303 | static void create_rtc(const VMAppleMachineState *vms) |
| 304 | { |
| 305 | hwaddr base = vms->memmap[VMAPPLE_RTC].base; |
| 306 | int irq = vms->irqmap[VMAPPLE_RTC]; |
| 307 | |
| 308 | sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq)); |
| 309 | } |
| 310 | |
| 311 | static DeviceState *gpio_key_dev; |
| 312 | static void vmapple_powerdown_req(Notifier *n, void *opaque) |
| 313 | { |
| 314 | /* use gpio Pin 3 for power button event */ |
| 315 | qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); |
| 316 | } |
| 317 | |
| 318 | static void create_gpio_devices(const VMAppleMachineState *vms, int gpio, |
| 319 | MemoryRegion *mem) |
| 320 | { |
| 321 | DeviceState *pl061_dev; |
| 322 | hwaddr base = vms->memmap[gpio].base; |
| 323 | int irq = vms->irqmap[gpio]; |
| 324 | SysBusDevice *s; |
| 325 | |
| 326 | pl061_dev = qdev_new("pl061"); |
| 327 | /* Pull lines down to 0 if not driven by the PL061 */ |
| 328 | qdev_prop_set_uint8(pl061_dev, "pullups", 0); |
| 329 | qdev_prop_set_uint8(pl061_dev, "pulldowns", 0xff); |
| 330 | s = SYS_BUS_DEVICE(pl061_dev); |
| 331 | sysbus_realize_and_unref(s, &error_fatal); |
| 332 | memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0)); |
| 333 | sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); |
| 334 | gpio_key_dev = sysbus_create_simple("gpio-key", -1, |
| 335 | qdev_get_gpio_in(pl061_dev, 3)); |
| 336 | } |
| 337 | |
| 338 | static void vmapple_firmware_init(VMAppleMachineState *vms, |
| 339 | MemoryRegion *sysmem) |
| 340 | { |
| 341 | hwaddr size = vms->memmap[VMAPPLE_FIRMWARE].size; |
| 342 | hwaddr base = vms->memmap[VMAPPLE_FIRMWARE].base; |
| 343 | const char *bios_name; |
| 344 | int image_size; |
| 345 | char *fname; |
| 346 | |
| 347 | bios_name = MACHINE(vms)->firmware; |
| 348 | if (!bios_name) { |
| 349 | error_report("No firmware specified"); |
| 350 | exit(1); |
| 351 | } |
| 352 | |
| 353 | fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
| 354 | if (!fname) { |
| 355 | error_report("Could not find ROM image '%s'", bios_name); |
| 356 | exit(1); |
| 357 | } |
| 358 | |
| 359 | memory_region_init_ram(&vms->fw_mr, NULL, "firmware", size, &error_fatal); |
| 360 | image_size = load_image_mr(fname, &vms->fw_mr); |
| 361 | |
| 362 | g_free(fname); |
| 363 | if (image_size < 0) { |
| 364 | error_report("Could not load ROM image '%s'", bios_name); |
| 365 | exit(1); |
| 366 | } |
| 367 | |
| 368 | memory_region_add_subregion(get_system_memory(), base, &vms->fw_mr); |
| 369 | } |
| 370 | |
| 371 | static void create_pcie(VMAppleMachineState *vms) |
| 372 | { |
| 373 | hwaddr base_mmio = vms->memmap[VMAPPLE_PCIE_MMIO].base; |
| 374 | hwaddr size_mmio = vms->memmap[VMAPPLE_PCIE_MMIO].size; |
| 375 | hwaddr base_ecam = vms->memmap[VMAPPLE_PCIE_ECAM].base; |
| 376 | hwaddr size_ecam = vms->memmap[VMAPPLE_PCIE_ECAM].size; |
| 377 | int irq = vms->irqmap[VMAPPLE_PCIE]; |
| 378 | MemoryRegion *mmio_alias; |
| 379 | MemoryRegion *mmio_reg; |
| 380 | MemoryRegion *ecam_reg; |
| 381 | DeviceState *dev; |
| 382 | int i; |
| 383 | PCIHostState *pci; |
| 384 | DeviceState *usb_controller; |
| 385 | USBBus *usb_bus; |
| 386 | |
| 387 | dev = qdev_new(TYPE_GPEX_HOST); |
| 388 | qdev_prop_set_uint32(dev, "num-irqs", GPEX_NUM_IRQS); |
| 389 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
| 390 | |
| 391 | /* Map only the first size_ecam bytes of ECAM space */ |
| 392 | ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); |
| 393 | memory_region_init_alias(&vms->ecam_alias, OBJECT(dev), "pcie-ecam", |
| 394 | ecam_reg, 0, size_ecam); |
| 395 | memory_region_add_subregion(get_system_memory(), base_ecam, |
| 396 | &vms->ecam_alias); |
| 397 | |
| 398 | /* |
| 399 | * Map the MMIO window from [0x50000000-0x7fff0000] in PCI space into |
| 400 | * system address space at [0x50000000-0x7fff0000]. |
| 401 | */ |
| 402 | mmio_alias = g_new0(MemoryRegion, 1); |
| 403 | mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); |
| 404 | memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", |
| 405 | mmio_reg, base_mmio, size_mmio); |
| 406 | memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); |
| 407 | |
| 408 | for (i = 0; i < GPEX_NUM_IRQS; i++) { |
| 409 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, |
| 410 | qdev_get_gpio_in(vms->gic, irq + i)); |
| 411 | gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); |
| 412 | } |
| 413 | |
| 414 | pci = PCI_HOST_BRIDGE(dev); |
| 415 | vms->bus = pci->bus; |
| 416 | g_assert(vms->bus); |
| 417 | |
| 418 | while ((dev = qemu_create_nic_device("virtio-net-pci", true, NULL))) { |
| 419 | qdev_realize_and_unref(dev, BUS(vms->bus), &error_fatal); |
| 420 | } |
| 421 | |
| 422 | if (defaults_enabled()) { |
| 423 | usb_controller = qdev_new(TYPE_QEMU_XHCI); |
| 424 | qdev_realize_and_unref(usb_controller, BUS(pci->bus), &error_fatal); |
| 425 | |
| 426 | usb_bus = USB_BUS(object_resolve_type_unambiguous(TYPE_USB_BUS, |
| 427 | &error_fatal)); |
| 428 | usb_create_simple(usb_bus, "usb-kbd"); |
| 429 | usb_create_simple(usb_bus, "usb-tablet"); |
| 430 | } |
| 431 | } |
| 432 | |
| 433 | static void vmapple_reset(void *opaque) |
| 434 | { |
| 435 | VMAppleMachineState *vms = opaque; |
| 436 | hwaddr base = vms->memmap[VMAPPLE_FIRMWARE].base; |
| 437 | |
| 438 | cpu_set_pc(first_cpu, base); |
| 439 | } |
| 440 | |
| 441 | static void mach_vmapple_init(MachineState *machine) |
| 442 | { |
| 443 | VMAppleMachineState *vms = VMAPPLE_MACHINE(machine); |
| 444 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
| 445 | const CPUArchIdList *possible_cpus; |
| 446 | MemoryRegion *sysmem = get_system_memory(); |
| 447 | int n; |
| 448 | unsigned int smp_cpus = machine->smp.cpus; |
| 449 | unsigned int max_cpus = machine->smp.max_cpus; |
| 450 | |
| 451 | vms->memmap = memmap; |
| 452 | machine->usb = true; |
| 453 | |
| 454 | possible_cpus = mc->possible_cpu_arch_ids(machine); |
| 455 | assert(possible_cpus->len == max_cpus); |
| 456 | for (n = 0; n < possible_cpus->len; n++) { |
| 457 | Object *cpu; |
| 458 | CPUState *cs; |
| 459 | |
| 460 | if (n >= smp_cpus) { |
| 461 | break; |
| 462 | } |
| 463 | |
| 464 | cpu = object_new(possible_cpus->cpus[n].type); |
| 465 | object_property_set_int(cpu, "mp-affinity", |
| 466 | possible_cpus->cpus[n].arch_id, &error_fatal); |
| 467 | |
| 468 | cs = CPU(cpu); |
| 469 | cs->cpu_index = n; |
| 470 | |
| 471 | numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpu), |
| 472 | &error_fatal); |
| 473 | |
| 474 | if (object_property_find(cpu, "has_el3")) { |
| 475 | object_property_set_bool(cpu, "has_el3", false, &error_fatal); |
| 476 | } |
| 477 | if (object_property_find(cpu, "has_el2")) { |
| 478 | object_property_set_bool(cpu, "has_el2", false, &error_fatal); |
| 479 | } |
| 480 | object_property_set_int(cpu, "psci-conduit", QEMU_PSCI_CONDUIT_HVC, |
| 481 | &error_fatal); |
| 482 | |
| 483 | /* Secondary CPUs start in PSCI powered-down state */ |
| 484 | if (n > 0) { |
| 485 | object_property_set_bool(cpu, "start-powered-off", true, |
| 486 | &error_fatal); |
| 487 | } |
| 488 | |
| 489 | object_property_set_link(cpu, "memory", OBJECT(sysmem), &error_abort); |
| 490 | qdev_realize(DEVICE(cpu), NULL, &error_fatal); |
| 491 | object_unref(cpu); |
| 492 | } |
| 493 | |
| 494 | memory_region_add_subregion(sysmem, vms->memmap[VMAPPLE_MEM].base, |
| 495 | machine->ram); |
| 496 | |
| 497 | create_gic(vms, sysmem); |
| 498 | create_bdif(vms, sysmem); |
| 499 | create_pvpanic(vms, sysmem); |
| 500 | create_aes(vms, sysmem); |
| 501 | create_gfx(vms, sysmem); |
| 502 | create_uart(vms, VMAPPLE_UART, sysmem, serial_hd(0)); |
| 503 | create_rtc(vms); |
| 504 | create_pcie(vms); |
| 505 | |
| 506 | create_gpio_devices(vms, VMAPPLE_GPIO, sysmem); |
| 507 | |
| 508 | vmapple_firmware_init(vms, sysmem); |
| 509 | create_cfg(vms, sysmem, &error_fatal); |
| 510 | |
| 511 | /* connect powerdown request */ |
| 512 | vms->powerdown_notifier.notify = vmapple_powerdown_req; |
| 513 | qemu_register_powerdown_notifier(&vms->powerdown_notifier); |
| 514 | |
| 515 | vms->bootinfo.ram_size = machine->ram_size; |
| 516 | vms->bootinfo.board_id = -1; |
| 517 | vms->bootinfo.loader_start = vms->memmap[VMAPPLE_MEM].base; |
| 518 | vms->bootinfo.skip_dtb_autoload = true; |
| 519 | vms->bootinfo.firmware_loaded = true; |
| 520 | arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo); |
| 521 | |
| 522 | qemu_register_reset(vmapple_reset, vms); |
| 523 | } |
| 524 | |
| 525 | static CpuInstanceProperties |
| 526 | vmapple_cpu_index_to_props(MachineState *ms, unsigned cpu_index) |
| 527 | { |
| 528 | MachineClass *mc = MACHINE_GET_CLASS(ms); |
| 529 | const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); |
| 530 | |
| 531 | assert(cpu_index < possible_cpus->len); |
| 532 | return possible_cpus->cpus[cpu_index].props; |
| 533 | } |
| 534 | |
| 535 | |
| 536 | static int64_t vmapple_get_default_cpu_node_id(const MachineState *ms, int idx) |
| 537 | { |
| 538 | return idx % ms->numa_state->num_nodes; |
| 539 | } |
| 540 | |
| 541 | static const CPUArchIdList *vmapple_possible_cpu_arch_ids(MachineState *ms) |
| 542 | { |
| 543 | int n; |
| 544 | unsigned int max_cpus = ms->smp.max_cpus; |
| 545 | |
| 546 | if (ms->possible_cpus) { |
| 547 | assert(ms->possible_cpus->len == max_cpus); |
| 548 | return ms->possible_cpus; |
| 549 | } |
| 550 | |
| 551 | ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + |
| 552 | sizeof(CPUArchId) * max_cpus); |
| 553 | ms->possible_cpus->len = max_cpus; |
| 554 | for (n = 0; n < ms->possible_cpus->len; n++) { |
| 555 | ms->possible_cpus->cpus[n].type = ms->cpu_type; |
| 556 | ms->possible_cpus->cpus[n].arch_id = |
| 557 | arm_build_mp_affinity(n, GICV3_TARGETLIST_BITS); |
| 558 | ms->possible_cpus->cpus[n].props.has_thread_id = true; |
| 559 | ms->possible_cpus->cpus[n].props.thread_id = n; |
| 560 | } |
| 561 | return ms->possible_cpus; |
| 562 | } |
| 563 | |
| 564 | static GlobalProperty vmapple_compat_defaults[] = { |
| 565 | { TYPE_VIRTIO_PCI, "disable-legacy", "on" }, |
| 566 | /* |
| 567 | * macOS XHCI driver attempts to schedule events onto even rings 1 & 2 |
| 568 | * even when (as here) there is no MSI(-X) support. Disabling interrupter |
| 569 | * mapping in the XHCI controller works around the problem. |
| 570 | */ |
| 571 | { TYPE_XHCI_PCI, "conditional-intr-mapping", "on" }, |
| 572 | }; |
| 573 | |
| 574 | static void vmapple_machine_class_init(ObjectClass *oc, const void *data) |
| 575 | { |
| 576 | MachineClass *mc = MACHINE_CLASS(oc); |
| 577 | |
| 578 | mc->init = mach_vmapple_init; |
| 579 | mc->max_cpus = 32; |
| 580 | mc->block_default_type = IF_VIRTIO; |
| 581 | mc->no_cdrom = 1; |
| 582 | mc->pci_allow_0_address = true; |
| 583 | mc->minimum_page_bits = 12; |
| 584 | mc->possible_cpu_arch_ids = vmapple_possible_cpu_arch_ids; |
| 585 | mc->cpu_index_to_instance_props = vmapple_cpu_index_to_props; |
| 586 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("host"); |
| 587 | mc->get_default_cpu_node_id = vmapple_get_default_cpu_node_id; |
| 588 | mc->default_ram_id = "mach-vmapple.ram"; |
| 589 | mc->desc = "Apple aarch64 Virtual Machine"; |
| 590 | |
| 591 | compat_props_add(mc->compat_props, vmapple_compat_defaults, |
| 592 | G_N_ELEMENTS(vmapple_compat_defaults)); |
| 593 | } |
| 594 | |
| 595 | static void vmapple_instance_init(Object *obj) |
| 596 | { |
| 597 | VMAppleMachineState *vms = VMAPPLE_MACHINE(obj); |
| 598 | |
| 599 | vms->irqmap = irqmap; |
| 600 | |
| 601 | object_property_add_uint64_ptr(obj, "uuid", &vms->uuid, |
| 602 | OBJ_PROP_FLAG_READWRITE); |
| 603 | object_property_set_description(obj, "uuid", "Machine UUID (SDOM)"); |
| 604 | } |
| 605 | |
| 606 | static const TypeInfo vmapple_machine_info = { |
| 607 | .name = TYPE_VMAPPLE_MACHINE, |
| 608 | .parent = TYPE_MACHINE, |
| 609 | .instance_size = sizeof(VMAppleMachineState), |
| 610 | .class_init = vmapple_machine_class_init, |
| 611 | .instance_init = vmapple_instance_init, |
| 612 | }; |
| 613 | |
| 614 | static void machvmapple_machine_init(void) |
| 615 | { |
| 616 | type_register_static(&vmapple_machine_info); |
| 617 | } |
| 618 | type_init(machvmapple_machine_init); |
| 619 |