| 1 | /* |
| 2 | * graphics passthrough |
| 3 | */ |
| 4 | #include "qemu/osdep.h" |
| 5 | #include "qapi/error.h" |
| 6 | #include "hw/xen/xen_pt.h" |
| 7 | #include "hw/xen/xen_igd.h" |
| 8 | #include "xen-host-pci-device.h" |
| 9 | #include "system/physmem.h" |
| 10 | |
| 11 | static unsigned long igd_guest_opregion; |
| 12 | static unsigned long igd_host_opregion; |
| 13 | |
| 14 | #define XEN_PCI_INTEL_OPREGION_MASK 0xfff |
| 15 | |
| 16 | typedef struct VGARegion { |
| 17 | int type; /* Memory or port I/O */ |
| 18 | uint64_t guest_base_addr; |
| 19 | uint64_t machine_base_addr; |
| 20 | uint64_t size; /* size of the region */ |
| 21 | int rc; |
| 22 | } VGARegion; |
| 23 | |
| 24 | #define IORESOURCE_IO 0x00000100 |
| 25 | #define IORESOURCE_MEM 0x00000200 |
| 26 | |
| 27 | static struct VGARegion vga_args[] = { |
| 28 | { |
| 29 | .type = IORESOURCE_IO, |
| 30 | .guest_base_addr = 0x3B0, |
| 31 | .machine_base_addr = 0x3B0, |
| 32 | .size = 0xC, |
| 33 | .rc = -1, |
| 34 | }, |
| 35 | { |
| 36 | .type = IORESOURCE_IO, |
| 37 | .guest_base_addr = 0x3C0, |
| 38 | .machine_base_addr = 0x3C0, |
| 39 | .size = 0x20, |
| 40 | .rc = -1, |
| 41 | }, |
| 42 | { |
| 43 | .type = IORESOURCE_MEM, |
| 44 | .guest_base_addr = 0xa0000 >> XC_PAGE_SHIFT, |
| 45 | .machine_base_addr = 0xa0000 >> XC_PAGE_SHIFT, |
| 46 | .size = 0x20, |
| 47 | .rc = -1, |
| 48 | }, |
| 49 | }; |
| 50 | |
| 51 | /* |
| 52 | * register VGA resources for the domain with assigned gfx |
| 53 | */ |
| 54 | int xen_pt_register_vga_regions(XenHostPCIDevice *dev) |
| 55 | { |
| 56 | int i = 0; |
| 57 | |
| 58 | if (!is_igd_vga_passthrough(dev)) { |
| 59 | return 0; |
| 60 | } |
| 61 | |
| 62 | for (i = 0 ; i < ARRAY_SIZE(vga_args); i++) { |
| 63 | if (vga_args[i].type == IORESOURCE_IO) { |
| 64 | vga_args[i].rc = xc_domain_ioport_mapping(xen_xc, xen_domid, |
| 65 | vga_args[i].guest_base_addr, |
| 66 | vga_args[i].machine_base_addr, |
| 67 | vga_args[i].size, DPCI_ADD_MAPPING); |
| 68 | } else { |
| 69 | vga_args[i].rc = xc_domain_memory_mapping(xen_xc, xen_domid, |
| 70 | vga_args[i].guest_base_addr, |
| 71 | vga_args[i].machine_base_addr, |
| 72 | vga_args[i].size, DPCI_ADD_MAPPING); |
| 73 | } |
| 74 | |
| 75 | if (vga_args[i].rc) { |
| 76 | XEN_PT_ERR(NULL, "VGA %s mapping failed! (rc: %i)\n", |
| 77 | vga_args[i].type == IORESOURCE_IO ? "ioport" : "memory", |
| 78 | vga_args[i].rc); |
| 79 | return vga_args[i].rc; |
| 80 | } |
| 81 | } |
| 82 | |
| 83 | return 0; |
| 84 | } |
| 85 | |
| 86 | /* |
| 87 | * unregister VGA resources for the domain with assigned gfx |
| 88 | */ |
| 89 | int xen_pt_unregister_vga_regions(XenHostPCIDevice *dev) |
| 90 | { |
| 91 | int i = 0; |
| 92 | int ret = 0; |
| 93 | |
| 94 | if (!is_igd_vga_passthrough(dev)) { |
| 95 | return 0; |
| 96 | } |
| 97 | |
| 98 | for (i = 0 ; i < ARRAY_SIZE(vga_args); i++) { |
| 99 | if (vga_args[i].type == IORESOURCE_IO) { |
| 100 | vga_args[i].rc = xc_domain_ioport_mapping(xen_xc, xen_domid, |
| 101 | vga_args[i].guest_base_addr, |
| 102 | vga_args[i].machine_base_addr, |
| 103 | vga_args[i].size, DPCI_REMOVE_MAPPING); |
| 104 | } else { |
| 105 | vga_args[i].rc = xc_domain_memory_mapping(xen_xc, xen_domid, |
| 106 | vga_args[i].guest_base_addr, |
| 107 | vga_args[i].machine_base_addr, |
| 108 | vga_args[i].size, DPCI_REMOVE_MAPPING); |
| 109 | } |
| 110 | |
| 111 | if (vga_args[i].rc) { |
| 112 | XEN_PT_ERR(NULL, "VGA %s unmapping failed! (rc: %i)\n", |
| 113 | vga_args[i].type == IORESOURCE_IO ? "ioport" : "memory", |
| 114 | vga_args[i].rc); |
| 115 | return vga_args[i].rc; |
| 116 | } |
| 117 | } |
| 118 | |
| 119 | if (igd_guest_opregion) { |
| 120 | ret = xc_domain_memory_mapping(xen_xc, xen_domid, |
| 121 | (unsigned long)(igd_guest_opregion >> XC_PAGE_SHIFT), |
| 122 | (unsigned long)(igd_host_opregion >> XC_PAGE_SHIFT), |
| 123 | 3, |
| 124 | DPCI_REMOVE_MAPPING); |
| 125 | if (ret) { |
| 126 | return ret; |
| 127 | } |
| 128 | } |
| 129 | |
| 130 | return 0; |
| 131 | } |
| 132 | |
| 133 | static void *get_vgabios(XenPCIPassthroughState *s, int *size, |
| 134 | XenHostPCIDevice *dev) |
| 135 | { |
| 136 | return pci_assign_dev_load_option_rom(&s->dev, size, |
| 137 | dev->domain, dev->bus, |
| 138 | dev->dev, dev->func); |
| 139 | } |
| 140 | |
| 141 | /* Refer to Seabios. */ |
| 142 | struct rom_header { |
| 143 | uint16_t signature; |
| 144 | uint8_t size; |
| 145 | uint8_t initVector[4]; |
| 146 | uint8_t reserved[17]; |
| 147 | uint16_t pcioffset; |
| 148 | uint16_t pnpoffset; |
| 149 | } __attribute__((packed)); |
| 150 | |
| 151 | struct pci_data { |
| 152 | uint32_t signature; |
| 153 | uint16_t vendor; |
| 154 | uint16_t device; |
| 155 | uint16_t vitaldata; |
| 156 | uint16_t dlen; |
| 157 | uint8_t drevision; |
| 158 | uint8_t class_lo; |
| 159 | uint16_t class_hi; |
| 160 | uint16_t ilen; |
| 161 | uint16_t irevision; |
| 162 | uint8_t type; |
| 163 | uint8_t indicator; |
| 164 | uint16_t reserved; |
| 165 | } __attribute__((packed)); |
| 166 | |
| 167 | void xen_pt_setup_vga(XenPCIPassthroughState *s, XenHostPCIDevice *dev, |
| 168 | Error **errp) |
| 169 | { |
| 170 | unsigned char *bios = NULL; |
| 171 | struct rom_header *rom; |
| 172 | int bios_size; |
| 173 | char *c = NULL; |
| 174 | char checksum = 0; |
| 175 | uint32_t len = 0; |
| 176 | struct pci_data *pd = NULL; |
| 177 | |
| 178 | if (!is_igd_vga_passthrough(dev)) { |
| 179 | error_setg(errp, "Need to enable igd-passthrough"); |
| 180 | return; |
| 181 | } |
| 182 | |
| 183 | bios = get_vgabios(s, &bios_size, dev); |
| 184 | if (!bios) { |
| 185 | error_setg(errp, "VGA: Can't get VBIOS"); |
| 186 | return; |
| 187 | } |
| 188 | |
| 189 | if (bios_size < sizeof(struct rom_header)) { |
| 190 | error_setg(errp, "VGA: VBIOS image corrupt (too small)"); |
| 191 | return; |
| 192 | } |
| 193 | |
| 194 | /* Currently we fixed this address as a primary. */ |
| 195 | rom = (struct rom_header *)bios; |
| 196 | |
| 197 | if (rom->pcioffset + sizeof(struct pci_data) > bios_size) { |
| 198 | error_setg(errp, "VGA: VBIOS image corrupt (bad pcioffset field)"); |
| 199 | return; |
| 200 | } |
| 201 | |
| 202 | pd = (void *)(bios + (unsigned char)rom->pcioffset); |
| 203 | |
| 204 | /* We may need to fixup Device Identification. */ |
| 205 | if (pd->device != s->real_device.device_id) { |
| 206 | pd->device = s->real_device.device_id; |
| 207 | |
| 208 | len = rom->size * 512; |
| 209 | if (len > bios_size) { |
| 210 | error_setg(errp, "VGA: VBIOS image corrupt (bad size field)"); |
| 211 | return; |
| 212 | } |
| 213 | |
| 214 | /* Then adjust the bios checksum */ |
| 215 | for (c = (char *)bios; c < ((char *)bios + len); c++) { |
| 216 | checksum += *c; |
| 217 | } |
| 218 | if (checksum) { |
| 219 | bios[len - 1] -= checksum; |
| 220 | XEN_PT_LOG(&s->dev, "vga bios checksum is adjusted %x!\n", |
| 221 | checksum); |
| 222 | } |
| 223 | } |
| 224 | |
| 225 | /* Currently we fixed this address as a primary for legacy BIOS. */ |
| 226 | physical_memory_write(0xc0000, bios, bios_size); |
| 227 | } |
| 228 | |
| 229 | uint32_t igd_read_opregion(XenPCIPassthroughState *s) |
| 230 | { |
| 231 | uint32_t val = 0; |
| 232 | |
| 233 | if (!igd_guest_opregion) { |
| 234 | return val; |
| 235 | } |
| 236 | |
| 237 | val = igd_guest_opregion; |
| 238 | |
| 239 | XEN_PT_LOG(&s->dev, "Read opregion val=%x\n", val); |
| 240 | return val; |
| 241 | } |
| 242 | |
| 243 | #define XEN_PCI_INTEL_OPREGION_PAGES 0x3 |
| 244 | #define XEN_PCI_INTEL_OPREGION_ENABLE_ACCESSED 0x1 |
| 245 | void igd_write_opregion(XenPCIPassthroughState *s, uint32_t val) |
| 246 | { |
| 247 | int ret; |
| 248 | |
| 249 | if (igd_guest_opregion) { |
| 250 | XEN_PT_LOG(&s->dev, "opregion register already been set, ignoring %x\n", |
| 251 | val); |
| 252 | return; |
| 253 | } |
| 254 | |
| 255 | /* We just work with LE. */ |
| 256 | xen_host_pci_get_block(&s->real_device, XEN_PCI_INTEL_OPREGION, |
| 257 | (uint8_t *)&igd_host_opregion, 4); |
| 258 | igd_guest_opregion = (unsigned long)(val & ~XEN_PCI_INTEL_OPREGION_MASK) |
| 259 | | (igd_host_opregion & XEN_PCI_INTEL_OPREGION_MASK); |
| 260 | |
| 261 | ret = xc_domain_iomem_permission(xen_xc, xen_domid, |
| 262 | (unsigned long)(igd_host_opregion >> XC_PAGE_SHIFT), |
| 263 | XEN_PCI_INTEL_OPREGION_PAGES, |
| 264 | XEN_PCI_INTEL_OPREGION_ENABLE_ACCESSED); |
| 265 | |
| 266 | if (ret) { |
| 267 | XEN_PT_ERR(&s->dev, "[%d]:Can't enable to access IGD host opregion:" |
| 268 | " 0x%lx.\n", ret, |
| 269 | (unsigned long)(igd_host_opregion >> XC_PAGE_SHIFT)), |
| 270 | igd_guest_opregion = 0; |
| 271 | return; |
| 272 | } |
| 273 | |
| 274 | ret = xc_domain_memory_mapping(xen_xc, xen_domid, |
| 275 | (unsigned long)(igd_guest_opregion >> XC_PAGE_SHIFT), |
| 276 | (unsigned long)(igd_host_opregion >> XC_PAGE_SHIFT), |
| 277 | XEN_PCI_INTEL_OPREGION_PAGES, |
| 278 | DPCI_ADD_MAPPING); |
| 279 | |
| 280 | if (ret) { |
| 281 | XEN_PT_ERR(&s->dev, "[%d]:Can't map IGD host opregion:0x%lx to" |
| 282 | " guest opregion:0x%lx.\n", ret, |
| 283 | (unsigned long)(igd_host_opregion >> XC_PAGE_SHIFT), |
| 284 | (unsigned long)(igd_guest_opregion >> XC_PAGE_SHIFT)); |
| 285 | igd_guest_opregion = 0; |
| 286 | return; |
| 287 | } |
| 288 | |
| 289 | XEN_PT_LOG(&s->dev, "Map OpRegion: 0x%lx -> 0x%lx\n", |
| 290 | (unsigned long)(igd_host_opregion >> XC_PAGE_SHIFT), |
| 291 | (unsigned long)(igd_guest_opregion >> XC_PAGE_SHIFT)); |
| 292 | } |
| 293 | |
| 294 | typedef struct { |
| 295 | uint16_t gpu_device_id; |
| 296 | uint16_t pch_device_id; |
| 297 | uint8_t pch_revision_id; |
| 298 | } IGDDeviceIDInfo; |
| 299 | |
| 300 | /* |
| 301 | * In real world different GPU should have different PCH. But actually |
| 302 | * the different PCH DIDs likely map to different PCH SKUs. We do the |
| 303 | * same thing for the GPU. For PCH, the different SKUs are going to be |
| 304 | * all the same silicon design and implementation, just different |
| 305 | * features turn on and off with fuses. The SW interfaces should be |
| 306 | * consistent across all SKUs in a given family (eg LPT). But just same |
| 307 | * features may not be supported. |
| 308 | * |
| 309 | * Most of these different PCH features probably don't matter to the |
| 310 | * Gfx driver, but obviously any difference in display port connections |
| 311 | * will so it should be fine with any PCH in case of passthrough. |
| 312 | * |
| 313 | * So currently use one PCH version, 0x8c4e, to cover all HSW(Haswell) |
| 314 | * scenarios, 0x9cc3 for BDW(Broadwell). |
| 315 | */ |
| 316 | static const IGDDeviceIDInfo igd_combo_id_infos[] = { |
| 317 | /* HSW Classic */ |
| 318 | {0x0402, 0x8c4e, 0x04}, /* HSWGT1D, HSWD_w7 */ |
| 319 | {0x0406, 0x8c4e, 0x04}, /* HSWGT1M, HSWM_w7 */ |
| 320 | {0x0412, 0x8c4e, 0x04}, /* HSWGT2D, HSWD_w7 */ |
| 321 | {0x0416, 0x8c4e, 0x04}, /* HSWGT2M, HSWM_w7 */ |
| 322 | {0x041E, 0x8c4e, 0x04}, /* HSWGT15D, HSWD_w7 */ |
| 323 | /* HSW ULT */ |
| 324 | {0x0A06, 0x8c4e, 0x04}, /* HSWGT1UT, HSWM_w7 */ |
| 325 | {0x0A16, 0x8c4e, 0x04}, /* HSWGT2UT, HSWM_w7 */ |
| 326 | {0x0A26, 0x8c4e, 0x06}, /* HSWGT3UT, HSWM_w7 */ |
| 327 | {0x0A2E, 0x8c4e, 0x04}, /* HSWGT3UT28W, HSWM_w7 */ |
| 328 | {0x0A1E, 0x8c4e, 0x04}, /* HSWGT2UX, HSWM_w7 */ |
| 329 | {0x0A0E, 0x8c4e, 0x04}, /* HSWGT1ULX, HSWM_w7 */ |
| 330 | /* HSW CRW */ |
| 331 | {0x0D26, 0x8c4e, 0x04}, /* HSWGT3CW, HSWM_w7 */ |
| 332 | {0x0D22, 0x8c4e, 0x04}, /* HSWGT3CWDT, HSWD_w7 */ |
| 333 | /* HSW Server */ |
| 334 | {0x041A, 0x8c4e, 0x04}, /* HSWSVGT2, HSWD_w7 */ |
| 335 | /* HSW SRVR */ |
| 336 | {0x040A, 0x8c4e, 0x04}, /* HSWSVGT1, HSWD_w7 */ |
| 337 | /* BSW */ |
| 338 | {0x1606, 0x9cc3, 0x03}, /* BDWULTGT1, BDWM_w7 */ |
| 339 | {0x1616, 0x9cc3, 0x03}, /* BDWULTGT2, BDWM_w7 */ |
| 340 | {0x1626, 0x9cc3, 0x03}, /* BDWULTGT3, BDWM_w7 */ |
| 341 | {0x160E, 0x9cc3, 0x03}, /* BDWULXGT1, BDWM_w7 */ |
| 342 | {0x161E, 0x9cc3, 0x03}, /* BDWULXGT2, BDWM_w7 */ |
| 343 | {0x1602, 0x9cc3, 0x03}, /* BDWHALOGT1, BDWM_w7 */ |
| 344 | {0x1612, 0x9cc3, 0x03}, /* BDWHALOGT2, BDWM_w7 */ |
| 345 | {0x1622, 0x9cc3, 0x03}, /* BDWHALOGT3, BDWM_w7 */ |
| 346 | {0x162B, 0x9cc3, 0x03}, /* BDWHALO28W, BDWM_w7 */ |
| 347 | {0x162A, 0x9cc3, 0x03}, /* BDWGT3WRKS, BDWM_w7 */ |
| 348 | {0x162D, 0x9cc3, 0x03}, /* BDWGT3SRVR, BDWM_w7 */ |
| 349 | }; |
| 350 | |
| 351 | static void isa_bridge_class_init(ObjectClass *klass, const void *data) |
| 352 | { |
| 353 | DeviceClass *dc = DEVICE_CLASS(klass); |
| 354 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
| 355 | |
| 356 | dc->desc = "ISA bridge faked to support IGD PT"; |
| 357 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
| 358 | k->vendor_id = PCI_VENDOR_ID_INTEL; |
| 359 | k->class_id = PCI_CLASS_BRIDGE_ISA; |
| 360 | }; |
| 361 | |
| 362 | static const TypeInfo isa_bridge_info = { |
| 363 | .name = "igd-passthrough-isa-bridge", |
| 364 | .parent = TYPE_PCI_DEVICE, |
| 365 | .instance_size = sizeof(PCIDevice), |
| 366 | .class_init = isa_bridge_class_init, |
| 367 | .interfaces = (const InterfaceInfo[]) { |
| 368 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, |
| 369 | { }, |
| 370 | }, |
| 371 | }; |
| 372 | |
| 373 | static void pt_graphics_register_types(void) |
| 374 | { |
| 375 | type_register_static(&isa_bridge_info); |
| 376 | } |
| 377 | type_init(pt_graphics_register_types) |
| 378 | |
| 379 | void xen_igd_passthrough_isa_bridge_create(XenPCIPassthroughState *s, |
| 380 | XenHostPCIDevice *dev) |
| 381 | { |
| 382 | PCIBus *bus = pci_get_bus(&s->dev); |
| 383 | struct PCIDevice *bridge_dev; |
| 384 | int i, num; |
| 385 | const uint16_t gpu_dev_id = dev->device_id; |
| 386 | uint16_t pch_dev_id = 0xffff; |
| 387 | uint8_t pch_rev_id = 0; |
| 388 | |
| 389 | num = ARRAY_SIZE(igd_combo_id_infos); |
| 390 | for (i = 0; i < num; i++) { |
| 391 | if (gpu_dev_id == igd_combo_id_infos[i].gpu_device_id) { |
| 392 | pch_dev_id = igd_combo_id_infos[i].pch_device_id; |
| 393 | pch_rev_id = igd_combo_id_infos[i].pch_revision_id; |
| 394 | } |
| 395 | } |
| 396 | |
| 397 | if (pch_dev_id == 0xffff) { |
| 398 | return; |
| 399 | } |
| 400 | |
| 401 | /* Currently IGD drivers always need to access PCH by 1f.0. */ |
| 402 | bridge_dev = pci_create_simple(bus, PCI_DEVFN(0x1f, 0), |
| 403 | "igd-passthrough-isa-bridge"); |
| 404 | |
| 405 | /* |
| 406 | * Note that vendor id is always PCI_VENDOR_ID_INTEL. |
| 407 | */ |
| 408 | if (!bridge_dev) { |
| 409 | fprintf(stderr, "set igd-passthrough-isa-bridge failed!\n"); |
| 410 | return; |
| 411 | } |
| 412 | pci_config_set_device_id(bridge_dev->config, pch_dev_id); |
| 413 | pci_config_set_revision(bridge_dev->config, pch_rev_id); |
| 414 | } |