| 1 | /* |
| 2 | * Copyright (c) 2007, Intel Corporation. |
| 3 | * |
| 4 | * This work is licensed under the terms of the GNU GPL, version 2. See |
| 5 | * the COPYING file in the top-level directory. |
| 6 | * |
| 7 | * Jiang Yunhong <yunhong.jiang@intel.com> |
| 8 | * |
| 9 | * This file implements direct PCI assignment to a HVM guest |
| 10 | */ |
| 11 | |
| 12 | #include "qemu/osdep.h" |
| 13 | |
| 14 | #include "hw/i386/apic-msidef.h" |
| 15 | #include "xen_pt.h" |
| 16 | #include "hw/xen/xen-legacy-backend.h" |
| 17 | |
| 18 | |
| 19 | #define XEN_PT_AUTO_ASSIGN -1 |
| 20 | |
| 21 | /* shift count for gflags */ |
| 22 | #define XEN_PT_GFLAGS_SHIFT_DEST_ID 0 |
| 23 | #define XEN_PT_GFLAGS_SHIFT_RH 8 |
| 24 | #define XEN_PT_GFLAGS_SHIFT_DM 9 |
| 25 | #define XEN_PT_GFLAGSSHIFT_DELIV_MODE 12 |
| 26 | #define XEN_PT_GFLAGSSHIFT_TRG_MODE 15 |
| 27 | #define XEN_PT_GFLAGSSHIFT_UNMASKED 16 |
| 28 | |
| 29 | #define latch(fld) latch[PCI_MSIX_ENTRY_##fld / sizeof(uint32_t)] |
| 30 | |
| 31 | /* |
| 32 | * Helpers |
| 33 | */ |
| 34 | |
| 35 | static inline uint8_t msi_vector(uint32_t data) |
| 36 | { |
| 37 | return (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT; |
| 38 | } |
| 39 | |
| 40 | static inline uint8_t msi_dest_id(uint32_t addr) |
| 41 | { |
| 42 | return (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT; |
| 43 | } |
| 44 | |
| 45 | static inline uint32_t msi_ext_dest_id(uint32_t addr_hi) |
| 46 | { |
| 47 | return addr_hi & 0xffffff00; |
| 48 | } |
| 49 | |
| 50 | static uint32_t msi_gflags(uint32_t data, uint64_t addr) |
| 51 | { |
| 52 | uint32_t result = 0; |
| 53 | int rh, dm, dest_id, deliv_mode, trig_mode; |
| 54 | |
| 55 | rh = (addr >> MSI_ADDR_REDIRECTION_SHIFT) & 0x1; |
| 56 | dm = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1; |
| 57 | dest_id = msi_dest_id(addr); |
| 58 | deliv_mode = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7; |
| 59 | trig_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1; |
| 60 | |
| 61 | result = dest_id | (rh << XEN_PT_GFLAGS_SHIFT_RH) |
| 62 | | (dm << XEN_PT_GFLAGS_SHIFT_DM) |
| 63 | | (deliv_mode << XEN_PT_GFLAGSSHIFT_DELIV_MODE) |
| 64 | | (trig_mode << XEN_PT_GFLAGSSHIFT_TRG_MODE); |
| 65 | |
| 66 | return result; |
| 67 | } |
| 68 | |
| 69 | static inline uint64_t msi_addr64(XenPTMSI *msi) |
| 70 | { |
| 71 | return (uint64_t)msi->addr_hi << 32 | msi->addr_lo; |
| 72 | } |
| 73 | |
| 74 | static int msi_msix_enable(XenPCIPassthroughState *s, |
| 75 | uint32_t address, |
| 76 | uint16_t flag, |
| 77 | bool enable) |
| 78 | { |
| 79 | uint16_t val = 0; |
| 80 | int rc; |
| 81 | |
| 82 | if (!address) { |
| 83 | return -1; |
| 84 | } |
| 85 | |
| 86 | rc = xen_host_pci_get_word(&s->real_device, address, &val); |
| 87 | if (rc) { |
| 88 | XEN_PT_ERR(&s->dev, "Failed to read MSI/MSI-X register (0x%x), rc:%d\n", |
| 89 | address, rc); |
| 90 | return rc; |
| 91 | } |
| 92 | if (enable) { |
| 93 | val |= flag; |
| 94 | } else { |
| 95 | val &= ~flag; |
| 96 | } |
| 97 | rc = xen_host_pci_set_word(&s->real_device, address, val); |
| 98 | if (rc) { |
| 99 | XEN_PT_ERR(&s->dev, "Failed to write MSI/MSI-X register (0x%x), rc:%d\n", |
| 100 | address, rc); |
| 101 | } |
| 102 | return rc; |
| 103 | } |
| 104 | |
| 105 | static int msi_msix_setup(XenPCIPassthroughState *s, |
| 106 | uint64_t addr, |
| 107 | uint32_t data, |
| 108 | int *ppirq, |
| 109 | bool is_msix, |
| 110 | int msix_entry, |
| 111 | bool is_not_mapped) |
| 112 | { |
| 113 | uint8_t gvec = msi_vector(data); |
| 114 | int rc = 0; |
| 115 | |
| 116 | assert((!is_msix && msix_entry == 0) || is_msix); |
| 117 | |
| 118 | if (xen_is_pirq_msi(data)) { |
| 119 | *ppirq = msi_ext_dest_id(addr >> 32) | msi_dest_id(addr); |
| 120 | if (!*ppirq) { |
| 121 | /* this probably identifies an misconfiguration of the guest, |
| 122 | * try the emulated path */ |
| 123 | *ppirq = XEN_PT_UNASSIGNED_PIRQ; |
| 124 | } else { |
| 125 | XEN_PT_LOG(&s->dev, "requested pirq %d for MSI%s" |
| 126 | " (vec: 0x%x, entry: 0x%x)\n", |
| 127 | *ppirq, is_msix ? "-X" : "", gvec, msix_entry); |
| 128 | } |
| 129 | } |
| 130 | |
| 131 | if (is_not_mapped) { |
| 132 | uint64_t table_base = 0; |
| 133 | |
| 134 | if (is_msix) { |
| 135 | table_base = s->msix->table_base; |
| 136 | } |
| 137 | |
| 138 | rc = xc_physdev_map_pirq_msi(xen_xc, xen_domid, XEN_PT_AUTO_ASSIGN, |
| 139 | ppirq, PCI_DEVFN(s->real_device.dev, |
| 140 | s->real_device.func), |
| 141 | ((uint32_t)s->real_device.domain << 16) | |
| 142 | s->real_device.bus, |
| 143 | msix_entry, table_base); |
| 144 | if (rc) { |
| 145 | XEN_PT_ERR(&s->dev, |
| 146 | "Mapping of MSI%s (err: %i, vec: 0x%x, entry 0x%x)\n", |
| 147 | is_msix ? "-X" : "", errno, gvec, msix_entry); |
| 148 | return rc; |
| 149 | } |
| 150 | } |
| 151 | |
| 152 | return 0; |
| 153 | } |
| 154 | static int msi_msix_update(XenPCIPassthroughState *s, |
| 155 | uint64_t addr, |
| 156 | uint32_t data, |
| 157 | int pirq, |
| 158 | bool is_msix, |
| 159 | int msix_entry, |
| 160 | int *old_pirq, |
| 161 | bool masked) |
| 162 | { |
| 163 | PCIDevice *d = &s->dev; |
| 164 | uint8_t gvec = msi_vector(data); |
| 165 | uint32_t gflags = msi_gflags(data, addr); |
| 166 | int rc = 0; |
| 167 | uint64_t table_addr = 0; |
| 168 | |
| 169 | XEN_PT_LOG(d, "Updating MSI%s with pirq %d gvec 0x%x gflags 0x%x" |
| 170 | " (entry: 0x%x)\n", |
| 171 | is_msix ? "-X" : "", pirq, gvec, gflags, msix_entry); |
| 172 | |
| 173 | if (is_msix) { |
| 174 | table_addr = s->msix->mmio_base_addr; |
| 175 | } |
| 176 | |
| 177 | gflags |= masked ? 0 : (1u << XEN_PT_GFLAGSSHIFT_UNMASKED); |
| 178 | |
| 179 | rc = xc_domain_update_msi_irq(xen_xc, xen_domid, gvec, |
| 180 | pirq, gflags, table_addr); |
| 181 | |
| 182 | if (rc) { |
| 183 | XEN_PT_ERR(d, "Updating of MSI%s failed. (err: %d)\n", |
| 184 | is_msix ? "-X" : "", errno); |
| 185 | |
| 186 | if (xc_physdev_unmap_pirq(xen_xc, xen_domid, *old_pirq)) { |
| 187 | XEN_PT_ERR(d, "Unmapping of MSI%s pirq %d failed. (err: %d)\n", |
| 188 | is_msix ? "-X" : "", *old_pirq, errno); |
| 189 | } |
| 190 | *old_pirq = XEN_PT_UNASSIGNED_PIRQ; |
| 191 | } |
| 192 | return rc; |
| 193 | } |
| 194 | |
| 195 | static int msi_msix_disable(XenPCIPassthroughState *s, |
| 196 | uint64_t addr, |
| 197 | uint32_t data, |
| 198 | int pirq, |
| 199 | bool is_msix, |
| 200 | bool is_binded) |
| 201 | { |
| 202 | PCIDevice *d = &s->dev; |
| 203 | uint8_t gvec = msi_vector(data); |
| 204 | uint32_t gflags = msi_gflags(data, addr); |
| 205 | int rc = 0; |
| 206 | |
| 207 | if (pirq == XEN_PT_UNASSIGNED_PIRQ) { |
| 208 | return 0; |
| 209 | } |
| 210 | |
| 211 | if (is_binded) { |
| 212 | XEN_PT_LOG(d, "Unbind MSI%s with pirq %d, gvec 0x%x\n", |
| 213 | is_msix ? "-X" : "", pirq, gvec); |
| 214 | rc = xc_domain_unbind_msi_irq(xen_xc, xen_domid, gvec, pirq, gflags); |
| 215 | if (rc) { |
| 216 | XEN_PT_ERR(d, "Unbinding of MSI%s failed. (err: %d, pirq: %d, gvec: 0x%x)\n", |
| 217 | is_msix ? "-X" : "", errno, pirq, gvec); |
| 218 | return rc; |
| 219 | } |
| 220 | } |
| 221 | |
| 222 | XEN_PT_LOG(d, "Unmap MSI%s pirq %d\n", is_msix ? "-X" : "", pirq); |
| 223 | rc = xc_physdev_unmap_pirq(xen_xc, xen_domid, pirq); |
| 224 | if (rc) { |
| 225 | XEN_PT_ERR(d, "Unmapping of MSI%s pirq %d failed. (err: %i)\n", |
| 226 | is_msix ? "-X" : "", pirq, errno); |
| 227 | return rc; |
| 228 | } |
| 229 | |
| 230 | return 0; |
| 231 | } |
| 232 | |
| 233 | /* |
| 234 | * MSI virtualization functions |
| 235 | */ |
| 236 | |
| 237 | static int xen_pt_msi_set_enable(XenPCIPassthroughState *s, bool enable) |
| 238 | { |
| 239 | XEN_PT_LOG(&s->dev, "%s MSI.\n", enable ? "enabling" : "disabling"); |
| 240 | |
| 241 | if (!s->msi) { |
| 242 | return -1; |
| 243 | } |
| 244 | |
| 245 | return msi_msix_enable(s, s->msi->ctrl_offset, PCI_MSI_FLAGS_ENABLE, |
| 246 | enable); |
| 247 | } |
| 248 | |
| 249 | /* setup physical msi, but don't enable it */ |
| 250 | int xen_pt_msi_setup(XenPCIPassthroughState *s) |
| 251 | { |
| 252 | int pirq = XEN_PT_UNASSIGNED_PIRQ; |
| 253 | int rc = 0; |
| 254 | XenPTMSI *msi = s->msi; |
| 255 | |
| 256 | if (msi->initialized) { |
| 257 | XEN_PT_ERR(&s->dev, |
| 258 | "Setup physical MSI when it has been properly initialized.\n"); |
| 259 | return -1; |
| 260 | } |
| 261 | |
| 262 | rc = msi_msix_setup(s, msi_addr64(msi), msi->data, &pirq, false, 0, true); |
| 263 | if (rc) { |
| 264 | return rc; |
| 265 | } |
| 266 | |
| 267 | if (pirq < 0) { |
| 268 | XEN_PT_ERR(&s->dev, "Invalid pirq number: %d.\n", pirq); |
| 269 | return -1; |
| 270 | } |
| 271 | |
| 272 | msi->pirq = pirq; |
| 273 | XEN_PT_LOG(&s->dev, "MSI mapped with pirq %d.\n", pirq); |
| 274 | |
| 275 | return 0; |
| 276 | } |
| 277 | |
| 278 | int xen_pt_msi_update(XenPCIPassthroughState *s) |
| 279 | { |
| 280 | XenPTMSI *msi = s->msi; |
| 281 | |
| 282 | /* Current MSI emulation in QEMU only supports 1 vector */ |
| 283 | return msi_msix_update(s, msi_addr64(msi), msi->data, msi->pirq, |
| 284 | false, 0, &msi->pirq, msi->mask & 1); |
| 285 | } |
| 286 | |
| 287 | void xen_pt_msi_disable(XenPCIPassthroughState *s) |
| 288 | { |
| 289 | XenPTMSI *msi = s->msi; |
| 290 | |
| 291 | if (!msi) { |
| 292 | return; |
| 293 | } |
| 294 | |
| 295 | (void)xen_pt_msi_set_enable(s, false); |
| 296 | |
| 297 | msi_msix_disable(s, msi_addr64(msi), msi->data, msi->pirq, false, |
| 298 | msi->initialized); |
| 299 | |
| 300 | /* clear msi info */ |
| 301 | msi->flags &= ~PCI_MSI_FLAGS_ENABLE; |
| 302 | msi->initialized = false; |
| 303 | msi->mapped = false; |
| 304 | msi->pirq = XEN_PT_UNASSIGNED_PIRQ; |
| 305 | } |
| 306 | |
| 307 | /* |
| 308 | * MSI-X virtualization functions |
| 309 | */ |
| 310 | |
| 311 | static int msix_set_enable(XenPCIPassthroughState *s, bool enabled) |
| 312 | { |
| 313 | XEN_PT_LOG(&s->dev, "%s MSI-X.\n", enabled ? "enabling" : "disabling"); |
| 314 | |
| 315 | if (!s->msix) { |
| 316 | return -1; |
| 317 | } |
| 318 | |
| 319 | return msi_msix_enable(s, s->msix->ctrl_offset, PCI_MSIX_FLAGS_ENABLE, |
| 320 | enabled); |
| 321 | } |
| 322 | |
| 323 | static int xen_pt_msix_update_one(XenPCIPassthroughState *s, int entry_nr, |
| 324 | uint32_t vec_ctrl) |
| 325 | { |
| 326 | XenPTMSIXEntry *entry = NULL; |
| 327 | int pirq; |
| 328 | int rc; |
| 329 | |
| 330 | if (entry_nr < 0 || entry_nr >= s->msix->total_entries) { |
| 331 | return -EINVAL; |
| 332 | } |
| 333 | |
| 334 | entry = &s->msix->msix_entry[entry_nr]; |
| 335 | |
| 336 | if (!entry->updated) { |
| 337 | return 0; |
| 338 | } |
| 339 | |
| 340 | pirq = entry->pirq; |
| 341 | |
| 342 | /* |
| 343 | * Update the entry addr and data to the latest values only when the |
| 344 | * entry is masked or they are all masked, as required by the spec. |
| 345 | * Addr and data changes while the MSI-X entry is unmasked get deferred |
| 346 | * until the next masked -> unmasked transition. |
| 347 | */ |
| 348 | if (pirq == XEN_PT_UNASSIGNED_PIRQ || s->msix->maskall || |
| 349 | (vec_ctrl & PCI_MSIX_ENTRY_CTRL_MASKBIT)) { |
| 350 | entry->addr = entry->latch(LOWER_ADDR) | |
| 351 | ((uint64_t)entry->latch(UPPER_ADDR) << 32); |
| 352 | entry->data = entry->latch(DATA); |
| 353 | } |
| 354 | |
| 355 | rc = msi_msix_setup(s, entry->addr, entry->data, &pirq, true, entry_nr, |
| 356 | entry->pirq == XEN_PT_UNASSIGNED_PIRQ); |
| 357 | if (rc) { |
| 358 | return rc; |
| 359 | } |
| 360 | if (entry->pirq == XEN_PT_UNASSIGNED_PIRQ) { |
| 361 | entry->pirq = pirq; |
| 362 | } |
| 363 | |
| 364 | rc = msi_msix_update(s, entry->addr, entry->data, pirq, true, |
| 365 | entry_nr, &entry->pirq, |
| 366 | vec_ctrl & PCI_MSIX_ENTRY_CTRL_MASKBIT); |
| 367 | |
| 368 | if (!rc) { |
| 369 | entry->updated = false; |
| 370 | } |
| 371 | |
| 372 | return rc; |
| 373 | } |
| 374 | |
| 375 | int xen_pt_msix_update(XenPCIPassthroughState *s) |
| 376 | { |
| 377 | XenPTMSIX *msix = s->msix; |
| 378 | int i; |
| 379 | |
| 380 | for (i = 0; i < msix->total_entries; i++) { |
| 381 | xen_pt_msix_update_one(s, i, msix->msix_entry[i].latch(VECTOR_CTRL)); |
| 382 | } |
| 383 | |
| 384 | return 0; |
| 385 | } |
| 386 | |
| 387 | void xen_pt_msix_disable(XenPCIPassthroughState *s) |
| 388 | { |
| 389 | int i = 0; |
| 390 | |
| 391 | msix_set_enable(s, false); |
| 392 | |
| 393 | for (i = 0; i < s->msix->total_entries; i++) { |
| 394 | XenPTMSIXEntry *entry = &s->msix->msix_entry[i]; |
| 395 | |
| 396 | msi_msix_disable(s, entry->addr, entry->data, entry->pirq, true, true); |
| 397 | |
| 398 | /* clear MSI-X info */ |
| 399 | entry->pirq = XEN_PT_UNASSIGNED_PIRQ; |
| 400 | entry->updated = false; |
| 401 | } |
| 402 | } |
| 403 | |
| 404 | int xen_pt_msix_update_remap(XenPCIPassthroughState *s, int bar_index) |
| 405 | { |
| 406 | XenPTMSIXEntry *entry; |
| 407 | int i, ret; |
| 408 | |
| 409 | if (!(s->msix && s->msix->bar_index == bar_index)) { |
| 410 | return 0; |
| 411 | } |
| 412 | |
| 413 | for (i = 0; i < s->msix->total_entries; i++) { |
| 414 | entry = &s->msix->msix_entry[i]; |
| 415 | if (entry->pirq != XEN_PT_UNASSIGNED_PIRQ) { |
| 416 | ret = xc_domain_unbind_pt_irq(xen_xc, xen_domid, entry->pirq, |
| 417 | PT_IRQ_TYPE_MSI, 0, 0, 0, 0); |
| 418 | if (ret) { |
| 419 | XEN_PT_ERR(&s->dev, "unbind MSI-X entry %d failed (err: %d)\n", |
| 420 | entry->pirq, errno); |
| 421 | } |
| 422 | entry->updated = true; |
| 423 | } |
| 424 | } |
| 425 | return xen_pt_msix_update(s); |
| 426 | } |
| 427 | |
| 428 | static uint32_t get_entry_value(XenPTMSIXEntry *e, int offset) |
| 429 | { |
| 430 | assert(!(offset % sizeof(*e->latch))); |
| 431 | return e->latch[offset / sizeof(*e->latch)]; |
| 432 | } |
| 433 | |
| 434 | static void set_entry_value(XenPTMSIXEntry *e, int offset, uint32_t val) |
| 435 | { |
| 436 | assert(!(offset % sizeof(*e->latch))); |
| 437 | e->latch[offset / sizeof(*e->latch)] = val; |
| 438 | } |
| 439 | |
| 440 | static void pci_msix_write(void *opaque, hwaddr addr, |
| 441 | uint64_t val, unsigned size) |
| 442 | { |
| 443 | XenPCIPassthroughState *s = opaque; |
| 444 | XenPTMSIX *msix = s->msix; |
| 445 | XenPTMSIXEntry *entry; |
| 446 | unsigned int entry_nr, offset; |
| 447 | |
| 448 | entry_nr = addr / PCI_MSIX_ENTRY_SIZE; |
| 449 | if (entry_nr >= msix->total_entries) { |
| 450 | return; |
| 451 | } |
| 452 | entry = &msix->msix_entry[entry_nr]; |
| 453 | offset = addr % PCI_MSIX_ENTRY_SIZE; |
| 454 | |
| 455 | if (offset != PCI_MSIX_ENTRY_VECTOR_CTRL) { |
| 456 | if (get_entry_value(entry, offset) == val |
| 457 | && entry->pirq != XEN_PT_UNASSIGNED_PIRQ) { |
| 458 | return; |
| 459 | } |
| 460 | |
| 461 | entry->updated = true; |
| 462 | } else if (msix->enabled && entry->updated && |
| 463 | !(val & PCI_MSIX_ENTRY_CTRL_MASKBIT)) { |
| 464 | const volatile uint32_t *vec_ctrl; |
| 465 | |
| 466 | /* |
| 467 | * If Xen intercepts the mask bit access, entry->vec_ctrl may not be |
| 468 | * up-to-date. Read from hardware directly. |
| 469 | */ |
| 470 | vec_ctrl = s->msix->phys_iomem_base + entry_nr * PCI_MSIX_ENTRY_SIZE |
| 471 | + PCI_MSIX_ENTRY_VECTOR_CTRL; |
| 472 | xen_pt_msix_update_one(s, entry_nr, *vec_ctrl); |
| 473 | } |
| 474 | |
| 475 | set_entry_value(entry, offset, val); |
| 476 | } |
| 477 | |
| 478 | static uint64_t pci_msix_read(void *opaque, hwaddr addr, |
| 479 | unsigned size) |
| 480 | { |
| 481 | XenPCIPassthroughState *s = opaque; |
| 482 | XenPTMSIX *msix = s->msix; |
| 483 | int entry_nr, offset; |
| 484 | |
| 485 | entry_nr = addr / PCI_MSIX_ENTRY_SIZE; |
| 486 | if (entry_nr < 0) { |
| 487 | XEN_PT_ERR(&s->dev, "asked MSI-X entry '%i' invalid!\n", entry_nr); |
| 488 | return 0; |
| 489 | } |
| 490 | |
| 491 | offset = addr % PCI_MSIX_ENTRY_SIZE; |
| 492 | |
| 493 | if (addr < msix->total_entries * PCI_MSIX_ENTRY_SIZE) { |
| 494 | return get_entry_value(&msix->msix_entry[entry_nr], offset); |
| 495 | } else { |
| 496 | /* Pending Bit Array (PBA) */ |
| 497 | return *(uint32_t *)(msix->phys_iomem_base + addr); |
| 498 | } |
| 499 | } |
| 500 | |
| 501 | static bool pci_msix_accepts(void *opaque, hwaddr addr, |
| 502 | unsigned size, bool is_write, |
| 503 | MemTxAttrs attrs) |
| 504 | { |
| 505 | return !(addr & (size - 1)); |
| 506 | } |
| 507 | |
| 508 | static const MemoryRegionOps pci_msix_ops = { |
| 509 | .read = pci_msix_read, |
| 510 | .write = pci_msix_write, |
| 511 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 512 | .valid = { |
| 513 | .min_access_size = 4, |
| 514 | .max_access_size = 4, |
| 515 | .unaligned = false, |
| 516 | .accepts = pci_msix_accepts |
| 517 | }, |
| 518 | .impl = { |
| 519 | .min_access_size = 4, |
| 520 | .max_access_size = 4, |
| 521 | .unaligned = false |
| 522 | } |
| 523 | }; |
| 524 | |
| 525 | int xen_pt_msix_init(XenPCIPassthroughState *s, uint32_t base) |
| 526 | { |
| 527 | uint8_t id = 0; |
| 528 | uint16_t control = 0; |
| 529 | uint32_t table_off = 0; |
| 530 | int i, total_entries, bar_index; |
| 531 | XenHostPCIDevice *hd = &s->real_device; |
| 532 | PCIDevice *d = &s->dev; |
| 533 | int fd = -1; |
| 534 | XenPTMSIX *msix = NULL; |
| 535 | int rc = 0; |
| 536 | |
| 537 | rc = xen_host_pci_get_byte(hd, base + PCI_CAP_LIST_ID, &id); |
| 538 | if (rc) { |
| 539 | return rc; |
| 540 | } |
| 541 | |
| 542 | if (id != PCI_CAP_ID_MSIX) { |
| 543 | XEN_PT_ERR(d, "Invalid id 0x%x base 0x%x\n", id, base); |
| 544 | return -1; |
| 545 | } |
| 546 | |
| 547 | rc = xen_host_pci_get_word(hd, base + PCI_MSIX_FLAGS, &control); |
| 548 | if (rc) { |
| 549 | XEN_PT_ERR(d, "Failed to read PCI_MSIX_FLAGS field\n"); |
| 550 | return rc; |
| 551 | } |
| 552 | total_entries = control & PCI_MSIX_FLAGS_QSIZE; |
| 553 | total_entries += 1; |
| 554 | |
| 555 | s->msix = g_malloc0(sizeof (XenPTMSIX) |
| 556 | + total_entries * sizeof (XenPTMSIXEntry)); |
| 557 | msix = s->msix; |
| 558 | |
| 559 | msix->total_entries = total_entries; |
| 560 | for (i = 0; i < total_entries; i++) { |
| 561 | msix->msix_entry[i].pirq = XEN_PT_UNASSIGNED_PIRQ; |
| 562 | } |
| 563 | |
| 564 | memory_region_init_io(&msix->mmio, OBJECT(s), &pci_msix_ops, |
| 565 | s, "xen-pci-pt-msix", |
| 566 | (total_entries * PCI_MSIX_ENTRY_SIZE |
| 567 | + XC_PAGE_SIZE - 1) |
| 568 | & XC_PAGE_MASK); |
| 569 | |
| 570 | rc = xen_host_pci_get_long(hd, base + PCI_MSIX_TABLE, &table_off); |
| 571 | if (rc) { |
| 572 | XEN_PT_ERR(d, "Failed to read PCI_MSIX_TABLE field\n"); |
| 573 | goto error_out; |
| 574 | } |
| 575 | bar_index = msix->bar_index = table_off & PCI_MSIX_FLAGS_BIRMASK; |
| 576 | table_off = table_off & ~PCI_MSIX_FLAGS_BIRMASK; |
| 577 | msix->table_base = s->real_device.io_regions[bar_index].base_addr; |
| 578 | XEN_PT_LOG(d, "get MSI-X table BAR base 0x%"PRIx64"\n", msix->table_base); |
| 579 | |
| 580 | fd = open("/dev/mem", O_RDWR); |
| 581 | if (fd == -1) { |
| 582 | rc = -errno; |
| 583 | XEN_PT_ERR(d, "Can't open /dev/mem: %s\n", strerror(errno)); |
| 584 | goto error_out; |
| 585 | } |
| 586 | XEN_PT_LOG(d, "table_off = 0x%x, total_entries = %d\n", |
| 587 | table_off, total_entries); |
| 588 | msix->table_offset_adjust = table_off & 0x0fff; |
| 589 | msix->phys_iomem_base = |
| 590 | mmap(NULL, |
| 591 | total_entries * PCI_MSIX_ENTRY_SIZE + msix->table_offset_adjust, |
| 592 | PROT_READ, |
| 593 | MAP_SHARED | MAP_LOCKED, |
| 594 | fd, |
| 595 | msix->table_base + table_off - msix->table_offset_adjust); |
| 596 | close(fd); |
| 597 | if (msix->phys_iomem_base == MAP_FAILED) { |
| 598 | rc = -errno; |
| 599 | XEN_PT_ERR(d, "Can't map physical MSI-X table: %s\n", strerror(errno)); |
| 600 | goto error_out; |
| 601 | } |
| 602 | msix->phys_iomem_base = (char *)msix->phys_iomem_base |
| 603 | + msix->table_offset_adjust; |
| 604 | |
| 605 | XEN_PT_LOG(d, "mapping physical MSI-X table to %p\n", |
| 606 | msix->phys_iomem_base); |
| 607 | |
| 608 | memory_region_add_subregion_overlap(&s->bar[bar_index], table_off, |
| 609 | &msix->mmio, |
| 610 | 2); /* Priority: pci default + 1 */ |
| 611 | |
| 612 | return 0; |
| 613 | |
| 614 | error_out: |
| 615 | g_free(s->msix); |
| 616 | s->msix = NULL; |
| 617 | return rc; |
| 618 | } |
| 619 | |
| 620 | void xen_pt_msix_unmap(XenPCIPassthroughState *s) |
| 621 | { |
| 622 | XenPTMSIX *msix = s->msix; |
| 623 | |
| 624 | if (!msix) { |
| 625 | return; |
| 626 | } |
| 627 | |
| 628 | /* unmap the MSI-X memory mapped register area */ |
| 629 | if (msix->phys_iomem_base) { |
| 630 | XEN_PT_LOG(&s->dev, "unmapping physical MSI-X table from %p\n", |
| 631 | msix->phys_iomem_base); |
| 632 | munmap(msix->phys_iomem_base, msix->total_entries * PCI_MSIX_ENTRY_SIZE |
| 633 | + msix->table_offset_adjust); |
| 634 | } |
| 635 | |
| 636 | memory_region_del_subregion(&s->bar[msix->bar_index], &msix->mmio); |
| 637 | } |
| 638 | |
| 639 | void xen_pt_msix_delete(XenPCIPassthroughState *s) |
| 640 | { |
| 641 | g_clear_pointer(&s->msix, g_free); |
| 642 | } |