| 1 | /* |
| 2 | * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. |
| 3 | * All rights reserved. |
| 4 | * |
| 5 | * Redistribution and use in source and binary forms, with or without |
| 6 | * modification, are permitted provided that the following conditions are met: |
| 7 | * * Redistributions of source code must retain the above copyright |
| 8 | * notice, this list of conditions and the following disclaimer. |
| 9 | * * Redistributions in binary form must reproduce the above copyright |
| 10 | * notice, this list of conditions and the following disclaimer in the |
| 11 | * documentation and/or other materials provided with the distribution. |
| 12 | * * Neither the name of the Open Source and Linux Lab nor the |
| 13 | * names of its contributors may be used to endorse or promote products |
| 14 | * derived from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY |
| 20 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 21 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 22 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 23 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 24 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 25 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 26 | */ |
| 27 | |
| 28 | #include "qemu/osdep.h" |
| 29 | #include "qemu/units.h" |
| 30 | #include "qapi/error.h" |
| 31 | #include "target/xtensa/cpu.h" |
| 32 | #include "system/system.h" |
| 33 | #include "hw/core/boards.h" |
| 34 | #include "hw/core/loader.h" |
| 35 | #include "hw/core/qdev-properties.h" |
| 36 | #include "elf.h" |
| 37 | #include "system/memory.h" |
| 38 | #include "system/physmem.h" |
| 39 | #include "exec/tswap.h" |
| 40 | #include "hw/char/serial-mm.h" |
| 41 | #include "net/net.h" |
| 42 | #include "hw/core/sysbus.h" |
| 43 | #include "hw/block/flash.h" |
| 44 | #include "chardev/char.h" |
| 45 | #include "system/device_tree.h" |
| 46 | #include "system/reset.h" |
| 47 | #include "system/runstate.h" |
| 48 | #include "qemu/error-report.h" |
| 49 | #include "qemu/option.h" |
| 50 | #include "bootparam.h" |
| 51 | #include "xtensa_memory.h" |
| 52 | #include "hw/xtensa/mx_pic.h" |
| 53 | #include "exec/cpu-common.h" |
| 54 | |
| 55 | typedef struct XtfpgaFlashDesc { |
| 56 | hwaddr base; |
| 57 | size_t size; |
| 58 | size_t boot_base; |
| 59 | size_t sector_size; |
| 60 | } XtfpgaFlashDesc; |
| 61 | |
| 62 | typedef struct XtfpgaBoardDesc { |
| 63 | const XtfpgaFlashDesc *flash; |
| 64 | size_t sram_size; |
| 65 | const hwaddr *io; |
| 66 | } XtfpgaBoardDesc; |
| 67 | |
| 68 | typedef struct XtfpgaFpgaState { |
| 69 | MemoryRegion iomem; |
| 70 | uint32_t freq; |
| 71 | uint32_t leds; |
| 72 | uint32_t switches; |
| 73 | } XtfpgaFpgaState; |
| 74 | |
| 75 | static void xtfpga_fpga_reset(void *opaque) |
| 76 | { |
| 77 | XtfpgaFpgaState *s = opaque; |
| 78 | |
| 79 | s->leds = 0; |
| 80 | s->switches = 0; |
| 81 | } |
| 82 | |
| 83 | static uint64_t xtfpga_fpga_read(void *opaque, hwaddr addr, |
| 84 | unsigned size) |
| 85 | { |
| 86 | XtfpgaFpgaState *s = opaque; |
| 87 | |
| 88 | switch (addr) { |
| 89 | case 0x0: /*build date code*/ |
| 90 | return 0x09272011; |
| 91 | |
| 92 | case 0x4: /*processor clock frequency, Hz*/ |
| 93 | return s->freq; |
| 94 | |
| 95 | case 0x8: /*LEDs (off = 0, on = 1)*/ |
| 96 | return s->leds; |
| 97 | |
| 98 | case 0xc: /*DIP switches (off = 0, on = 1)*/ |
| 99 | return s->switches; |
| 100 | } |
| 101 | return 0; |
| 102 | } |
| 103 | |
| 104 | static void xtfpga_fpga_write(void *opaque, hwaddr addr, |
| 105 | uint64_t val, unsigned size) |
| 106 | { |
| 107 | XtfpgaFpgaState *s = opaque; |
| 108 | |
| 109 | switch (addr) { |
| 110 | case 0x8: /*LEDs (off = 0, on = 1)*/ |
| 111 | s->leds = val; |
| 112 | break; |
| 113 | |
| 114 | case 0x10: /*board reset*/ |
| 115 | if (val == 0xdead) { |
| 116 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
| 117 | } |
| 118 | break; |
| 119 | } |
| 120 | } |
| 121 | |
| 122 | static const MemoryRegionOps xtfpga_fpga_ops = { |
| 123 | .read = xtfpga_fpga_read, |
| 124 | .write = xtfpga_fpga_write, |
| 125 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 126 | }; |
| 127 | |
| 128 | static XtfpgaFpgaState *xtfpga_fpga_init(MemoryRegion *address_space, |
| 129 | hwaddr base, uint32_t freq) |
| 130 | { |
| 131 | XtfpgaFpgaState *s = g_new(XtfpgaFpgaState, 1); |
| 132 | |
| 133 | memory_region_init_io(&s->iomem, NULL, &xtfpga_fpga_ops, s, |
| 134 | "xtfpga.fpga", 0x10000); |
| 135 | memory_region_add_subregion(address_space, base, &s->iomem); |
| 136 | s->freq = freq; |
| 137 | xtfpga_fpga_reset(s); |
| 138 | qemu_register_reset(xtfpga_fpga_reset, s); |
| 139 | return s; |
| 140 | } |
| 141 | |
| 142 | static void xtfpga_net_init(MemoryRegion *address_space, |
| 143 | hwaddr base, |
| 144 | hwaddr descriptors, |
| 145 | hwaddr buffers, |
| 146 | qemu_irq irq) |
| 147 | { |
| 148 | DeviceState *dev; |
| 149 | SysBusDevice *s; |
| 150 | MemoryRegion *ram; |
| 151 | |
| 152 | dev = qemu_create_nic_device("open_eth", true, NULL); |
| 153 | if (!dev) { |
| 154 | return; |
| 155 | } |
| 156 | |
| 157 | s = SYS_BUS_DEVICE(dev); |
| 158 | sysbus_realize_and_unref(s, &error_fatal); |
| 159 | sysbus_connect_irq(s, 0, irq); |
| 160 | memory_region_add_subregion(address_space, base, |
| 161 | sysbus_mmio_get_region(s, 0)); |
| 162 | memory_region_add_subregion(address_space, descriptors, |
| 163 | sysbus_mmio_get_region(s, 1)); |
| 164 | |
| 165 | ram = g_malloc(sizeof(*ram)); |
| 166 | memory_region_init_ram(ram, OBJECT(s), "open_eth.ram", 16 * KiB, |
| 167 | &error_fatal); |
| 168 | memory_region_add_subregion(address_space, buffers, ram); |
| 169 | } |
| 170 | |
| 171 | static PFlashCFI01 *xtfpga_flash_init(MemoryRegion *address_space, |
| 172 | const XtfpgaBoardDesc *board, |
| 173 | DriveInfo *dinfo, int be) |
| 174 | { |
| 175 | SysBusDevice *s; |
| 176 | DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); |
| 177 | |
| 178 | qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo)); |
| 179 | qdev_prop_set_uint32(dev, "num-blocks", |
| 180 | board->flash->size / board->flash->sector_size); |
| 181 | qdev_prop_set_uint64(dev, "sector-length", board->flash->sector_size); |
| 182 | qdev_prop_set_uint8(dev, "width", 2); |
| 183 | qdev_prop_set_bit(dev, "big-endian", be); |
| 184 | qdev_prop_set_string(dev, "name", "xtfpga.io.flash"); |
| 185 | s = SYS_BUS_DEVICE(dev); |
| 186 | sysbus_realize_and_unref(s, &error_fatal); |
| 187 | memory_region_add_subregion(address_space, board->flash->base, |
| 188 | sysbus_mmio_get_region(s, 0)); |
| 189 | return PFLASH_CFI01(dev); |
| 190 | } |
| 191 | |
| 192 | static uint64_t translate_phys_addr(void *opaque, uint64_t addr) |
| 193 | { |
| 194 | XtensaCPU *cpu = opaque; |
| 195 | TranslateForDebugResult tres; |
| 196 | |
| 197 | if (!cpu_translate_for_debug(CPU(cpu), addr, &tres)) { |
| 198 | return -1; |
| 199 | } |
| 200 | return tres.physaddr; |
| 201 | } |
| 202 | |
| 203 | static void xtfpga_reset(void *opaque) |
| 204 | { |
| 205 | XtensaCPU *cpu = opaque; |
| 206 | |
| 207 | cpu_reset(CPU(cpu)); |
| 208 | } |
| 209 | |
| 210 | static uint64_t xtfpga_io_read(void *opaque, hwaddr addr, |
| 211 | unsigned size) |
| 212 | { |
| 213 | return 0; |
| 214 | } |
| 215 | |
| 216 | static void xtfpga_io_write(void *opaque, hwaddr addr, |
| 217 | uint64_t val, unsigned size) |
| 218 | { |
| 219 | } |
| 220 | |
| 221 | static const MemoryRegionOps xtfpga_io_ops = { |
| 222 | .read = xtfpga_io_read, |
| 223 | .write = xtfpga_io_write, |
| 224 | .endianness = DEVICE_NATIVE_ENDIAN, |
| 225 | }; |
| 226 | |
| 227 | static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine) |
| 228 | { |
| 229 | MemoryRegion *system_memory = get_system_memory(); |
| 230 | XtensaCPU *cpu = NULL; |
| 231 | CPUXtensaState *env = NULL; |
| 232 | MemoryRegion *system_io; |
| 233 | XtensaMxPic *mx_pic = NULL; |
| 234 | qemu_irq *extints; |
| 235 | DriveInfo *dinfo; |
| 236 | PFlashCFI01 *flash = NULL; |
| 237 | const char *kernel_filename = machine->kernel_filename; |
| 238 | const char *kernel_cmdline = machine->kernel_cmdline; |
| 239 | const char *dtb_filename = machine->dtb; |
| 240 | const char *initrd_filename = machine->initrd_filename; |
| 241 | const unsigned system_io_size = 224 * MiB; |
| 242 | uint32_t freq = 10000000; |
| 243 | int n; |
| 244 | unsigned int smp_cpus = machine->smp.cpus; |
| 245 | |
| 246 | if (smp_cpus > 1) { |
| 247 | mx_pic = xtensa_mx_pic_init(31); |
| 248 | qemu_register_reset(xtensa_mx_pic_reset, mx_pic); |
| 249 | } |
| 250 | for (n = 0; n < smp_cpus; n++) { |
| 251 | CPUXtensaState *cenv = NULL; |
| 252 | |
| 253 | cpu = XTENSA_CPU(cpu_create(machine->cpu_type)); |
| 254 | cenv = &cpu->env; |
| 255 | if (!env) { |
| 256 | env = cenv; |
| 257 | freq = env->config->clock_freq_khz * 1000; |
| 258 | } |
| 259 | |
| 260 | if (mx_pic) { |
| 261 | MemoryRegion *mx_eri; |
| 262 | |
| 263 | mx_eri = xtensa_mx_pic_register_cpu(mx_pic, |
| 264 | xtensa_get_extints(cenv), |
| 265 | xtensa_get_runstall(cenv)); |
| 266 | memory_region_add_subregion(xtensa_get_er_region(cenv), |
| 267 | 0, mx_eri); |
| 268 | } |
| 269 | cenv->sregs[PRID] = n; |
| 270 | xtensa_select_static_vectors(cenv, n != 0); |
| 271 | qemu_register_reset(xtfpga_reset, cpu); |
| 272 | /* Need MMU initialized prior to ELF loading, |
| 273 | * so that ELF gets loaded into virtual addresses |
| 274 | */ |
| 275 | reset_mmu(cenv); |
| 276 | } |
| 277 | if (smp_cpus > 1) { |
| 278 | extints = xtensa_mx_pic_get_extints(mx_pic); |
| 279 | } else { |
| 280 | extints = xtensa_get_extints(env); |
| 281 | } |
| 282 | |
| 283 | if (env) { |
| 284 | XtensaMemory sysram = env->config->sysram; |
| 285 | |
| 286 | sysram.location[0].size = machine->ram_size; |
| 287 | xtensa_create_memory_regions(&env->config->instrom, "xtensa.instrom", |
| 288 | system_memory); |
| 289 | xtensa_create_memory_regions(&env->config->instram, "xtensa.instram", |
| 290 | system_memory); |
| 291 | xtensa_create_memory_regions(&env->config->datarom, "xtensa.datarom", |
| 292 | system_memory); |
| 293 | xtensa_create_memory_regions(&env->config->dataram, "xtensa.dataram", |
| 294 | system_memory); |
| 295 | xtensa_create_memory_regions(&sysram, "xtensa.sysram", |
| 296 | system_memory); |
| 297 | } |
| 298 | |
| 299 | system_io = g_malloc(sizeof(*system_io)); |
| 300 | memory_region_init_io(system_io, NULL, &xtfpga_io_ops, NULL, "xtfpga.io", |
| 301 | system_io_size); |
| 302 | memory_region_add_subregion(system_memory, board->io[0], system_io); |
| 303 | if (board->io[1]) { |
| 304 | MemoryRegion *io = g_malloc(sizeof(*io)); |
| 305 | |
| 306 | memory_region_init_alias(io, NULL, "xtfpga.io.cached", |
| 307 | system_io, 0, system_io_size); |
| 308 | memory_region_add_subregion(system_memory, board->io[1], io); |
| 309 | } |
| 310 | xtfpga_fpga_init(system_io, 0x0d020000, freq); |
| 311 | xtfpga_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000, extints[1]); |
| 312 | |
| 313 | serial_mm_init(system_io, 0x0d050020, 2, extints[0], |
| 314 | 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN); |
| 315 | |
| 316 | dinfo = drive_get(IF_PFLASH, 0, 0); |
| 317 | if (dinfo) { |
| 318 | flash = xtfpga_flash_init(system_io, board, dinfo, TARGET_BIG_ENDIAN); |
| 319 | } |
| 320 | |
| 321 | /* Use presence of kernel file name as 'boot from SRAM' switch. */ |
| 322 | if (kernel_filename) { |
| 323 | uint32_t entry_point = env->pc; |
| 324 | size_t bp_size = 3 * get_tag_size(0); /* first/last and memory tags */ |
| 325 | uint32_t tagptr = env->config->sysrom.location[0].addr + |
| 326 | board->sram_size; |
| 327 | uint32_t cur_tagptr; |
| 328 | BpMemInfo memory_location = { |
| 329 | .type = tswap32(MEMORY_TYPE_CONVENTIONAL), |
| 330 | .start = tswap32(env->config->sysram.location[0].addr), |
| 331 | .end = tswap32(env->config->sysram.location[0].addr + |
| 332 | machine->ram_size), |
| 333 | }; |
| 334 | uint32_t lowmem_end = machine->ram_size < 0x08000000 ? |
| 335 | machine->ram_size : 0x08000000; |
| 336 | uint32_t cur_lowmem = QEMU_ALIGN_UP(lowmem_end / 2, 4096); |
| 337 | |
| 338 | lowmem_end += env->config->sysram.location[0].addr; |
| 339 | cur_lowmem += env->config->sysram.location[0].addr; |
| 340 | |
| 341 | xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom", |
| 342 | system_memory); |
| 343 | |
| 344 | if (kernel_cmdline) { |
| 345 | bp_size += get_tag_size(strlen(kernel_cmdline) + 1); |
| 346 | } |
| 347 | if (dtb_filename) { |
| 348 | bp_size += get_tag_size(sizeof(uint32_t)); |
| 349 | } |
| 350 | if (initrd_filename) { |
| 351 | bp_size += get_tag_size(sizeof(BpMemInfo)); |
| 352 | } |
| 353 | |
| 354 | /* Put kernel bootparameters to the end of that SRAM */ |
| 355 | tagptr = (tagptr - bp_size) & ~0xff; |
| 356 | cur_tagptr = put_tag(tagptr, BP_TAG_FIRST, 0, NULL); |
| 357 | cur_tagptr = put_tag(cur_tagptr, BP_TAG_MEMORY, |
| 358 | sizeof(memory_location), &memory_location); |
| 359 | |
| 360 | if (kernel_cmdline) { |
| 361 | cur_tagptr = put_tag(cur_tagptr, BP_TAG_COMMAND_LINE, |
| 362 | strlen(kernel_cmdline) + 1, kernel_cmdline); |
| 363 | } |
| 364 | if (dtb_filename) { |
| 365 | int fdt_size; |
| 366 | void *fdt = load_device_tree(dtb_filename, &fdt_size); |
| 367 | uint32_t dtb_addr = tswap32(cur_lowmem); |
| 368 | |
| 369 | if (!fdt) { |
| 370 | error_report("could not load DTB '%s'", dtb_filename); |
| 371 | exit(EXIT_FAILURE); |
| 372 | } |
| 373 | |
| 374 | physical_memory_write(cur_lowmem, fdt, fdt_size); |
| 375 | cur_tagptr = put_tag(cur_tagptr, BP_TAG_FDT, |
| 376 | sizeof(dtb_addr), &dtb_addr); |
| 377 | cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + fdt_size, 4 * KiB); |
| 378 | g_free(fdt); |
| 379 | } |
| 380 | if (initrd_filename) { |
| 381 | BpMemInfo initrd_location = { 0 }; |
| 382 | int initrd_size = load_ramdisk(initrd_filename, cur_lowmem, |
| 383 | lowmem_end - cur_lowmem); |
| 384 | |
| 385 | if (initrd_size < 0) { |
| 386 | initrd_size = load_image_targphys(initrd_filename, |
| 387 | cur_lowmem, |
| 388 | lowmem_end - cur_lowmem, |
| 389 | NULL); |
| 390 | } |
| 391 | if (initrd_size < 0) { |
| 392 | error_report("could not load initrd '%s'", initrd_filename); |
| 393 | exit(EXIT_FAILURE); |
| 394 | } |
| 395 | initrd_location.start = tswap32(cur_lowmem); |
| 396 | initrd_location.end = tswap32(cur_lowmem + initrd_size); |
| 397 | cur_tagptr = put_tag(cur_tagptr, BP_TAG_INITRD, |
| 398 | sizeof(initrd_location), &initrd_location); |
| 399 | cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + initrd_size, 4 * KiB); |
| 400 | } |
| 401 | cur_tagptr = put_tag(cur_tagptr, BP_TAG_LAST, 0, NULL); |
| 402 | env->regs[2] = tagptr; |
| 403 | |
| 404 | uint64_t elf_entry; |
| 405 | int success = load_elf(kernel_filename, NULL, translate_phys_addr, cpu, |
| 406 | &elf_entry, NULL, NULL, NULL, |
| 407 | TARGET_BIG_ENDIAN ? ELFDATA2MSB : ELFDATA2LSB, |
| 408 | EM_XTENSA, 0, 0); |
| 409 | if (success > 0) { |
| 410 | entry_point = elf_entry; |
| 411 | } else { |
| 412 | hwaddr ep; |
| 413 | int is_linux; |
| 414 | success = load_uimage(kernel_filename, &ep, NULL, &is_linux, |
| 415 | translate_phys_addr, cpu); |
| 416 | if (success > 0 && is_linux) { |
| 417 | entry_point = ep; |
| 418 | } else { |
| 419 | error_report("could not load kernel '%s'", |
| 420 | kernel_filename); |
| 421 | exit(EXIT_FAILURE); |
| 422 | } |
| 423 | } |
| 424 | if (entry_point != env->pc) { |
| 425 | uint8_t boot_be[] = { |
| 426 | 0x60, 0x00, 0x08, /* j 1f */ |
| 427 | 0x00, /* .literal_position */ |
| 428 | 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */ |
| 429 | 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */ |
| 430 | /* 1: */ |
| 431 | 0x10, 0xff, 0xfe, /* l32r a0, entry_pc */ |
| 432 | 0x12, 0xff, 0xfe, /* l32r a2, entry_a2 */ |
| 433 | 0x0a, 0x00, 0x00, /* jx a0 */ |
| 434 | }; |
| 435 | uint8_t boot_le[] = { |
| 436 | 0x06, 0x02, 0x00, /* j 1f */ |
| 437 | 0x00, /* .literal_position */ |
| 438 | 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */ |
| 439 | 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */ |
| 440 | /* 1: */ |
| 441 | 0x01, 0xfe, 0xff, /* l32r a0, entry_pc */ |
| 442 | 0x21, 0xfe, 0xff, /* l32r a2, entry_a2 */ |
| 443 | 0xa0, 0x00, 0x00, /* jx a0 */ |
| 444 | }; |
| 445 | const size_t boot_sz = TARGET_BIG_ENDIAN ? sizeof(boot_be) |
| 446 | : sizeof(boot_le); |
| 447 | uint8_t *boot = TARGET_BIG_ENDIAN ? boot_be : boot_le; |
| 448 | uint32_t entry_pc = tswap32(entry_point); |
| 449 | uint32_t entry_a2 = tswap32(tagptr); |
| 450 | |
| 451 | memcpy(boot + 4, &entry_pc, sizeof(entry_pc)); |
| 452 | memcpy(boot + 8, &entry_a2, sizeof(entry_a2)); |
| 453 | physical_memory_write(env->pc, boot, boot_sz); |
| 454 | } |
| 455 | } else { |
| 456 | if (flash) { |
| 457 | MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash); |
| 458 | MemoryRegion *flash_io = g_malloc(sizeof(*flash_io)); |
| 459 | uint32_t size = env->config->sysrom.location[0].size; |
| 460 | |
| 461 | if (board->flash->size - board->flash->boot_base < size) { |
| 462 | size = board->flash->size - board->flash->boot_base; |
| 463 | } |
| 464 | |
| 465 | memory_region_init_alias(flash_io, NULL, "xtfpga.flash", |
| 466 | flash_mr, board->flash->boot_base, size); |
| 467 | memory_region_add_subregion(system_memory, |
| 468 | env->config->sysrom.location[0].addr, |
| 469 | flash_io); |
| 470 | } else { |
| 471 | xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom", |
| 472 | system_memory); |
| 473 | } |
| 474 | } |
| 475 | } |
| 476 | |
| 477 | #define XTFPGA_MMU_RESERVED_MEMORY_SIZE (128 * MiB) |
| 478 | |
| 479 | static const hwaddr xtfpga_mmu_io[2] = { |
| 480 | 0xf0000000, |
| 481 | }; |
| 482 | |
| 483 | static const hwaddr xtfpga_nommu_io[2] = { |
| 484 | 0x90000000, |
| 485 | 0x70000000, |
| 486 | }; |
| 487 | |
| 488 | static const XtfpgaFlashDesc lx60_flash = { |
| 489 | .base = 0x08000000, |
| 490 | .size = 0x00400000, |
| 491 | .sector_size = 0x10000, |
| 492 | }; |
| 493 | |
| 494 | static void xtfpga_lx60_init(MachineState *machine) |
| 495 | { |
| 496 | static const XtfpgaBoardDesc lx60_board = { |
| 497 | .flash = &lx60_flash, |
| 498 | .sram_size = 0x20000, |
| 499 | .io = xtfpga_mmu_io, |
| 500 | }; |
| 501 | xtfpga_init(&lx60_board, machine); |
| 502 | } |
| 503 | |
| 504 | static void xtfpga_lx60_nommu_init(MachineState *machine) |
| 505 | { |
| 506 | static const XtfpgaBoardDesc lx60_board = { |
| 507 | .flash = &lx60_flash, |
| 508 | .sram_size = 0x20000, |
| 509 | .io = xtfpga_nommu_io, |
| 510 | }; |
| 511 | xtfpga_init(&lx60_board, machine); |
| 512 | } |
| 513 | |
| 514 | static const XtfpgaFlashDesc lx200_flash = { |
| 515 | .base = 0x08000000, |
| 516 | .size = 0x01000000, |
| 517 | .sector_size = 0x20000, |
| 518 | }; |
| 519 | |
| 520 | static void xtfpga_lx200_init(MachineState *machine) |
| 521 | { |
| 522 | static const XtfpgaBoardDesc lx200_board = { |
| 523 | .flash = &lx200_flash, |
| 524 | .sram_size = 0x2000000, |
| 525 | .io = xtfpga_mmu_io, |
| 526 | }; |
| 527 | xtfpga_init(&lx200_board, machine); |
| 528 | } |
| 529 | |
| 530 | static void xtfpga_lx200_nommu_init(MachineState *machine) |
| 531 | { |
| 532 | static const XtfpgaBoardDesc lx200_board = { |
| 533 | .flash = &lx200_flash, |
| 534 | .sram_size = 0x2000000, |
| 535 | .io = xtfpga_nommu_io, |
| 536 | }; |
| 537 | xtfpga_init(&lx200_board, machine); |
| 538 | } |
| 539 | |
| 540 | static const XtfpgaFlashDesc ml605_flash = { |
| 541 | .base = 0x08000000, |
| 542 | .size = 0x01000000, |
| 543 | .sector_size = 0x20000, |
| 544 | }; |
| 545 | |
| 546 | static void xtfpga_ml605_init(MachineState *machine) |
| 547 | { |
| 548 | static const XtfpgaBoardDesc ml605_board = { |
| 549 | .flash = &ml605_flash, |
| 550 | .sram_size = 0x2000000, |
| 551 | .io = xtfpga_mmu_io, |
| 552 | }; |
| 553 | xtfpga_init(&ml605_board, machine); |
| 554 | } |
| 555 | |
| 556 | static void xtfpga_ml605_nommu_init(MachineState *machine) |
| 557 | { |
| 558 | static const XtfpgaBoardDesc ml605_board = { |
| 559 | .flash = &ml605_flash, |
| 560 | .sram_size = 0x2000000, |
| 561 | .io = xtfpga_nommu_io, |
| 562 | }; |
| 563 | xtfpga_init(&ml605_board, machine); |
| 564 | } |
| 565 | |
| 566 | static const XtfpgaFlashDesc kc705_flash = { |
| 567 | .base = 0x00000000, |
| 568 | .size = 0x08000000, |
| 569 | .boot_base = 0x06000000, |
| 570 | .sector_size = 0x20000, |
| 571 | }; |
| 572 | |
| 573 | static void xtfpga_kc705_init(MachineState *machine) |
| 574 | { |
| 575 | static const XtfpgaBoardDesc kc705_board = { |
| 576 | .flash = &kc705_flash, |
| 577 | .sram_size = 0x2000000, |
| 578 | .io = xtfpga_mmu_io, |
| 579 | }; |
| 580 | xtfpga_init(&kc705_board, machine); |
| 581 | } |
| 582 | |
| 583 | static void xtfpga_kc705_nommu_init(MachineState *machine) |
| 584 | { |
| 585 | static const XtfpgaBoardDesc kc705_board = { |
| 586 | .flash = &kc705_flash, |
| 587 | .sram_size = 0x2000000, |
| 588 | .io = xtfpga_nommu_io, |
| 589 | }; |
| 590 | xtfpga_init(&kc705_board, machine); |
| 591 | } |
| 592 | |
| 593 | static void xtfpga_lx60_class_init(ObjectClass *oc, const void *data) |
| 594 | { |
| 595 | MachineClass *mc = MACHINE_CLASS(oc); |
| 596 | |
| 597 | mc->desc = "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; |
| 598 | mc->init = xtfpga_lx60_init; |
| 599 | mc->max_cpus = 32; |
| 600 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; |
| 601 | mc->default_ram_size = 64 * MiB; |
| 602 | } |
| 603 | |
| 604 | static const TypeInfo xtfpga_lx60_type = { |
| 605 | .name = MACHINE_TYPE_NAME("lx60"), |
| 606 | .parent = TYPE_MACHINE, |
| 607 | .class_init = xtfpga_lx60_class_init, |
| 608 | }; |
| 609 | |
| 610 | static void xtfpga_lx60_nommu_class_init(ObjectClass *oc, const void *data) |
| 611 | { |
| 612 | MachineClass *mc = MACHINE_CLASS(oc); |
| 613 | |
| 614 | mc->desc = "lx60 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; |
| 615 | mc->init = xtfpga_lx60_nommu_init; |
| 616 | mc->max_cpus = 32; |
| 617 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; |
| 618 | mc->default_ram_size = 64 * MiB; |
| 619 | } |
| 620 | |
| 621 | static const TypeInfo xtfpga_lx60_nommu_type = { |
| 622 | .name = MACHINE_TYPE_NAME("lx60-nommu"), |
| 623 | .parent = TYPE_MACHINE, |
| 624 | .class_init = xtfpga_lx60_nommu_class_init, |
| 625 | }; |
| 626 | |
| 627 | static void xtfpga_lx200_class_init(ObjectClass *oc, const void *data) |
| 628 | { |
| 629 | MachineClass *mc = MACHINE_CLASS(oc); |
| 630 | |
| 631 | mc->desc = "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; |
| 632 | mc->init = xtfpga_lx200_init; |
| 633 | mc->max_cpus = 32; |
| 634 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; |
| 635 | mc->default_ram_size = 96 * MiB; |
| 636 | } |
| 637 | |
| 638 | static const TypeInfo xtfpga_lx200_type = { |
| 639 | .name = MACHINE_TYPE_NAME("lx200"), |
| 640 | .parent = TYPE_MACHINE, |
| 641 | .class_init = xtfpga_lx200_class_init, |
| 642 | }; |
| 643 | |
| 644 | static void xtfpga_lx200_nommu_class_init(ObjectClass *oc, const void *data) |
| 645 | { |
| 646 | MachineClass *mc = MACHINE_CLASS(oc); |
| 647 | |
| 648 | mc->desc = "lx200 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; |
| 649 | mc->init = xtfpga_lx200_nommu_init; |
| 650 | mc->max_cpus = 32; |
| 651 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; |
| 652 | mc->default_ram_size = 96 * MiB; |
| 653 | } |
| 654 | |
| 655 | static const TypeInfo xtfpga_lx200_nommu_type = { |
| 656 | .name = MACHINE_TYPE_NAME("lx200-nommu"), |
| 657 | .parent = TYPE_MACHINE, |
| 658 | .class_init = xtfpga_lx200_nommu_class_init, |
| 659 | }; |
| 660 | |
| 661 | static void xtfpga_ml605_class_init(ObjectClass *oc, const void *data) |
| 662 | { |
| 663 | MachineClass *mc = MACHINE_CLASS(oc); |
| 664 | |
| 665 | mc->desc = "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; |
| 666 | mc->init = xtfpga_ml605_init; |
| 667 | mc->max_cpus = 32; |
| 668 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; |
| 669 | mc->default_ram_size = 512 * MiB - XTFPGA_MMU_RESERVED_MEMORY_SIZE; |
| 670 | } |
| 671 | |
| 672 | static const TypeInfo xtfpga_ml605_type = { |
| 673 | .name = MACHINE_TYPE_NAME("ml605"), |
| 674 | .parent = TYPE_MACHINE, |
| 675 | .class_init = xtfpga_ml605_class_init, |
| 676 | }; |
| 677 | |
| 678 | static void xtfpga_ml605_nommu_class_init(ObjectClass *oc, const void *data) |
| 679 | { |
| 680 | MachineClass *mc = MACHINE_CLASS(oc); |
| 681 | |
| 682 | mc->desc = "ml605 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; |
| 683 | mc->init = xtfpga_ml605_nommu_init; |
| 684 | mc->max_cpus = 32; |
| 685 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; |
| 686 | mc->default_ram_size = 256 * MiB; |
| 687 | } |
| 688 | |
| 689 | static const TypeInfo xtfpga_ml605_nommu_type = { |
| 690 | .name = MACHINE_TYPE_NAME("ml605-nommu"), |
| 691 | .parent = TYPE_MACHINE, |
| 692 | .class_init = xtfpga_ml605_nommu_class_init, |
| 693 | }; |
| 694 | |
| 695 | static void xtfpga_kc705_class_init(ObjectClass *oc, const void *data) |
| 696 | { |
| 697 | MachineClass *mc = MACHINE_CLASS(oc); |
| 698 | |
| 699 | mc->desc = "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; |
| 700 | mc->init = xtfpga_kc705_init; |
| 701 | mc->max_cpus = 32; |
| 702 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; |
| 703 | mc->default_ram_size = 1 * GiB - XTFPGA_MMU_RESERVED_MEMORY_SIZE; |
| 704 | } |
| 705 | |
| 706 | static const TypeInfo xtfpga_kc705_type = { |
| 707 | .name = MACHINE_TYPE_NAME("kc705"), |
| 708 | .parent = TYPE_MACHINE, |
| 709 | .class_init = xtfpga_kc705_class_init, |
| 710 | }; |
| 711 | |
| 712 | static void xtfpga_kc705_nommu_class_init(ObjectClass *oc, const void *data) |
| 713 | { |
| 714 | MachineClass *mc = MACHINE_CLASS(oc); |
| 715 | |
| 716 | mc->desc = "kc705 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; |
| 717 | mc->init = xtfpga_kc705_nommu_init; |
| 718 | mc->max_cpus = 32; |
| 719 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; |
| 720 | mc->default_ram_size = 256 * MiB; |
| 721 | } |
| 722 | |
| 723 | static const TypeInfo xtfpga_kc705_nommu_type = { |
| 724 | .name = MACHINE_TYPE_NAME("kc705-nommu"), |
| 725 | .parent = TYPE_MACHINE, |
| 726 | .class_init = xtfpga_kc705_nommu_class_init, |
| 727 | }; |
| 728 | |
| 729 | static void xtfpga_machines_init(void) |
| 730 | { |
| 731 | type_register_static(&xtfpga_lx60_type); |
| 732 | type_register_static(&xtfpga_lx200_type); |
| 733 | type_register_static(&xtfpga_ml605_type); |
| 734 | type_register_static(&xtfpga_kc705_type); |
| 735 | type_register_static(&xtfpga_lx60_nommu_type); |
| 736 | type_register_static(&xtfpga_lx200_nommu_type); |
| 737 | type_register_static(&xtfpga_ml605_nommu_type); |
| 738 | type_register_static(&xtfpga_kc705_nommu_type); |
| 739 | } |
| 740 | |
| 741 | type_init(xtfpga_machines_init) |