| 1 | /* |
| 2 | * Probe guest virtual addresses for access permissions. |
| 3 | * |
| 4 | * Copyright (c) 2003 Fabrice Bellard |
| 5 | * SPDX-License-Identifier: LGPL-2.1-or-later |
| 6 | */ |
| 7 | #ifndef ACCEL_TCG_PROBE_H |
| 8 | #define ACCEL_TCG_PROBE_H |
| 9 | |
| 10 | #ifndef CONFIG_TCG |
| 11 | #error Can only include this header with TCG |
| 12 | #endif |
| 13 | |
| 14 | #include "exec/mmu-access-type.h" |
| 15 | #include "exec/vaddr.h" |
| 16 | |
| 17 | /** |
| 18 | * probe_access: |
| 19 | * @env: CPUArchState |
| 20 | * @addr: guest virtual address to look up |
| 21 | * @size: size of the access |
| 22 | * @access_type: read, write or execute permission |
| 23 | * @mmu_idx: MMU index to use for lookup |
| 24 | * @retaddr: return address for unwinding |
| 25 | * |
| 26 | * Look up the guest virtual address @addr. Raise an exception if the |
| 27 | * page does not satisfy @access_type. Raise an exception if the |
| 28 | * access (@addr, @size) hits a watchpoint. For writes, mark a clean |
| 29 | * page as dirty. |
| 30 | * |
| 31 | * Finally, return the host address for a page that is backed by RAM, |
| 32 | * or NULL if the page requires I/O. |
| 33 | */ |
| 34 | void *probe_access(CPUArchState *env, vaddr addr, int size, |
| 35 | MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); |
| 36 | |
| 37 | static inline void *probe_write(CPUArchState *env, vaddr addr, int size, |
| 38 | int mmu_idx, uintptr_t retaddr) |
| 39 | { |
| 40 | return probe_access(env, addr, size, MMU_DATA_STORE, mmu_idx, retaddr); |
| 41 | } |
| 42 | |
| 43 | static inline void *probe_read(CPUArchState *env, vaddr addr, int size, |
| 44 | int mmu_idx, uintptr_t retaddr) |
| 45 | { |
| 46 | return probe_access(env, addr, size, MMU_DATA_LOAD, mmu_idx, retaddr); |
| 47 | } |
| 48 | |
| 49 | /** |
| 50 | * probe_access_flags: |
| 51 | * @env: CPUArchState |
| 52 | * @addr: guest virtual address to look up |
| 53 | * @size: size of the access |
| 54 | * @access_type: read, write or execute permission |
| 55 | * @mmu_idx: MMU index to use for lookup |
| 56 | * @nonfault: suppress the fault |
| 57 | * @phost: return value for host address |
| 58 | * @retaddr: return address for unwinding |
| 59 | * |
| 60 | * Similar to probe_access, loosely returning the TLB_FLAGS_MASK for |
| 61 | * the page, and storing the host address for RAM in @phost. |
| 62 | * |
| 63 | * If @nonfault is set, do not raise an exception but return TLB_INVALID_MASK. |
| 64 | * Do not handle watchpoints, but include TLB_WATCHPOINT in the returned flags. |
| 65 | * Do handle clean pages, so exclude TLB_NOTDIRY from the returned flags. |
| 66 | * For simplicity, all "mmio-like" flags are folded to TLB_MMIO. |
| 67 | */ |
| 68 | int probe_access_flags(CPUArchState *env, vaddr addr, int size, |
| 69 | MMUAccessType access_type, int mmu_idx, |
| 70 | bool nonfault, void **phost, uintptr_t retaddr); |
| 71 | |
| 72 | #ifndef CONFIG_USER_ONLY |
| 73 | |
| 74 | /** |
| 75 | * probe_access_full: |
| 76 | * Like probe_access_flags, except also return into @pfull. |
| 77 | * |
| 78 | * The CPUTLBEntryFull structure returned via @pfull is transient |
| 79 | * and must be consumed or copied immediately, before any further |
| 80 | * access or changes to TLB @mmu_idx. |
| 81 | * |
| 82 | * This function will not fault if @nonfault is set, but will |
| 83 | * return TLB_INVALID_MASK if the page is not mapped, or is not |
| 84 | * accessible with @access_type. |
| 85 | * |
| 86 | * This function will return TLB_MMIO in order to force the access |
| 87 | * to be handled out-of-line if plugins wish to instrument the access. |
| 88 | */ |
| 89 | int probe_access_full(CPUArchState *env, vaddr addr, int size, |
| 90 | MMUAccessType access_type, int mmu_idx, |
| 91 | bool nonfault, void **phost, |
| 92 | CPUTLBEntryFull **pfull, uintptr_t retaddr); |
| 93 | |
| 94 | /** |
| 95 | * probe_access_full_mmu: |
| 96 | * Like probe_access_full, except: |
| 97 | * |
| 98 | * This function is intended to be used for page table accesses by |
| 99 | * the target mmu itself. Since such page walking happens while |
| 100 | * handling another potential mmu fault, this function never raises |
| 101 | * exceptions (akin to @nonfault true for probe_access_full). |
| 102 | * Likewise this function does not trigger plugin instrumentation. |
| 103 | */ |
| 104 | int probe_access_full_mmu(CPUArchState *env, vaddr addr, int size, |
| 105 | MMUAccessType access_type, int mmu_idx, |
| 106 | void **phost, CPUTLBEntryFull **pfull); |
| 107 | |
| 108 | #endif /* !CONFIG_USER_ONLY */ |
| 109 | |
| 110 | /** |
| 111 | * tlb_vaddr_to_host: |
| 112 | * @env: CPUArchState |
| 113 | * @addr: guest virtual address to look up |
| 114 | * @access_type: 0 for read, 1 for write, 2 for execute |
| 115 | * @mmu_idx: MMU index to use for lookup |
| 116 | * |
| 117 | * Look up the specified guest virtual index in the TCG softmmu TLB. |
| 118 | * If we can translate a host virtual address suitable for direct RAM |
| 119 | * access, without causing a guest exception, then return it. |
| 120 | * Otherwise (TLB entry is for an I/O access, guest software |
| 121 | * TLB fill required, etc) return NULL. |
| 122 | */ |
| 123 | void *tlb_vaddr_to_host(CPUArchState *env, vaddr addr, |
| 124 | MMUAccessType access_type, int mmu_idx); |
| 125 | |
| 126 | #endif |