| 1 | #ifndef BLOCK_NVME_H |
| 2 | #define BLOCK_NVME_H |
| 3 | |
| 4 | #include "hw/core/registerfields.h" |
| 5 | |
| 6 | typedef struct QEMU_PACKED NvmeBar { |
| 7 | uint64_t cap; |
| 8 | uint32_t vs; |
| 9 | uint32_t intms; |
| 10 | uint32_t intmc; |
| 11 | uint32_t cc; |
| 12 | uint8_t rsvd24[4]; |
| 13 | uint32_t csts; |
| 14 | uint32_t nssr; |
| 15 | uint32_t aqa; |
| 16 | uint64_t asq; |
| 17 | uint64_t acq; |
| 18 | uint32_t cmbloc; |
| 19 | uint32_t cmbsz; |
| 20 | uint32_t bpinfo; |
| 21 | uint32_t bprsel; |
| 22 | uint64_t bpmbl; |
| 23 | uint64_t cmbmsc; |
| 24 | uint32_t cmbsts; |
| 25 | uint8_t rsvd92[3492]; |
| 26 | uint32_t pmrcap; |
| 27 | uint32_t pmrctl; |
| 28 | uint32_t pmrsts; |
| 29 | uint32_t pmrebs; |
| 30 | uint32_t pmrswtp; |
| 31 | uint32_t pmrmscl; |
| 32 | uint32_t pmrmscu; |
| 33 | uint8_t css[484]; |
| 34 | } NvmeBar; |
| 35 | |
| 36 | enum NvmeBarRegs { |
| 37 | NVME_REG_CAP = offsetof(NvmeBar, cap), |
| 38 | NVME_REG_VS = offsetof(NvmeBar, vs), |
| 39 | NVME_REG_INTMS = offsetof(NvmeBar, intms), |
| 40 | NVME_REG_INTMC = offsetof(NvmeBar, intmc), |
| 41 | NVME_REG_CC = offsetof(NvmeBar, cc), |
| 42 | NVME_REG_CSTS = offsetof(NvmeBar, csts), |
| 43 | NVME_REG_NSSR = offsetof(NvmeBar, nssr), |
| 44 | NVME_REG_AQA = offsetof(NvmeBar, aqa), |
| 45 | NVME_REG_ASQ = offsetof(NvmeBar, asq), |
| 46 | NVME_REG_ACQ = offsetof(NvmeBar, acq), |
| 47 | NVME_REG_CMBLOC = offsetof(NvmeBar, cmbloc), |
| 48 | NVME_REG_CMBSZ = offsetof(NvmeBar, cmbsz), |
| 49 | NVME_REG_BPINFO = offsetof(NvmeBar, bpinfo), |
| 50 | NVME_REG_BPRSEL = offsetof(NvmeBar, bprsel), |
| 51 | NVME_REG_BPMBL = offsetof(NvmeBar, bpmbl), |
| 52 | NVME_REG_CMBMSC = offsetof(NvmeBar, cmbmsc), |
| 53 | NVME_REG_CMBSTS = offsetof(NvmeBar, cmbsts), |
| 54 | NVME_REG_PMRCAP = offsetof(NvmeBar, pmrcap), |
| 55 | NVME_REG_PMRCTL = offsetof(NvmeBar, pmrctl), |
| 56 | NVME_REG_PMRSTS = offsetof(NvmeBar, pmrsts), |
| 57 | NVME_REG_PMREBS = offsetof(NvmeBar, pmrebs), |
| 58 | NVME_REG_PMRSWTP = offsetof(NvmeBar, pmrswtp), |
| 59 | NVME_REG_PMRMSCL = offsetof(NvmeBar, pmrmscl), |
| 60 | NVME_REG_PMRMSCU = offsetof(NvmeBar, pmrmscu), |
| 61 | }; |
| 62 | |
| 63 | typedef struct QEMU_PACKED NvmeEndGrpLog { |
| 64 | uint8_t critical_warning; |
| 65 | uint8_t rsvd[2]; |
| 66 | uint8_t avail_spare; |
| 67 | uint8_t avail_spare_thres; |
| 68 | uint8_t percet_used; |
| 69 | uint8_t rsvd1[26]; |
| 70 | uint64_t end_estimate[2]; |
| 71 | uint64_t data_units_read[2]; |
| 72 | uint64_t data_units_written[2]; |
| 73 | uint64_t media_units_written[2]; |
| 74 | uint64_t host_read_commands[2]; |
| 75 | uint64_t host_write_commands[2]; |
| 76 | uint64_t media_integrity_errors[2]; |
| 77 | uint64_t no_err_info_log_entries[2]; |
| 78 | uint8_t rsvd2[352]; |
| 79 | } NvmeEndGrpLog; |
| 80 | |
| 81 | enum NvmeCapShift { |
| 82 | CAP_MQES_SHIFT = 0, |
| 83 | CAP_CQR_SHIFT = 16, |
| 84 | CAP_AMS_SHIFT = 17, |
| 85 | CAP_TO_SHIFT = 24, |
| 86 | CAP_DSTRD_SHIFT = 32, |
| 87 | CAP_NSSRS_SHIFT = 36, |
| 88 | CAP_CSS_SHIFT = 37, |
| 89 | CAP_MPSMIN_SHIFT = 48, |
| 90 | CAP_MPSMAX_SHIFT = 52, |
| 91 | CAP_PMRS_SHIFT = 56, |
| 92 | CAP_CMBS_SHIFT = 57, |
| 93 | }; |
| 94 | |
| 95 | enum NvmeCapMask { |
| 96 | CAP_MQES_MASK = 0xffff, |
| 97 | CAP_CQR_MASK = 0x1, |
| 98 | CAP_AMS_MASK = 0x3, |
| 99 | CAP_TO_MASK = 0xff, |
| 100 | CAP_DSTRD_MASK = 0xf, |
| 101 | CAP_NSSRS_MASK = 0x1, |
| 102 | CAP_CSS_MASK = 0xff, |
| 103 | CAP_MPSMIN_MASK = 0xf, |
| 104 | CAP_MPSMAX_MASK = 0xf, |
| 105 | CAP_PMRS_MASK = 0x1, |
| 106 | CAP_CMBS_MASK = 0x1, |
| 107 | }; |
| 108 | |
| 109 | #define NVME_CAP_MQES(cap) (((cap) >> CAP_MQES_SHIFT) & CAP_MQES_MASK) |
| 110 | #define NVME_CAP_CQR(cap) (((cap) >> CAP_CQR_SHIFT) & CAP_CQR_MASK) |
| 111 | #define NVME_CAP_AMS(cap) (((cap) >> CAP_AMS_SHIFT) & CAP_AMS_MASK) |
| 112 | #define NVME_CAP_TO(cap) (((cap) >> CAP_TO_SHIFT) & CAP_TO_MASK) |
| 113 | #define NVME_CAP_DSTRD(cap) (((cap) >> CAP_DSTRD_SHIFT) & CAP_DSTRD_MASK) |
| 114 | #define NVME_CAP_NSSRS(cap) (((cap) >> CAP_NSSRS_SHIFT) & CAP_NSSRS_MASK) |
| 115 | #define NVME_CAP_CSS(cap) (((cap) >> CAP_CSS_SHIFT) & CAP_CSS_MASK) |
| 116 | #define NVME_CAP_MPSMIN(cap)(((cap) >> CAP_MPSMIN_SHIFT) & CAP_MPSMIN_MASK) |
| 117 | #define NVME_CAP_MPSMAX(cap)(((cap) >> CAP_MPSMAX_SHIFT) & CAP_MPSMAX_MASK) |
| 118 | #define NVME_CAP_PMRS(cap) (((cap) >> CAP_PMRS_SHIFT) & CAP_PMRS_MASK) |
| 119 | #define NVME_CAP_CMBS(cap) (((cap) >> CAP_CMBS_SHIFT) & CAP_CMBS_MASK) |
| 120 | |
| 121 | #define NVME_CAP_SET_MQES(cap, val) \ |
| 122 | ((cap) |= (uint64_t)((val) & CAP_MQES_MASK) << CAP_MQES_SHIFT) |
| 123 | #define NVME_CAP_SET_CQR(cap, val) \ |
| 124 | ((cap) |= (uint64_t)((val) & CAP_CQR_MASK) << CAP_CQR_SHIFT) |
| 125 | #define NVME_CAP_SET_AMS(cap, val) \ |
| 126 | ((cap) |= (uint64_t)((val) & CAP_AMS_MASK) << CAP_AMS_SHIFT) |
| 127 | #define NVME_CAP_SET_TO(cap, val) \ |
| 128 | ((cap) |= (uint64_t)((val) & CAP_TO_MASK) << CAP_TO_SHIFT) |
| 129 | #define NVME_CAP_SET_DSTRD(cap, val) \ |
| 130 | ((cap) |= (uint64_t)((val) & CAP_DSTRD_MASK) << CAP_DSTRD_SHIFT) |
| 131 | #define NVME_CAP_SET_NSSRS(cap, val) \ |
| 132 | ((cap) |= (uint64_t)((val) & CAP_NSSRS_MASK) << CAP_NSSRS_SHIFT) |
| 133 | #define NVME_CAP_SET_CSS(cap, val) \ |
| 134 | ((cap) |= (uint64_t)((val) & CAP_CSS_MASK) << CAP_CSS_SHIFT) |
| 135 | #define NVME_CAP_SET_MPSMIN(cap, val) \ |
| 136 | ((cap) |= (uint64_t)((val) & CAP_MPSMIN_MASK) << CAP_MPSMIN_SHIFT) |
| 137 | #define NVME_CAP_SET_MPSMAX(cap, val) \ |
| 138 | ((cap) |= (uint64_t)((val) & CAP_MPSMAX_MASK) << CAP_MPSMAX_SHIFT) |
| 139 | #define NVME_CAP_SET_PMRS(cap, val) \ |
| 140 | ((cap) |= (uint64_t)((val) & CAP_PMRS_MASK) << CAP_PMRS_SHIFT) |
| 141 | #define NVME_CAP_SET_CMBS(cap, val) \ |
| 142 | ((cap) |= (uint64_t)((val) & CAP_CMBS_MASK) << CAP_CMBS_SHIFT) |
| 143 | |
| 144 | #define NVME_MIGRATION_SUPPORTED_CAP_BITS ( \ |
| 145 | ((uint64_t)CAP_MQES_MASK << CAP_MQES_SHIFT) \ |
| 146 | | ((uint64_t)CAP_CQR_MASK << CAP_CQR_SHIFT) \ |
| 147 | | ((uint64_t)CAP_AMS_MASK << CAP_AMS_SHIFT) \ |
| 148 | | ((uint64_t)CAP_TO_MASK << CAP_TO_SHIFT) \ |
| 149 | | ((uint64_t)CAP_DSTRD_MASK << CAP_DSTRD_SHIFT) \ |
| 150 | | ((uint64_t)CAP_NSSRS_MASK << CAP_NSSRS_SHIFT) \ |
| 151 | | ((uint64_t)CAP_CSS_MASK << CAP_CSS_SHIFT) \ |
| 152 | | ((uint64_t)CAP_MPSMIN_MASK << CAP_MPSMIN_SHIFT) \ |
| 153 | | ((uint64_t)CAP_MPSMAX_MASK << CAP_MPSMAX_SHIFT) \ |
| 154 | ) |
| 155 | |
| 156 | enum NvmeCapCss { |
| 157 | NVME_CAP_CSS_NCSS = 1 << 0, |
| 158 | NVME_CAP_CSS_IOCSS = 1 << 6, |
| 159 | NVME_CAP_CSS_NOIOCSS = 1 << 7, |
| 160 | }; |
| 161 | |
| 162 | enum NvmeCcShift { |
| 163 | CC_EN_SHIFT = 0, |
| 164 | CC_CSS_SHIFT = 4, |
| 165 | CC_MPS_SHIFT = 7, |
| 166 | CC_AMS_SHIFT = 11, |
| 167 | CC_SHN_SHIFT = 14, |
| 168 | CC_IOSQES_SHIFT = 16, |
| 169 | CC_IOCQES_SHIFT = 20, |
| 170 | }; |
| 171 | |
| 172 | enum NvmeCcMask { |
| 173 | CC_EN_MASK = 0x1, |
| 174 | CC_CSS_MASK = 0x7, |
| 175 | CC_MPS_MASK = 0xf, |
| 176 | CC_AMS_MASK = 0x7, |
| 177 | CC_SHN_MASK = 0x3, |
| 178 | CC_IOSQES_MASK = 0xf, |
| 179 | CC_IOCQES_MASK = 0xf, |
| 180 | }; |
| 181 | |
| 182 | #define NVME_CC_EN(cc) ((cc >> CC_EN_SHIFT) & CC_EN_MASK) |
| 183 | #define NVME_CC_CSS(cc) ((cc >> CC_CSS_SHIFT) & CC_CSS_MASK) |
| 184 | #define NVME_CC_MPS(cc) ((cc >> CC_MPS_SHIFT) & CC_MPS_MASK) |
| 185 | #define NVME_CC_AMS(cc) ((cc >> CC_AMS_SHIFT) & CC_AMS_MASK) |
| 186 | #define NVME_CC_SHN(cc) ((cc >> CC_SHN_SHIFT) & CC_SHN_MASK) |
| 187 | #define NVME_CC_IOSQES(cc) ((cc >> CC_IOSQES_SHIFT) & CC_IOSQES_MASK) |
| 188 | #define NVME_CC_IOCQES(cc) ((cc >> CC_IOCQES_SHIFT) & CC_IOCQES_MASK) |
| 189 | |
| 190 | enum NvmeCcCss { |
| 191 | NVME_CC_CSS_NVM = 0x0, |
| 192 | NVME_CC_CSS_ALL = 0x6, |
| 193 | NVME_CC_CSS_ADMIN_ONLY = 0x7, |
| 194 | }; |
| 195 | |
| 196 | #define NVME_SET_CC_EN(cc, val) \ |
| 197 | (cc |= (uint32_t)((val) & CC_EN_MASK) << CC_EN_SHIFT) |
| 198 | #define NVME_SET_CC_CSS(cc, val) \ |
| 199 | (cc |= (uint32_t)((val) & CC_CSS_MASK) << CC_CSS_SHIFT) |
| 200 | #define NVME_SET_CC_MPS(cc, val) \ |
| 201 | (cc |= (uint32_t)((val) & CC_MPS_MASK) << CC_MPS_SHIFT) |
| 202 | #define NVME_SET_CC_AMS(cc, val) \ |
| 203 | (cc |= (uint32_t)((val) & CC_AMS_MASK) << CC_AMS_SHIFT) |
| 204 | #define NVME_SET_CC_SHN(cc, val) \ |
| 205 | (cc |= (uint32_t)((val) & CC_SHN_MASK) << CC_SHN_SHIFT) |
| 206 | #define NVME_SET_CC_IOSQES(cc, val) \ |
| 207 | (cc |= (uint32_t)((val) & CC_IOSQES_MASK) << CC_IOSQES_SHIFT) |
| 208 | #define NVME_SET_CC_IOCQES(cc, val) \ |
| 209 | (cc |= (uint32_t)((val) & CC_IOCQES_MASK) << CC_IOCQES_SHIFT) |
| 210 | |
| 211 | enum NvmeCstsShift { |
| 212 | CSTS_RDY_SHIFT = 0, |
| 213 | CSTS_CFS_SHIFT = 1, |
| 214 | CSTS_SHST_SHIFT = 2, |
| 215 | CSTS_NSSRO_SHIFT = 4, |
| 216 | }; |
| 217 | |
| 218 | enum NvmeCstsMask { |
| 219 | CSTS_RDY_MASK = 0x1, |
| 220 | CSTS_CFS_MASK = 0x1, |
| 221 | CSTS_SHST_MASK = 0x3, |
| 222 | CSTS_NSSRO_MASK = 0x1, |
| 223 | }; |
| 224 | |
| 225 | enum NvmeCsts { |
| 226 | NVME_CSTS_READY = 1 << CSTS_RDY_SHIFT, |
| 227 | NVME_CSTS_FAILED = 1 << CSTS_CFS_SHIFT, |
| 228 | NVME_CSTS_SHST_NORMAL = 0 << CSTS_SHST_SHIFT, |
| 229 | NVME_CSTS_SHST_PROGRESS = 1 << CSTS_SHST_SHIFT, |
| 230 | NVME_CSTS_SHST_COMPLETE = 2 << CSTS_SHST_SHIFT, |
| 231 | NVME_CSTS_NSSRO = 1 << CSTS_NSSRO_SHIFT, |
| 232 | }; |
| 233 | |
| 234 | #define NVME_CSTS_RDY(csts) ((csts >> CSTS_RDY_SHIFT) & CSTS_RDY_MASK) |
| 235 | #define NVME_CSTS_CFS(csts) ((csts >> CSTS_CFS_SHIFT) & CSTS_CFS_MASK) |
| 236 | #define NVME_CSTS_SHST(csts) ((csts >> CSTS_SHST_SHIFT) & CSTS_SHST_MASK) |
| 237 | #define NVME_CSTS_NSSRO(csts) ((csts >> CSTS_NSSRO_SHIFT) & CSTS_NSSRO_MASK) |
| 238 | |
| 239 | enum NvmeAqaShift { |
| 240 | AQA_ASQS_SHIFT = 0, |
| 241 | AQA_ACQS_SHIFT = 16, |
| 242 | }; |
| 243 | |
| 244 | enum NvmeAqaMask { |
| 245 | AQA_ASQS_MASK = 0xfff, |
| 246 | AQA_ACQS_MASK = 0xfff, |
| 247 | }; |
| 248 | |
| 249 | #define NVME_AQA_ASQS(aqa) ((aqa >> AQA_ASQS_SHIFT) & AQA_ASQS_MASK) |
| 250 | #define NVME_AQA_ACQS(aqa) ((aqa >> AQA_ACQS_SHIFT) & AQA_ACQS_MASK) |
| 251 | |
| 252 | enum NvmeCmblocShift { |
| 253 | CMBLOC_BIR_SHIFT = 0, |
| 254 | CMBLOC_CQMMS_SHIFT = 3, |
| 255 | CMBLOC_CQPDS_SHIFT = 4, |
| 256 | CMBLOC_CDPMLS_SHIFT = 5, |
| 257 | CMBLOC_CDPCILS_SHIFT = 6, |
| 258 | CMBLOC_CDMMMS_SHIFT = 7, |
| 259 | CMBLOC_CQDA_SHIFT = 8, |
| 260 | CMBLOC_OFST_SHIFT = 12, |
| 261 | }; |
| 262 | |
| 263 | enum NvmeCmblocMask { |
| 264 | CMBLOC_BIR_MASK = 0x7, |
| 265 | CMBLOC_CQMMS_MASK = 0x1, |
| 266 | CMBLOC_CQPDS_MASK = 0x1, |
| 267 | CMBLOC_CDPMLS_MASK = 0x1, |
| 268 | CMBLOC_CDPCILS_MASK = 0x1, |
| 269 | CMBLOC_CDMMMS_MASK = 0x1, |
| 270 | CMBLOC_CQDA_MASK = 0x1, |
| 271 | CMBLOC_OFST_MASK = 0xfffff, |
| 272 | }; |
| 273 | |
| 274 | #define NVME_CMBLOC_BIR(cmbloc) \ |
| 275 | ((cmbloc >> CMBLOC_BIR_SHIFT) & CMBLOC_BIR_MASK) |
| 276 | #define NVME_CMBLOC_CQMMS(cmbloc) \ |
| 277 | ((cmbloc >> CMBLOC_CQMMS_SHIFT) & CMBLOC_CQMMS_MASK) |
| 278 | #define NVME_CMBLOC_CQPDS(cmbloc) \ |
| 279 | ((cmbloc >> CMBLOC_CQPDS_SHIFT) & CMBLOC_CQPDS_MASK) |
| 280 | #define NVME_CMBLOC_CDPMLS(cmbloc) \ |
| 281 | ((cmbloc >> CMBLOC_CDPMLS_SHIFT) & CMBLOC_CDPMLS_MASK) |
| 282 | #define NVME_CMBLOC_CDPCILS(cmbloc) \ |
| 283 | ((cmbloc >> CMBLOC_CDPCILS_SHIFT) & CMBLOC_CDPCILS_MASK) |
| 284 | #define NVME_CMBLOC_CDMMMS(cmbloc) \ |
| 285 | ((cmbloc >> CMBLOC_CDMMMS_SHIFT) & CMBLOC_CDMMMS_MASK) |
| 286 | #define NVME_CMBLOC_CQDA(cmbloc) \ |
| 287 | ((cmbloc >> CMBLOC_CQDA_SHIFT) & CMBLOC_CQDA_MASK) |
| 288 | #define NVME_CMBLOC_OFST(cmbloc) \ |
| 289 | ((cmbloc >> CMBLOC_OFST_SHIFT) & CMBLOC_OFST_MASK) |
| 290 | |
| 291 | #define NVME_CMBLOC_SET_BIR(cmbloc, val) \ |
| 292 | (cmbloc |= (uint64_t)(val & CMBLOC_BIR_MASK) << CMBLOC_BIR_SHIFT) |
| 293 | #define NVME_CMBLOC_SET_CQMMS(cmbloc, val) \ |
| 294 | (cmbloc |= (uint64_t)(val & CMBLOC_CQMMS_MASK) << CMBLOC_CQMMS_SHIFT) |
| 295 | #define NVME_CMBLOC_SET_CQPDS(cmbloc, val) \ |
| 296 | (cmbloc |= (uint64_t)(val & CMBLOC_CQPDS_MASK) << CMBLOC_CQPDS_SHIFT) |
| 297 | #define NVME_CMBLOC_SET_CDPMLS(cmbloc, val) \ |
| 298 | (cmbloc |= (uint64_t)(val & CMBLOC_CDPMLS_MASK) << CMBLOC_CDPMLS_SHIFT) |
| 299 | #define NVME_CMBLOC_SET_CDPCILS(cmbloc, val) \ |
| 300 | (cmbloc |= (uint64_t)(val & CMBLOC_CDPCILS_MASK) << CMBLOC_CDPCILS_SHIFT) |
| 301 | #define NVME_CMBLOC_SET_CDMMMS(cmbloc, val) \ |
| 302 | (cmbloc |= (uint64_t)(val & CMBLOC_CDMMMS_MASK) << CMBLOC_CDMMMS_SHIFT) |
| 303 | #define NVME_CMBLOC_SET_CQDA(cmbloc, val) \ |
| 304 | (cmbloc |= (uint64_t)(val & CMBLOC_CQDA_MASK) << CMBLOC_CQDA_SHIFT) |
| 305 | #define NVME_CMBLOC_SET_OFST(cmbloc, val) \ |
| 306 | (cmbloc |= (uint64_t)(val & CMBLOC_OFST_MASK) << CMBLOC_OFST_SHIFT) |
| 307 | |
| 308 | #define NVME_CMBMSMC_SET_CRE (cmbmsc, val) \ |
| 309 | (cmbmsc |= (uint64_t)(val & CMBLOC_OFST_MASK) << CMBMSC_CRE_SHIFT) |
| 310 | |
| 311 | enum NvmeCmbszShift { |
| 312 | CMBSZ_SQS_SHIFT = 0, |
| 313 | CMBSZ_CQS_SHIFT = 1, |
| 314 | CMBSZ_LISTS_SHIFT = 2, |
| 315 | CMBSZ_RDS_SHIFT = 3, |
| 316 | CMBSZ_WDS_SHIFT = 4, |
| 317 | CMBSZ_SZU_SHIFT = 8, |
| 318 | CMBSZ_SZ_SHIFT = 12, |
| 319 | }; |
| 320 | |
| 321 | enum NvmeCmbszMask { |
| 322 | CMBSZ_SQS_MASK = 0x1, |
| 323 | CMBSZ_CQS_MASK = 0x1, |
| 324 | CMBSZ_LISTS_MASK = 0x1, |
| 325 | CMBSZ_RDS_MASK = 0x1, |
| 326 | CMBSZ_WDS_MASK = 0x1, |
| 327 | CMBSZ_SZU_MASK = 0xf, |
| 328 | CMBSZ_SZ_MASK = 0xfffff, |
| 329 | }; |
| 330 | |
| 331 | #define NVME_CMBSZ_SQS(cmbsz) ((cmbsz >> CMBSZ_SQS_SHIFT) & CMBSZ_SQS_MASK) |
| 332 | #define NVME_CMBSZ_CQS(cmbsz) ((cmbsz >> CMBSZ_CQS_SHIFT) & CMBSZ_CQS_MASK) |
| 333 | #define NVME_CMBSZ_LISTS(cmbsz)((cmbsz >> CMBSZ_LISTS_SHIFT) & CMBSZ_LISTS_MASK) |
| 334 | #define NVME_CMBSZ_RDS(cmbsz) ((cmbsz >> CMBSZ_RDS_SHIFT) & CMBSZ_RDS_MASK) |
| 335 | #define NVME_CMBSZ_WDS(cmbsz) ((cmbsz >> CMBSZ_WDS_SHIFT) & CMBSZ_WDS_MASK) |
| 336 | #define NVME_CMBSZ_SZU(cmbsz) ((cmbsz >> CMBSZ_SZU_SHIFT) & CMBSZ_SZU_MASK) |
| 337 | #define NVME_CMBSZ_SZ(cmbsz) ((cmbsz >> CMBSZ_SZ_SHIFT) & CMBSZ_SZ_MASK) |
| 338 | |
| 339 | #define NVME_CMBSZ_SET_SQS(cmbsz, val) \ |
| 340 | (cmbsz |= (uint64_t)(val & CMBSZ_SQS_MASK) << CMBSZ_SQS_SHIFT) |
| 341 | #define NVME_CMBSZ_SET_CQS(cmbsz, val) \ |
| 342 | (cmbsz |= (uint64_t)(val & CMBSZ_CQS_MASK) << CMBSZ_CQS_SHIFT) |
| 343 | #define NVME_CMBSZ_SET_LISTS(cmbsz, val) \ |
| 344 | (cmbsz |= (uint64_t)(val & CMBSZ_LISTS_MASK) << CMBSZ_LISTS_SHIFT) |
| 345 | #define NVME_CMBSZ_SET_RDS(cmbsz, val) \ |
| 346 | (cmbsz |= (uint64_t)(val & CMBSZ_RDS_MASK) << CMBSZ_RDS_SHIFT) |
| 347 | #define NVME_CMBSZ_SET_WDS(cmbsz, val) \ |
| 348 | (cmbsz |= (uint64_t)(val & CMBSZ_WDS_MASK) << CMBSZ_WDS_SHIFT) |
| 349 | #define NVME_CMBSZ_SET_SZU(cmbsz, val) \ |
| 350 | (cmbsz |= (uint64_t)(val & CMBSZ_SZU_MASK) << CMBSZ_SZU_SHIFT) |
| 351 | #define NVME_CMBSZ_SET_SZ(cmbsz, val) \ |
| 352 | (cmbsz |= (uint64_t)(val & CMBSZ_SZ_MASK) << CMBSZ_SZ_SHIFT) |
| 353 | |
| 354 | #define NVME_CMBSZ_GETSIZE(cmbsz) \ |
| 355 | (NVME_CMBSZ_SZ(cmbsz) * (1 << (12 + 4 * NVME_CMBSZ_SZU(cmbsz)))) |
| 356 | |
| 357 | enum NvmeCmbmscShift { |
| 358 | CMBMSC_CRE_SHIFT = 0, |
| 359 | CMBMSC_CMSE_SHIFT = 1, |
| 360 | CMBMSC_CBA_SHIFT = 12, |
| 361 | }; |
| 362 | |
| 363 | enum NvmeCmbmscMask { |
| 364 | CMBMSC_CRE_MASK = 0x1, |
| 365 | CMBMSC_CMSE_MASK = 0x1, |
| 366 | CMBMSC_CBA_MASK = ((1ULL << 52) - 1), |
| 367 | }; |
| 368 | |
| 369 | #define NVME_CMBMSC_CRE(cmbmsc) \ |
| 370 | ((cmbmsc >> CMBMSC_CRE_SHIFT) & CMBMSC_CRE_MASK) |
| 371 | #define NVME_CMBMSC_CMSE(cmbmsc) \ |
| 372 | ((cmbmsc >> CMBMSC_CMSE_SHIFT) & CMBMSC_CMSE_MASK) |
| 373 | #define NVME_CMBMSC_CBA(cmbmsc) \ |
| 374 | ((cmbmsc >> CMBMSC_CBA_SHIFT) & CMBMSC_CBA_MASK) |
| 375 | |
| 376 | |
| 377 | #define NVME_CMBMSC_SET_CRE(cmbmsc, val) \ |
| 378 | (cmbmsc |= (uint64_t)(val & CMBMSC_CRE_MASK) << CMBMSC_CRE_SHIFT) |
| 379 | #define NVME_CMBMSC_SET_CMSE(cmbmsc, val) \ |
| 380 | (cmbmsc |= (uint64_t)(val & CMBMSC_CMSE_MASK) << CMBMSC_CMSE_SHIFT) |
| 381 | #define NVME_CMBMSC_SET_CBA(cmbmsc, val) \ |
| 382 | (cmbmsc |= (uint64_t)(val & CMBMSC_CBA_MASK) << CMBMSC_CBA_SHIFT) |
| 383 | |
| 384 | enum NvmeCmbstsShift { |
| 385 | CMBSTS_CBAI_SHIFT = 0, |
| 386 | }; |
| 387 | enum NvmeCmbstsMask { |
| 388 | CMBSTS_CBAI_MASK = 0x1, |
| 389 | }; |
| 390 | |
| 391 | #define NVME_CMBSTS_CBAI(cmbsts) \ |
| 392 | ((cmbsts >> CMBSTS_CBAI_SHIFT) & CMBSTS_CBAI_MASK) |
| 393 | |
| 394 | #define NVME_CMBSTS_SET_CBAI(cmbsts, val) \ |
| 395 | (cmbsts |= (uint64_t)(val & CMBSTS_CBAI_MASK) << CMBSTS_CBAI_SHIFT) |
| 396 | |
| 397 | enum NvmePmrcapShift { |
| 398 | PMRCAP_RDS_SHIFT = 3, |
| 399 | PMRCAP_WDS_SHIFT = 4, |
| 400 | PMRCAP_BIR_SHIFT = 5, |
| 401 | PMRCAP_PMRTU_SHIFT = 8, |
| 402 | PMRCAP_PMRWBM_SHIFT = 10, |
| 403 | PMRCAP_PMRTO_SHIFT = 16, |
| 404 | PMRCAP_CMSS_SHIFT = 24, |
| 405 | }; |
| 406 | |
| 407 | enum NvmePmrcapMask { |
| 408 | PMRCAP_RDS_MASK = 0x1, |
| 409 | PMRCAP_WDS_MASK = 0x1, |
| 410 | PMRCAP_BIR_MASK = 0x7, |
| 411 | PMRCAP_PMRTU_MASK = 0x3, |
| 412 | PMRCAP_PMRWBM_MASK = 0xf, |
| 413 | PMRCAP_PMRTO_MASK = 0xff, |
| 414 | PMRCAP_CMSS_MASK = 0x1, |
| 415 | }; |
| 416 | |
| 417 | #define NVME_PMRCAP_RDS(pmrcap) \ |
| 418 | ((pmrcap >> PMRCAP_RDS_SHIFT) & PMRCAP_RDS_MASK) |
| 419 | #define NVME_PMRCAP_WDS(pmrcap) \ |
| 420 | ((pmrcap >> PMRCAP_WDS_SHIFT) & PMRCAP_WDS_MASK) |
| 421 | #define NVME_PMRCAP_BIR(pmrcap) \ |
| 422 | ((pmrcap >> PMRCAP_BIR_SHIFT) & PMRCAP_BIR_MASK) |
| 423 | #define NVME_PMRCAP_PMRTU(pmrcap) \ |
| 424 | ((pmrcap >> PMRCAP_PMRTU_SHIFT) & PMRCAP_PMRTU_MASK) |
| 425 | #define NVME_PMRCAP_PMRWBM(pmrcap) \ |
| 426 | ((pmrcap >> PMRCAP_PMRWBM_SHIFT) & PMRCAP_PMRWBM_MASK) |
| 427 | #define NVME_PMRCAP_PMRTO(pmrcap) \ |
| 428 | ((pmrcap >> PMRCAP_PMRTO_SHIFT) & PMRCAP_PMRTO_MASK) |
| 429 | #define NVME_PMRCAP_CMSS(pmrcap) \ |
| 430 | ((pmrcap >> PMRCAP_CMSS_SHIFT) & PMRCAP_CMSS_MASK) |
| 431 | |
| 432 | #define NVME_PMRCAP_SET_RDS(pmrcap, val) \ |
| 433 | (pmrcap |= (uint64_t)(val & PMRCAP_RDS_MASK) << PMRCAP_RDS_SHIFT) |
| 434 | #define NVME_PMRCAP_SET_WDS(pmrcap, val) \ |
| 435 | (pmrcap |= (uint64_t)(val & PMRCAP_WDS_MASK) << PMRCAP_WDS_SHIFT) |
| 436 | #define NVME_PMRCAP_SET_BIR(pmrcap, val) \ |
| 437 | (pmrcap |= (uint64_t)(val & PMRCAP_BIR_MASK) << PMRCAP_BIR_SHIFT) |
| 438 | #define NVME_PMRCAP_SET_PMRTU(pmrcap, val) \ |
| 439 | (pmrcap |= (uint64_t)(val & PMRCAP_PMRTU_MASK) << PMRCAP_PMRTU_SHIFT) |
| 440 | #define NVME_PMRCAP_SET_PMRWBM(pmrcap, val) \ |
| 441 | (pmrcap |= (uint64_t)(val & PMRCAP_PMRWBM_MASK) << PMRCAP_PMRWBM_SHIFT) |
| 442 | #define NVME_PMRCAP_SET_PMRTO(pmrcap, val) \ |
| 443 | (pmrcap |= (uint64_t)(val & PMRCAP_PMRTO_MASK) << PMRCAP_PMRTO_SHIFT) |
| 444 | #define NVME_PMRCAP_SET_CMSS(pmrcap, val) \ |
| 445 | (pmrcap |= (uint64_t)(val & PMRCAP_CMSS_MASK) << PMRCAP_CMSS_SHIFT) |
| 446 | |
| 447 | enum NvmePmrctlShift { |
| 448 | PMRCTL_EN_SHIFT = 0, |
| 449 | }; |
| 450 | |
| 451 | enum NvmePmrctlMask { |
| 452 | PMRCTL_EN_MASK = 0x1, |
| 453 | }; |
| 454 | |
| 455 | #define NVME_PMRCTL_EN(pmrctl) ((pmrctl >> PMRCTL_EN_SHIFT) & PMRCTL_EN_MASK) |
| 456 | |
| 457 | #define NVME_PMRCTL_SET_EN(pmrctl, val) \ |
| 458 | (pmrctl |= (uint64_t)(val & PMRCTL_EN_MASK) << PMRCTL_EN_SHIFT) |
| 459 | |
| 460 | enum NvmePmrstsShift { |
| 461 | PMRSTS_ERR_SHIFT = 0, |
| 462 | PMRSTS_NRDY_SHIFT = 8, |
| 463 | PMRSTS_HSTS_SHIFT = 9, |
| 464 | PMRSTS_CBAI_SHIFT = 12, |
| 465 | }; |
| 466 | |
| 467 | enum NvmePmrstsMask { |
| 468 | PMRSTS_ERR_MASK = 0xff, |
| 469 | PMRSTS_NRDY_MASK = 0x1, |
| 470 | PMRSTS_HSTS_MASK = 0x7, |
| 471 | PMRSTS_CBAI_MASK = 0x1, |
| 472 | }; |
| 473 | |
| 474 | #define NVME_PMRSTS_ERR(pmrsts) \ |
| 475 | ((pmrsts >> PMRSTS_ERR_SHIFT) & PMRSTS_ERR_MASK) |
| 476 | #define NVME_PMRSTS_NRDY(pmrsts) \ |
| 477 | ((pmrsts >> PMRSTS_NRDY_SHIFT) & PMRSTS_NRDY_MASK) |
| 478 | #define NVME_PMRSTS_HSTS(pmrsts) \ |
| 479 | ((pmrsts >> PMRSTS_HSTS_SHIFT) & PMRSTS_HSTS_MASK) |
| 480 | #define NVME_PMRSTS_CBAI(pmrsts) \ |
| 481 | ((pmrsts >> PMRSTS_CBAI_SHIFT) & PMRSTS_CBAI_MASK) |
| 482 | |
| 483 | #define NVME_PMRSTS_SET_ERR(pmrsts, val) \ |
| 484 | (pmrsts |= (uint64_t)(val & PMRSTS_ERR_MASK) << PMRSTS_ERR_SHIFT) |
| 485 | #define NVME_PMRSTS_SET_NRDY(pmrsts, val) \ |
| 486 | (pmrsts |= (uint64_t)(val & PMRSTS_NRDY_MASK) << PMRSTS_NRDY_SHIFT) |
| 487 | #define NVME_PMRSTS_SET_HSTS(pmrsts, val) \ |
| 488 | (pmrsts |= (uint64_t)(val & PMRSTS_HSTS_MASK) << PMRSTS_HSTS_SHIFT) |
| 489 | #define NVME_PMRSTS_SET_CBAI(pmrsts, val) \ |
| 490 | (pmrsts |= (uint64_t)(val & PMRSTS_CBAI_MASK) << PMRSTS_CBAI_SHIFT) |
| 491 | |
| 492 | enum NvmePmrebsShift { |
| 493 | PMREBS_PMRSZU_SHIFT = 0, |
| 494 | PMREBS_RBB_SHIFT = 4, |
| 495 | PMREBS_PMRWBZ_SHIFT = 8, |
| 496 | }; |
| 497 | |
| 498 | enum NvmePmrebsMask { |
| 499 | PMREBS_PMRSZU_MASK = 0xf, |
| 500 | PMREBS_RBB_MASK = 0x1, |
| 501 | PMREBS_PMRWBZ_MASK = 0xffffff, |
| 502 | }; |
| 503 | |
| 504 | #define NVME_PMREBS_PMRSZU(pmrebs) \ |
| 505 | ((pmrebs >> PMREBS_PMRSZU_SHIFT) & PMREBS_PMRSZU_MASK) |
| 506 | #define NVME_PMREBS_RBB(pmrebs) \ |
| 507 | ((pmrebs >> PMREBS_RBB_SHIFT) & PMREBS_RBB_MASK) |
| 508 | #define NVME_PMREBS_PMRWBZ(pmrebs) \ |
| 509 | ((pmrebs >> PMREBS_PMRWBZ_SHIFT) & PMREBS_PMRWBZ_MASK) |
| 510 | |
| 511 | #define NVME_PMREBS_SET_PMRSZU(pmrebs, val) \ |
| 512 | (pmrebs |= (uint64_t)(val & PMREBS_PMRSZU_MASK) << PMREBS_PMRSZU_SHIFT) |
| 513 | #define NVME_PMREBS_SET_RBB(pmrebs, val) \ |
| 514 | (pmrebs |= (uint64_t)(val & PMREBS_RBB_MASK) << PMREBS_RBB_SHIFT) |
| 515 | #define NVME_PMREBS_SET_PMRWBZ(pmrebs, val) \ |
| 516 | (pmrebs |= (uint64_t)(val & PMREBS_PMRWBZ_MASK) << PMREBS_PMRWBZ_SHIFT) |
| 517 | |
| 518 | enum NvmePmrswtpShift { |
| 519 | PMRSWTP_PMRSWTU_SHIFT = 0, |
| 520 | PMRSWTP_PMRSWTV_SHIFT = 8, |
| 521 | }; |
| 522 | |
| 523 | enum NvmePmrswtpMask { |
| 524 | PMRSWTP_PMRSWTU_MASK = 0xf, |
| 525 | PMRSWTP_PMRSWTV_MASK = 0xffffff, |
| 526 | }; |
| 527 | |
| 528 | #define NVME_PMRSWTP_PMRSWTU(pmrswtp) \ |
| 529 | ((pmrswtp >> PMRSWTP_PMRSWTU_SHIFT) & PMRSWTP_PMRSWTU_MASK) |
| 530 | #define NVME_PMRSWTP_PMRSWTV(pmrswtp) \ |
| 531 | ((pmrswtp >> PMRSWTP_PMRSWTV_SHIFT) & PMRSWTP_PMRSWTV_MASK) |
| 532 | |
| 533 | #define NVME_PMRSWTP_SET_PMRSWTU(pmrswtp, val) \ |
| 534 | (pmrswtp |= (uint64_t)(val & PMRSWTP_PMRSWTU_MASK) << PMRSWTP_PMRSWTU_SHIFT) |
| 535 | #define NVME_PMRSWTP_SET_PMRSWTV(pmrswtp, val) \ |
| 536 | (pmrswtp |= (uint64_t)(val & PMRSWTP_PMRSWTV_MASK) << PMRSWTP_PMRSWTV_SHIFT) |
| 537 | |
| 538 | enum NvmePmrmsclShift { |
| 539 | PMRMSCL_CMSE_SHIFT = 1, |
| 540 | PMRMSCL_CBA_SHIFT = 12, |
| 541 | }; |
| 542 | |
| 543 | enum NvmePmrmsclMask { |
| 544 | PMRMSCL_CMSE_MASK = 0x1, |
| 545 | PMRMSCL_CBA_MASK = 0xfffff, |
| 546 | }; |
| 547 | |
| 548 | #define NVME_PMRMSCL_CMSE(pmrmscl) \ |
| 549 | ((pmrmscl >> PMRMSCL_CMSE_SHIFT) & PMRMSCL_CMSE_MASK) |
| 550 | #define NVME_PMRMSCL_CBA(pmrmscl) \ |
| 551 | ((pmrmscl >> PMRMSCL_CBA_SHIFT) & PMRMSCL_CBA_MASK) |
| 552 | |
| 553 | #define NVME_PMRMSCL_SET_CMSE(pmrmscl, val) \ |
| 554 | (pmrmscl |= (uint32_t)(val & PMRMSCL_CMSE_MASK) << PMRMSCL_CMSE_SHIFT) |
| 555 | #define NVME_PMRMSCL_SET_CBA(pmrmscl, val) \ |
| 556 | (pmrmscl |= (uint32_t)(val & PMRMSCL_CBA_MASK) << PMRMSCL_CBA_SHIFT) |
| 557 | |
| 558 | enum NvmeSglDescriptorType { |
| 559 | NVME_SGL_DESCR_TYPE_DATA_BLOCK = 0x0, |
| 560 | NVME_SGL_DESCR_TYPE_BIT_BUCKET = 0x1, |
| 561 | NVME_SGL_DESCR_TYPE_SEGMENT = 0x2, |
| 562 | NVME_SGL_DESCR_TYPE_LAST_SEGMENT = 0x3, |
| 563 | NVME_SGL_DESCR_TYPE_KEYED_DATA_BLOCK = 0x4, |
| 564 | |
| 565 | NVME_SGL_DESCR_TYPE_VENDOR_SPECIFIC = 0xf, |
| 566 | }; |
| 567 | |
| 568 | enum NvmeSglDescriptorSubtype { |
| 569 | NVME_SGL_DESCR_SUBTYPE_ADDRESS = 0x0, |
| 570 | }; |
| 571 | |
| 572 | typedef struct QEMU_PACKED NvmeSglDescriptor { |
| 573 | uint64_t addr; |
| 574 | uint32_t len; |
| 575 | uint8_t rsvd[3]; |
| 576 | uint8_t type; |
| 577 | } NvmeSglDescriptor; |
| 578 | |
| 579 | #define NVME_SGL_TYPE(type) ((type >> 4) & 0xf) |
| 580 | #define NVME_SGL_SUBTYPE(type) (type & 0xf) |
| 581 | |
| 582 | typedef union NvmeCmdDptr { |
| 583 | struct { |
| 584 | uint64_t prp1; |
| 585 | uint64_t prp2; |
| 586 | }; |
| 587 | |
| 588 | NvmeSglDescriptor sgl; |
| 589 | } NvmeCmdDptr; |
| 590 | |
| 591 | enum NvmePsdt { |
| 592 | NVME_PSDT_PRP = 0x0, |
| 593 | NVME_PSDT_SGL_MPTR_CONTIGUOUS = 0x1, |
| 594 | NVME_PSDT_SGL_MPTR_SGL = 0x2, |
| 595 | }; |
| 596 | |
| 597 | typedef struct QEMU_PACKED NvmeCmd { |
| 598 | uint8_t opcode; |
| 599 | uint8_t flags; |
| 600 | uint16_t cid; |
| 601 | uint32_t nsid; |
| 602 | uint64_t res1; |
| 603 | uint64_t mptr; |
| 604 | NvmeCmdDptr dptr; |
| 605 | uint32_t cdw10; |
| 606 | uint32_t cdw11; |
| 607 | uint32_t cdw12; |
| 608 | uint32_t cdw13; |
| 609 | uint32_t cdw14; |
| 610 | uint32_t cdw15; |
| 611 | } NvmeCmd; |
| 612 | |
| 613 | #define NVME_CMD_FLAGS_FUSE(flags) (flags & 0x3) |
| 614 | #define NVME_CMD_FLAGS_PSDT(flags) ((flags >> 6) & 0x3) |
| 615 | |
| 616 | enum NvmeAdminCommands { |
| 617 | NVME_ADM_CMD_DELETE_SQ = 0x00, |
| 618 | NVME_ADM_CMD_CREATE_SQ = 0x01, |
| 619 | NVME_ADM_CMD_GET_LOG_PAGE = 0x02, |
| 620 | NVME_ADM_CMD_DELETE_CQ = 0x04, |
| 621 | NVME_ADM_CMD_CREATE_CQ = 0x05, |
| 622 | NVME_ADM_CMD_IDENTIFY = 0x06, |
| 623 | NVME_ADM_CMD_ABORT = 0x08, |
| 624 | NVME_ADM_CMD_SET_FEATURES = 0x09, |
| 625 | NVME_ADM_CMD_GET_FEATURES = 0x0a, |
| 626 | NVME_ADM_CMD_ASYNC_EV_REQ = 0x0c, |
| 627 | NVME_ADM_CMD_ACTIVATE_FW = 0x10, |
| 628 | NVME_ADM_CMD_DOWNLOAD_FW = 0x11, |
| 629 | NVME_ADM_CMD_NS_ATTACHMENT = 0x15, |
| 630 | NVME_ADM_CMD_DIRECTIVE_SEND = 0x19, |
| 631 | NVME_ADM_CMD_VIRT_MNGMT = 0x1c, |
| 632 | NVME_ADM_CMD_DIRECTIVE_RECV = 0x1a, |
| 633 | NVME_ADM_CMD_DBBUF_CONFIG = 0x7c, |
| 634 | NVME_ADM_CMD_FORMAT_NVM = 0x80, |
| 635 | NVME_ADM_CMD_SECURITY_SEND = 0x81, |
| 636 | NVME_ADM_CMD_SECURITY_RECV = 0x82, |
| 637 | }; |
| 638 | |
| 639 | enum NvmeIoCommands { |
| 640 | NVME_CMD_FLUSH = 0x00, |
| 641 | NVME_CMD_WRITE = 0x01, |
| 642 | NVME_CMD_READ = 0x02, |
| 643 | NVME_CMD_WRITE_UNCOR = 0x04, |
| 644 | NVME_CMD_COMPARE = 0x05, |
| 645 | NVME_CMD_WRITE_ZEROES = 0x08, |
| 646 | NVME_CMD_DSM = 0x09, |
| 647 | NVME_CMD_VERIFY = 0x0c, |
| 648 | NVME_CMD_IO_MGMT_RECV = 0x12, |
| 649 | NVME_CMD_COPY = 0x19, |
| 650 | NVME_CMD_IO_MGMT_SEND = 0x1d, |
| 651 | NVME_CMD_ZONE_MGMT_SEND = 0x79, |
| 652 | NVME_CMD_ZONE_MGMT_RECV = 0x7a, |
| 653 | NVME_CMD_ZONE_APPEND = 0x7d, |
| 654 | }; |
| 655 | |
| 656 | typedef struct QEMU_PACKED NvmeDeleteQ { |
| 657 | uint8_t opcode; |
| 658 | uint8_t flags; |
| 659 | uint16_t cid; |
| 660 | uint32_t rsvd1[9]; |
| 661 | uint16_t qid; |
| 662 | uint16_t rsvd10; |
| 663 | uint32_t rsvd11[5]; |
| 664 | } NvmeDeleteQ; |
| 665 | |
| 666 | typedef struct QEMU_PACKED NvmeCreateCq { |
| 667 | uint8_t opcode; |
| 668 | uint8_t flags; |
| 669 | uint16_t cid; |
| 670 | uint32_t rsvd1[5]; |
| 671 | uint64_t prp1; |
| 672 | uint64_t rsvd8; |
| 673 | uint16_t cqid; |
| 674 | uint16_t qsize; |
| 675 | uint16_t cq_flags; |
| 676 | uint16_t irq_vector; |
| 677 | uint32_t rsvd12[4]; |
| 678 | } NvmeCreateCq; |
| 679 | |
| 680 | #define NVME_CQ_FLAGS_PC(cq_flags) (cq_flags & 0x1) |
| 681 | #define NVME_CQ_FLAGS_IEN(cq_flags) ((cq_flags >> 1) & 0x1) |
| 682 | |
| 683 | enum NvmeFlagsCq { |
| 684 | NVME_CQ_PC = 1, |
| 685 | NVME_CQ_IEN = 2, |
| 686 | }; |
| 687 | |
| 688 | typedef struct QEMU_PACKED NvmeCreateSq { |
| 689 | uint8_t opcode; |
| 690 | uint8_t flags; |
| 691 | uint16_t cid; |
| 692 | uint32_t rsvd1[5]; |
| 693 | uint64_t prp1; |
| 694 | uint64_t rsvd8; |
| 695 | uint16_t sqid; |
| 696 | uint16_t qsize; |
| 697 | uint16_t sq_flags; |
| 698 | uint16_t cqid; |
| 699 | uint32_t rsvd12[4]; |
| 700 | } NvmeCreateSq; |
| 701 | |
| 702 | #define NVME_SQ_FLAGS_PC(sq_flags) (sq_flags & 0x1) |
| 703 | #define NVME_SQ_FLAGS_QPRIO(sq_flags) ((sq_flags >> 1) & 0x3) |
| 704 | |
| 705 | enum NvmeFlagsSq { |
| 706 | NVME_SQ_PC = 1, |
| 707 | |
| 708 | NVME_SQ_PRIO_URGENT = 0, |
| 709 | NVME_SQ_PRIO_HIGH = 1, |
| 710 | NVME_SQ_PRIO_NORMAL = 2, |
| 711 | NVME_SQ_PRIO_LOW = 3, |
| 712 | }; |
| 713 | |
| 714 | typedef struct QEMU_PACKED NvmeIdentify { |
| 715 | uint8_t opcode; |
| 716 | uint8_t flags; |
| 717 | uint16_t cid; |
| 718 | uint32_t nsid; |
| 719 | uint64_t rsvd2[2]; |
| 720 | uint64_t prp1; |
| 721 | uint64_t prp2; |
| 722 | uint8_t cns; |
| 723 | uint8_t rsvd10; |
| 724 | uint16_t ctrlid; |
| 725 | uint16_t nvmsetid; |
| 726 | uint8_t rsvd11; |
| 727 | uint8_t csi; |
| 728 | uint32_t rsvd12[4]; |
| 729 | } NvmeIdentify; |
| 730 | |
| 731 | typedef struct QEMU_PACKED NvmeRwCmd { |
| 732 | uint8_t opcode; |
| 733 | uint8_t flags; |
| 734 | uint16_t cid; |
| 735 | uint32_t nsid; |
| 736 | uint32_t cdw2; |
| 737 | uint32_t cdw3; |
| 738 | uint64_t mptr; |
| 739 | NvmeCmdDptr dptr; |
| 740 | uint64_t slba; |
| 741 | uint16_t nlb; |
| 742 | uint16_t control; |
| 743 | uint8_t dsmgmt; |
| 744 | uint8_t rsvd; |
| 745 | uint16_t dspec; |
| 746 | uint32_t reftag; |
| 747 | uint16_t apptag; |
| 748 | uint16_t appmask; |
| 749 | } NvmeRwCmd; |
| 750 | |
| 751 | enum { |
| 752 | NVME_RW_LR = 1 << 15, |
| 753 | NVME_RW_FUA = 1 << 14, |
| 754 | NVME_RW_DSM_FREQ_UNSPEC = 0, |
| 755 | NVME_RW_DSM_FREQ_TYPICAL = 1, |
| 756 | NVME_RW_DSM_FREQ_RARE = 2, |
| 757 | NVME_RW_DSM_FREQ_READS = 3, |
| 758 | NVME_RW_DSM_FREQ_WRITES = 4, |
| 759 | NVME_RW_DSM_FREQ_RW = 5, |
| 760 | NVME_RW_DSM_FREQ_ONCE = 6, |
| 761 | NVME_RW_DSM_FREQ_PREFETCH = 7, |
| 762 | NVME_RW_DSM_FREQ_TEMP = 8, |
| 763 | NVME_RW_DSM_LATENCY_NONE = 0 << 4, |
| 764 | NVME_RW_DSM_LATENCY_IDLE = 1 << 4, |
| 765 | NVME_RW_DSM_LATENCY_NORM = 2 << 4, |
| 766 | NVME_RW_DSM_LATENCY_LOW = 3 << 4, |
| 767 | NVME_RW_DSM_SEQ_REQ = 1 << 6, |
| 768 | NVME_RW_DSM_COMPRESSED = 1 << 7, |
| 769 | NVME_RW_PIREMAP = 1 << 9, |
| 770 | NVME_RW_PRINFO_PRACT = 1 << 13, |
| 771 | NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12, |
| 772 | NVME_RW_PRINFO_PRCHK_APP = 1 << 11, |
| 773 | NVME_RW_PRINFO_PRCHK_REF = 1 << 10, |
| 774 | NVME_RW_PRINFO_PRCHK_MASK = 7 << 10, |
| 775 | }; |
| 776 | |
| 777 | #define NVME_RW_PRINFO(control) ((control >> 10) & 0xf) |
| 778 | |
| 779 | enum { |
| 780 | NVME_PRINFO_PRACT = 1 << 3, |
| 781 | NVME_PRINFO_PRCHK_GUARD = 1 << 2, |
| 782 | NVME_PRINFO_PRCHK_APP = 1 << 1, |
| 783 | NVME_PRINFO_PRCHK_REF = 1 << 0, |
| 784 | NVME_PRINFO_PRCHK_MASK = 7 << 0, |
| 785 | }; |
| 786 | |
| 787 | typedef struct QEMU_PACKED NvmeDsmCmd { |
| 788 | uint8_t opcode; |
| 789 | uint8_t flags; |
| 790 | uint16_t cid; |
| 791 | uint32_t nsid; |
| 792 | uint64_t rsvd2[2]; |
| 793 | NvmeCmdDptr dptr; |
| 794 | uint32_t nr; |
| 795 | uint32_t attributes; |
| 796 | uint32_t rsvd12[4]; |
| 797 | } NvmeDsmCmd; |
| 798 | |
| 799 | enum { |
| 800 | NVME_DSMGMT_IDR = 1 << 0, |
| 801 | NVME_DSMGMT_IDW = 1 << 1, |
| 802 | NVME_DSMGMT_AD = 1 << 2, |
| 803 | }; |
| 804 | |
| 805 | typedef struct QEMU_PACKED NvmeDsmRange { |
| 806 | uint32_t cattr; |
| 807 | uint32_t nlb; |
| 808 | uint64_t slba; |
| 809 | } NvmeDsmRange; |
| 810 | |
| 811 | enum { |
| 812 | NVME_COPY_FORMAT_0 = 0x0, |
| 813 | NVME_COPY_FORMAT_1 = 0x1, |
| 814 | NVME_COPY_FORMAT_2 = 0x2, |
| 815 | NVME_COPY_FORMAT_3 = 0x3, |
| 816 | }; |
| 817 | |
| 818 | typedef struct QEMU_PACKED NvmeCopyCmd { |
| 819 | uint8_t opcode; |
| 820 | uint8_t flags; |
| 821 | uint16_t cid; |
| 822 | uint32_t nsid; |
| 823 | uint32_t cdw2; |
| 824 | uint32_t cdw3; |
| 825 | uint32_t rsvd2[2]; |
| 826 | NvmeCmdDptr dptr; |
| 827 | uint64_t sdlba; |
| 828 | uint8_t nr; |
| 829 | uint8_t control[3]; |
| 830 | uint16_t rsvd13; |
| 831 | uint16_t dspec; |
| 832 | uint32_t reftag; |
| 833 | uint16_t apptag; |
| 834 | uint16_t appmask; |
| 835 | } NvmeCopyCmd; |
| 836 | |
| 837 | typedef struct QEMU_PACKED NvmeCopySourceRangeFormat0_2 { |
| 838 | uint32_t sparams; |
| 839 | uint8_t rsvd4[4]; |
| 840 | uint64_t slba; |
| 841 | uint16_t nlb; |
| 842 | uint8_t rsvd18[4]; |
| 843 | uint16_t sopt; |
| 844 | uint32_t reftag; |
| 845 | uint16_t apptag; |
| 846 | uint16_t appmask; |
| 847 | } NvmeCopySourceRangeFormat0_2; |
| 848 | |
| 849 | typedef struct QEMU_PACKED NvmeCopySourceRangeFormat1_3 { |
| 850 | uint32_t sparams; |
| 851 | uint8_t rsvd4[4]; |
| 852 | uint64_t slba; |
| 853 | uint16_t nlb; |
| 854 | uint8_t rsvd18[4]; |
| 855 | uint16_t sopt; |
| 856 | uint8_t rsvd24[2]; |
| 857 | uint8_t sr[10]; |
| 858 | uint16_t apptag; |
| 859 | uint16_t appmask; |
| 860 | } NvmeCopySourceRangeFormat1_3; |
| 861 | |
| 862 | enum NvmeAsyncEventRequest { |
| 863 | NVME_AER_TYPE_ERROR = 0, |
| 864 | NVME_AER_TYPE_SMART = 1, |
| 865 | NVME_AER_TYPE_NOTICE = 2, |
| 866 | NVME_AER_TYPE_IO_SPECIFIC = 6, |
| 867 | NVME_AER_TYPE_VENDOR_SPECIFIC = 7, |
| 868 | NVME_AER_INFO_ERR_INVALID_DB_REGISTER = 0, |
| 869 | NVME_AER_INFO_ERR_INVALID_DB_VALUE = 1, |
| 870 | NVME_AER_INFO_ERR_DIAG_FAIL = 2, |
| 871 | NVME_AER_INFO_ERR_PERS_INTERNAL_ERR = 3, |
| 872 | NVME_AER_INFO_ERR_TRANS_INTERNAL_ERR = 4, |
| 873 | NVME_AER_INFO_ERR_FW_IMG_LOAD_ERR = 5, |
| 874 | NVME_AER_INFO_SMART_RELIABILITY = 0, |
| 875 | NVME_AER_INFO_SMART_TEMP_THRESH = 1, |
| 876 | NVME_AER_INFO_SMART_SPARE_THRESH = 2, |
| 877 | NVME_AER_INFO_NOTICE_NS_ATTR_CHANGED = 0, |
| 878 | }; |
| 879 | |
| 880 | typedef struct QEMU_PACKED NvmeAerResult { |
| 881 | uint8_t event_type; |
| 882 | uint8_t event_info; |
| 883 | uint8_t log_page; |
| 884 | uint8_t resv; |
| 885 | } NvmeAerResult; |
| 886 | |
| 887 | typedef struct QEMU_PACKED NvmeZonedResult { |
| 888 | uint64_t slba; |
| 889 | } NvmeZonedResult; |
| 890 | |
| 891 | typedef struct QEMU_PACKED NvmeCqe { |
| 892 | uint32_t result; |
| 893 | uint32_t dw1; |
| 894 | uint16_t sq_head; |
| 895 | uint16_t sq_id; |
| 896 | uint16_t cid; |
| 897 | uint16_t status; |
| 898 | } NvmeCqe; |
| 899 | |
| 900 | enum NvmeStatusCodes { |
| 901 | NVME_SUCCESS = 0x0000, |
| 902 | NVME_INVALID_OPCODE = 0x0001, |
| 903 | NVME_INVALID_FIELD = 0x0002, |
| 904 | NVME_CID_CONFLICT = 0x0003, |
| 905 | NVME_DATA_TRAS_ERROR = 0x0004, |
| 906 | NVME_POWER_LOSS_ABORT = 0x0005, |
| 907 | NVME_INTERNAL_DEV_ERROR = 0x0006, |
| 908 | NVME_CMD_ABORT_REQ = 0x0007, |
| 909 | NVME_CMD_ABORT_SQ_DEL = 0x0008, |
| 910 | NVME_CMD_ABORT_FAILED_FUSE = 0x0009, |
| 911 | NVME_CMD_ABORT_MISSING_FUSE = 0x000a, |
| 912 | NVME_INVALID_NSID = 0x000b, |
| 913 | NVME_CMD_SEQ_ERROR = 0x000c, |
| 914 | NVME_INVALID_SGL_SEG_DESCR = 0x000d, |
| 915 | NVME_INVALID_NUM_SGL_DESCRS = 0x000e, |
| 916 | NVME_DATA_SGL_LEN_INVALID = 0x000f, |
| 917 | NVME_MD_SGL_LEN_INVALID = 0x0010, |
| 918 | NVME_SGL_DESCR_TYPE_INVALID = 0x0011, |
| 919 | NVME_INVALID_USE_OF_CMB = 0x0012, |
| 920 | NVME_INVALID_PRP_OFFSET = 0x0013, |
| 921 | NVME_COMMAND_INTERRUPTED = 0x0021, |
| 922 | NVME_FDP_DISABLED = 0x0029, |
| 923 | NVME_INVALID_PHID_LIST = 0x002a, |
| 924 | NVME_LBA_RANGE = 0x0080, |
| 925 | NVME_CAP_EXCEEDED = 0x0081, |
| 926 | NVME_NS_NOT_READY = 0x0082, |
| 927 | NVME_NS_RESV_CONFLICT = 0x0083, |
| 928 | NVME_FORMAT_IN_PROGRESS = 0x0084, |
| 929 | NVME_INVALID_CQID = 0x0100, |
| 930 | NVME_INVALID_QID = 0x0101, |
| 931 | NVME_MAX_QSIZE_EXCEEDED = 0x0102, |
| 932 | NVME_ACL_EXCEEDED = 0x0103, |
| 933 | NVME_RESERVED = 0x0104, |
| 934 | NVME_AER_LIMIT_EXCEEDED = 0x0105, |
| 935 | NVME_INVALID_FW_SLOT = 0x0106, |
| 936 | NVME_INVALID_FW_IMAGE = 0x0107, |
| 937 | NVME_INVALID_IRQ_VECTOR = 0x0108, |
| 938 | NVME_INVALID_LOG_ID = 0x0109, |
| 939 | NVME_INVALID_FORMAT = 0x010a, |
| 940 | NVME_FW_REQ_RESET = 0x010b, |
| 941 | NVME_INVALID_QUEUE_DEL = 0x010c, |
| 942 | NVME_FID_NOT_SAVEABLE = 0x010d, |
| 943 | NVME_FEAT_NOT_CHANGEABLE = 0x010e, |
| 944 | NVME_FEAT_NOT_NS_SPEC = 0x010f, |
| 945 | NVME_FW_REQ_SUSYSTEM_RESET = 0x0110, |
| 946 | NVME_NS_ALREADY_ATTACHED = 0x0118, |
| 947 | NVME_NS_PRIVATE = 0x0119, |
| 948 | NVME_NS_NOT_ATTACHED = 0x011a, |
| 949 | NVME_NS_CTRL_LIST_INVALID = 0x011c, |
| 950 | NVME_INVALID_CTRL_ID = 0x011f, |
| 951 | NVME_INVALID_SEC_CTRL_STATE = 0x0120, |
| 952 | NVME_INVALID_NUM_RESOURCES = 0x0121, |
| 953 | NVME_INVALID_RESOURCE_ID = 0x0122, |
| 954 | NVME_IOCS_NOT_SUPPORTED = 0x0129, |
| 955 | NVME_IOCS_NOT_ENABLED = 0x012a, |
| 956 | NVME_IOCS_COMBINATION_REJECTED = 0x012b, |
| 957 | NVME_INVALID_IOCS = 0x012c, |
| 958 | NVME_CONFLICTING_ATTRS = 0x0180, |
| 959 | NVME_INVALID_PROT_INFO = 0x0181, |
| 960 | NVME_WRITE_TO_RO = 0x0182, |
| 961 | NVME_CMD_SIZE_LIMIT = 0x0183, |
| 962 | NVME_CMD_INCOMP_NS_OR_FMT = 0x0185, |
| 963 | NVME_CMD_OVERLAP_IO_RANGE = 0x0187, |
| 964 | NVME_INVALID_ZONE_OP = 0x01b6, |
| 965 | NVME_NOZRWA = 0x01b7, |
| 966 | NVME_ZONE_BOUNDARY_ERROR = 0x01b8, |
| 967 | NVME_ZONE_FULL = 0x01b9, |
| 968 | NVME_ZONE_READ_ONLY = 0x01ba, |
| 969 | NVME_ZONE_OFFLINE = 0x01bb, |
| 970 | NVME_ZONE_INVALID_WRITE = 0x01bc, |
| 971 | NVME_ZONE_TOO_MANY_ACTIVE = 0x01bd, |
| 972 | NVME_ZONE_TOO_MANY_OPEN = 0x01be, |
| 973 | NVME_ZONE_INVAL_TRANSITION = 0x01bf, |
| 974 | NVME_WRITE_FAULT = 0x0280, |
| 975 | NVME_UNRECOVERED_READ = 0x0281, |
| 976 | NVME_E2E_GUARD_ERROR = 0x0282, |
| 977 | NVME_E2E_APP_ERROR = 0x0283, |
| 978 | NVME_E2E_REF_ERROR = 0x0284, |
| 979 | NVME_CMP_FAILURE = 0x0285, |
| 980 | NVME_ACCESS_DENIED = 0x0286, |
| 981 | NVME_DULB = 0x0287, |
| 982 | NVME_E2E_STORAGE_TAG_ERROR = 0x0288, |
| 983 | NVME_MORE = 0x2000, |
| 984 | NVME_DNR = 0x4000, |
| 985 | NVME_NO_COMPLETE = 0xffff, |
| 986 | }; |
| 987 | |
| 988 | typedef struct QEMU_PACKED NvmeFwSlotInfoLog { |
| 989 | uint8_t afi; |
| 990 | uint8_t reserved1[7]; |
| 991 | uint8_t frs1[8]; |
| 992 | uint8_t frs2[8]; |
| 993 | uint8_t frs3[8]; |
| 994 | uint8_t frs4[8]; |
| 995 | uint8_t frs5[8]; |
| 996 | uint8_t frs6[8]; |
| 997 | uint8_t frs7[8]; |
| 998 | uint8_t reserved2[448]; |
| 999 | } NvmeFwSlotInfoLog; |
| 1000 | |
| 1001 | typedef struct QEMU_PACKED NvmeErrorLog { |
| 1002 | uint64_t error_count; |
| 1003 | uint16_t sqid; |
| 1004 | uint16_t cid; |
| 1005 | uint16_t status_field; |
| 1006 | uint16_t param_error_location; |
| 1007 | uint64_t lba; |
| 1008 | uint32_t nsid; |
| 1009 | uint8_t vs; |
| 1010 | uint8_t resv[35]; |
| 1011 | } NvmeErrorLog; |
| 1012 | |
| 1013 | typedef struct QEMU_PACKED NvmeSmartLog { |
| 1014 | uint8_t critical_warning; |
| 1015 | uint16_t temperature; |
| 1016 | uint8_t available_spare; |
| 1017 | uint8_t available_spare_threshold; |
| 1018 | uint8_t percentage_used; |
| 1019 | uint8_t reserved1[26]; |
| 1020 | uint64_t data_units_read[2]; |
| 1021 | uint64_t data_units_written[2]; |
| 1022 | uint64_t host_read_commands[2]; |
| 1023 | uint64_t host_write_commands[2]; |
| 1024 | uint64_t controller_busy_time[2]; |
| 1025 | uint64_t power_cycles[2]; |
| 1026 | uint64_t power_on_hours[2]; |
| 1027 | uint64_t unsafe_shutdowns[2]; |
| 1028 | uint64_t media_errors[2]; |
| 1029 | uint64_t number_of_error_log_entries[2]; |
| 1030 | uint8_t reserved2[320]; |
| 1031 | } NvmeSmartLog; |
| 1032 | |
| 1033 | typedef struct QEMU_PACKED NvmeSmartLogExtended { |
| 1034 | uint64_t physical_media_units_written[2]; |
| 1035 | uint64_t physical_media_units_read[2]; |
| 1036 | uint64_t bad_user_blocks; |
| 1037 | uint64_t bad_system_nand_blocks; |
| 1038 | uint64_t xor_recovery_count; |
| 1039 | uint64_t uncorrectable_read_error_count; |
| 1040 | uint64_t soft_ecc_error_count; |
| 1041 | uint64_t end2end_correction_counts; |
| 1042 | uint8_t system_data_percent_used; |
| 1043 | uint8_t refresh_counts[7]; |
| 1044 | uint64_t user_data_erase_counts; |
| 1045 | uint16_t thermal_throttling_stat_and_count; |
| 1046 | uint16_t dssd_spec_version[3]; |
| 1047 | uint64_t pcie_correctable_error_count; |
| 1048 | uint32_t incomplete_shutdowns; |
| 1049 | uint32_t rsvd116; |
| 1050 | uint8_t percent_free_blocks; |
| 1051 | uint8_t rsvd121[7]; |
| 1052 | uint16_t capacity_health; |
| 1053 | uint8_t nvme_errata_ver; |
| 1054 | uint8_t rsvd131[5]; |
| 1055 | uint64_t unaligned_io; |
| 1056 | uint64_t security_ver_num; |
| 1057 | uint64_t total_nuse; |
| 1058 | uint64_t plp_start_count[2]; |
| 1059 | uint64_t endurance_estimate[2]; |
| 1060 | uint64_t pcie_retraining_count; |
| 1061 | uint64_t power_state_change_count; |
| 1062 | uint8_t rsvd208[286]; |
| 1063 | uint16_t log_page_version; |
| 1064 | uint64_t log_page_guid[2]; |
| 1065 | } NvmeSmartLogExtended; |
| 1066 | |
| 1067 | #define NVME_SMART_WARN_MAX 6 |
| 1068 | enum NvmeSmartWarn { |
| 1069 | NVME_SMART_SPARE = 1 << 0, |
| 1070 | NVME_SMART_TEMPERATURE = 1 << 1, |
| 1071 | NVME_SMART_RELIABILITY = 1 << 2, |
| 1072 | NVME_SMART_MEDIA_READ_ONLY = 1 << 3, |
| 1073 | NVME_SMART_FAILED_VOLATILE_MEDIA = 1 << 4, |
| 1074 | NVME_SMART_PMR_UNRELIABLE = 1 << 5, |
| 1075 | }; |
| 1076 | |
| 1077 | typedef struct NvmeEffectsLog { |
| 1078 | uint32_t acs[256]; |
| 1079 | uint32_t iocs[256]; |
| 1080 | uint8_t resv[2048]; |
| 1081 | } NvmeEffectsLog; |
| 1082 | |
| 1083 | enum { |
| 1084 | NVME_CMD_EFF_CSUPP = 1 << 0, |
| 1085 | NVME_CMD_EFF_LBCC = 1 << 1, |
| 1086 | NVME_CMD_EFF_NCC = 1 << 2, |
| 1087 | NVME_CMD_EFF_NIC = 1 << 3, |
| 1088 | NVME_CMD_EFF_CCC = 1 << 4, |
| 1089 | NVME_CMD_EFF_CSE_MASK = 3 << 16, |
| 1090 | NVME_CMD_EFF_UUID_SEL = 1 << 19, |
| 1091 | }; |
| 1092 | |
| 1093 | enum NvmeLogIdentifier { |
| 1094 | NVME_LOG_ERROR_INFO = 0x01, |
| 1095 | NVME_LOG_SMART_INFO = 0x02, |
| 1096 | NVME_LOG_FW_SLOT_INFO = 0x03, |
| 1097 | NVME_LOG_CHANGED_NSLIST = 0x04, |
| 1098 | NVME_LOG_CMD_EFFECTS = 0x05, |
| 1099 | NVME_LOG_ENDGRP = 0x09, |
| 1100 | NVME_LOG_FDP_CONFS = 0x20, |
| 1101 | NVME_LOG_FDP_RUH_USAGE = 0x21, |
| 1102 | NVME_LOG_FDP_STATS = 0x22, |
| 1103 | NVME_LOG_FDP_EVENTS = 0x23, |
| 1104 | NVME_LOG_VENDOR_START = 0xc0, |
| 1105 | NVME_LOG_VENDOR_END = 0xff, |
| 1106 | }; |
| 1107 | |
| 1108 | enum NvmeOcpLogIdentifier { |
| 1109 | NVME_OCP_EXTENDED_SMART_INFO = 0xc0, |
| 1110 | }; |
| 1111 | |
| 1112 | typedef struct QEMU_PACKED NvmePSD { |
| 1113 | uint16_t mp; |
| 1114 | uint16_t reserved; |
| 1115 | uint32_t enlat; |
| 1116 | uint32_t exlat; |
| 1117 | uint8_t rrt; |
| 1118 | uint8_t rrl; |
| 1119 | uint8_t rwt; |
| 1120 | uint8_t rwl; |
| 1121 | uint8_t resv[16]; |
| 1122 | } NvmePSD; |
| 1123 | |
| 1124 | #define NVME_CONTROLLER_LIST_SIZE 2048 |
| 1125 | #define NVME_IDENTIFY_DATA_SIZE 4096 |
| 1126 | |
| 1127 | enum NvmeIdCns { |
| 1128 | NVME_ID_CNS_NS = 0x00, |
| 1129 | NVME_ID_CNS_CTRL = 0x01, |
| 1130 | NVME_ID_CNS_NS_ACTIVE_LIST = 0x02, |
| 1131 | NVME_ID_CNS_NS_DESCR_LIST = 0x03, |
| 1132 | NVME_ID_CNS_CS_NS = 0x05, |
| 1133 | NVME_ID_CNS_CS_CTRL = 0x06, |
| 1134 | NVME_ID_CNS_CS_NS_ACTIVE_LIST = 0x07, |
| 1135 | NVME_ID_CNS_CS_IND_NS = 0x08, |
| 1136 | NVME_ID_CNS_NS_PRESENT_LIST = 0x10, |
| 1137 | NVME_ID_CNS_NS_PRESENT = 0x11, |
| 1138 | NVME_ID_CNS_NS_ATTACHED_CTRL_LIST = 0x12, |
| 1139 | NVME_ID_CNS_CTRL_LIST = 0x13, |
| 1140 | NVME_ID_CNS_PRIMARY_CTRL_CAP = 0x14, |
| 1141 | NVME_ID_CNS_SECONDARY_CTRL_LIST = 0x15, |
| 1142 | NVME_ID_CNS_ENDURANCE_GROUP_LIST = 0x19, |
| 1143 | NVME_ID_CNS_CS_NS_PRESENT_LIST = 0x1a, |
| 1144 | NVME_ID_CNS_CS_NS_PRESENT = 0x1b, |
| 1145 | NVME_ID_CNS_IO_COMMAND_SET = 0x1c, |
| 1146 | NVME_ID_CNS_CS_IND_NS_ALLOCATED = 0x1f, |
| 1147 | }; |
| 1148 | |
| 1149 | #define NVME_ID_CTRL_SN_MAX_LEN 20 |
| 1150 | #define NVME_ID_CTRL_MN_MAX_LEN 40 |
| 1151 | #define NVME_ID_CTRL_FR_MAX_LEN 8 |
| 1152 | |
| 1153 | typedef struct QEMU_PACKED NvmeIdCtrl { |
| 1154 | uint16_t vid; |
| 1155 | uint16_t ssvid; |
| 1156 | uint8_t sn[NVME_ID_CTRL_SN_MAX_LEN]; |
| 1157 | uint8_t mn[NVME_ID_CTRL_MN_MAX_LEN]; |
| 1158 | uint8_t fr[NVME_ID_CTRL_FR_MAX_LEN]; |
| 1159 | uint8_t rab; |
| 1160 | uint8_t ieee[3]; |
| 1161 | uint8_t cmic; |
| 1162 | uint8_t mdts; |
| 1163 | uint16_t cntlid; |
| 1164 | uint32_t ver; |
| 1165 | uint32_t rtd3r; |
| 1166 | uint32_t rtd3e; |
| 1167 | uint32_t oaes; |
| 1168 | uint32_t ctratt; |
| 1169 | uint8_t rsvd100[11]; |
| 1170 | uint8_t cntrltype; |
| 1171 | uint8_t fguid[16]; |
| 1172 | uint8_t rsvd128[128]; |
| 1173 | uint16_t oacs; |
| 1174 | uint8_t acl; |
| 1175 | uint8_t aerl; |
| 1176 | uint8_t frmw; |
| 1177 | uint8_t lpa; |
| 1178 | uint8_t elpe; |
| 1179 | uint8_t npss; |
| 1180 | uint8_t avscc; |
| 1181 | uint8_t apsta; |
| 1182 | uint16_t wctemp; |
| 1183 | uint16_t cctemp; |
| 1184 | uint16_t mtfa; |
| 1185 | uint32_t hmpre; |
| 1186 | uint32_t hmmin; |
| 1187 | uint8_t tnvmcap[16]; |
| 1188 | uint8_t unvmcap[16]; |
| 1189 | uint32_t rpmbs; |
| 1190 | uint16_t edstt; |
| 1191 | uint8_t dsto; |
| 1192 | uint8_t fwug; |
| 1193 | uint16_t kas; |
| 1194 | uint16_t hctma; |
| 1195 | uint16_t mntmt; |
| 1196 | uint16_t mxtmt; |
| 1197 | uint32_t sanicap; |
| 1198 | uint8_t rsvd332[6]; |
| 1199 | uint16_t nsetidmax; |
| 1200 | uint16_t endgidmax; |
| 1201 | uint8_t rsvd342[170]; |
| 1202 | uint8_t sqes; |
| 1203 | uint8_t cqes; |
| 1204 | uint16_t maxcmd; |
| 1205 | uint32_t nn; |
| 1206 | uint16_t oncs; |
| 1207 | uint16_t fuses; |
| 1208 | uint8_t fna; |
| 1209 | uint8_t vwc; |
| 1210 | uint16_t awun; |
| 1211 | uint16_t awupf; |
| 1212 | uint8_t nvscc; |
| 1213 | uint8_t rsvd531; |
| 1214 | uint16_t acwu; |
| 1215 | uint16_t ocfs; |
| 1216 | uint32_t sgls; |
| 1217 | uint8_t rsvd540[228]; |
| 1218 | uint8_t subnqn[256]; |
| 1219 | uint8_t rsvd1024[1024]; |
| 1220 | NvmePSD psd[32]; |
| 1221 | uint8_t vs[1024]; |
| 1222 | } NvmeIdCtrl; |
| 1223 | |
| 1224 | typedef struct NvmeIdCtrlZoned { |
| 1225 | uint8_t zasl; |
| 1226 | uint8_t rsvd1[4095]; |
| 1227 | } NvmeIdCtrlZoned; |
| 1228 | |
| 1229 | #define NVME_ID_CTRL_NVM_DMRL_MAX 255 |
| 1230 | |
| 1231 | typedef struct NvmeIdCtrlNvm { |
| 1232 | uint8_t vsl; |
| 1233 | uint8_t wzsl; |
| 1234 | uint8_t wusl; |
| 1235 | uint8_t dmrl; |
| 1236 | uint32_t dmrsl; |
| 1237 | uint64_t dmsl; |
| 1238 | uint8_t rsvd16[4080]; |
| 1239 | } NvmeIdCtrlNvm; |
| 1240 | |
| 1241 | enum NvmeIdCtrlOaes { |
| 1242 | NVME_OAES_NS_ATTR = 1 << 8, |
| 1243 | }; |
| 1244 | |
| 1245 | enum NvmeIdCtrlCtratt { |
| 1246 | NVME_CTRATT_ENDGRPS = 1 << 4, |
| 1247 | NVME_CTRATT_ELBAS = 1 << 15, |
| 1248 | NVME_CTRATT_MEM = 1 << 16, |
| 1249 | NVME_CTRATT_FDPS = 1 << 19, |
| 1250 | }; |
| 1251 | |
| 1252 | enum NvmeIdCtrlOacs { |
| 1253 | NVME_OACS_SECURITY = 1 << 0, |
| 1254 | NVME_OACS_FORMAT = 1 << 1, |
| 1255 | NVME_OACS_FW = 1 << 2, |
| 1256 | NVME_OACS_NMS = 1 << 3, |
| 1257 | NVME_OACS_DIRECTIVES = 1 << 5, |
| 1258 | NVME_OACS_VMS = 1 << 7, |
| 1259 | NVME_OACS_DBCS = 1 << 8, |
| 1260 | }; |
| 1261 | |
| 1262 | enum NvmeIdCtrlOncs { |
| 1263 | NVME_ONCS_COMPARE = 1 << 0, |
| 1264 | NVME_ONCS_WRITE_UNCORR = 1 << 1, |
| 1265 | NVME_ONCS_DSM = 1 << 2, |
| 1266 | NVME_ONCS_WRITE_ZEROES = 1 << 3, |
| 1267 | NVME_ONCS_FEATURES = 1 << 4, |
| 1268 | NVME_ONCS_RESRVATIONS = 1 << 5, |
| 1269 | NVME_ONCS_TIMESTAMP = 1 << 6, |
| 1270 | NVME_ONCS_VERIFY = 1 << 7, |
| 1271 | NVME_ONCS_COPY = 1 << 8, |
| 1272 | NVME_ONCS_NVMCSA = 1 << 9, |
| 1273 | NVME_ONCS_NVMAFC = 1 << 10, |
| 1274 | }; |
| 1275 | |
| 1276 | enum NvmeIdCtrlOcfs { |
| 1277 | NVME_OCFS_COPY_FORMAT_0 = 1 << NVME_COPY_FORMAT_0, |
| 1278 | NVME_OCFS_COPY_FORMAT_1 = 1 << NVME_COPY_FORMAT_1, |
| 1279 | NVME_OCFS_COPY_FORMAT_2 = 1 << NVME_COPY_FORMAT_2, |
| 1280 | NVME_OCFS_COPY_FORMAT_3 = 1 << NVME_COPY_FORMAT_3, |
| 1281 | }; |
| 1282 | |
| 1283 | enum NvmeIdctrlVwc { |
| 1284 | NVME_VWC_PRESENT = 1 << 0, |
| 1285 | NVME_VWC_NSID_BROADCAST_NO_SUPPORT = 0 << 1, |
| 1286 | NVME_VWC_NSID_BROADCAST_RESERVED = 1 << 1, |
| 1287 | NVME_VWC_NSID_BROADCAST_CTRL_SPEC = 2 << 1, |
| 1288 | NVME_VWC_NSID_BROADCAST_SUPPORT = 3 << 1, |
| 1289 | }; |
| 1290 | |
| 1291 | enum NvmeIdCtrlFrmw { |
| 1292 | NVME_FRMW_SLOT1_RO = 1 << 0, |
| 1293 | }; |
| 1294 | |
| 1295 | enum NvmeIdCtrlLpa { |
| 1296 | NVME_LPA_NS_SMART = 1 << 0, |
| 1297 | NVME_LPA_CSE = 1 << 1, |
| 1298 | NVME_LPA_EXTENDED = 1 << 2, |
| 1299 | }; |
| 1300 | |
| 1301 | enum NvmeIdCtrlCmic { |
| 1302 | NVME_CMIC_MULTI_CTRL = 1 << 1, |
| 1303 | }; |
| 1304 | |
| 1305 | enum NvmeNsAttachmentOperation { |
| 1306 | NVME_NS_ATTACHMENT_ATTACH = 0x0, |
| 1307 | NVME_NS_ATTACHMENT_DETACH = 0x1, |
| 1308 | }; |
| 1309 | |
| 1310 | #define NVME_CTRL_SQES_MIN(sqes) ((sqes) & 0xf) |
| 1311 | #define NVME_CTRL_SQES_MAX(sqes) (((sqes) >> 4) & 0xf) |
| 1312 | #define NVME_CTRL_CQES_MIN(cqes) ((cqes) & 0xf) |
| 1313 | #define NVME_CTRL_CQES_MAX(cqes) (((cqes) >> 4) & 0xf) |
| 1314 | |
| 1315 | #define NVME_CTRL_SGLS_SUPPORT_MASK (0x3 << 0) |
| 1316 | #define NVME_CTRL_SGLS_SUPPORT_NO_ALIGN (0x1 << 0) |
| 1317 | #define NVME_CTRL_SGLS_SUPPORT_DWORD_ALIGN (0x1 << 1) |
| 1318 | #define NVME_CTRL_SGLS_KEYED (0x1 << 2) |
| 1319 | #define NVME_CTRL_SGLS_BITBUCKET (0x1 << 16) |
| 1320 | #define NVME_CTRL_SGLS_MPTR_CONTIGUOUS (0x1 << 17) |
| 1321 | #define NVME_CTRL_SGLS_EXCESS_LENGTH (0x1 << 18) |
| 1322 | #define NVME_CTRL_SGLS_MPTR_SGL (0x1 << 19) |
| 1323 | #define NVME_CTRL_SGLS_ADDR_OFFSET (0x1 << 20) |
| 1324 | |
| 1325 | #define NVME_ARB_AB(arb) (arb & 0x7) |
| 1326 | #define NVME_ARB_AB_NOLIMIT 0x7 |
| 1327 | #define NVME_ARB_LPW(arb) ((arb >> 8) & 0xff) |
| 1328 | #define NVME_ARB_MPW(arb) ((arb >> 16) & 0xff) |
| 1329 | #define NVME_ARB_HPW(arb) ((arb >> 24) & 0xff) |
| 1330 | |
| 1331 | #define NVME_INTC_THR(intc) (intc & 0xff) |
| 1332 | #define NVME_INTC_TIME(intc) ((intc >> 8) & 0xff) |
| 1333 | |
| 1334 | #define NVME_INTVC_NOCOALESCING (0x1 << 16) |
| 1335 | |
| 1336 | #define NVME_TEMP_THSEL(temp) ((temp >> 20) & 0x3) |
| 1337 | #define NVME_TEMP_THSEL_OVER 0x0 |
| 1338 | #define NVME_TEMP_THSEL_UNDER 0x1 |
| 1339 | |
| 1340 | #define NVME_TEMP_TMPSEL(temp) ((temp >> 16) & 0xf) |
| 1341 | #define NVME_TEMP_TMPSEL_COMPOSITE 0x0 |
| 1342 | |
| 1343 | #define NVME_TEMP_TMPTH(temp) (temp & 0xffff) |
| 1344 | |
| 1345 | #define NVME_AEC_SMART(aec) (aec & 0xff) |
| 1346 | #define NVME_AEC_NS_ATTR(aec) ((aec >> 8) & 0x1) |
| 1347 | #define NVME_AEC_FW_ACTIVATION(aec) ((aec >> 9) & 0x1) |
| 1348 | #define NVME_AEC_ENDGRP_NOTICE(aec) ((aec >> 14) & 0x1) |
| 1349 | |
| 1350 | #define NVME_ERR_REC_TLER(err_rec) (err_rec & 0xffff) |
| 1351 | #define NVME_ERR_REC_DULBE(err_rec) (err_rec & 0x10000) |
| 1352 | |
| 1353 | #define NVME_ID_CTRL_CTRATT_MEM(ctratt) (ctratt & NVME_CTRATT_MEM) |
| 1354 | |
| 1355 | enum NvmeFeatureIds { |
| 1356 | NVME_ARBITRATION = 0x1, |
| 1357 | NVME_POWER_MANAGEMENT = 0x2, |
| 1358 | NVME_LBA_RANGE_TYPE = 0x3, |
| 1359 | NVME_TEMPERATURE_THRESHOLD = 0x4, |
| 1360 | NVME_ERROR_RECOVERY = 0x5, |
| 1361 | NVME_VOLATILE_WRITE_CACHE = 0x6, |
| 1362 | NVME_NUMBER_OF_QUEUES = 0x7, |
| 1363 | NVME_INTERRUPT_COALESCING = 0x8, |
| 1364 | NVME_INTERRUPT_VECTOR_CONF = 0x9, |
| 1365 | NVME_WRITE_ATOMICITY = 0xa, |
| 1366 | NVME_ASYNCHRONOUS_EVENT_CONF = 0xb, |
| 1367 | NVME_TIMESTAMP = 0xe, |
| 1368 | NVME_HOST_BEHAVIOR_SUPPORT = 0x16, |
| 1369 | NVME_COMMAND_SET_PROFILE = 0x19, |
| 1370 | NVME_FDP_MODE = 0x1d, |
| 1371 | NVME_FDP_EVENTS = 0x1e, |
| 1372 | NVME_SOFTWARE_PROGRESS_MARKER = 0x80, |
| 1373 | NVME_FID_MAX = 0x100, |
| 1374 | }; |
| 1375 | |
| 1376 | typedef enum NvmeFeatureCap { |
| 1377 | NVME_FEAT_CAP_SAVE = 1 << 0, |
| 1378 | NVME_FEAT_CAP_NS = 1 << 1, |
| 1379 | NVME_FEAT_CAP_CHANGE = 1 << 2, |
| 1380 | } NvmeFeatureCap; |
| 1381 | |
| 1382 | typedef enum NvmeGetFeatureSelect { |
| 1383 | NVME_GETFEAT_SELECT_CURRENT = 0x0, |
| 1384 | NVME_GETFEAT_SELECT_DEFAULT = 0x1, |
| 1385 | NVME_GETFEAT_SELECT_SAVED = 0x2, |
| 1386 | NVME_GETFEAT_SELECT_CAP = 0x3, |
| 1387 | } NvmeGetFeatureSelect; |
| 1388 | |
| 1389 | #define NVME_GETSETFEAT_FID_MASK 0xff |
| 1390 | #define NVME_GETSETFEAT_FID(dw10) (dw10 & NVME_GETSETFEAT_FID_MASK) |
| 1391 | |
| 1392 | #define NVME_GETFEAT_SELECT_SHIFT 8 |
| 1393 | #define NVME_GETFEAT_SELECT_MASK 0x7 |
| 1394 | #define NVME_GETFEAT_SELECT(dw10) \ |
| 1395 | ((dw10 >> NVME_GETFEAT_SELECT_SHIFT) & NVME_GETFEAT_SELECT_MASK) |
| 1396 | |
| 1397 | #define NVME_SETFEAT_SAVE_SHIFT 31 |
| 1398 | #define NVME_SETFEAT_SAVE_MASK 0x1 |
| 1399 | #define NVME_SETFEAT_SAVE(dw10) \ |
| 1400 | ((dw10 >> NVME_SETFEAT_SAVE_SHIFT) & NVME_SETFEAT_SAVE_MASK) |
| 1401 | |
| 1402 | typedef struct QEMU_PACKED NvmeRangeType { |
| 1403 | uint8_t type; |
| 1404 | uint8_t attributes; |
| 1405 | uint8_t rsvd2[14]; |
| 1406 | uint64_t slba; |
| 1407 | uint64_t nlb; |
| 1408 | uint8_t guid[16]; |
| 1409 | uint8_t rsvd48[16]; |
| 1410 | } NvmeRangeType; |
| 1411 | |
| 1412 | typedef struct NvmeHostBehaviorSupport { |
| 1413 | uint8_t acre; |
| 1414 | uint8_t etdas; |
| 1415 | uint8_t lbafee; |
| 1416 | uint8_t rsvd3; |
| 1417 | uint16_t cdfe; |
| 1418 | uint8_t rsvd6[506]; |
| 1419 | } NvmeHostBehaviorSupport; |
| 1420 | |
| 1421 | typedef struct QEMU_PACKED NvmeLBAF { |
| 1422 | uint16_t ms; |
| 1423 | uint8_t ds; |
| 1424 | uint8_t rp; |
| 1425 | } NvmeLBAF; |
| 1426 | |
| 1427 | typedef struct QEMU_PACKED NvmeLBAFE { |
| 1428 | uint64_t zsze; |
| 1429 | uint8_t zdes; |
| 1430 | uint8_t rsvd9[7]; |
| 1431 | } NvmeLBAFE; |
| 1432 | |
| 1433 | #define NVME_NSID_BROADCAST 0xffffffff |
| 1434 | #define NVME_MAX_NLBAF 64 |
| 1435 | |
| 1436 | typedef struct QEMU_PACKED NvmeIdNs { |
| 1437 | uint64_t nsze; |
| 1438 | uint64_t ncap; |
| 1439 | uint64_t nuse; |
| 1440 | uint8_t nsfeat; |
| 1441 | uint8_t nlbaf; |
| 1442 | uint8_t flbas; |
| 1443 | uint8_t mc; |
| 1444 | uint8_t dpc; |
| 1445 | uint8_t dps; |
| 1446 | uint8_t nmic; |
| 1447 | uint8_t rescap; |
| 1448 | uint8_t fpi; |
| 1449 | uint8_t dlfeat; |
| 1450 | uint16_t nawun; |
| 1451 | uint16_t nawupf; |
| 1452 | uint16_t nacwu; |
| 1453 | uint16_t nabsn; |
| 1454 | uint16_t nabo; |
| 1455 | uint16_t nabspf; |
| 1456 | uint16_t noiob; |
| 1457 | uint8_t nvmcap[16]; |
| 1458 | uint16_t npwg; |
| 1459 | uint16_t npwa; |
| 1460 | uint16_t npdg; |
| 1461 | uint16_t npda; |
| 1462 | uint16_t nows; |
| 1463 | uint16_t mssrl; |
| 1464 | uint32_t mcl; |
| 1465 | uint8_t msrc; |
| 1466 | uint8_t rsvd81[18]; |
| 1467 | uint8_t nsattr; |
| 1468 | uint16_t nvmsetid; |
| 1469 | uint16_t endgid; |
| 1470 | uint8_t nguid[16]; |
| 1471 | uint64_t eui64; |
| 1472 | NvmeLBAF lbaf[NVME_MAX_NLBAF]; |
| 1473 | uint8_t vs[3712]; |
| 1474 | } NvmeIdNs; |
| 1475 | |
| 1476 | #define NVME_ID_NS_NVM_ELBAF_PIF(elbaf) (((elbaf) >> 7) & 0x3) |
| 1477 | |
| 1478 | typedef struct QEMU_PACKED NvmeIdNsNvm { |
| 1479 | uint64_t lbstm; |
| 1480 | uint8_t pic; |
| 1481 | uint8_t rsvd9[3]; |
| 1482 | uint32_t elbaf[NVME_MAX_NLBAF]; |
| 1483 | uint32_t npdgl; |
| 1484 | uint32_t nprg; |
| 1485 | uint32_t npra; |
| 1486 | uint32_t nors; |
| 1487 | uint32_t npdal; |
| 1488 | uint8_t rsvd288[3808]; |
| 1489 | } NvmeIdNsNvm; |
| 1490 | |
| 1491 | typedef struct QEMU_PACKED NvmeIdNsInd { |
| 1492 | uint8_t nsfeat; |
| 1493 | uint8_t nmic; |
| 1494 | uint8_t rescap; |
| 1495 | uint8_t fpi; |
| 1496 | uint32_t anagrpid; |
| 1497 | uint8_t nsattr; |
| 1498 | uint8_t rsvd9; |
| 1499 | uint16_t nvmsetid; |
| 1500 | uint16_t endgrpid; |
| 1501 | uint8_t nstat; |
| 1502 | uint8_t rsvd15[4081]; |
| 1503 | } NvmeIdNsInd; |
| 1504 | |
| 1505 | typedef struct QEMU_PACKED NvmeIdNsDescr { |
| 1506 | uint8_t nidt; |
| 1507 | uint8_t nidl; |
| 1508 | uint8_t rsvd2[2]; |
| 1509 | } NvmeIdNsDescr; |
| 1510 | |
| 1511 | enum NvmeNsIdentifierLength { |
| 1512 | NVME_NIDL_EUI64 = 8, |
| 1513 | NVME_NIDL_NGUID = 16, |
| 1514 | NVME_NIDL_UUID = 16, |
| 1515 | NVME_NIDL_CSI = 1, |
| 1516 | }; |
| 1517 | |
| 1518 | enum NvmeNsIdentifierType { |
| 1519 | NVME_NIDT_EUI64 = 0x01, |
| 1520 | NVME_NIDT_NGUID = 0x02, |
| 1521 | NVME_NIDT_UUID = 0x03, |
| 1522 | NVME_NIDT_CSI = 0x04, |
| 1523 | }; |
| 1524 | |
| 1525 | enum NvmeIdNsIndependent { |
| 1526 | NVME_ID_NS_IND_NMIC_SHRNS = 1 << 0, |
| 1527 | NVME_ID_NS_IND_NMIC_DISNS = 1 << 1, |
| 1528 | NVME_ID_NS_IND_NSTAT_NRDY = 1 << 0, |
| 1529 | }; |
| 1530 | |
| 1531 | enum NvmeCsi { |
| 1532 | NVME_CSI_NVM = 0x00, |
| 1533 | NVME_CSI_ZONED = 0x02, |
| 1534 | }; |
| 1535 | |
| 1536 | #define NVME_SET_CSI(vec, csi) (vec |= (uint8_t)(1 << (csi))) |
| 1537 | |
| 1538 | typedef struct QEMU_PACKED NvmeIdNsZoned { |
| 1539 | uint16_t zoc; |
| 1540 | uint16_t ozcs; |
| 1541 | uint32_t mar; |
| 1542 | uint32_t mor; |
| 1543 | uint32_t rrl; |
| 1544 | uint32_t frl; |
| 1545 | uint8_t rsvd12[24]; |
| 1546 | uint32_t numzrwa; |
| 1547 | uint16_t zrwafg; |
| 1548 | uint16_t zrwas; |
| 1549 | uint8_t zrwacap; |
| 1550 | uint8_t rsvd53[2763]; |
| 1551 | NvmeLBAFE lbafe[16]; |
| 1552 | uint8_t rsvd3072[768]; |
| 1553 | uint8_t vs[256]; |
| 1554 | } NvmeIdNsZoned; |
| 1555 | |
| 1556 | enum NvmeIdNsZonedOzcs { |
| 1557 | NVME_ID_NS_ZONED_OZCS_RAZB = 1 << 0, |
| 1558 | NVME_ID_NS_ZONED_OZCS_ZRWASUP = 1 << 1, |
| 1559 | }; |
| 1560 | |
| 1561 | enum NvmeIdNsZonedZrwacap { |
| 1562 | NVME_ID_NS_ZONED_ZRWACAP_EXPFLUSHSUP = 1 << 0, |
| 1563 | }; |
| 1564 | |
| 1565 | /*Deallocate Logical Block Features*/ |
| 1566 | #define NVME_ID_NS_DLFEAT_GUARD_CRC(dlfeat) ((dlfeat) & 0x10) |
| 1567 | #define NVME_ID_NS_DLFEAT_WRITE_ZEROES(dlfeat) ((dlfeat) & 0x08) |
| 1568 | |
| 1569 | #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR(dlfeat) ((dlfeat) & 0x7) |
| 1570 | #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_UNDEFINED 0 |
| 1571 | #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_ZEROES 1 |
| 1572 | #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_ONES 2 |
| 1573 | |
| 1574 | |
| 1575 | #define NVME_ID_NS_NSFEAT_THIN(nsfeat) ((nsfeat & 0x1)) |
| 1576 | #define NVME_ID_NS_NSFEAT_DULBE(nsfeat) ((nsfeat >> 2) & 0x1) |
| 1577 | #define NVME_ID_NS_FLBAS_EXTENDED(flbas) ((flbas >> 4) & 0x1) |
| 1578 | #define NVME_ID_NS_FLBAS_INDEX(flbas) ((flbas & 0xf)) |
| 1579 | #define NVME_ID_NS_MC_SEPARATE(mc) ((mc >> 1) & 0x1) |
| 1580 | #define NVME_ID_NS_MC_EXTENDED(mc) ((mc & 0x1)) |
| 1581 | #define NVME_ID_NS_DPC_LAST_EIGHT(dpc) ((dpc >> 4) & 0x1) |
| 1582 | #define NVME_ID_NS_DPC_FIRST_EIGHT(dpc) ((dpc >> 3) & 0x1) |
| 1583 | #define NVME_ID_NS_DPC_TYPE_3(dpc) ((dpc >> 2) & 0x1) |
| 1584 | #define NVME_ID_NS_DPC_TYPE_2(dpc) ((dpc >> 1) & 0x1) |
| 1585 | #define NVME_ID_NS_DPC_TYPE_1(dpc) ((dpc & 0x1)) |
| 1586 | #define NVME_ID_NS_DPC_TYPE_MASK 0x7 |
| 1587 | |
| 1588 | enum NvmeIdNsDps { |
| 1589 | NVME_ID_NS_DPS_TYPE_NONE = 0, |
| 1590 | NVME_ID_NS_DPS_TYPE_1 = 1, |
| 1591 | NVME_ID_NS_DPS_TYPE_2 = 2, |
| 1592 | NVME_ID_NS_DPS_TYPE_3 = 3, |
| 1593 | NVME_ID_NS_DPS_TYPE_MASK = 0x7, |
| 1594 | NVME_ID_NS_DPS_FIRST_EIGHT = 8, |
| 1595 | }; |
| 1596 | |
| 1597 | enum NvmeIdNsFlbas { |
| 1598 | NVME_ID_NS_FLBAS_EXTENDED = 1 << 4, |
| 1599 | }; |
| 1600 | |
| 1601 | enum NvmeIdNsMc { |
| 1602 | NVME_ID_NS_MC_EXTENDED = 1 << 0, |
| 1603 | NVME_ID_NS_MC_SEPARATE = 1 << 1, |
| 1604 | }; |
| 1605 | |
| 1606 | enum NvmeIdNsNsfeat { |
| 1607 | NVME_ID_NS_NSFEAT_THINP = 1 << 0, |
| 1608 | NVME_ID_NS_NSFEAT_NSABP = 1 << 1, |
| 1609 | NVME_ID_NS_NSFEAT_DAE = 1 << 2, |
| 1610 | NVME_ID_NS_NSFEAT_UIDREUSE = 1 << 3, |
| 1611 | NVME_ID_NS_NSFEAT_OPTPERF_ALL = 3 << 4, |
| 1612 | NVME_ID_NS_NSFEAT_MAM = 1 << 6, |
| 1613 | NVME_ID_NS_NSFEAT_OPTRPERF = 1 << 7, |
| 1614 | }; |
| 1615 | |
| 1616 | #define NVME_ID_NS_DPS_TYPE(dps) (dps & NVME_ID_NS_DPS_TYPE_MASK) |
| 1617 | |
| 1618 | enum NvmePIFormat { |
| 1619 | NVME_PI_GUARD_16 = 0, |
| 1620 | NVME_PI_GUARD_64 = 2, |
| 1621 | }; |
| 1622 | |
| 1623 | typedef union NvmeDifTuple { |
| 1624 | struct { |
| 1625 | uint16_t guard; |
| 1626 | uint16_t apptag; |
| 1627 | uint32_t reftag; |
| 1628 | } g16; |
| 1629 | |
| 1630 | struct { |
| 1631 | uint64_t guard; |
| 1632 | uint16_t apptag; |
| 1633 | uint8_t sr[6]; |
| 1634 | } g64; |
| 1635 | } NvmeDifTuple; |
| 1636 | |
| 1637 | enum NvmeZoneAttr { |
| 1638 | NVME_ZA_FINISHED_BY_CTLR = 1 << 0, |
| 1639 | NVME_ZA_FINISH_RECOMMENDED = 1 << 1, |
| 1640 | NVME_ZA_RESET_RECOMMENDED = 1 << 2, |
| 1641 | NVME_ZA_ZRWA_VALID = 1 << 3, |
| 1642 | NVME_ZA_ZD_EXT_VALID = 1 << 7, |
| 1643 | }; |
| 1644 | |
| 1645 | typedef struct QEMU_PACKED NvmeZoneReportHeader { |
| 1646 | uint64_t nr_zones; |
| 1647 | uint8_t rsvd[56]; |
| 1648 | } NvmeZoneReportHeader; |
| 1649 | |
| 1650 | enum NvmeZoneReceiveAction { |
| 1651 | NVME_ZONE_REPORT = 0, |
| 1652 | NVME_ZONE_REPORT_EXTENDED = 1, |
| 1653 | }; |
| 1654 | |
| 1655 | enum NvmeZoneReportType { |
| 1656 | NVME_ZONE_REPORT_ALL = 0, |
| 1657 | NVME_ZONE_REPORT_EMPTY = 1, |
| 1658 | NVME_ZONE_REPORT_IMPLICITLY_OPEN = 2, |
| 1659 | NVME_ZONE_REPORT_EXPLICITLY_OPEN = 3, |
| 1660 | NVME_ZONE_REPORT_CLOSED = 4, |
| 1661 | NVME_ZONE_REPORT_FULL = 5, |
| 1662 | NVME_ZONE_REPORT_READ_ONLY = 6, |
| 1663 | NVME_ZONE_REPORT_OFFLINE = 7, |
| 1664 | }; |
| 1665 | |
| 1666 | enum NvmeZoneType { |
| 1667 | NVME_ZONE_TYPE_RESERVED = 0x00, |
| 1668 | NVME_ZONE_TYPE_SEQ_WRITE = 0x02, |
| 1669 | }; |
| 1670 | |
| 1671 | typedef struct QEMU_PACKED NvmeZoneSendCmd { |
| 1672 | uint8_t opcode; |
| 1673 | uint8_t flags; |
| 1674 | uint16_t cid; |
| 1675 | uint32_t nsid; |
| 1676 | uint32_t rsvd8[4]; |
| 1677 | NvmeCmdDptr dptr; |
| 1678 | uint64_t slba; |
| 1679 | uint32_t rsvd48; |
| 1680 | uint8_t zsa; |
| 1681 | uint8_t zsflags; |
| 1682 | uint8_t rsvd54[2]; |
| 1683 | uint32_t rsvd56[2]; |
| 1684 | } NvmeZoneSendCmd; |
| 1685 | |
| 1686 | enum NvmeZoneSendAction { |
| 1687 | NVME_ZONE_ACTION_RSD = 0x00, |
| 1688 | NVME_ZONE_ACTION_CLOSE = 0x01, |
| 1689 | NVME_ZONE_ACTION_FINISH = 0x02, |
| 1690 | NVME_ZONE_ACTION_OPEN = 0x03, |
| 1691 | NVME_ZONE_ACTION_RESET = 0x04, |
| 1692 | NVME_ZONE_ACTION_OFFLINE = 0x05, |
| 1693 | NVME_ZONE_ACTION_SET_ZD_EXT = 0x10, |
| 1694 | NVME_ZONE_ACTION_ZRWA_FLUSH = 0x11, |
| 1695 | }; |
| 1696 | |
| 1697 | enum { |
| 1698 | NVME_ZSFLAG_SELECT_ALL = 1 << 0, |
| 1699 | NVME_ZSFLAG_ZRWA_ALLOC = 1 << 1, |
| 1700 | }; |
| 1701 | |
| 1702 | typedef struct QEMU_PACKED NvmeZoneDescr { |
| 1703 | uint8_t zt; |
| 1704 | uint8_t zs; |
| 1705 | uint8_t za; |
| 1706 | uint8_t rsvd3[5]; |
| 1707 | uint64_t zcap; |
| 1708 | uint64_t zslba; |
| 1709 | uint64_t wp; |
| 1710 | uint8_t rsvd32[32]; |
| 1711 | } NvmeZoneDescr; |
| 1712 | |
| 1713 | typedef enum NvmeZoneState { |
| 1714 | NVME_ZONE_STATE_RESERVED = 0x00, |
| 1715 | NVME_ZONE_STATE_EMPTY = 0x01, |
| 1716 | NVME_ZONE_STATE_IMPLICITLY_OPEN = 0x02, |
| 1717 | NVME_ZONE_STATE_EXPLICITLY_OPEN = 0x03, |
| 1718 | NVME_ZONE_STATE_CLOSED = 0x04, |
| 1719 | NVME_ZONE_STATE_READ_ONLY = 0x0d, |
| 1720 | NVME_ZONE_STATE_FULL = 0x0e, |
| 1721 | NVME_ZONE_STATE_OFFLINE = 0x0f, |
| 1722 | } NvmeZoneState; |
| 1723 | |
| 1724 | typedef struct QEMU_PACKED NvmePriCtrlCap { |
| 1725 | uint16_t cntlid; |
| 1726 | uint16_t portid; |
| 1727 | uint8_t crt; |
| 1728 | uint8_t rsvd5[27]; |
| 1729 | uint32_t vqfrt; |
| 1730 | uint32_t vqrfa; |
| 1731 | uint16_t vqrfap; |
| 1732 | uint16_t vqprt; |
| 1733 | uint16_t vqfrsm; |
| 1734 | uint16_t vqgran; |
| 1735 | uint8_t rsvd48[16]; |
| 1736 | uint32_t vifrt; |
| 1737 | uint32_t virfa; |
| 1738 | uint16_t virfap; |
| 1739 | uint16_t viprt; |
| 1740 | uint16_t vifrsm; |
| 1741 | uint16_t vigran; |
| 1742 | uint8_t rsvd80[4016]; |
| 1743 | } NvmePriCtrlCap; |
| 1744 | |
| 1745 | typedef enum NvmePriCtrlCapCrt { |
| 1746 | NVME_CRT_VQ = 1 << 0, |
| 1747 | NVME_CRT_VI = 1 << 1, |
| 1748 | } NvmePriCtrlCapCrt; |
| 1749 | |
| 1750 | typedef struct QEMU_PACKED NvmeSecCtrlEntry { |
| 1751 | uint16_t scid; |
| 1752 | uint16_t pcid; |
| 1753 | uint8_t scs; |
| 1754 | uint8_t rsvd5[3]; |
| 1755 | uint16_t vfn; |
| 1756 | uint16_t nvq; |
| 1757 | uint16_t nvi; |
| 1758 | uint8_t rsvd14[18]; |
| 1759 | } NvmeSecCtrlEntry; |
| 1760 | |
| 1761 | typedef struct QEMU_PACKED NvmeSecCtrlList { |
| 1762 | uint8_t numcntl; |
| 1763 | uint8_t rsvd1[31]; |
| 1764 | NvmeSecCtrlEntry sec[127]; |
| 1765 | } NvmeSecCtrlList; |
| 1766 | |
| 1767 | typedef enum NvmeVirtMngmtAction { |
| 1768 | NVME_VIRT_MNGMT_ACTION_PRM_ALLOC = 0x01, |
| 1769 | NVME_VIRT_MNGMT_ACTION_SEC_OFFLINE = 0x07, |
| 1770 | NVME_VIRT_MNGMT_ACTION_SEC_ASSIGN = 0x08, |
| 1771 | NVME_VIRT_MNGMT_ACTION_SEC_ONLINE = 0x09, |
| 1772 | } NvmeVirtMngmtAction; |
| 1773 | |
| 1774 | typedef enum NvmeVirtualResourceType { |
| 1775 | NVME_VIRT_RES_QUEUE = 0x00, |
| 1776 | NVME_VIRT_RES_INTERRUPT = 0x01, |
| 1777 | } NvmeVirtualResourceType; |
| 1778 | |
| 1779 | typedef struct NvmeDirectiveIdentify { |
| 1780 | uint8_t supported; |
| 1781 | uint8_t unused1[31]; |
| 1782 | uint8_t enabled; |
| 1783 | uint8_t unused33[31]; |
| 1784 | uint8_t persistent; |
| 1785 | uint8_t unused65[31]; |
| 1786 | uint8_t rsvd64[4000]; |
| 1787 | } NvmeDirectiveIdentify; |
| 1788 | |
| 1789 | enum NvmeDirectiveTypes { |
| 1790 | NVME_DIRECTIVE_IDENTIFY = 0x0, |
| 1791 | NVME_DIRECTIVE_DATA_PLACEMENT = 0x2, |
| 1792 | }; |
| 1793 | |
| 1794 | enum NvmeDirectiveOperations { |
| 1795 | NVME_DIRECTIVE_RETURN_PARAMS = 0x1, |
| 1796 | }; |
| 1797 | |
| 1798 | typedef enum SfscSecurityProtocol { |
| 1799 | SFSC_SECURITY_PROT_INFO = 0x00, |
| 1800 | } SfscSecurityProtocol; |
| 1801 | |
| 1802 | typedef enum NvmeSecurityProtocols { |
| 1803 | NVME_SEC_PROT_DMTF_SPDM = 0xE8, |
| 1804 | } NvmeSecurityProtocols; |
| 1805 | |
| 1806 | typedef enum SpdmOperationCodes { |
| 1807 | SPDM_STORAGE_DISCOVERY = 0x1, /* Mandatory */ |
| 1808 | SPDM_STORAGE_PENDING_INFO = 0x2, /* Optional */ |
| 1809 | SPDM_STORAGE_MSG = 0x5, /* Mandatory */ |
| 1810 | SPDM_STORAGE_SEC_MSG = 0x6, /* Optional */ |
| 1811 | } SpdmOperationCodes; |
| 1812 | |
| 1813 | typedef struct QEMU_PACKED NvmeFdpConfsHdr { |
| 1814 | uint16_t num_confs; |
| 1815 | uint8_t version; |
| 1816 | uint8_t rsvd3; |
| 1817 | uint32_t size; |
| 1818 | uint8_t rsvd8[8]; |
| 1819 | } NvmeFdpConfsHdr; |
| 1820 | |
| 1821 | REG8(FDPA, 0x0) |
| 1822 | FIELD(FDPA, RGIF, 0, 4) |
| 1823 | FIELD(FDPA, VWC, 4, 1) |
| 1824 | FIELD(FDPA, VALID, 7, 1); |
| 1825 | |
| 1826 | typedef struct QEMU_PACKED NvmeFdpDescrHdr { |
| 1827 | uint16_t descr_size; |
| 1828 | uint8_t fdpa; |
| 1829 | uint8_t vss; |
| 1830 | uint32_t nrg; |
| 1831 | uint16_t nruh; |
| 1832 | uint16_t maxpids; |
| 1833 | uint32_t nnss; |
| 1834 | uint64_t runs; |
| 1835 | uint32_t erutl; |
| 1836 | uint8_t rsvd28[36]; |
| 1837 | } NvmeFdpDescrHdr; |
| 1838 | |
| 1839 | enum NvmeRuhType { |
| 1840 | NVME_RUHT_INITIALLY_ISOLATED = 1, |
| 1841 | NVME_RUHT_PERSISTENTLY_ISOLATED = 2, |
| 1842 | }; |
| 1843 | |
| 1844 | typedef struct QEMU_PACKED NvmeRuhDescr { |
| 1845 | uint8_t ruht; |
| 1846 | uint8_t rsvd1[3]; |
| 1847 | } NvmeRuhDescr; |
| 1848 | |
| 1849 | typedef struct QEMU_PACKED NvmeRuhuLog { |
| 1850 | uint16_t nruh; |
| 1851 | uint8_t rsvd2[6]; |
| 1852 | } NvmeRuhuLog; |
| 1853 | |
| 1854 | enum NvmeRuhAttributes { |
| 1855 | NVME_RUHA_UNUSED = 0, |
| 1856 | NVME_RUHA_HOST = 1, |
| 1857 | NVME_RUHA_CTRL = 2, |
| 1858 | }; |
| 1859 | |
| 1860 | typedef struct QEMU_PACKED NvmeRuhuDescr { |
| 1861 | uint8_t ruha; |
| 1862 | uint8_t rsvd1[7]; |
| 1863 | } NvmeRuhuDescr; |
| 1864 | |
| 1865 | typedef struct QEMU_PACKED NvmeFdpStatsLog { |
| 1866 | uint64_t hbmw[2]; |
| 1867 | uint64_t mbmw[2]; |
| 1868 | uint64_t mbe[2]; |
| 1869 | uint8_t rsvd48[16]; |
| 1870 | } NvmeFdpStatsLog; |
| 1871 | |
| 1872 | typedef struct QEMU_PACKED NvmeFdpEventsLog { |
| 1873 | uint32_t num_events; |
| 1874 | uint8_t rsvd4[60]; |
| 1875 | } NvmeFdpEventsLog; |
| 1876 | |
| 1877 | enum NvmeFdpEventType { |
| 1878 | FDP_EVT_RU_NOT_FULLY_WRITTEN = 0x0, |
| 1879 | FDP_EVT_RU_ATL_EXCEEDED = 0x1, |
| 1880 | FDP_EVT_CTRL_RESET_RUH = 0x2, |
| 1881 | FDP_EVT_INVALID_PID = 0x3, |
| 1882 | FDP_EVT_MEDIA_REALLOC = 0x80, |
| 1883 | FDP_EVT_RUH_IMPLICIT_RU_CHANGE = 0x81, |
| 1884 | }; |
| 1885 | |
| 1886 | enum NvmeFdpEventFlags { |
| 1887 | FDPEF_PIV = 1 << 0, |
| 1888 | FDPEF_NSIDV = 1 << 1, |
| 1889 | FDPEF_LV = 1 << 2, |
| 1890 | }; |
| 1891 | |
| 1892 | typedef struct QEMU_PACKED NvmeFdpEvent { |
| 1893 | uint8_t type; |
| 1894 | uint8_t flags; |
| 1895 | uint16_t pid; |
| 1896 | uint64_t timestamp; |
| 1897 | uint32_t nsid; |
| 1898 | uint64_t type_specific[2]; |
| 1899 | uint16_t rgid; |
| 1900 | uint8_t ruhid; |
| 1901 | uint8_t rsvd35[5]; |
| 1902 | uint64_t vendor[3]; |
| 1903 | } NvmeFdpEvent; |
| 1904 | |
| 1905 | typedef struct QEMU_PACKED NvmePhidList { |
| 1906 | uint16_t nnruhd; |
| 1907 | uint8_t rsvd2[6]; |
| 1908 | } NvmePhidList; |
| 1909 | |
| 1910 | typedef struct QEMU_PACKED NvmePhidDescr { |
| 1911 | uint8_t ruht; |
| 1912 | uint8_t rsvd1; |
| 1913 | uint16_t ruhid; |
| 1914 | } NvmePhidDescr; |
| 1915 | |
| 1916 | REG32(FEAT_FDP, 0x0) |
| 1917 | FIELD(FEAT_FDP, FDPE, 0, 1) |
| 1918 | FIELD(FEAT_FDP, CONF_NDX, 8, 8); |
| 1919 | |
| 1920 | typedef struct QEMU_PACKED NvmeFdpEventDescr { |
| 1921 | uint8_t evt; |
| 1922 | uint8_t evta; |
| 1923 | } NvmeFdpEventDescr; |
| 1924 | |
| 1925 | REG32(NVME_IOMR, 0x0) |
| 1926 | FIELD(NVME_IOMR, MO, 0, 8) |
| 1927 | FIELD(NVME_IOMR, MOS, 16, 16); |
| 1928 | |
| 1929 | enum NvmeIomr2Mo { |
| 1930 | NVME_IOMR_MO_NOP = 0x0, |
| 1931 | NVME_IOMR_MO_RUH_STATUS = 0x1, |
| 1932 | NVME_IOMR_MO_VENDOR_SPECIFIC = 0x255, |
| 1933 | }; |
| 1934 | |
| 1935 | typedef struct QEMU_PACKED NvmeRuhStatus { |
| 1936 | uint8_t rsvd0[14]; |
| 1937 | uint16_t nruhsd; |
| 1938 | } NvmeRuhStatus; |
| 1939 | |
| 1940 | typedef struct QEMU_PACKED NvmeRuhStatusDescr { |
| 1941 | uint16_t pid; |
| 1942 | uint16_t ruhid; |
| 1943 | uint32_t earutr; |
| 1944 | uint64_t ruamw; |
| 1945 | uint8_t rsvd16[16]; |
| 1946 | } NvmeRuhStatusDescr; |
| 1947 | |
| 1948 | REG32(NVME_IOMS, 0x0) |
| 1949 | FIELD(NVME_IOMS, MO, 0, 8) |
| 1950 | FIELD(NVME_IOMS, MOS, 16, 16); |
| 1951 | |
| 1952 | enum NvmeIoms2Mo { |
| 1953 | NVME_IOMS_MO_NOP = 0x0, |
| 1954 | NVME_IOMS_MO_RUH_UPDATE = 0x1, |
| 1955 | }; |
| 1956 | |
| 1957 | static inline void _nvme_check_size(void) |
| 1958 | { |
| 1959 | QEMU_BUILD_BUG_ON(sizeof(NvmeBar) != 4096); |
| 1960 | QEMU_BUILD_BUG_ON(sizeof(NvmeAerResult) != 4); |
| 1961 | QEMU_BUILD_BUG_ON(sizeof(NvmeZonedResult) != 8); |
| 1962 | QEMU_BUILD_BUG_ON(sizeof(NvmeCqe) != 16); |
| 1963 | QEMU_BUILD_BUG_ON(sizeof(NvmeDsmRange) != 16); |
| 1964 | QEMU_BUILD_BUG_ON(sizeof(NvmeCopySourceRangeFormat0_2) != 32); |
| 1965 | QEMU_BUILD_BUG_ON(sizeof(NvmeCopySourceRangeFormat1_3) != 40); |
| 1966 | QEMU_BUILD_BUG_ON(sizeof(NvmeCmd) != 64); |
| 1967 | QEMU_BUILD_BUG_ON(sizeof(NvmeDeleteQ) != 64); |
| 1968 | QEMU_BUILD_BUG_ON(sizeof(NvmeCreateCq) != 64); |
| 1969 | QEMU_BUILD_BUG_ON(sizeof(NvmeCreateSq) != 64); |
| 1970 | QEMU_BUILD_BUG_ON(sizeof(NvmeIdentify) != 64); |
| 1971 | QEMU_BUILD_BUG_ON(sizeof(NvmeRwCmd) != 64); |
| 1972 | QEMU_BUILD_BUG_ON(sizeof(NvmeDsmCmd) != 64); |
| 1973 | QEMU_BUILD_BUG_ON(sizeof(NvmeCopyCmd) != 64); |
| 1974 | QEMU_BUILD_BUG_ON(sizeof(NvmeRangeType) != 64); |
| 1975 | QEMU_BUILD_BUG_ON(sizeof(NvmeHostBehaviorSupport) != 512); |
| 1976 | QEMU_BUILD_BUG_ON(sizeof(NvmeErrorLog) != 64); |
| 1977 | QEMU_BUILD_BUG_ON(sizeof(NvmeFwSlotInfoLog) != 512); |
| 1978 | QEMU_BUILD_BUG_ON(sizeof(NvmeSmartLog) != 512); |
| 1979 | QEMU_BUILD_BUG_ON(sizeof(NvmeSmartLogExtended) != 512); |
| 1980 | QEMU_BUILD_BUG_ON(sizeof(NvmeEffectsLog) != 4096); |
| 1981 | QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrl) != 4096); |
| 1982 | QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrlZoned) != 4096); |
| 1983 | QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrlNvm) != 4096); |
| 1984 | QEMU_BUILD_BUG_ON(sizeof(NvmeLBAF) != 4); |
| 1985 | QEMU_BUILD_BUG_ON(sizeof(NvmeLBAFE) != 16); |
| 1986 | QEMU_BUILD_BUG_ON(sizeof(NvmeIdNs) != 4096); |
| 1987 | QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsInd) != 4096); |
| 1988 | QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsNvm) != 4096); |
| 1989 | QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsZoned) != 4096); |
| 1990 | QEMU_BUILD_BUG_ON(sizeof(NvmeSglDescriptor) != 16); |
| 1991 | QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsDescr) != 4); |
| 1992 | QEMU_BUILD_BUG_ON(sizeof(NvmeZoneDescr) != 64); |
| 1993 | QEMU_BUILD_BUG_ON(sizeof(NvmeDifTuple) != 16); |
| 1994 | QEMU_BUILD_BUG_ON(sizeof(NvmePriCtrlCap) != 4096); |
| 1995 | QEMU_BUILD_BUG_ON(sizeof(NvmeSecCtrlEntry) != 32); |
| 1996 | QEMU_BUILD_BUG_ON(sizeof(NvmeSecCtrlList) != 4096); |
| 1997 | QEMU_BUILD_BUG_ON(sizeof(NvmeEndGrpLog) != 512); |
| 1998 | QEMU_BUILD_BUG_ON(sizeof(NvmeDirectiveIdentify) != 4096); |
| 1999 | } |
| 2000 | #endif |