| 1 | /* Interface between the opcode library and its callers. |
| 2 | Written by Cygnus Support, 1993. |
| 3 | |
| 4 | The opcode library (libopcodes.a) provides instruction decoders for |
| 5 | a large variety of instruction sets, callable with an identical |
| 6 | interface, for making instruction-processing programs more independent |
| 7 | of the instruction set being processed. */ |
| 8 | |
| 9 | #ifndef DISAS_DIS_ASM_H |
| 10 | #define DISAS_DIS_ASM_H |
| 11 | |
| 12 | #include "qemu/bswap.h" |
| 13 | |
| 14 | typedef void *PTR; |
| 15 | typedef uint64_t bfd_vma; |
| 16 | typedef int64_t bfd_signed_vma; |
| 17 | typedef uint8_t bfd_byte; |
| 18 | #define sprintf_vma(s,x) sprintf (s, "%0" PRIx64, x) |
| 19 | #define snprintf_vma(s,ss,x) snprintf (s, ss, "%0" PRIx64, x) |
| 20 | |
| 21 | #define BFD64 |
| 22 | |
| 23 | enum bfd_flavour { |
| 24 | bfd_target_unknown_flavour, |
| 25 | bfd_target_aout_flavour, |
| 26 | bfd_target_coff_flavour, |
| 27 | bfd_target_ecoff_flavour, |
| 28 | bfd_target_elf_flavour, |
| 29 | bfd_target_ieee_flavour, |
| 30 | bfd_target_nlm_flavour, |
| 31 | bfd_target_oasys_flavour, |
| 32 | bfd_target_tekhex_flavour, |
| 33 | bfd_target_srec_flavour, |
| 34 | bfd_target_ihex_flavour, |
| 35 | bfd_target_som_flavour, |
| 36 | bfd_target_os9k_flavour, |
| 37 | bfd_target_versados_flavour, |
| 38 | bfd_target_msdos_flavour, |
| 39 | bfd_target_evax_flavour |
| 40 | }; |
| 41 | |
| 42 | enum bfd_endian { BFD_ENDIAN_BIG, BFD_ENDIAN_LITTLE, BFD_ENDIAN_UNKNOWN }; |
| 43 | |
| 44 | enum bfd_architecture |
| 45 | { |
| 46 | bfd_arch_unknown, /* File arch not known */ |
| 47 | bfd_arch_obscure, /* Arch known, not one of these */ |
| 48 | bfd_arch_m68k, /* Motorola 68xxx */ |
| 49 | #define bfd_mach_m68000 1 |
| 50 | #define bfd_mach_m68008 2 |
| 51 | #define bfd_mach_m68010 3 |
| 52 | #define bfd_mach_m68020 4 |
| 53 | #define bfd_mach_m68030 5 |
| 54 | #define bfd_mach_m68040 6 |
| 55 | #define bfd_mach_m68060 7 |
| 56 | #define bfd_mach_cpu32 8 |
| 57 | #define bfd_mach_mcf5200 9 |
| 58 | #define bfd_mach_mcf5206e 10 |
| 59 | #define bfd_mach_mcf5307 11 |
| 60 | #define bfd_mach_mcf5407 12 |
| 61 | #define bfd_mach_mcf528x 13 |
| 62 | #define bfd_mach_mcfv4e 14 |
| 63 | #define bfd_mach_mcf521x 15 |
| 64 | #define bfd_mach_mcf5249 16 |
| 65 | #define bfd_mach_mcf547x 17 |
| 66 | #define bfd_mach_mcf548x 18 |
| 67 | bfd_arch_vax, /* DEC Vax */ |
| 68 | bfd_arch_i960, /* Intel 960 */ |
| 69 | /* The order of the following is important. |
| 70 | lower number indicates a machine type that |
| 71 | only accepts a subset of the instructions |
| 72 | available to machines with higher numbers. |
| 73 | The exception is the "ca", which is |
| 74 | incompatible with all other machines except |
| 75 | "core". */ |
| 76 | |
| 77 | #define bfd_mach_i960_core 1 |
| 78 | #define bfd_mach_i960_ka_sa 2 |
| 79 | #define bfd_mach_i960_kb_sb 3 |
| 80 | #define bfd_mach_i960_mc 4 |
| 81 | #define bfd_mach_i960_xa 5 |
| 82 | #define bfd_mach_i960_ca 6 |
| 83 | #define bfd_mach_i960_jx 7 |
| 84 | #define bfd_mach_i960_hx 8 |
| 85 | |
| 86 | bfd_arch_a29k, /* AMD 29000 */ |
| 87 | bfd_arch_sparc, /* SPARC */ |
| 88 | #define bfd_mach_sparc 1 |
| 89 | /* The difference between v8plus and v9 is that v9 is a true 64 bit env. */ |
| 90 | #define bfd_mach_sparc_sparclet 2 |
| 91 | #define bfd_mach_sparc_sparclite 3 |
| 92 | #define bfd_mach_sparc_v8plus 4 |
| 93 | #define bfd_mach_sparc_v8plusa 5 /* with ultrasparc add'ns. */ |
| 94 | #define bfd_mach_sparc_sparclite_le 6 |
| 95 | #define bfd_mach_sparc_v9 7 |
| 96 | #define bfd_mach_sparc_v9a 8 /* with ultrasparc add'ns. */ |
| 97 | #define bfd_mach_sparc_v8plusb 9 /* with cheetah add'ns. */ |
| 98 | #define bfd_mach_sparc_v9b 10 /* with cheetah add'ns. */ |
| 99 | /* Nonzero if MACH has the v9 instruction set. */ |
| 100 | #define bfd_mach_sparc_v9_p(mach) \ |
| 101 | ((mach) >= bfd_mach_sparc_v8plus && (mach) <= bfd_mach_sparc_v9b \ |
| 102 | && (mach) != bfd_mach_sparc_sparclite_le) |
| 103 | bfd_arch_mips, /* MIPS Rxxxx */ |
| 104 | #define bfd_mach_mips3000 3000 |
| 105 | #define bfd_mach_mips3900 3900 |
| 106 | #define bfd_mach_mips4000 4000 |
| 107 | #define bfd_mach_mips4010 4010 |
| 108 | #define bfd_mach_mips4100 4100 |
| 109 | #define bfd_mach_mips4300 4300 |
| 110 | #define bfd_mach_mips4400 4400 |
| 111 | #define bfd_mach_mips4600 4600 |
| 112 | #define bfd_mach_mips4650 4650 |
| 113 | #define bfd_mach_mips5000 5000 |
| 114 | #define bfd_mach_mips6000 6000 |
| 115 | #define bfd_mach_mips8000 8000 |
| 116 | #define bfd_mach_mips10000 10000 |
| 117 | #define bfd_mach_mips16 16 |
| 118 | bfd_arch_i386, /* Intel 386 */ |
| 119 | #define bfd_mach_i386_i386 0 |
| 120 | #define bfd_mach_i386_i8086 1 |
| 121 | #define bfd_mach_i386_i386_intel_syntax 2 |
| 122 | #define bfd_mach_x86_64 3 |
| 123 | #define bfd_mach_x86_64_intel_syntax 4 |
| 124 | bfd_arch_we32k, /* AT&T WE32xxx */ |
| 125 | bfd_arch_tahoe, /* CCI/Harris Tahoe */ |
| 126 | bfd_arch_i860, /* Intel 860 */ |
| 127 | bfd_arch_romp, /* IBM ROMP PC/RT */ |
| 128 | bfd_arch_alliant, /* Alliant */ |
| 129 | bfd_arch_convex, /* Convex */ |
| 130 | bfd_arch_m88k, /* Motorola 88xxx */ |
| 131 | bfd_arch_pyramid, /* Pyramid Technology */ |
| 132 | bfd_arch_h8300, /* Hitachi H8/300 */ |
| 133 | #define bfd_mach_h8300 1 |
| 134 | #define bfd_mach_h8300h 2 |
| 135 | #define bfd_mach_h8300s 3 |
| 136 | bfd_arch_powerpc, /* PowerPC */ |
| 137 | #define bfd_mach_ppc 0 |
| 138 | #define bfd_mach_ppc64 1 |
| 139 | #define bfd_mach_ppc_403 403 |
| 140 | #define bfd_mach_ppc_403gc 4030 |
| 141 | #define bfd_mach_ppc_e500 500 |
| 142 | #define bfd_mach_ppc_505 505 |
| 143 | #define bfd_mach_ppc_601 601 |
| 144 | #define bfd_mach_ppc_602 602 |
| 145 | #define bfd_mach_ppc_603 603 |
| 146 | #define bfd_mach_ppc_ec603e 6031 |
| 147 | #define bfd_mach_ppc_604 604 |
| 148 | #define bfd_mach_ppc_620 620 |
| 149 | #define bfd_mach_ppc_630 630 |
| 150 | #define bfd_mach_ppc_750 750 |
| 151 | #define bfd_mach_ppc_860 860 |
| 152 | #define bfd_mach_ppc_a35 35 |
| 153 | #define bfd_mach_ppc_rs64ii 642 |
| 154 | #define bfd_mach_ppc_rs64iii 643 |
| 155 | #define bfd_mach_ppc_7400 7400 |
| 156 | bfd_arch_rs6000, /* IBM RS/6000 */ |
| 157 | bfd_arch_hppa, /* HP PA RISC */ |
| 158 | #define bfd_mach_hppa10 10 |
| 159 | #define bfd_mach_hppa11 11 |
| 160 | #define bfd_mach_hppa20 20 |
| 161 | #define bfd_mach_hppa20w 25 |
| 162 | bfd_arch_d10v, /* Mitsubishi D10V */ |
| 163 | bfd_arch_z8k, /* Zilog Z8000 */ |
| 164 | #define bfd_mach_z8001 1 |
| 165 | #define bfd_mach_z8002 2 |
| 166 | bfd_arch_h8500, /* Hitachi H8/500 */ |
| 167 | bfd_arch_sh, /* Hitachi SH */ |
| 168 | #define bfd_mach_sh 1 |
| 169 | #define bfd_mach_sh2 0x20 |
| 170 | #define bfd_mach_sh_dsp 0x2d |
| 171 | #define bfd_mach_sh2a 0x2a |
| 172 | #define bfd_mach_sh2a_nofpu 0x2b |
| 173 | #define bfd_mach_sh2e 0x2e |
| 174 | #define bfd_mach_sh3 0x30 |
| 175 | #define bfd_mach_sh3_nommu 0x31 |
| 176 | #define bfd_mach_sh3_dsp 0x3d |
| 177 | #define bfd_mach_sh3e 0x3e |
| 178 | #define bfd_mach_sh4 0x40 |
| 179 | #define bfd_mach_sh4_nofpu 0x41 |
| 180 | #define bfd_mach_sh4_nommu_nofpu 0x42 |
| 181 | #define bfd_mach_sh4a 0x4a |
| 182 | #define bfd_mach_sh4a_nofpu 0x4b |
| 183 | #define bfd_mach_sh4al_dsp 0x4d |
| 184 | #define bfd_mach_sh5 0x50 |
| 185 | bfd_arch_alpha, /* Dec Alpha */ |
| 186 | #define bfd_mach_alpha 1 |
| 187 | #define bfd_mach_alpha_ev4 0x10 |
| 188 | #define bfd_mach_alpha_ev5 0x20 |
| 189 | #define bfd_mach_alpha_ev6 0x30 |
| 190 | bfd_arch_arm, /* Advanced Risc Machines ARM */ |
| 191 | #define bfd_mach_arm_unknown 0 |
| 192 | #define bfd_mach_arm_2 1 |
| 193 | #define bfd_mach_arm_2a 2 |
| 194 | #define bfd_mach_arm_3 3 |
| 195 | #define bfd_mach_arm_3M 4 |
| 196 | #define bfd_mach_arm_4 5 |
| 197 | #define bfd_mach_arm_4T 6 |
| 198 | #define bfd_mach_arm_5 7 |
| 199 | #define bfd_mach_arm_5T 8 |
| 200 | #define bfd_mach_arm_5TE 9 |
| 201 | #define bfd_mach_arm_XScale 10 |
| 202 | #define bfd_mach_arm_ep9312 11 |
| 203 | #define bfd_mach_arm_iWMMXt 12 |
| 204 | #define bfd_mach_arm_iWMMXt2 13 |
| 205 | bfd_arch_ns32k, /* National Semiconductors ns32000 */ |
| 206 | bfd_arch_w65, /* WDC 65816 */ |
| 207 | bfd_arch_tic30, /* Texas Instruments TMS320C30 */ |
| 208 | bfd_arch_v850, /* NEC V850 */ |
| 209 | #define bfd_mach_v850 0 |
| 210 | bfd_arch_arc, /* Argonaut RISC Core */ |
| 211 | #define bfd_mach_arc_base 0 |
| 212 | bfd_arch_m32r, /* Mitsubishi M32R/D */ |
| 213 | #define bfd_mach_m32r 0 /* backwards compatibility */ |
| 214 | bfd_arch_mn10200, /* Matsushita MN10200 */ |
| 215 | bfd_arch_mn10300, /* Matsushita MN10300 */ |
| 216 | bfd_arch_avr, /* AVR microcontrollers */ |
| 217 | #define bfd_mach_avr1 1 |
| 218 | #define bfd_mach_avr2 2 |
| 219 | #define bfd_mach_avr25 25 |
| 220 | #define bfd_mach_avr3 3 |
| 221 | #define bfd_mach_avr31 31 |
| 222 | #define bfd_mach_avr35 35 |
| 223 | #define bfd_mach_avr4 4 |
| 224 | #define bfd_mach_avr5 5 |
| 225 | #define bfd_mach_avr51 51 |
| 226 | #define bfd_mach_avr6 6 |
| 227 | #define bfd_mach_avrtiny 100 |
| 228 | #define bfd_mach_avrxmega1 101 |
| 229 | #define bfd_mach_avrxmega2 102 |
| 230 | #define bfd_mach_avrxmega3 103 |
| 231 | #define bfd_mach_avrxmega4 104 |
| 232 | #define bfd_mach_avrxmega5 105 |
| 233 | #define bfd_mach_avrxmega6 106 |
| 234 | #define bfd_mach_avrxmega7 107 |
| 235 | bfd_arch_microblaze, /* Xilinx MicroBlaze. */ |
| 236 | bfd_arch_moxie, /* The Moxie core. */ |
| 237 | bfd_arch_ia64, /* HP/Intel ia64 */ |
| 238 | #define bfd_mach_ia64_elf64 64 |
| 239 | #define bfd_mach_ia64_elf32 32 |
| 240 | bfd_arch_rx, /* Renesas RX */ |
| 241 | #define bfd_mach_rx 0x75 |
| 242 | #define bfd_mach_rx_v2 0x76 |
| 243 | #define bfd_mach_rx_v3 0x77 |
| 244 | bfd_arch_loongarch, |
| 245 | bfd_arch_last |
| 246 | }; |
| 247 | #define bfd_mach_s390_31 31 |
| 248 | #define bfd_mach_s390_64 64 |
| 249 | |
| 250 | typedef struct symbol_cache_entry |
| 251 | { |
| 252 | const char *name; |
| 253 | union |
| 254 | { |
| 255 | PTR p; |
| 256 | bfd_vma i; |
| 257 | } udata; |
| 258 | } asymbol; |
| 259 | |
| 260 | typedef int (*fprintf_function)(FILE *f, const char *fmt, ...) |
| 261 | G_GNUC_PRINTF(2, 3); |
| 262 | |
| 263 | enum dis_insn_type { |
| 264 | dis_noninsn, /* Not a valid instruction */ |
| 265 | dis_nonbranch, /* Not a branch instruction */ |
| 266 | dis_branch, /* Unconditional branch */ |
| 267 | dis_condbranch, /* Conditional branch */ |
| 268 | dis_jsr, /* Jump to subroutine */ |
| 269 | dis_condjsr, /* Conditional jump to subroutine */ |
| 270 | dis_dref, /* Data reference instruction */ |
| 271 | dis_dref2 /* Two data references in instruction */ |
| 272 | }; |
| 273 | |
| 274 | /* This struct is passed into the instruction decoding routine, |
| 275 | and is passed back out into each callback. The various fields are used |
| 276 | for conveying information from your main routine into your callbacks, |
| 277 | for passing information into the instruction decoders (such as the |
| 278 | addresses of the callback functions), or for passing information |
| 279 | back from the instruction decoders to their callers. |
| 280 | |
| 281 | It must be initialized before it is first passed; this can be done |
| 282 | by hand, or using one of the initialization macros below. */ |
| 283 | |
| 284 | typedef struct disassemble_info { |
| 285 | fprintf_function fprintf_func; |
| 286 | FILE *stream; |
| 287 | PTR application_data; |
| 288 | |
| 289 | /* Target description. We could replace this with a pointer to the bfd, |
| 290 | but that would require one. There currently isn't any such requirement |
| 291 | so to avoid introducing one we record these explicitly. */ |
| 292 | /* The bfd_flavour. This can be bfd_target_unknown_flavour. */ |
| 293 | enum bfd_flavour flavour; |
| 294 | /* The bfd_arch value. */ |
| 295 | enum bfd_architecture arch; |
| 296 | /* The bfd_mach value. */ |
| 297 | unsigned long mach; |
| 298 | /* Endianness (for bi-endian cpus). Mono-endian cpus can ignore this. */ |
| 299 | enum bfd_endian endian; |
| 300 | |
| 301 | /* An array of pointers to symbols either at the location being disassembled |
| 302 | or at the start of the function being disassembled. The array is sorted |
| 303 | so that the first symbol is intended to be the one used. The others are |
| 304 | present for any misc. purposes. This is not set reliably, but if it is |
| 305 | not NULL, it is correct. */ |
| 306 | asymbol **symbols; |
| 307 | /* Number of symbols in array. */ |
| 308 | int num_symbols; |
| 309 | |
| 310 | /* For use by the disassembler. |
| 311 | The top 16 bits are reserved for public use (and are documented here). |
| 312 | The bottom 16 bits are for the internal use of the disassembler. */ |
| 313 | unsigned long flags; |
| 314 | #define INSN_HAS_RELOC 0x80000000 |
| 315 | #define INSN_ARM_BE32 0x00010000 |
| 316 | PTR private_data; |
| 317 | |
| 318 | /* Function used to get bytes to disassemble. MEMADDR is the |
| 319 | address of the stuff to be disassembled, MYADDR is the address to |
| 320 | put the bytes in, and LENGTH is the number of bytes to read. |
| 321 | INFO is a pointer to this struct. |
| 322 | Returns an errno value or 0 for success. */ |
| 323 | int (*read_memory_func) |
| 324 | (bfd_vma memaddr, bfd_byte *myaddr, int length, |
| 325 | struct disassemble_info *info); |
| 326 | |
| 327 | /* Function which should be called if we get an error that we can't |
| 328 | recover from. STATUS is the errno value from read_memory_func and |
| 329 | MEMADDR is the address that we were trying to read. INFO is a |
| 330 | pointer to this struct. */ |
| 331 | void (*memory_error_func) |
| 332 | (int status, bfd_vma memaddr, struct disassemble_info *info); |
| 333 | |
| 334 | /* Function called to print ADDR. */ |
| 335 | void (*print_address_func) |
| 336 | (bfd_vma addr, struct disassemble_info *info); |
| 337 | |
| 338 | /* Function called to print an instruction. The function is architecture |
| 339 | * specific. |
| 340 | */ |
| 341 | int (*print_insn)(bfd_vma addr, struct disassemble_info *info); |
| 342 | |
| 343 | /* Function called to determine if there is a symbol at the given ADDR. |
| 344 | If there is, the function returns 1, otherwise it returns 0. |
| 345 | This is used by ports which support an overlay manager where |
| 346 | the overlay number is held in the top part of an address. In |
| 347 | some circumstances we want to include the overlay number in the |
| 348 | address, (normally because there is a symbol associated with |
| 349 | that address), but sometimes we want to mask out the overlay bits. */ |
| 350 | int (* symbol_at_address_func) |
| 351 | (bfd_vma addr, struct disassemble_info * info); |
| 352 | |
| 353 | /* These are for buffer_read_memory. */ |
| 354 | const bfd_byte *buffer; |
| 355 | bfd_vma buffer_vma; |
| 356 | int buffer_length; |
| 357 | |
| 358 | /* This variable may be set by the instruction decoder. It suggests |
| 359 | the number of bytes objdump should display on a single line. If |
| 360 | the instruction decoder sets this, it should always set it to |
| 361 | the same value in order to get reasonable looking output. */ |
| 362 | int bytes_per_line; |
| 363 | |
| 364 | /* the next two variables control the way objdump displays the raw data */ |
| 365 | /* For example, if bytes_per_line is 8 and bytes_per_chunk is 4, the */ |
| 366 | /* output will look like this: |
| 367 | 00: 00000000 00000000 |
| 368 | with the chunks displayed according to "display_endian". */ |
| 369 | int bytes_per_chunk; |
| 370 | enum bfd_endian display_endian; |
| 371 | |
| 372 | /* Results from instruction decoders. Not all decoders yet support |
| 373 | this information. This info is set each time an instruction is |
| 374 | decoded, and is only valid for the last such instruction. |
| 375 | |
| 376 | To determine whether this decoder supports this information, set |
| 377 | insn_info_valid to 0, decode an instruction, then check it. */ |
| 378 | |
| 379 | char insn_info_valid; /* Branch info has been set. */ |
| 380 | char branch_delay_insns; /* How many sequential insn's will run before |
| 381 | a branch takes effect. (0 = normal) */ |
| 382 | char data_size; /* Size of data reference in insn, in bytes */ |
| 383 | enum dis_insn_type insn_type; /* Type of instruction */ |
| 384 | bfd_vma target; /* Target address of branch or dref, if known; |
| 385 | zero if unknown. */ |
| 386 | bfd_vma target2; /* Second target address for dref2 */ |
| 387 | |
| 388 | /* Command line options specific to the target disassembler. */ |
| 389 | char * disassembler_options; |
| 390 | |
| 391 | /* |
| 392 | * When true instruct the disassembler it may preface the |
| 393 | * disassembly with the opcodes values if it wants to. This is |
| 394 | * mainly for the benefit of the plugin interface which doesn't want |
| 395 | * that. |
| 396 | */ |
| 397 | bool show_opcodes; |
| 398 | |
| 399 | /* Field intended to be used by targets in any way they deem suitable. */ |
| 400 | const void *target_info; |
| 401 | |
| 402 | /* Options for Capstone disassembly. */ |
| 403 | int cap_arch; |
| 404 | int cap_mode; |
| 405 | int cap_insn_unit; |
| 406 | int cap_insn_split; |
| 407 | |
| 408 | } disassemble_info; |
| 409 | |
| 410 | /* Standard disassemblers. Disassemble one instruction at the given |
| 411 | target address. Return number of bytes processed. */ |
| 412 | typedef int (*disassembler_ftype) (bfd_vma, disassemble_info *); |
| 413 | |
| 414 | int print_insn_tci(bfd_vma, disassemble_info*); |
| 415 | int print_insn_big_mips (bfd_vma, disassemble_info*); |
| 416 | int print_insn_little_mips (bfd_vma, disassemble_info*); |
| 417 | int print_insn_nanomips (bfd_vma, disassemble_info*); |
| 418 | int print_insn_m68k (bfd_vma, disassemble_info*); |
| 419 | int print_insn_z8001 (bfd_vma, disassemble_info*); |
| 420 | int print_insn_z8002 (bfd_vma, disassemble_info*); |
| 421 | int print_insn_h8300 (bfd_vma, disassemble_info*); |
| 422 | int print_insn_h8300h (bfd_vma, disassemble_info*); |
| 423 | int print_insn_h8300s (bfd_vma, disassemble_info*); |
| 424 | int print_insn_h8500 (bfd_vma, disassemble_info*); |
| 425 | int print_insn_arm_a64 (bfd_vma, disassemble_info*); |
| 426 | int print_insn_alpha (bfd_vma, disassemble_info*); |
| 427 | disassembler_ftype arc_get_disassembler (int, int); |
| 428 | int print_insn_sparc (bfd_vma, disassemble_info*); |
| 429 | int print_insn_big_a29k (bfd_vma, disassemble_info*); |
| 430 | int print_insn_little_a29k (bfd_vma, disassemble_info*); |
| 431 | int print_insn_i960 (bfd_vma, disassemble_info*); |
| 432 | int print_insn_sh (bfd_vma, disassemble_info*); |
| 433 | int print_insn_shl (bfd_vma, disassemble_info*); |
| 434 | int print_insn_hppa (bfd_vma, disassemble_info*); |
| 435 | int print_insn_m32r (bfd_vma, disassemble_info*); |
| 436 | int print_insn_m88k (bfd_vma, disassemble_info*); |
| 437 | int print_insn_mn10200 (bfd_vma, disassemble_info*); |
| 438 | int print_insn_mn10300 (bfd_vma, disassemble_info*); |
| 439 | int print_insn_ns32k (bfd_vma, disassemble_info*); |
| 440 | int print_insn_big_powerpc (bfd_vma, disassemble_info*); |
| 441 | int print_insn_little_powerpc (bfd_vma, disassemble_info*); |
| 442 | int print_insn_rs6000 (bfd_vma, disassemble_info*); |
| 443 | int print_insn_w65 (bfd_vma, disassemble_info*); |
| 444 | int print_insn_d10v (bfd_vma, disassemble_info*); |
| 445 | int print_insn_v850 (bfd_vma, disassemble_info*); |
| 446 | int print_insn_tic30 (bfd_vma, disassemble_info*); |
| 447 | int print_insn_microblaze (bfd_vma, disassemble_info*); |
| 448 | int print_insn_ia64 (bfd_vma, disassemble_info*); |
| 449 | int print_insn_xtensa (bfd_vma, disassemble_info*); |
| 450 | int print_insn_riscv32 (bfd_vma, disassemble_info*); |
| 451 | int print_insn_riscv64 (bfd_vma, disassemble_info*); |
| 452 | int print_insn_riscv128 (bfd_vma, disassemble_info*); |
| 453 | int print_insn_rx(bfd_vma, disassemble_info *); |
| 454 | int print_insn_hexagon(bfd_vma, disassemble_info *); |
| 455 | int print_insn_loongarch(bfd_vma, disassemble_info *); |
| 456 | |
| 457 | #ifdef CONFIG_CAPSTONE |
| 458 | bool cap_disas_target(disassemble_info *info, uint64_t pc, size_t size); |
| 459 | bool cap_disas_host(disassemble_info *info, const void *code, size_t size); |
| 460 | bool cap_disas_monitor(disassemble_info *info, uint64_t pc, int count); |
| 461 | bool cap_disas_plugin(disassemble_info *info, uint64_t pc, size_t size); |
| 462 | #else |
| 463 | # define cap_disas_target(i, p, s) false |
| 464 | # define cap_disas_host(i, p, s) false |
| 465 | # define cap_disas_monitor(i, p, c) false |
| 466 | # define cap_disas_plugin(i, p, c) false |
| 467 | #endif /* CONFIG_CAPSTONE */ |
| 468 | |
| 469 | #ifndef ATTRIBUTE_UNUSED |
| 470 | #define ATTRIBUTE_UNUSED __attribute__((unused)) |
| 471 | #endif |
| 472 | |
| 473 | /* from libbfd */ |
| 474 | |
| 475 | static inline bfd_vma bfd_getl64(const bfd_byte *addr) |
| 476 | { |
| 477 | return ldq_le_p(addr); |
| 478 | } |
| 479 | |
| 480 | static inline bfd_vma bfd_getl32(const bfd_byte *addr) |
| 481 | { |
| 482 | return (uint32_t)ldl_le_p(addr); |
| 483 | } |
| 484 | |
| 485 | static inline bfd_vma bfd_getl16(const bfd_byte *addr) |
| 486 | { |
| 487 | return lduw_le_p(addr); |
| 488 | } |
| 489 | |
| 490 | static inline bfd_vma bfd_getb32(const bfd_byte *addr) |
| 491 | { |
| 492 | return (uint32_t)ldl_be_p(addr); |
| 493 | } |
| 494 | |
| 495 | static inline bfd_vma bfd_getb16(const bfd_byte *addr) |
| 496 | { |
| 497 | return lduw_be_p(addr); |
| 498 | } |
| 499 | |
| 500 | typedef bool bfd_boolean; |
| 501 | |
| 502 | #endif /* DISAS_DIS_ASM_H */ |