| 1 | /* |
| 2 | * Common CPU TLB handling |
| 3 | * |
| 4 | * Copyright (c) 2003 Fabrice Bellard |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2.1 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #ifndef CPUTLB_H |
| 21 | #define CPUTLB_H |
| 22 | |
| 23 | #include "exec/cpu-common.h" |
| 24 | #include "exec/hwaddr.h" |
| 25 | #include "exec/memattrs.h" |
| 26 | #include "exec/vaddr.h" |
| 27 | |
| 28 | #ifndef CONFIG_USER_ONLY |
| 29 | #include "system/ram_addr.h" |
| 30 | |
| 31 | void tlb_reset_dirty(CPUState *cpu, uintptr_t start, uintptr_t length); |
| 32 | void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length); |
| 33 | #endif |
| 34 | |
| 35 | /** |
| 36 | * tlb_set_page_full: |
| 37 | * @cpu: CPU context |
| 38 | * @mmu_idx: mmu index of the tlb to modify |
| 39 | * @addr: virtual address of the entry to add |
| 40 | * @full: the details of the tlb entry |
| 41 | * |
| 42 | * Add an entry to @cpu tlb index @mmu_idx. All of the fields of |
| 43 | * @full must be filled, except for xlat_offset & section, and |
| 44 | * constitute the complete description of the translated page. |
| 45 | * |
| 46 | * This is generally called by the target tlb_fill function after |
| 47 | * having performed a successful page table walk to find the physical |
| 48 | * address and attributes for the translation. |
| 49 | * |
| 50 | * At most one entry for a given virtual address is permitted. Only a |
| 51 | * single TARGET_PAGE_SIZE region is mapped; @full->lg_page_size is only |
| 52 | * used by tlb_flush_page. |
| 53 | */ |
| 54 | void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr addr, |
| 55 | CPUTLBEntryFull *full); |
| 56 | |
| 57 | /** |
| 58 | * tlb_set_page_with_attrs: |
| 59 | * @cpu: CPU to add this TLB entry for |
| 60 | * @addr: virtual address of page to add entry for |
| 61 | * @paddr: physical address of the page |
| 62 | * @attrs: memory transaction attributes |
| 63 | * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits) |
| 64 | * @mmu_idx: MMU index to insert TLB entry for |
| 65 | * @size: size of the page in bytes |
| 66 | * |
| 67 | * Add an entry to this CPU's TLB (a mapping from virtual address |
| 68 | * @addr to physical address @paddr) with the specified memory |
| 69 | * transaction attributes. This is generally called by the target CPU |
| 70 | * specific code after it has been called through the tlb_fill() |
| 71 | * entry point and performed a successful page table walk to find |
| 72 | * the physical address and attributes for the virtual address |
| 73 | * which provoked the TLB miss. |
| 74 | * |
| 75 | * At most one entry for a given virtual address is permitted. Only a |
| 76 | * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only |
| 77 | * used by tlb_flush_page. |
| 78 | */ |
| 79 | void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr, |
| 80 | hwaddr paddr, MemTxAttrs attrs, |
| 81 | int prot, int mmu_idx, vaddr size); |
| 82 | |
| 83 | /** |
| 84 | * tlb_set_page: |
| 85 | * |
| 86 | * This function is equivalent to calling tlb_set_page_with_attrs() |
| 87 | * with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided |
| 88 | * as a convenience for CPUs which don't use memory transaction attributes. |
| 89 | */ |
| 90 | void tlb_set_page(CPUState *cpu, vaddr addr, |
| 91 | hwaddr paddr, int prot, |
| 92 | int mmu_idx, vaddr size); |
| 93 | |
| 94 | #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) |
| 95 | /** |
| 96 | * tlb_flush_page: |
| 97 | * @cpu: CPU whose TLB should be flushed |
| 98 | * @addr: virtual address of page to be flushed |
| 99 | * |
| 100 | * Flush one page from the TLB of the specified CPU, for all |
| 101 | * MMU indexes. |
| 102 | */ |
| 103 | void tlb_flush_page(CPUState *cpu, vaddr addr); |
| 104 | |
| 105 | /** |
| 106 | * tlb_flush_page_all_cpus_synced: |
| 107 | * @cpu: src CPU of the flush |
| 108 | * @addr: virtual address of page to be flushed |
| 109 | * |
| 110 | * Flush one page from the TLB of all CPUs, for all |
| 111 | * MMU indexes. |
| 112 | * |
| 113 | * When this function returns, no CPUs will subsequently perform |
| 114 | * translations using the flushed TLBs. |
| 115 | */ |
| 116 | void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr); |
| 117 | |
| 118 | /** |
| 119 | * tlb_flush: |
| 120 | * @cpu: CPU whose TLB should be flushed |
| 121 | * |
| 122 | * Flush the entire TLB for the specified CPU. Most CPU architectures |
| 123 | * allow the implementation to drop entries from the TLB at any time |
| 124 | * so this is generally safe. If more selective flushing is required |
| 125 | * use one of the other functions for efficiency. |
| 126 | */ |
| 127 | void tlb_flush(CPUState *cpu); |
| 128 | |
| 129 | /** |
| 130 | * tlb_flush_all_cpus_synced: |
| 131 | * @cpu: src CPU of the flush |
| 132 | * |
| 133 | * Flush the entire TLB for all CPUs, for all MMU indexes. |
| 134 | * |
| 135 | * When this function returns, no CPUs will subsequently perform |
| 136 | * translations using the flushed TLBs. |
| 137 | */ |
| 138 | void tlb_flush_all_cpus_synced(CPUState *src_cpu); |
| 139 | |
| 140 | /** |
| 141 | * tlb_flush_page_by_mmuidx: |
| 142 | * @cpu: CPU whose TLB should be flushed |
| 143 | * @addr: virtual address of page to be flushed |
| 144 | * @idxmap: bitmap of MMU indexes to flush |
| 145 | * |
| 146 | * Flush one page from the TLB of the specified CPU, for the specified |
| 147 | * MMU indexes. |
| 148 | */ |
| 149 | void tlb_flush_page_by_mmuidx(CPUState *cpu, vaddr addr, |
| 150 | MMUIdxMap idxmap); |
| 151 | |
| 152 | /** |
| 153 | * tlb_flush_page_by_mmuidx_all_cpus_synced: |
| 154 | * @cpu: Originating CPU of the flush |
| 155 | * @addr: virtual address of page to be flushed |
| 156 | * @idxmap: bitmap of MMU indexes to flush |
| 157 | * |
| 158 | * Flush one page from the TLB of all CPUs, for the specified |
| 159 | * MMU indexes. |
| 160 | * |
| 161 | * When this function returns, no CPUs will subsequently perform |
| 162 | * translations using the flushed TLBs. |
| 163 | */ |
| 164 | void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr, |
| 165 | MMUIdxMap idxmap); |
| 166 | |
| 167 | /** |
| 168 | * tlb_flush_by_mmuidx: |
| 169 | * @cpu: CPU whose TLB should be flushed |
| 170 | * @wait: If true ensure synchronisation by exiting the cpu_loop |
| 171 | * @idxmap: bitmap of MMU indexes to flush |
| 172 | * |
| 173 | * Flush all entries from the TLB of the specified CPU, for the specified |
| 174 | * MMU indexes. |
| 175 | */ |
| 176 | void tlb_flush_by_mmuidx(CPUState *cpu, MMUIdxMap idxmap); |
| 177 | |
| 178 | /** |
| 179 | * tlb_flush_by_mmuidx_all_cpus_synced: |
| 180 | * @cpu: Originating CPU of the flush |
| 181 | * @idxmap: bitmap of MMU indexes to flush |
| 182 | * |
| 183 | * Flush all entries from the TLB of all CPUs, for the specified |
| 184 | * MMU indexes. |
| 185 | * |
| 186 | * When this function returns, no CPUs will subsequently perform |
| 187 | * translations using the flushed TLBs. |
| 188 | */ |
| 189 | void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, MMUIdxMap idxmap); |
| 190 | |
| 191 | /** |
| 192 | * tlb_flush_page_bits_by_mmuidx |
| 193 | * @cpu: CPU whose TLB should be flushed |
| 194 | * @addr: virtual address of page to be flushed |
| 195 | * @idxmap: bitmap of mmu indexes to flush |
| 196 | * @bits: number of significant bits in address |
| 197 | * |
| 198 | * Similar to tlb_flush_page_mask, but with a bitmap of indexes. |
| 199 | */ |
| 200 | void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, vaddr addr, |
| 201 | MMUIdxMap idxmap, unsigned bits); |
| 202 | |
| 203 | /* Similarly, with broadcast and syncing. */ |
| 204 | void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr, |
| 205 | MMUIdxMap idxmap, |
| 206 | unsigned bits); |
| 207 | |
| 208 | /** |
| 209 | * tlb_flush_range_by_mmuidx |
| 210 | * @cpu: CPU whose TLB should be flushed |
| 211 | * @addr: virtual address of the start of the range to be flushed |
| 212 | * @len: length of range to be flushed |
| 213 | * @idxmap: bitmap of mmu indexes to flush |
| 214 | * @bits: number of significant bits in address |
| 215 | * |
| 216 | * For each mmuidx in @idxmap, flush all pages within [@addr,@addr+@len), |
| 217 | * comparing only the low @bits worth of each virtual page. |
| 218 | */ |
| 219 | void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr, |
| 220 | vaddr len, MMUIdxMap idxmap, |
| 221 | unsigned bits); |
| 222 | |
| 223 | /* Similarly, with broadcast and syncing. */ |
| 224 | void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, |
| 225 | vaddr addr, |
| 226 | vaddr len, |
| 227 | MMUIdxMap idxmap, |
| 228 | unsigned bits); |
| 229 | #else |
| 230 | static inline void tlb_flush_page(CPUState *cpu, vaddr addr) |
| 231 | { |
| 232 | } |
| 233 | static inline void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr) |
| 234 | { |
| 235 | } |
| 236 | static inline void tlb_flush(CPUState *cpu) |
| 237 | { |
| 238 | } |
| 239 | static inline void tlb_flush_all_cpus_synced(CPUState *src_cpu) |
| 240 | { |
| 241 | } |
| 242 | static inline void tlb_flush_page_by_mmuidx(CPUState *cpu, |
| 243 | vaddr addr, MMUIdxMap idxmap) |
| 244 | { |
| 245 | } |
| 246 | |
| 247 | static inline void tlb_flush_by_mmuidx(CPUState *cpu, MMUIdxMap idxmap) |
| 248 | { |
| 249 | } |
| 250 | static inline void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, |
| 251 | vaddr addr, |
| 252 | MMUIdxMap idxmap) |
| 253 | { |
| 254 | } |
| 255 | static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, |
| 256 | MMUIdxMap idxmap) |
| 257 | { |
| 258 | } |
| 259 | static inline void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, |
| 260 | vaddr addr, |
| 261 | MMUIdxMap idxmap, |
| 262 | unsigned bits) |
| 263 | { |
| 264 | } |
| 265 | static inline void |
| 266 | tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr, |
| 267 | MMUIdxMap idxmap, unsigned bits) |
| 268 | { |
| 269 | } |
| 270 | static inline void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr, |
| 271 | vaddr len, MMUIdxMap idxmap, |
| 272 | unsigned bits) |
| 273 | { |
| 274 | } |
| 275 | static inline void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, |
| 276 | vaddr addr, |
| 277 | vaddr len, |
| 278 | MMUIdxMap idxmap, |
| 279 | unsigned bits) |
| 280 | { |
| 281 | } |
| 282 | #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ |
| 283 | #endif /* CPUTLB_H */ |