| 1 | /* |
| 2 | * Allwinner R40/A40i/T3 System on Chip emulation |
| 3 | * |
| 4 | * Copyright (C) 2023 qianfan Zhao <qianfanguijin@163.com> |
| 5 | * |
| 6 | * This program is free software: you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation, either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #ifndef HW_ARM_ALLWINNER_R40_H |
| 21 | #define HW_ARM_ALLWINNER_R40_H |
| 22 | |
| 23 | #include "qom/object.h" |
| 24 | #include "hw/timer/allwinner-a10-pit.h" |
| 25 | #include "hw/ide/ahci-sysbus.h" |
| 26 | #include "hw/intc/arm_gic.h" |
| 27 | #include "hw/sd/allwinner-sdhost.h" |
| 28 | #include "hw/misc/allwinner-r40-ccu.h" |
| 29 | #include "hw/misc/allwinner-r40-dramc.h" |
| 30 | #include "hw/misc/allwinner-sramc.h" |
| 31 | #include "hw/i2c/allwinner-i2c.h" |
| 32 | #include "hw/net/allwinner_emac.h" |
| 33 | #include "hw/net/allwinner-sun8i-emac.h" |
| 34 | #include "hw/usb/hcd-ohci.h" |
| 35 | #include "hw/usb/hcd-ehci.h" |
| 36 | #include "hw/watchdog/allwinner-wdt.h" |
| 37 | #include "target/arm/cpu.h" |
| 38 | #include "system/block-backend.h" |
| 39 | |
| 40 | enum { |
| 41 | AW_R40_DEV_SRAM_A1, |
| 42 | AW_R40_DEV_SRAM_A2, |
| 43 | AW_R40_DEV_SRAM_A3, |
| 44 | AW_R40_DEV_SRAM_A4, |
| 45 | AW_R40_DEV_SRAMC, |
| 46 | AW_R40_DEV_EMAC, |
| 47 | AW_R40_DEV_MMC0, |
| 48 | AW_R40_DEV_MMC1, |
| 49 | AW_R40_DEV_MMC2, |
| 50 | AW_R40_DEV_MMC3, |
| 51 | AW_R40_DEV_AHCI, |
| 52 | AW_R40_DEV_EHCI1, |
| 53 | AW_R40_DEV_OHCI1, |
| 54 | AW_R40_DEV_EHCI2, |
| 55 | AW_R40_DEV_OHCI2, |
| 56 | AW_R40_DEV_CCU, |
| 57 | AW_R40_DEV_PIT, |
| 58 | AW_R40_DEV_WDT, |
| 59 | AW_R40_DEV_UART0, |
| 60 | AW_R40_DEV_UART1, |
| 61 | AW_R40_DEV_UART2, |
| 62 | AW_R40_DEV_UART3, |
| 63 | AW_R40_DEV_UART4, |
| 64 | AW_R40_DEV_UART5, |
| 65 | AW_R40_DEV_UART6, |
| 66 | AW_R40_DEV_UART7, |
| 67 | AW_R40_DEV_TWI0, |
| 68 | AW_R40_DEV_GMAC, |
| 69 | AW_R40_DEV_GIC_DIST, |
| 70 | AW_R40_DEV_GIC_CPU, |
| 71 | AW_R40_DEV_GIC_HYP, |
| 72 | AW_R40_DEV_GIC_VCPU, |
| 73 | AW_R40_DEV_SDRAM, |
| 74 | AW_R40_DEV_DRAMCOM, |
| 75 | AW_R40_DEV_DRAMCTL, |
| 76 | AW_R40_DEV_DRAMPHY, |
| 77 | }; |
| 78 | |
| 79 | #define AW_R40_NUM_CPUS (4) |
| 80 | |
| 81 | /** |
| 82 | * Allwinner R40 object model |
| 83 | * @{ |
| 84 | */ |
| 85 | |
| 86 | /** Object type for the Allwinner R40 SoC */ |
| 87 | #define TYPE_AW_R40 "allwinner-r40" |
| 88 | |
| 89 | /** Convert input object to Allwinner R40 state object */ |
| 90 | OBJECT_DECLARE_SIMPLE_TYPE(AwR40State, AW_R40) |
| 91 | |
| 92 | /** @} */ |
| 93 | |
| 94 | /** |
| 95 | * Allwinner R40 object |
| 96 | * |
| 97 | * This struct contains the state of all the devices |
| 98 | * which are currently emulated by the R40 SoC code. |
| 99 | */ |
| 100 | #define AW_R40_NUM_MMCS 4 |
| 101 | #define AW_R40_NUM_USB 2 |
| 102 | #define AW_R40_NUM_UARTS 8 |
| 103 | |
| 104 | struct AwR40State { |
| 105 | /*< private >*/ |
| 106 | DeviceState parent_obj; |
| 107 | /*< public >*/ |
| 108 | |
| 109 | /** Physical base address for start of RAM */ |
| 110 | hwaddr ram_addr; |
| 111 | |
| 112 | /** Total RAM size in megabytes */ |
| 113 | uint32_t ram_size; |
| 114 | |
| 115 | ARMCPU cpus[AW_R40_NUM_CPUS]; |
| 116 | const hwaddr *memmap; |
| 117 | AwSRAMCState sramc; |
| 118 | AwA10PITState timer; |
| 119 | AwWdtState wdt; |
| 120 | AllwinnerAHCIState sata; |
| 121 | AwSdHostState mmc[AW_R40_NUM_MMCS]; |
| 122 | EHCISysBusState ehci[AW_R40_NUM_USB]; |
| 123 | OHCISysBusState ohci[AW_R40_NUM_USB]; |
| 124 | AwR40ClockCtlState ccu; |
| 125 | AwR40DramCtlState dramc; |
| 126 | AWI2CState i2c0; |
| 127 | AwEmacState emac; |
| 128 | AwSun8iEmacState gmac; |
| 129 | GICState gic; |
| 130 | MemoryRegion sram_a1; |
| 131 | MemoryRegion sram_a2; |
| 132 | MemoryRegion sram_a3; |
| 133 | MemoryRegion sram_a4; |
| 134 | }; |
| 135 | |
| 136 | /** |
| 137 | * Emulate Boot ROM firmware setup functionality. |
| 138 | * |
| 139 | * A real Allwinner R40 SoC contains a Boot ROM |
| 140 | * which is the first code that runs right after |
| 141 | * the SoC is powered on. The Boot ROM is responsible |
| 142 | * for loading user code (e.g. a bootloader) from any |
| 143 | * of the supported external devices and writing the |
| 144 | * downloaded code to internal SRAM. After loading the SoC |
| 145 | * begins executing the code written to SRAM. |
| 146 | * |
| 147 | * This function emulates the Boot ROM by copying 32 KiB |
| 148 | * of data from the given block device and writes it to |
| 149 | * the start of the first internal SRAM memory. |
| 150 | * |
| 151 | * @s: Allwinner R40 state object pointer |
| 152 | * @blk: Block backend device object pointer |
| 153 | * @unit: the mmc control's unit |
| 154 | */ |
| 155 | bool allwinner_r40_bootrom_setup(AwR40State *s, BlockBackend *blk, int unit); |
| 156 | |
| 157 | #endif /* HW_ARM_ALLWINNER_R40_H */ |