| 1 | /* |
| 2 | * ARM SSE (Subsystems for Embedded): IoTKit, SSE-200 |
| 3 | * |
| 4 | * Copyright (c) 2018 Linaro Limited |
| 5 | * Written by Peter Maydell |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 or |
| 9 | * (at your option) any later version. |
| 10 | */ |
| 11 | |
| 12 | /* |
| 13 | * This is a model of the Arm "Subsystems for Embedded" family of |
| 14 | * hardware, which include the IoT Kit and the SSE-050, SSE-100, |
| 15 | * SSE-200, SSE-300, and SSE-310. Currently we model: |
| 16 | * - the Arm IoT Kit which is documented in |
| 17 | * https://developer.arm.com/documentation/ecm0601256/latest |
| 18 | * - the SSE-200 which is documented in |
| 19 | * https://developer.arm.com/documentation/101104/latest/ |
| 20 | * - the SSE-300 which is documented in |
| 21 | * https://support.arm.com/documentation/101773/latest/ |
| 22 | * - the SSE-310 which is documented in |
| 23 | * https://support.arm.com/documentation/102778/latest/ |
| 24 | * |
| 25 | * The IoTKit contains: |
| 26 | * a Cortex-M33 |
| 27 | * the IDAU |
| 28 | * some timers and watchdogs |
| 29 | * two peripheral protection controllers |
| 30 | * a memory protection controller |
| 31 | * a security controller |
| 32 | * a bus fabric which arranges that some parts of the address |
| 33 | * space are secure and non-secure aliases of each other |
| 34 | * The SSE-200 additionally contains: |
| 35 | * a second Cortex-M33 |
| 36 | * two Message Handling Units (MHUs) |
| 37 | * an optional CryptoCell (which we do not model) |
| 38 | * more SRAM banks with associated MPCs |
| 39 | * multiple Power Policy Units (PPUs) |
| 40 | * a control interface for an icache for each CPU |
| 41 | * per-CPU identity and control register blocks |
| 42 | * |
| 43 | * QEMU interface: |
| 44 | * + Clock input "MAINCLK": clock for CPUs and most peripherals |
| 45 | * + Clock input "S32KCLK": slow 32KHz clock used for a few peripherals |
| 46 | * + QOM property "memory" is a MemoryRegion containing the devices provided |
| 47 | * by the board model. |
| 48 | * + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts. |
| 49 | * (In hardware, the SSE-200 permits the number of expansion interrupts |
| 50 | * for the two CPUs to be configured separately, but we restrict it to |
| 51 | * being the same for both, to avoid having to have separate Property |
| 52 | * lists for different variants. This restriction can be relaxed later |
| 53 | * if necessary.) |
| 54 | * + QOM property "SRAM_ADDR_WIDTH" sets the number of bits used for the |
| 55 | * address of each SRAM bank (and thus the total amount of internal SRAM) |
| 56 | * + QOM property "init-svtor" sets the initial value of the CPU SVTOR register |
| 57 | * (where it expects to load the PC and SP from the vector table on reset) |
| 58 | * + QOM properties "CPU0_FPU", "CPU0_DSP", "CPU1_FPU" and "CPU1_DSP" which |
| 59 | * set whether the CPUs have the FPU and DSP features present. The default |
| 60 | * (matching the hardware) is that for CPU0 in an IoTKit and CPU1 in an |
| 61 | * SSE-200 both are present; CPU0 in an SSE-200 has neither. |
| 62 | * Since the IoTKit has only one CPU, it does not have the CPU1_* properties. |
| 63 | * + QOM properties "CPU0_MPU_NS", "CPU0_MPU_S", "CPU1_MPU_NS" and "CPU1_MPU_S" |
| 64 | * which set the number of MPU regions on the CPUs. If there is only one |
| 65 | * CPU the CPU1 properties are not present. |
| 66 | * + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CPU 0, |
| 67 | * which are wired to its NVIC lines 32 .. n+32 |
| 68 | * + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts for |
| 69 | * CPU 1, which are wired to its NVIC lines 32 .. n+32 |
| 70 | * + sysbus MMIO region 0 is the "AHB Slave Expansion" which allows |
| 71 | * bus master devices in the board model to make transactions into |
| 72 | * all the devices and memory areas in the IoTKit |
| 73 | * Controlling up to 4 AHB expansion PPBs which a system using the IoTKit |
| 74 | * might provide: |
| 75 | * + named GPIO outputs apb_ppcexp{0,1,2,3}_nonsec[0..15] |
| 76 | * + named GPIO outputs apb_ppcexp{0,1,2,3}_ap[0..15] |
| 77 | * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_enable |
| 78 | * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_clear |
| 79 | * + named GPIO inputs apb_ppcexp{0,1,2,3}_irq_status |
| 80 | * Controlling each of the 4 expansion AHB PPCs which a system using the IoTKit |
| 81 | * might provide: |
| 82 | * + named GPIO outputs ahb_ppcexp{0,1,2,3}_nonsec[0..15] |
| 83 | * + named GPIO outputs ahb_ppcexp{0,1,2,3}_ap[0..15] |
| 84 | * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable |
| 85 | * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear |
| 86 | * + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status |
| 87 | * Controlling each of the 16 expansion MPCs which a system using the IoTKit |
| 88 | * might provide: |
| 89 | * + named GPIO inputs mpcexp_status[0..15] |
| 90 | * Controlling each of the 16 expansion MSCs which a system using the IoTKit |
| 91 | * might provide: |
| 92 | * + named GPIO inputs mscexp_status[0..15] |
| 93 | * + named GPIO outputs mscexp_clear[0..15] |
| 94 | * + named GPIO outputs mscexp_ns[0..15] |
| 95 | */ |
| 96 | |
| 97 | #ifndef ARMSSE_H |
| 98 | #define ARMSSE_H |
| 99 | |
| 100 | #include "hw/core/sysbus.h" |
| 101 | #include "hw/arm/armv7m.h" |
| 102 | #include "hw/misc/iotkit-secctl.h" |
| 103 | #include "hw/misc/tz-ppc.h" |
| 104 | #include "hw/misc/tz-mpc.h" |
| 105 | #include "hw/timer/cmsdk-apb-timer.h" |
| 106 | #include "hw/timer/cmsdk-apb-dualtimer.h" |
| 107 | #include "hw/timer/sse-counter.h" |
| 108 | #include "hw/timer/sse-timer.h" |
| 109 | #include "hw/watchdog/cmsdk-apb-watchdog.h" |
| 110 | #include "hw/misc/iotkit-sysctl.h" |
| 111 | #include "hw/misc/iotkit-sysinfo.h" |
| 112 | #include "hw/misc/armsse-cpuid.h" |
| 113 | #include "hw/misc/armsse-mhu.h" |
| 114 | #include "hw/misc/armsse-cpu-pwrctrl.h" |
| 115 | #include "hw/misc/unimp.h" |
| 116 | #include "hw/core/or-irq.h" |
| 117 | #include "hw/core/clock.h" |
| 118 | #include "hw/core/split-irq.h" |
| 119 | #include "hw/cpu/cluster.h" |
| 120 | #include "qom/object.h" |
| 121 | |
| 122 | #define TYPE_ARM_SSE "arm-sse" |
| 123 | OBJECT_DECLARE_TYPE(ARMSSE, ARMSSEClass, |
| 124 | ARM_SSE) |
| 125 | |
| 126 | /* |
| 127 | * These type names are for specific IoTKit subsystems; other than |
| 128 | * instantiating them, code using these devices should always handle |
| 129 | * them via the ARMSSE base class, so they have no IOTKIT() etc macros. |
| 130 | */ |
| 131 | #define TYPE_IOTKIT "iotkit" |
| 132 | #define TYPE_SSE200 "sse-200" |
| 133 | #define TYPE_SSE300 "sse-300" |
| 134 | #define TYPE_SSE310 "sse-310" |
| 135 | |
| 136 | /* We have an IRQ splitter and an OR gate input for each external PPC |
| 137 | * and the 2 internal PPCs |
| 138 | */ |
| 139 | #define NUM_INTERNAL_PPCS 2 |
| 140 | #define NUM_EXTERNAL_PPCS (IOTS_NUM_AHB_EXP_PPC + IOTS_NUM_APB_EXP_PPC) |
| 141 | #define NUM_PPCS (NUM_EXTERNAL_PPCS + NUM_INTERNAL_PPCS) |
| 142 | |
| 143 | #define MAX_SRAM_BANKS 4 |
| 144 | #if MAX_SRAM_BANKS > IOTS_NUM_MPC |
| 145 | #error Too many SRAM banks |
| 146 | #endif |
| 147 | |
| 148 | #define SSE_MAX_CPUS 2 |
| 149 | |
| 150 | #define NUM_PPUS 8 |
| 151 | |
| 152 | /* Number of CPU IRQs used by the SSE itself */ |
| 153 | #define NUM_SSE_IRQS 32 |
| 154 | |
| 155 | struct ARMSSE { |
| 156 | /*< private >*/ |
| 157 | SysBusDevice parent_obj; |
| 158 | |
| 159 | /*< public >*/ |
| 160 | ARMv7MState armv7m[SSE_MAX_CPUS]; |
| 161 | CPUClusterState cluster[SSE_MAX_CPUS]; |
| 162 | IoTKitSecCtl secctl; |
| 163 | TZPPC apb_ppc[NUM_INTERNAL_PPCS]; |
| 164 | TZMPC mpc[IOTS_NUM_MPC]; |
| 165 | CMSDKAPBTimer timer[3]; |
| 166 | OrIRQState ppc_irq_orgate; |
| 167 | SplitIRQ sec_resp_splitter; |
| 168 | SplitIRQ ppc_irq_splitter[NUM_PPCS]; |
| 169 | SplitIRQ mpc_irq_splitter[IOTS_NUM_EXP_MPC + IOTS_NUM_MPC]; |
| 170 | OrIRQState mpc_irq_orgate; |
| 171 | OrIRQState nmi_orgate; |
| 172 | |
| 173 | SplitIRQ cpu_irq_splitter[NUM_SSE_IRQS]; |
| 174 | |
| 175 | CMSDKAPBDualTimer dualtimer; |
| 176 | |
| 177 | CMSDKAPBWatchdog cmsdk_watchdog[3]; |
| 178 | |
| 179 | SSECounter sse_counter; |
| 180 | SSETimer sse_timer[4]; |
| 181 | |
| 182 | IoTKitSysCtl sysctl; |
| 183 | IoTKitSysCtl sysinfo; |
| 184 | |
| 185 | ARMSSEMHU mhu[2]; |
| 186 | UnimplementedDeviceState unimp[NUM_PPUS]; |
| 187 | UnimplementedDeviceState cachectrl[SSE_MAX_CPUS]; |
| 188 | UnimplementedDeviceState cpusecctrl[SSE_MAX_CPUS]; |
| 189 | |
| 190 | ARMSSECPUID cpuid[SSE_MAX_CPUS]; |
| 191 | |
| 192 | ARMSSECPUPwrCtrl cpu_pwrctrl[SSE_MAX_CPUS]; |
| 193 | |
| 194 | /* |
| 195 | * 'container' holds all devices seen by all CPUs. |
| 196 | * 'cpu_container[i]' is the view that CPU i has: this has the |
| 197 | * per-CPU devices of that CPU, plus as the background 'container' |
| 198 | * (or an alias of it, since we can only use it directly once). |
| 199 | * container_alias[i] is the alias of 'container' used by CPU i+1; |
| 200 | * CPU 0 can use 'container' directly. |
| 201 | */ |
| 202 | MemoryRegion container; |
| 203 | MemoryRegion container_alias[SSE_MAX_CPUS - 1]; |
| 204 | MemoryRegion cpu_container[SSE_MAX_CPUS]; |
| 205 | MemoryRegion alias1; |
| 206 | MemoryRegion alias2; |
| 207 | MemoryRegion alias3[SSE_MAX_CPUS]; |
| 208 | MemoryRegion sram[MAX_SRAM_BANKS]; |
| 209 | MemoryRegion itcm; |
| 210 | MemoryRegion dtcm; |
| 211 | |
| 212 | qemu_irq *exp_irqs[SSE_MAX_CPUS]; |
| 213 | qemu_irq ppc0_irq; |
| 214 | qemu_irq ppc1_irq; |
| 215 | qemu_irq sec_resp_cfg; |
| 216 | qemu_irq sec_resp_cfg_in; |
| 217 | qemu_irq nsc_cfg_in; |
| 218 | |
| 219 | qemu_irq irq_status_in[NUM_EXTERNAL_PPCS]; |
| 220 | qemu_irq mpcexp_status_in[IOTS_NUM_EXP_MPC]; |
| 221 | |
| 222 | uint32_t nsccfg; |
| 223 | |
| 224 | Clock *mainclk; |
| 225 | Clock *s32kclk; |
| 226 | |
| 227 | /* Properties */ |
| 228 | MemoryRegion *board_memory; |
| 229 | uint32_t exp_numirq; |
| 230 | uint32_t sram_addr_width; |
| 231 | uint32_t init_svtor; |
| 232 | uint32_t cpu_mpu_ns[SSE_MAX_CPUS]; |
| 233 | uint32_t cpu_mpu_s[SSE_MAX_CPUS]; |
| 234 | bool cpu_fpu[SSE_MAX_CPUS]; |
| 235 | bool cpu_dsp[SSE_MAX_CPUS]; |
| 236 | }; |
| 237 | |
| 238 | typedef struct ARMSSEInfo ARMSSEInfo; |
| 239 | |
| 240 | struct ARMSSEClass { |
| 241 | SysBusDeviceClass parent_class; |
| 242 | const ARMSSEInfo *info; |
| 243 | }; |
| 244 | |
| 245 | |
| 246 | #endif |