| 1 | /* |
| 2 | * Aspeed Machines |
| 3 | * |
| 4 | * Copyright 2018 IBM Corp. |
| 5 | * |
| 6 | * This code is licensed under the GPL version 2 or later. See |
| 7 | * the COPYING file in the top-level directory. |
| 8 | */ |
| 9 | #ifndef ARM_ASPEED_H |
| 10 | #define ARM_ASPEED_H |
| 11 | |
| 12 | #include "hw/core/boards.h" |
| 13 | #include "qom/object.h" |
| 14 | #include "hw/arm/aspeed_soc.h" |
| 15 | #include "hw/arm/boot.h" |
| 16 | |
| 17 | typedef struct AspeedMachineState AspeedMachineState; |
| 18 | |
| 19 | #define TYPE_ASPEED_MACHINE MACHINE_TYPE_NAME("aspeed") |
| 20 | typedef struct AspeedMachineClass AspeedMachineClass; |
| 21 | DECLARE_OBJ_CHECKERS(AspeedMachineState, AspeedMachineClass, |
| 22 | ASPEED_MACHINE, TYPE_ASPEED_MACHINE) |
| 23 | |
| 24 | #define ASPEED_MAC0_ON (1 << 0) |
| 25 | #define ASPEED_MAC1_ON (1 << 1) |
| 26 | #define ASPEED_MAC2_ON (1 << 2) |
| 27 | #define ASPEED_MAC3_ON (1 << 3) |
| 28 | |
| 29 | /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */ |
| 30 | #if HOST_LONG_BITS == 32 |
| 31 | #define ASPEED_RAM_SIZE(sz) MIN((sz), 1 * GiB) |
| 32 | #else |
| 33 | #define ASPEED_RAM_SIZE(sz) (sz) |
| 34 | #endif |
| 35 | |
| 36 | struct AspeedMachineState { |
| 37 | MachineState parent_obj; |
| 38 | |
| 39 | AspeedSoCState *soc; |
| 40 | MemoryRegion boot_rom; |
| 41 | bool mmio_exec; |
| 42 | uint32_t uart_chosen; |
| 43 | char *fmc_model; |
| 44 | char *spi_model; |
| 45 | uint32_t hw_strap1; |
| 46 | struct arm_boot_info bootinfo; |
| 47 | }; |
| 48 | |
| 49 | struct AspeedMachineClass { |
| 50 | MachineClass parent_obj; |
| 51 | |
| 52 | const char *name; |
| 53 | const char *desc; |
| 54 | const char *soc_name; |
| 55 | uint32_t hw_strap1; |
| 56 | uint32_t hw_strap2; |
| 57 | const char *fmc_model; |
| 58 | const char *spi_model; |
| 59 | const char *spi2_model; |
| 60 | uint32_t num_cs; |
| 61 | uint32_t num_cs2; |
| 62 | uint32_t macs_mask; |
| 63 | void (*i2c_init)(AspeedMachineState *bmc); |
| 64 | uint32_t uart_default; |
| 65 | bool sdhci_wp_inverted; |
| 66 | bool vbootrom; |
| 67 | }; |
| 68 | |
| 69 | /* |
| 70 | * aspeed_machine_class_init_cpus_defaults: |
| 71 | * @mc: the #MachineClass to be initialized. |
| 72 | * |
| 73 | * Initialize the default CPU configuration for an Aspeed machine class. |
| 74 | * This function sets the default, minimum, and maximum CPU counts |
| 75 | * to match the number of CPUs defined in the associated SoC class, |
| 76 | * and copies its list of valid CPU types. |
| 77 | */ |
| 78 | void aspeed_machine_class_init_cpus_defaults(MachineClass *mc); |
| 79 | |
| 80 | /* |
| 81 | * aspeed_create_pca9552: |
| 82 | * @soc: pointer to the #AspeedSoCState. |
| 83 | * @bus_id: the I2C bus index to attach the device. |
| 84 | * @addr: the I2C address of the PCA9552 device. |
| 85 | * |
| 86 | * Create and attach a PCA9552 LED controller device to the specified I2C bus |
| 87 | * of the given Aspeed SoC. The device is instantiated using |
| 88 | * i2c_slave_create_simple() with the PCA9552 device type. |
| 89 | */ |
| 90 | void aspeed_create_pca9552(AspeedSoCState *soc, int bus_id, int addr); |
| 91 | |
| 92 | /* |
| 93 | * aspeed_create_pca9554: |
| 94 | * @soc: pointer to the #AspeedSoCState. |
| 95 | * @bus_id: the I2C bus index to attach the device. |
| 96 | * @addr: the I2C address of the PCA9554 device. |
| 97 | * |
| 98 | * Create and attach a PCA9554 I/O expander to the specified I2C bus |
| 99 | * of the given Aspeed SoC. The device is created via |
| 100 | * i2c_slave_create_simple() and returned as an #I2CSlave pointer. |
| 101 | * |
| 102 | * Returns: a pointer to the newly created #I2CSlave instance. |
| 103 | */ |
| 104 | I2CSlave *aspeed_create_pca9554(AspeedSoCState *soc, int bus_id, int addr); |
| 105 | |
| 106 | /* |
| 107 | * aspeed_machine_ast2600_class_emmc_init: |
| 108 | * @oc: the #ObjectClass to initialize. |
| 109 | * |
| 110 | * Initialize eMMC-related properties for the AST2600 Aspeed machine class. |
| 111 | * This function is typically invoked during class initialization to set up |
| 112 | * default configuration or attach eMMC-specific devices for AST2600 platforms. |
| 113 | */ |
| 114 | void aspeed_machine_ast2600_class_emmc_init(ObjectClass *oc); |
| 115 | |
| 116 | /* |
| 117 | * aspeed_connect_serial_hds_to_uarts: |
| 118 | * @bmc: pointer to the #AspeedMachineState. |
| 119 | * |
| 120 | * Connect host serial backends (character devices) to the UART interfaces |
| 121 | * of the Aspeed SoC used by the given BMC machine. |
| 122 | * |
| 123 | * The function assigns `serial_hd(0)` to the primary UART channel |
| 124 | * (either chosen via `bmc->uart_chosen` or the machine class default), |
| 125 | * and iteratively connects remaining serial ports to other available UARTs |
| 126 | * on the SoC based on their index. |
| 127 | */ |
| 128 | void aspeed_connect_serial_hds_to_uarts(AspeedMachineState *bmc); |
| 129 | |
| 130 | #endif |